diff --git a/Core/Inc/Backup/FreeRTOSConfig.h.bak b/Core/Inc/Backup/FreeRTOSConfig.h.bak new file mode 100644 index 0000000..20b39a2 --- /dev/null +++ b/Core/Inc/Backup/FreeRTOSConfig.h.bak @@ -0,0 +1,173 @@ +/* USER CODE BEGIN Header */ +/* + * FreeRTOS Kernel V10.3.1 + * Portion Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Portion Copyright (C) 2019 StMicroelectronics, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ +/* USER CODE END Header */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * These parameters and more are described within the 'configuration' section of the + * FreeRTOS API documentation available on the FreeRTOS.org web site. + * + * See http://www.freertos.org/a00110.html + *----------------------------------------------------------*/ + +/* USER CODE BEGIN Includes */ +/* Section where include file can be added */ +/* USER CODE END Includes */ + +/* Ensure definitions are only used by the compiler, and not by the assembler. */ +#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__) + #include + extern uint32_t SystemCoreClock; +#endif +#ifndef CMSIS_device_header +#define CMSIS_device_header "stm32f4xx.h" +#endif /* CMSIS_device_header */ + +#define configENABLE_FPU 0 +#define configENABLE_MPU 0 + +#define configUSE_PREEMPTION 1 +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( SystemCoreClock ) +#define configTICK_RATE_HZ ((TickType_t)1000) +#define configMAX_PRIORITIES ( 56 ) +#define configMINIMAL_STACK_SIZE ((uint16_t)128) +#define configTOTAL_HEAP_SIZE ((size_t)15360) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configUSE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +/* USER CODE BEGIN MESSAGE_BUFFER_LENGTH_TYPE */ +/* Defaults to size_t for backward compatibility, but can be changed + if lengths will always be less than the number of bytes in a size_t. */ +#define configMESSAGE_BUFFER_LENGTH_TYPE size_t +/* USER CODE END MESSAGE_BUFFER_LENGTH_TYPE */ + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( 2 ) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH 256 + +/* The following flag must be enabled only when using newlib */ +#define configUSE_NEWLIB_REENTRANT 1 + +/* CMSIS-RTOS V2 flags */ +#define configUSE_OS2_THREAD_SUSPEND_RESUME 1 +#define configUSE_OS2_THREAD_ENUMERATE 1 +#define configUSE_OS2_EVENTFLAGS_FROM_ISR 1 +#define configUSE_OS2_THREAD_FLAGS 1 +#define configUSE_OS2_TIMER 1 +#define configUSE_OS2_MUTEX 1 + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xQueueGetMutexHolder 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_eTaskGetState 1 + +/* + * The CMSIS-RTOS V2 FreeRTOS wrapper is dependent on the heap implementation used + * by the application thus the correct define need to be enabled below + */ +#define USE_FreeRTOS_HEAP_4 + +/* Cortex-M specific definitions. */ +#ifdef __NVIC_PRIO_BITS + /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ + #define configPRIO_BITS __NVIC_PRIO_BITS +#else + #define configPRIO_BITS 4 +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15 + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) + +/* Normal assert() semantics without relying on the provision of an assert.h +header file. */ +/* USER CODE BEGIN 1 */ +#define configASSERT( x ) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );} +/* USER CODE END 1 */ + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler + +/* IMPORTANT: After 10.3.1 update, Systick_Handler comes from NVIC (if SYS timebase = systick), otherwise from cmsis_os2.c */ + +#define USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION 0 + +/* USER CODE BEGIN Defines */ +/* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */ +/* USER CODE END Defines */ + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Core/Inc/Backup/main.h.bak b/Core/Inc/Backup/main.h.bak new file mode 100644 index 0000000..b31c169 --- /dev/null +++ b/Core/Inc/Backup/main.h.bak @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/Core/Inc/Backup/stm32f4xx_hal_conf.h.bak b/Core/Inc/Backup/stm32f4xx_hal_conf.h.bak new file mode 100644 index 0000000..455b260 --- /dev/null +++ b/Core/Inc/Backup/stm32f4xx_hal_conf.h.bak @@ -0,0 +1,495 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32f4xx_hal_conf.h. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_CONF_H +#define __STM32F4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + + /* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_ADC_MODULE_ENABLED */ +#define HAL_CAN_MODULE_ENABLED +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ +/* #define HAL_ETH_LEGACY_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_PCCARD_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_I2C_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +#define HAL_TIM_MODULE_ENABLED +/* #define HAL_UART_MODULE_ENABLED */ +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_FMPI2C_MODULE_ENABLED */ +/* #define HAL_FMPSMBUS_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External audio frequency in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 15U /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CAN_REGISTER_CALLBACKS 1U /* CAN register callback enabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ +#define USE_HAL_FMPSMBUS_REGISTER_CALLBACKS 0U /* FMPSMBUS register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ + #define USE_FULL_ASSERT 1U + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848_PHY_ADDRESS Address*/ +#define DP83848_PHY_ADDRESS +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY 0x000000FFU +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY 0x00000FFFU + +#define PHY_READ_TO 0x0000FFFFU +#define PHY_WRITE_TO 0x0000FFFFU + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ +#define PHY_SR ((uint16_t)) /*!< PHY status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)) /*!< PHY Duplex mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f4xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f4xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32f4xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f4xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f4xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f4xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_ETH_LEGACY_MODULE_ENABLED + #include "stm32f4xx_hal_eth_legacy.h" +#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_PCCARD_MODULE_ENABLED + #include "stm32f4xx_hal_pccard.h" +#endif /* HAL_PCCARD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f4xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f4xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f4xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f4xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f4xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f4xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f4xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_FMPI2C_MODULE_ENABLED + #include "stm32f4xx_hal_fmpi2c.h" +#endif /* HAL_FMPI2C_MODULE_ENABLED */ + +#ifdef HAL_FMPSMBUS_MODULE_ENABLED + #include "stm32f4xx_hal_fmpsmbus.h" +#endif /* HAL_FMPSMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f4xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f4xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_CONF_H */ diff --git a/Core/Inc/Backup/stm32f4xx_it.h.bak b/Core/Inc/Backup/stm32f4xx_it.h.bak new file mode 100644 index 0000000..0391fb8 --- /dev/null +++ b/Core/Inc/Backup/stm32f4xx_it.h.bak @@ -0,0 +1,64 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_IT_H +#define __STM32F4xx_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void DebugMon_Handler(void); +void TIM6_DAC_IRQHandler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_IT_H */ diff --git a/Core/Inc/stm32f4xx_hal_conf.h b/Core/Inc/stm32f4xx_hal_conf.h index 455b260..6ccf0ac 100644 --- a/Core/Inc/stm32f4xx_hal_conf.h +++ b/Core/Inc/stm32f4xx_hal_conf.h @@ -60,7 +60,7 @@ /* #define HAL_RNG_MODULE_ENABLED */ /* #define HAL_RTC_MODULE_ENABLED */ /* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ +#define HAL_SD_MODULE_ENABLED /* #define HAL_MMC_MODULE_ENABLED */ /* #define HAL_SPI_MODULE_ENABLED */ #define HAL_TIM_MODULE_ENABLED diff --git a/Core/Inc/stm32f4xx_it.h b/Core/Inc/stm32f4xx_it.h index 0391fb8..e20bc71 100644 --- a/Core/Inc/stm32f4xx_it.h +++ b/Core/Inc/stm32f4xx_it.h @@ -52,7 +52,10 @@ void MemManage_Handler(void); void BusFault_Handler(void); void UsageFault_Handler(void); void DebugMon_Handler(void); +void SDIO_IRQHandler(void); void TIM6_DAC_IRQHandler(void); +void DMA2_Stream3_IRQHandler(void); +void DMA2_Stream6_IRQHandler(void); /* USER CODE BEGIN EFP */ /* USER CODE END EFP */ diff --git a/Core/Src/Backup/freertos.c.bak b/Core/Src/Backup/freertos.c.bak new file mode 100644 index 0000000..95f65a7 --- /dev/null +++ b/Core/Src/Backup/freertos.c.bak @@ -0,0 +1,59 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * File Name : freertos.c + * Description : Code for freertos applications + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "FreeRTOS.h" +#include "task.h" +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN Variables */ + +/* USER CODE END Variables */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN FunctionPrototypes */ + +/* USER CODE END FunctionPrototypes */ + +/* Private application code --------------------------------------------------*/ +/* USER CODE BEGIN Application */ + +/* USER CODE END Application */ + diff --git a/Core/Src/Backup/main.c.bak b/Core/Src/Backup/main.c.bak new file mode 100644 index 0000000..ea120e6 --- /dev/null +++ b/Core/Src/Backup/main.c.bak @@ -0,0 +1,414 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "cmsis_os.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +CAN_HandleTypeDef hcan1; +CAN_HandleTypeDef hcan2; + +/* Definitions for defaultTask */ +osThreadId_t defaultTaskHandle; +const osThreadAttr_t defaultTask_attributes = { + .name = "defaultTask", + .stack_size = 128 * 4, + .priority = (osPriority_t) osPriorityNormal, +}; +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_CAN1_Init(void); +static void MX_CAN2_Init(void); +void StartDefaultTask(void *argument); + +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_CAN1_Init(); + MX_CAN2_Init(); + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /* Init scheduler */ + osKernelInitialize(); + + /* USER CODE BEGIN RTOS_MUTEX */ + /* add mutexes, ... */ + /* USER CODE END RTOS_MUTEX */ + + /* USER CODE BEGIN RTOS_SEMAPHORES */ + /* add semaphores, ... */ + /* USER CODE END RTOS_SEMAPHORES */ + + /* USER CODE BEGIN RTOS_TIMERS */ + /* start timers, add new ones, ... */ + /* USER CODE END RTOS_TIMERS */ + + /* USER CODE BEGIN RTOS_QUEUES */ + /* add queues, ... */ + /* USER CODE END RTOS_QUEUES */ + + /* Create the thread(s) */ + /* creation of defaultTask */ + defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes); + + /* USER CODE BEGIN RTOS_THREADS */ + /* add threads, ... */ + /* USER CODE END RTOS_THREADS */ + + /* USER CODE BEGIN RTOS_EVENTS */ + /* add events, ... */ + /* USER CODE END RTOS_EVENTS */ + + /* Start scheduler */ + osKernelStart(); + + /* We should never get here as control is now taken by the scheduler */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief CAN1 Initialization Function + * @param None + * @retval None + */ +static void MX_CAN1_Init(void) +{ + + /* USER CODE BEGIN CAN1_Init 0 */ + + /* USER CODE END CAN1_Init 0 */ + + /* USER CODE BEGIN CAN1_Init 1 */ + + /* USER CODE END CAN1_Init 1 */ + hcan1.Instance = CAN1; + hcan1.Init.Prescaler = 16; + hcan1.Init.Mode = CAN_MODE_NORMAL; + hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ; + hcan1.Init.TimeSeg1 = CAN_BS1_1TQ; + hcan1.Init.TimeSeg2 = CAN_BS2_1TQ; + hcan1.Init.TimeTriggeredMode = DISABLE; + hcan1.Init.AutoBusOff = DISABLE; + hcan1.Init.AutoWakeUp = DISABLE; + hcan1.Init.AutoRetransmission = DISABLE; + hcan1.Init.ReceiveFifoLocked = DISABLE; + hcan1.Init.TransmitFifoPriority = DISABLE; + if (HAL_CAN_Init(&hcan1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN CAN1_Init 2 */ + + /* USER CODE END CAN1_Init 2 */ + +} + +/** + * @brief CAN2 Initialization Function + * @param None + * @retval None + */ +static void MX_CAN2_Init(void) +{ + + /* USER CODE BEGIN CAN2_Init 0 */ + + /* USER CODE END CAN2_Init 0 */ + + /* USER CODE BEGIN CAN2_Init 1 */ + + /* USER CODE END CAN2_Init 1 */ + hcan2.Instance = CAN2; + hcan2.Init.Prescaler = 16; + hcan2.Init.Mode = CAN_MODE_NORMAL; + hcan2.Init.SyncJumpWidth = CAN_SJW_1TQ; + hcan2.Init.TimeSeg1 = CAN_BS1_1TQ; + hcan2.Init.TimeSeg2 = CAN_BS2_1TQ; + hcan2.Init.TimeTriggeredMode = DISABLE; + hcan2.Init.AutoBusOff = DISABLE; + hcan2.Init.AutoWakeUp = DISABLE; + hcan2.Init.AutoRetransmission = DISABLE; + hcan2.Init.ReceiveFifoLocked = DISABLE; + hcan2.Init.TransmitFifoPriority = DISABLE; + if (HAL_CAN_Init(&hcan2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN CAN2_Init 2 */ + + /* USER CODE END CAN2_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + /* USER CODE BEGIN MX_GPIO_Init_1 */ + + /* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + + /*Configure GPIO pins : PC13 PC14 PC15 PC0 + PC1 PC2 PC3 PC4 + PC5 PC6 PC7 PC8 + PC9 PC10 PC11 PC12 */ + GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15|GPIO_PIN_0 + |GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4 + |GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8 + |GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /*Configure GPIO pins : PH0 PH1 */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + + /*Configure GPIO pins : PA0 PA1 PA2 PA3 + PA4 PA5 PA6 PA7 + PA8 PA9 PA10 PA11 + PA12 PA13 PA14 PA15 */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7 + |GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*Configure GPIO pins : PB0 PB1 PB2 PB10 + PB11 PB14 PB15 PB3 + PB4 PB5 PB6 PB7 */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_15|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /*Configure GPIO pin : PD2 */ + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN MX_GPIO_Init_2 */ + + /* USER CODE END MX_GPIO_Init_2 */ +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/* USER CODE BEGIN Header_StartDefaultTask */ +/** + * @brief Function implementing the defaultTask thread. + * @param argument: Not used + * @retval None + */ +/* USER CODE END Header_StartDefaultTask */ +void StartDefaultTask(void *argument) +{ + /* USER CODE BEGIN 5 */ + /* Infinite loop */ + for(;;) + { + osDelay(1); + } + /* USER CODE END 5 */ +} + +/** + * @brief Period elapsed callback in non blocking mode + * @note This function is called when TIM6 interrupt took place, inside + * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment + * a global variable "uwTick" used as application time base. + * @param htim : TIM handle + * @retval None + */ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* USER CODE BEGIN Callback 0 */ + + /* USER CODE END Callback 0 */ + if (htim->Instance == TIM6) + { + HAL_IncTick(); + } + /* USER CODE BEGIN Callback 1 */ + + /* USER CODE END Callback 1 */ +} + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/Core/Src/Backup/stm32f4xx_hal_msp.c.bak b/Core/Src/Backup/stm32f4xx_hal_msp.c.bak new file mode 100644 index 0000000..f92fc8e --- /dev/null +++ b/Core/Src/Backup/stm32f4xx_hal_msp.c.bak @@ -0,0 +1,206 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + /* PendSV_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +static uint32_t HAL_RCC_CAN1_CLK_ENABLED=0; + +/** + * @brief CAN MSP Initialization + * This function configures the hardware resources used in this example + * @param hcan: CAN handle pointer + * @retval None + */ +void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hcan->Instance==CAN1) + { + /* USER CODE BEGIN CAN1_MspInit 0 */ + + /* USER CODE END CAN1_MspInit 0 */ + /* Peripheral clock enable */ + HAL_RCC_CAN1_CLK_ENABLED++; + if(HAL_RCC_CAN1_CLK_ENABLED==1){ + __HAL_RCC_CAN1_CLK_ENABLE(); + } + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**CAN1 GPIO Configuration + PB8 ------> CAN1_RX + PB9 ------> CAN1_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF9_CAN1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN CAN1_MspInit 1 */ + + /* USER CODE END CAN1_MspInit 1 */ + } + else if(hcan->Instance==CAN2) + { + /* USER CODE BEGIN CAN2_MspInit 0 */ + + /* USER CODE END CAN2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_CAN2_CLK_ENABLE(); + HAL_RCC_CAN1_CLK_ENABLED++; + if(HAL_RCC_CAN1_CLK_ENABLED==1){ + __HAL_RCC_CAN1_CLK_ENABLE(); + } + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**CAN2 GPIO Configuration + PB12 ------> CAN2_RX + PB13 ------> CAN2_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF9_CAN2; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN CAN2_MspInit 1 */ + + /* USER CODE END CAN2_MspInit 1 */ + } + +} + +/** + * @brief CAN MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param hcan: CAN handle pointer + * @retval None + */ +void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) +{ + if(hcan->Instance==CAN1) + { + /* USER CODE BEGIN CAN1_MspDeInit 0 */ + + /* USER CODE END CAN1_MspDeInit 0 */ + /* Peripheral clock disable */ + HAL_RCC_CAN1_CLK_ENABLED--; + if(HAL_RCC_CAN1_CLK_ENABLED==0){ + __HAL_RCC_CAN1_CLK_DISABLE(); + } + + /**CAN1 GPIO Configuration + PB8 ------> CAN1_RX + PB9 ------> CAN1_TX + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8|GPIO_PIN_9); + + /* USER CODE BEGIN CAN1_MspDeInit 1 */ + + /* USER CODE END CAN1_MspDeInit 1 */ + } + else if(hcan->Instance==CAN2) + { + /* USER CODE BEGIN CAN2_MspDeInit 0 */ + + /* USER CODE END CAN2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_CAN2_CLK_DISABLE(); + HAL_RCC_CAN1_CLK_ENABLED--; + if(HAL_RCC_CAN1_CLK_ENABLED==0){ + __HAL_RCC_CAN1_CLK_DISABLE(); + } + + /**CAN2 GPIO Configuration + PB12 ------> CAN2_RX + PB13 ------> CAN2_TX + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_12|GPIO_PIN_13); + + /* USER CODE BEGIN CAN2_MspDeInit 1 */ + + /* USER CODE END CAN2_MspDeInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Core/Src/Backup/stm32f4xx_hal_timebase_tim.c.bak b/Core/Src/Backup/stm32f4xx_hal_timebase_tim.c.bak new file mode 100644 index 0000000..ca1d88f --- /dev/null +++ b/Core/Src/Backup/stm32f4xx_hal_timebase_tim.c.bak @@ -0,0 +1,138 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_hal_timebase_tim.c + * @brief HAL time base based on the hardware TIM. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" +#include "stm32f4xx_hal_tim.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +TIM_HandleTypeDef htim6; +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief This function configures the TIM6 as a time base source. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). + * @param TickPriority: Tick interrupt priority. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + RCC_ClkInitTypeDef clkconfig; + uint32_t uwTimclock, uwAPB1Prescaler = 0U; + + uint32_t uwPrescalerValue = 0U; + uint32_t pFLatency; + + HAL_StatusTypeDef status; + + /* Enable TIM6 clock */ + __HAL_RCC_TIM6_CLK_ENABLE(); + + /* Get clock configuration */ + HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); + + /* Get APB1 prescaler */ + uwAPB1Prescaler = clkconfig.APB1CLKDivider; + /* Compute TIM6 clock */ + if (uwAPB1Prescaler == RCC_HCLK_DIV1) + { + uwTimclock = HAL_RCC_GetPCLK1Freq(); + } + else + { + uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq(); + } + + /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */ + uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); + + /* Initialize TIM6 */ + htim6.Instance = TIM6; + + /* Initialize TIMx peripheral as follow: + * Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base. + * Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + * ClockDivision = 0 + * Counter direction = Up + */ + htim6.Init.Period = (1000000U / 1000U) - 1U; + htim6.Init.Prescaler = uwPrescalerValue; + htim6.Init.ClockDivision = 0; + htim6.Init.CounterMode = TIM_COUNTERMODE_UP; + htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + + status = HAL_TIM_Base_Init(&htim6); + if (status == HAL_OK) + { + + /* Start the TIM time Base generation in interrupt mode */ + status = HAL_TIM_Base_Start_IT(&htim6); + if (status == HAL_OK) + { + /* Enable the TIM6 global Interrupt */ + HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + /* Configure the TIM IRQ priority */ + HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + status = HAL_ERROR; + } + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Suspend Tick increment. + * @note Disable the tick increment by disabling TIM6 update interrupt. + * @param None + * @retval None + */ +void HAL_SuspendTick(void) +{ + /* Disable TIM6 update Interrupt */ + __HAL_TIM_DISABLE_IT(&htim6, TIM_IT_UPDATE); +} + +/** + * @brief Resume Tick increment. + * @note Enable the tick increment by Enabling TIM6 update interrupt. + * @param None + * @retval None + */ +void HAL_ResumeTick(void) +{ + /* Enable TIM6 Update interrupt */ + __HAL_TIM_ENABLE_IT(&htim6, TIM_IT_UPDATE); +} + diff --git a/Core/Src/Backup/stm32f4xx_it.c.bak b/Core/Src/Backup/stm32f4xx_it.c.bak new file mode 100644 index 0000000..bd6ad12 --- /dev/null +++ b/Core/Src/Backup/stm32f4xx_it.c.bak @@ -0,0 +1,178 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32f4xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +extern TIM_HandleTypeDef htim6; + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M4 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32F4xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f4xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts. + */ +void TIM6_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ + + /* USER CODE END TIM6_DAC_IRQn 0 */ + HAL_TIM_IRQHandler(&htim6); + /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ + + /* USER CODE END TIM6_DAC_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Core/Src/Backup/syscalls.c.bak b/Core/Src/Backup/syscalls.c.bak new file mode 100644 index 0000000..0197f26 --- /dev/null +++ b/Core/Src/Backup/syscalls.c.bak @@ -0,0 +1,176 @@ +/** + ****************************************************************************** + * @file syscalls.c + * @author Auto-generated by STM32CubeIDE + * @brief STM32CubeIDE Minimal System calls file + * + * For more information about which c-functions + * need which of these lowlevel functions + * please consult the Newlib libc-manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Variables */ +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + + +char *__env[1] = { 0 }; +char **environ = __env; + + +/* Functions */ +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + (void)pid; + (void)sig; + errno = EINVAL; + return -1; +} + +void _exit (int status) +{ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + + return len; +} + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + __io_putchar(*ptr++); + } + return len; +} + +int _close(int file) +{ + (void)file; + return -1; +} + + +int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + (void)file; + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + (void)file; + (void)ptr; + (void)dir; + return 0; +} + +int _open(char *path, int flags, ...) +{ + (void)path; + (void)flags; + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + (void)status; + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + (void)name; + errno = ENOENT; + return -1; +} + +int _times(struct tms *buf) +{ + (void)buf; + return -1; +} + +int _stat(char *file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + (void)old; + (void)new; + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + (void)name; + (void)argv; + (void)env; + errno = ENOMEM; + return -1; +} diff --git a/Core/Src/Backup/sysmem.c.bak b/Core/Src/Backup/sysmem.c.bak new file mode 100644 index 0000000..23ea8e0 --- /dev/null +++ b/Core/Src/Backup/sysmem.c.bak @@ -0,0 +1,79 @@ +/** + ****************************************************************************** + * @file sysmem.c + * @author Generated by STM32CubeIDE + * @brief STM32CubeIDE System Memory calls file + * + * For more information about which C functions + * need which of these lowlevel functions + * please consult the newlib libc manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include + +/** + * Pointer to the current high watermark of the heap usage + */ +static uint8_t *__sbrk_heap_end = NULL; + +/** + * @brief _sbrk() allocates memory to the newlib heap and is used by malloc + * and others from the C library + * + * @verbatim + * ############################################################################ + * # .data # .bss # newlib heap # MSP stack # + * # # # # Reserved by _Min_Stack_Size # + * ############################################################################ + * ^-- RAM start ^-- _end _estack, RAM end --^ + * @endverbatim + * + * This implementation starts allocating at the '_end' linker symbol + * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack + * The implementation considers '_estack' linker symbol to be RAM end + * NOTE: If the MSP stack, at any point during execution, grows larger than the + * reserved size, please increase the '_Min_Stack_Size'. + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + const uint8_t *max_heap = (uint8_t *)stack_limit; + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + { + __sbrk_heap_end = &_end; + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + { + errno = ENOMEM; + return (void *)-1; + } + + prev_heap_end = __sbrk_heap_end; + __sbrk_heap_end += incr; + + return (void *)prev_heap_end; +} diff --git a/Core/Src/Backup/system_stm32f4xx.c.bak b/Core/Src/Backup/system_stm32f4xx.c.bak new file mode 100644 index 0000000..7a61e9c --- /dev/null +++ b/Core/Src/Backup/system_stm32f4xx.c.bak @@ -0,0 +1,747 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** @addtogroup STM32F4xx_System_Private_Includes + * @{ + */ + + +#include "stm32f4xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) +/* #define DATA_IN_ExtSRAM */ +#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ + STM32F412Zx || STM32F412Vx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/* #define DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ + STM32F479xx */ + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#if !defined(VECT_TAB_OFFSET) +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ +#endif /* USER_VECT_TAB_ADDRESS */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = 16000000; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value + * depends on the application requirements), user has to ensure that HSE_VALUE + * is same as the real frequency of the crystal used. Otherwise, this function + * may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp, pllvco, pllp, pllsource, pllm; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; + + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + FMC_Bank5_6->SDCR[0] = 0x000019E4; + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x00000073; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ + + (void)(tmp); +} +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#if defined (DATA_IN_ExtSDRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + +#if defined(STM32F446xx) + /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface + clock */ + RCC->AHB1ENR |= 0x0000007D; +#else + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001F8; +#endif /* STM32F446xx */ + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + +#if defined(STM32F446xx) + /* Connect PAx pins to FMC Alternate function */ + GPIOA->AFR[0] |= 0xC0000000; + GPIOA->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOA->MODER |= 0x00008000; + /* Configure PDx pins speed to 50 MHz */ + GPIOA->OSPEEDR |= 0x00008000; + /* Configure PDx pins Output type to push-pull */ + GPIOA->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOA->PUPDR |= 0x00000000; + + /* Connect PCx pins to FMC Alternate function */ + GPIOC->AFR[0] |= 0x00CC0000; + GPIOC->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOC->MODER |= 0x00000A00; + /* Configure PDx pins speed to 50 MHz */ + GPIOC->OSPEEDR |= 0x00000A00; + /* Configure PDx pins Output type to push-pull */ + GPIOC->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOC->PUPDR |= 0x00000000; +#endif /* STM32F446xx */ + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xA02A000A; + /* Configure PDx pins speed to 50 MHz */ + GPIOD->OSPEEDR = 0xA02A000A; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xAAAA800A; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* Configure and enable SDRAM bank1 */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCR[0] = 0x00001954; +#else + FMC_Bank5_6->SDCR[0] = 0x000019E4; +#endif /* STM32F446xx */ + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x000000F3; +#else + FMC_Bank5_6->SDCMR = 0x00000073; +#endif /* STM32F446xx */ + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x00044014; +#else + FMC_Bank5_6->SDCMR = 0x00046014; +#endif /* STM32F446xx */ + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; +#if defined(STM32F446xx) + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); +#else + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); +#endif /* STM32F446xx */ + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); +#endif /* DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) + +#if defined(DATA_IN_ExtSRAM) +/*-- GPIOs Configuration -----------------------------------------------------*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR |= 0x00000078; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x000000C0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00085AAA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000CAFFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FMC/FSMC Configuration --------------------------------------------------*/ + /* Enable the FMC/FSMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ + || defined(STM32F412Zx) || defined(STM32F412Vx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001011; + FSMC_Bank1->BTCR[3] = 0x00000201; + FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ + +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ + STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ + (void)(tmp); +} +#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/Core/Src/main.c b/Core/Src/main.c index ea120e6..3e9998a 100644 --- a/Core/Src/main.c +++ b/Core/Src/main.c @@ -44,6 +44,10 @@ CAN_HandleTypeDef hcan1; CAN_HandleTypeDef hcan2; +SD_HandleTypeDef hsd; +DMA_HandleTypeDef hdma_sdio_rx; +DMA_HandleTypeDef hdma_sdio_tx; + /* Definitions for defaultTask */ osThreadId_t defaultTaskHandle; const osThreadAttr_t defaultTask_attributes = { @@ -58,8 +62,10 @@ const osThreadAttr_t defaultTask_attributes = { /* Private function prototypes -----------------------------------------------*/ void SystemClock_Config(void); static void MX_GPIO_Init(void); +static void MX_DMA_Init(void); static void MX_CAN1_Init(void); static void MX_CAN2_Init(void); +static void MX_SDIO_SD_Init(void); void StartDefaultTask(void *argument); /* USER CODE BEGIN PFP */ @@ -100,8 +106,10 @@ int main(void) /* Initialize all configured peripherals */ MX_GPIO_Init(); + MX_DMA_Init(); MX_CAN1_Init(); MX_CAN2_Init(); + MX_SDIO_SD_Init(); /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ @@ -173,7 +181,12 @@ void SystemClock_Config(void) RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 16; + RCC_OscInitStruct.PLL.PLLN = 336; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 7; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); @@ -183,12 +196,12 @@ void SystemClock_Config(void) */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV4; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { Error_Handler(); } @@ -268,6 +281,61 @@ static void MX_CAN2_Init(void) } +/** + * @brief SDIO Initialization Function + * @param None + * @retval None + */ +static void MX_SDIO_SD_Init(void) +{ + + /* USER CODE BEGIN SDIO_Init 0 */ + + /* USER CODE END SDIO_Init 0 */ + + /* USER CODE BEGIN SDIO_Init 1 */ + + /* USER CODE END SDIO_Init 1 */ + hsd.Instance = SDIO; + hsd.Init.ClockEdge = SDIO_CLOCK_EDGE_RISING; + hsd.Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; + hsd.Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; + hsd.Init.BusWide = SDIO_BUS_WIDE_1B; + hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; + hsd.Init.ClockDiv = 0; + if (HAL_SD_Init(&hsd) != HAL_OK) + { + Error_Handler(); + } + if (HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SDIO_Init 2 */ + + /* USER CODE END SDIO_Init 2 */ + +} + +/** + * Enable DMA controller clock + */ +static void MX_DMA_Init(void) +{ + + /* DMA controller clock enable */ + __HAL_RCC_DMA2_CLK_ENABLE(); + + /* DMA interrupt init */ + /* DMA2_Stream3_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA2_Stream3_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream3_IRQn); + /* DMA2_Stream6_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA2_Stream6_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream6_IRQn); + +} + /** * @brief GPIO Initialization Function * @param None @@ -289,12 +357,10 @@ static void MX_GPIO_Init(void) /*Configure GPIO pins : PC13 PC14 PC15 PC0 PC1 PC2 PC3 PC4 - PC5 PC6 PC7 PC8 - PC9 PC10 PC11 PC12 */ + PC5 PC6 PC7 */ GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15|GPIO_PIN_0 |GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4 - |GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8 - |GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12; + |GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); @@ -327,12 +393,6 @@ static void MX_GPIO_Init(void) GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - /*Configure GPIO pin : PD2 */ - GPIO_InitStruct.Pin = GPIO_PIN_2; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ diff --git a/Core/Src/stm32f4xx_hal_msp.c b/Core/Src/stm32f4xx_hal_msp.c index f92fc8e..52cf01a 100644 --- a/Core/Src/stm32f4xx_hal_msp.c +++ b/Core/Src/stm32f4xx_hal_msp.c @@ -22,6 +22,9 @@ /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ +extern DMA_HandleTypeDef hdma_sdio_rx; + +extern DMA_HandleTypeDef hdma_sdio_tx; /* Private typedef -----------------------------------------------------------*/ /* USER CODE BEGIN TD */ @@ -201,6 +204,144 @@ void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) } +/** + * @brief SD MSP Initialization + * This function configures the hardware resources used in this example + * @param hsd: SD handle pointer + * @retval None + */ +void HAL_SD_MspInit(SD_HandleTypeDef* hsd) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hsd->Instance==SDIO) + { + /* USER CODE BEGIN SDIO_MspInit 0 */ + + /* USER CODE END SDIO_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SDIO_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**SDIO GPIO Configuration + PC8 ------> SDIO_D0 + PC9 ------> SDIO_D1 + PC10 ------> SDIO_D2 + PC11 ------> SDIO_D3 + PC12 ------> SDIO_CK + PD2 ------> SDIO_CMD + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_SDIO; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_SDIO; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* SDIO DMA Init */ + /* SDIO_RX Init */ + hdma_sdio_rx.Instance = DMA2_Stream3; + hdma_sdio_rx.Init.Channel = DMA_CHANNEL_4; + hdma_sdio_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_sdio_rx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_sdio_rx.Init.MemInc = DMA_MINC_ENABLE; + hdma_sdio_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + hdma_sdio_rx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + hdma_sdio_rx.Init.Mode = DMA_PFCTRL; + hdma_sdio_rx.Init.Priority = DMA_PRIORITY_LOW; + hdma_sdio_rx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + hdma_sdio_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + hdma_sdio_rx.Init.MemBurst = DMA_MBURST_INC4; + hdma_sdio_rx.Init.PeriphBurst = DMA_PBURST_INC4; + if (HAL_DMA_Init(&hdma_sdio_rx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(hsd,hdmarx,hdma_sdio_rx); + + /* SDIO_TX Init */ + hdma_sdio_tx.Instance = DMA2_Stream6; + hdma_sdio_tx.Init.Channel = DMA_CHANNEL_4; + hdma_sdio_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_sdio_tx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_sdio_tx.Init.MemInc = DMA_MINC_ENABLE; + hdma_sdio_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + hdma_sdio_tx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + hdma_sdio_tx.Init.Mode = DMA_PFCTRL; + hdma_sdio_tx.Init.Priority = DMA_PRIORITY_LOW; + hdma_sdio_tx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + hdma_sdio_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + hdma_sdio_tx.Init.MemBurst = DMA_MBURST_INC4; + hdma_sdio_tx.Init.PeriphBurst = DMA_PBURST_INC4; + if (HAL_DMA_Init(&hdma_sdio_tx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(hsd,hdmatx,hdma_sdio_tx); + + /* SDIO interrupt Init */ + HAL_NVIC_SetPriority(SDIO_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(SDIO_IRQn); + /* USER CODE BEGIN SDIO_MspInit 1 */ + + /* USER CODE END SDIO_MspInit 1 */ + + } + +} + +/** + * @brief SD MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param hsd: SD handle pointer + * @retval None + */ +void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) +{ + if(hsd->Instance==SDIO) + { + /* USER CODE BEGIN SDIO_MspDeInit 0 */ + + /* USER CODE END SDIO_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SDIO_CLK_DISABLE(); + + /**SDIO GPIO Configuration + PC8 ------> SDIO_D0 + PC9 ------> SDIO_D1 + PC10 ------> SDIO_D2 + PC11 ------> SDIO_D3 + PC12 ------> SDIO_CK + PD2 ------> SDIO_CMD + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); + + /* SDIO DMA DeInit */ + HAL_DMA_DeInit(hsd->hdmarx); + HAL_DMA_DeInit(hsd->hdmatx); + + /* SDIO interrupt DeInit */ + HAL_NVIC_DisableIRQ(SDIO_IRQn); + /* USER CODE BEGIN SDIO_MspDeInit 1 */ + + /* USER CODE END SDIO_MspDeInit 1 */ + } + +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/Core/Src/stm32f4xx_it.c b/Core/Src/stm32f4xx_it.c index bd6ad12..a10c042 100644 --- a/Core/Src/stm32f4xx_it.c +++ b/Core/Src/stm32f4xx_it.c @@ -55,6 +55,9 @@ /* USER CODE END 0 */ /* External variables --------------------------------------------------------*/ +extern DMA_HandleTypeDef hdma_sdio_rx; +extern DMA_HandleTypeDef hdma_sdio_tx; +extern SD_HandleTypeDef hsd; extern TIM_HandleTypeDef htim6; /* USER CODE BEGIN EV */ @@ -159,6 +162,20 @@ void DebugMon_Handler(void) /* please refer to the startup file (startup_stm32f4xx.s). */ /******************************************************************************/ +/** + * @brief This function handles SDIO global interrupt. + */ +void SDIO_IRQHandler(void) +{ + /* USER CODE BEGIN SDIO_IRQn 0 */ + + /* USER CODE END SDIO_IRQn 0 */ + HAL_SD_IRQHandler(&hsd); + /* USER CODE BEGIN SDIO_IRQn 1 */ + + /* USER CODE END SDIO_IRQn 1 */ +} + /** * @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts. */ @@ -173,6 +190,34 @@ void TIM6_DAC_IRQHandler(void) /* USER CODE END TIM6_DAC_IRQn 1 */ } +/** + * @brief This function handles DMA2 stream3 global interrupt. + */ +void DMA2_Stream3_IRQHandler(void) +{ + /* USER CODE BEGIN DMA2_Stream3_IRQn 0 */ + + /* USER CODE END DMA2_Stream3_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_sdio_rx); + /* USER CODE BEGIN DMA2_Stream3_IRQn 1 */ + + /* USER CODE END DMA2_Stream3_IRQn 1 */ +} + +/** + * @brief This function handles DMA2 stream6 global interrupt. + */ +void DMA2_Stream6_IRQHandler(void) +{ + /* USER CODE BEGIN DMA2_Stream6_IRQn 0 */ + + /* USER CODE END DMA2_Stream6_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_sdio_tx); + /* USER CODE BEGIN DMA2_Stream6_IRQn 1 */ + + /* USER CODE END DMA2_Stream6_IRQn 1 */ +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/Debug/Core/Src/freertos.cyclo b/Debug/Core/Src/freertos.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Core/Src/freertos.d b/Debug/Core/Src/freertos.d new file mode 100644 index 0000000..97bd882 --- /dev/null +++ b/Debug/Core/Src/freertos.d @@ -0,0 +1,76 @@ +Core/Src/freertos.o: ../Core/Src/freertos.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Core/Inc/main.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Core/Inc/main.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Core/Src/freertos.o b/Debug/Core/Src/freertos.o new file mode 100644 index 0000000..daabdde Binary files /dev/null and b/Debug/Core/Src/freertos.o differ diff --git a/Debug/Core/Src/freertos.su b/Debug/Core/Src/freertos.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Core/Src/main.cyclo b/Debug/Core/Src/main.cyclo new file mode 100644 index 0000000..74b58ae --- /dev/null +++ b/Debug/Core/Src/main.cyclo @@ -0,0 +1,9 @@ +../Core/Src/main.c:78:5:main 1 +../Core/Src/main.c:160:6:SystemClock_Config 3 +../Core/Src/main.c:202:13:MX_CAN1_Init 2 +../Core/Src/main.c:239:13:MX_CAN2_Init 2 +../Core/Src/main.c:276:13:MX_GPIO_Init 1 +../Core/Src/main.c:352:6:StartDefaultTask 1 +../Core/Src/main.c:371:6:HAL_TIM_PeriodElapsedCallback 2 +../Core/Src/main.c:389:6:Error_Handler 1 +../Core/Src/main.c:407:6:assert_failed 1 diff --git a/Debug/Core/Src/main.d b/Debug/Core/Src/main.d new file mode 100644 index 0000000..321b6a6 --- /dev/null +++ b/Debug/Core/Src/main.d @@ -0,0 +1,80 @@ +Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h +../Core/Inc/main.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h: diff --git a/Debug/Core/Src/main.o b/Debug/Core/Src/main.o new file mode 100644 index 0000000..28fe647 Binary files /dev/null and b/Debug/Core/Src/main.o differ diff --git a/Debug/Core/Src/main.su b/Debug/Core/Src/main.su new file mode 100644 index 0000000..2f7eac2 --- /dev/null +++ b/Debug/Core/Src/main.su @@ -0,0 +1,9 @@ +../Core/Src/main.c:78:5:main 8 static +../Core/Src/main.c:160:6:SystemClock_Config 88 static +../Core/Src/main.c:202:13:MX_CAN1_Init 8 static +../Core/Src/main.c:239:13:MX_CAN2_Init 8 static +../Core/Src/main.c:276:13:MX_GPIO_Init 48 static +../Core/Src/main.c:352:6:StartDefaultTask 16 static +../Core/Src/main.c:371:6:HAL_TIM_PeriodElapsedCallback 16 static +../Core/Src/main.c:389:6:Error_Handler 4 static,ignoring_inline_asm +../Core/Src/main.c:407:6:assert_failed 16 static diff --git a/Debug/Core/Src/stm32f4xx_hal_msp.cyclo b/Debug/Core/Src/stm32f4xx_hal_msp.cyclo new file mode 100644 index 0000000..ad85900 --- /dev/null +++ b/Debug/Core/Src/stm32f4xx_hal_msp.cyclo @@ -0,0 +1,3 @@ +../Core/Src/stm32f4xx_hal_msp.c:62:6:HAL_MspInit 1 +../Core/Src/stm32f4xx_hal_msp.c:89:6:HAL_CAN_MspInit 5 +../Core/Src/stm32f4xx_hal_msp.c:156:6:HAL_CAN_MspDeInit 5 diff --git a/Debug/Core/Src/stm32f4xx_hal_msp.d b/Debug/Core/Src/stm32f4xx_hal_msp.d new file mode 100644 index 0000000..2c0e58f --- /dev/null +++ b/Debug/Core/Src/stm32f4xx_hal_msp.d @@ -0,0 +1,58 @@ +Core/Src/stm32f4xx_hal_msp.o: ../Core/Src/stm32f4xx_hal_msp.c \ + ../Core/Inc/main.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h +../Core/Inc/main.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Core/Src/stm32f4xx_hal_msp.o b/Debug/Core/Src/stm32f4xx_hal_msp.o new file mode 100644 index 0000000..69c1500 Binary files /dev/null and b/Debug/Core/Src/stm32f4xx_hal_msp.o differ diff --git a/Debug/Core/Src/stm32f4xx_hal_msp.su b/Debug/Core/Src/stm32f4xx_hal_msp.su new file mode 100644 index 0000000..25a071a --- /dev/null +++ b/Debug/Core/Src/stm32f4xx_hal_msp.su @@ -0,0 +1,3 @@ +../Core/Src/stm32f4xx_hal_msp.c:62:6:HAL_MspInit 16 static +../Core/Src/stm32f4xx_hal_msp.c:89:6:HAL_CAN_MspInit 56 static +../Core/Src/stm32f4xx_hal_msp.c:156:6:HAL_CAN_MspDeInit 16 static diff --git a/Debug/Core/Src/stm32f4xx_hal_timebase_tim.cyclo b/Debug/Core/Src/stm32f4xx_hal_timebase_tim.cyclo new file mode 100644 index 0000000..52947fe --- /dev/null +++ b/Debug/Core/Src/stm32f4xx_hal_timebase_tim.cyclo @@ -0,0 +1,3 @@ +../Core/Src/stm32f4xx_hal_timebase_tim.c:41:19:HAL_InitTick 5 +../Core/Src/stm32f4xx_hal_timebase_tim.c:121:6:HAL_SuspendTick 1 +../Core/Src/stm32f4xx_hal_timebase_tim.c:133:6:HAL_ResumeTick 1 diff --git a/Debug/Core/Src/stm32f4xx_hal_timebase_tim.d b/Debug/Core/Src/stm32f4xx_hal_timebase_tim.d new file mode 100644 index 0000000..dbfb08e --- /dev/null +++ b/Debug/Core/Src/stm32f4xx_hal_timebase_tim.d @@ -0,0 +1,58 @@ +Core/Src/stm32f4xx_hal_timebase_tim.o: \ + ../Core/Src/stm32f4xx_hal_timebase_tim.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Core/Src/stm32f4xx_hal_timebase_tim.o b/Debug/Core/Src/stm32f4xx_hal_timebase_tim.o new file mode 100644 index 0000000..71b1cc1 Binary files /dev/null and b/Debug/Core/Src/stm32f4xx_hal_timebase_tim.o differ diff --git a/Debug/Core/Src/stm32f4xx_hal_timebase_tim.su b/Debug/Core/Src/stm32f4xx_hal_timebase_tim.su new file mode 100644 index 0000000..7700848 --- /dev/null +++ b/Debug/Core/Src/stm32f4xx_hal_timebase_tim.su @@ -0,0 +1,3 @@ +../Core/Src/stm32f4xx_hal_timebase_tim.c:41:19:HAL_InitTick 64 static +../Core/Src/stm32f4xx_hal_timebase_tim.c:121:6:HAL_SuspendTick 4 static +../Core/Src/stm32f4xx_hal_timebase_tim.c:133:6:HAL_ResumeTick 4 static diff --git a/Debug/Core/Src/stm32f4xx_it.cyclo b/Debug/Core/Src/stm32f4xx_it.cyclo new file mode 100644 index 0000000..a6ea334 --- /dev/null +++ b/Debug/Core/Src/stm32f4xx_it.cyclo @@ -0,0 +1,7 @@ +../Core/Src/stm32f4xx_it.c:70:6:NMI_Handler 1 +../Core/Src/stm32f4xx_it.c:85:6:HardFault_Handler 1 +../Core/Src/stm32f4xx_it.c:100:6:MemManage_Handler 1 +../Core/Src/stm32f4xx_it.c:115:6:BusFault_Handler 1 +../Core/Src/stm32f4xx_it.c:130:6:UsageFault_Handler 1 +../Core/Src/stm32f4xx_it.c:145:6:DebugMon_Handler 1 +../Core/Src/stm32f4xx_it.c:165:6:TIM6_DAC_IRQHandler 1 diff --git a/Debug/Core/Src/stm32f4xx_it.d b/Debug/Core/Src/stm32f4xx_it.d new file mode 100644 index 0000000..5f3a03d --- /dev/null +++ b/Debug/Core/Src/stm32f4xx_it.d @@ -0,0 +1,60 @@ +Core/Src/stm32f4xx_it.o: ../Core/Src/stm32f4xx_it.c ../Core/Inc/main.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Core/Inc/stm32f4xx_it.h +../Core/Inc/main.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Core/Inc/stm32f4xx_it.h: diff --git a/Debug/Core/Src/stm32f4xx_it.o b/Debug/Core/Src/stm32f4xx_it.o new file mode 100644 index 0000000..610a081 Binary files /dev/null and b/Debug/Core/Src/stm32f4xx_it.o differ diff --git a/Debug/Core/Src/stm32f4xx_it.su b/Debug/Core/Src/stm32f4xx_it.su new file mode 100644 index 0000000..f298b88 --- /dev/null +++ b/Debug/Core/Src/stm32f4xx_it.su @@ -0,0 +1,7 @@ +../Core/Src/stm32f4xx_it.c:70:6:NMI_Handler 4 static +../Core/Src/stm32f4xx_it.c:85:6:HardFault_Handler 4 static +../Core/Src/stm32f4xx_it.c:100:6:MemManage_Handler 4 static +../Core/Src/stm32f4xx_it.c:115:6:BusFault_Handler 4 static +../Core/Src/stm32f4xx_it.c:130:6:UsageFault_Handler 4 static +../Core/Src/stm32f4xx_it.c:145:6:DebugMon_Handler 4 static +../Core/Src/stm32f4xx_it.c:165:6:TIM6_DAC_IRQHandler 8 static diff --git a/Debug/Core/Src/subdir.mk b/Debug/Core/Src/subdir.mk new file mode 100644 index 0000000..3350efc --- /dev/null +++ b/Debug/Core/Src/subdir.mk @@ -0,0 +1,48 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (14.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Core/Src/freertos.c \ +../Core/Src/main.c \ +../Core/Src/stm32f4xx_hal_msp.c \ +../Core/Src/stm32f4xx_hal_timebase_tim.c \ +../Core/Src/stm32f4xx_it.c \ +../Core/Src/syscalls.c \ +../Core/Src/sysmem.c \ +../Core/Src/system_stm32f4xx.c + +OBJS += \ +./Core/Src/freertos.o \ +./Core/Src/main.o \ +./Core/Src/stm32f4xx_hal_msp.o \ +./Core/Src/stm32f4xx_hal_timebase_tim.o \ +./Core/Src/stm32f4xx_it.o \ +./Core/Src/syscalls.o \ +./Core/Src/sysmem.o \ +./Core/Src/system_stm32f4xx.o + +C_DEPS += \ +./Core/Src/freertos.d \ +./Core/Src/main.d \ +./Core/Src/stm32f4xx_hal_msp.d \ +./Core/Src/stm32f4xx_hal_timebase_tim.d \ +./Core/Src/stm32f4xx_it.d \ +./Core/Src/syscalls.d \ +./Core/Src/sysmem.d \ +./Core/Src/system_stm32f4xx.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/Src/%.o Core/Src/%.su Core/Src/%.cyclo: ../Core/Src/%.c Core/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F405xx -DSTM32_THREAD_SAFE_STRATEGY=4 -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../Core/ThreadSafe -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Core-2f-Src + +clean-Core-2f-Src: + -$(RM) ./Core/Src/freertos.cyclo ./Core/Src/freertos.d ./Core/Src/freertos.o ./Core/Src/freertos.su ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/stm32f4xx_hal_msp.cyclo ./Core/Src/stm32f4xx_hal_msp.d ./Core/Src/stm32f4xx_hal_msp.o ./Core/Src/stm32f4xx_hal_msp.su ./Core/Src/stm32f4xx_hal_timebase_tim.cyclo ./Core/Src/stm32f4xx_hal_timebase_tim.d ./Core/Src/stm32f4xx_hal_timebase_tim.o ./Core/Src/stm32f4xx_hal_timebase_tim.su ./Core/Src/stm32f4xx_it.cyclo ./Core/Src/stm32f4xx_it.d ./Core/Src/stm32f4xx_it.o ./Core/Src/stm32f4xx_it.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32f4xx.cyclo ./Core/Src/system_stm32f4xx.d ./Core/Src/system_stm32f4xx.o ./Core/Src/system_stm32f4xx.su + +.PHONY: clean-Core-2f-Src + diff --git a/Debug/Core/Src/syscalls.cyclo b/Debug/Core/Src/syscalls.cyclo new file mode 100644 index 0000000..6cbfdd0 --- /dev/null +++ b/Debug/Core/Src/syscalls.cyclo @@ -0,0 +1,18 @@ +../Core/Src/syscalls.c:44:6:initialise_monitor_handles 1 +../Core/Src/syscalls.c:48:5:_getpid 1 +../Core/Src/syscalls.c:53:5:_kill 1 +../Core/Src/syscalls.c:61:6:_exit 1 +../Core/Src/syscalls.c:67:27:_read 2 +../Core/Src/syscalls.c:80:27:_write 2 +../Core/Src/syscalls.c:92:5:_close 1 +../Core/Src/syscalls.c:99:5:_fstat 1 +../Core/Src/syscalls.c:106:5:_isatty 1 +../Core/Src/syscalls.c:112:5:_lseek 1 +../Core/Src/syscalls.c:120:5:_open 1 +../Core/Src/syscalls.c:128:5:_wait 1 +../Core/Src/syscalls.c:135:5:_unlink 1 +../Core/Src/syscalls.c:142:5:_times 1 +../Core/Src/syscalls.c:148:5:_stat 1 +../Core/Src/syscalls.c:155:5:_link 1 +../Core/Src/syscalls.c:163:5:_fork 1 +../Core/Src/syscalls.c:169:5:_execve 1 diff --git a/Debug/Core/Src/syscalls.d b/Debug/Core/Src/syscalls.d new file mode 100644 index 0000000..8667c70 --- /dev/null +++ b/Debug/Core/Src/syscalls.d @@ -0,0 +1 @@ +Core/Src/syscalls.o: ../Core/Src/syscalls.c diff --git a/Debug/Core/Src/syscalls.o b/Debug/Core/Src/syscalls.o new file mode 100644 index 0000000..aff9b28 Binary files /dev/null and b/Debug/Core/Src/syscalls.o differ diff --git a/Debug/Core/Src/syscalls.su b/Debug/Core/Src/syscalls.su new file mode 100644 index 0000000..50b547a --- /dev/null +++ b/Debug/Core/Src/syscalls.su @@ -0,0 +1,18 @@ +../Core/Src/syscalls.c:44:6:initialise_monitor_handles 4 static +../Core/Src/syscalls.c:48:5:_getpid 4 static +../Core/Src/syscalls.c:53:5:_kill 16 static +../Core/Src/syscalls.c:61:6:_exit 16 static +../Core/Src/syscalls.c:67:27:_read 32 static +../Core/Src/syscalls.c:80:27:_write 32 static +../Core/Src/syscalls.c:92:5:_close 16 static +../Core/Src/syscalls.c:99:5:_fstat 16 static +../Core/Src/syscalls.c:106:5:_isatty 16 static +../Core/Src/syscalls.c:112:5:_lseek 24 static +../Core/Src/syscalls.c:120:5:_open 12 static +../Core/Src/syscalls.c:128:5:_wait 16 static +../Core/Src/syscalls.c:135:5:_unlink 16 static +../Core/Src/syscalls.c:142:5:_times 16 static +../Core/Src/syscalls.c:148:5:_stat 16 static +../Core/Src/syscalls.c:155:5:_link 16 static +../Core/Src/syscalls.c:163:5:_fork 8 static +../Core/Src/syscalls.c:169:5:_execve 24 static diff --git a/Debug/Core/Src/sysmem.cyclo b/Debug/Core/Src/sysmem.cyclo new file mode 100644 index 0000000..0090c10 --- /dev/null +++ b/Debug/Core/Src/sysmem.cyclo @@ -0,0 +1 @@ +../Core/Src/sysmem.c:53:7:_sbrk 3 diff --git a/Debug/Core/Src/sysmem.d b/Debug/Core/Src/sysmem.d new file mode 100644 index 0000000..74fecf9 --- /dev/null +++ b/Debug/Core/Src/sysmem.d @@ -0,0 +1 @@ +Core/Src/sysmem.o: ../Core/Src/sysmem.c diff --git a/Debug/Core/Src/sysmem.o b/Debug/Core/Src/sysmem.o new file mode 100644 index 0000000..914e537 Binary files /dev/null and b/Debug/Core/Src/sysmem.o differ diff --git a/Debug/Core/Src/sysmem.su b/Debug/Core/Src/sysmem.su new file mode 100644 index 0000000..12d5f17 --- /dev/null +++ b/Debug/Core/Src/sysmem.su @@ -0,0 +1 @@ +../Core/Src/sysmem.c:53:7:_sbrk 32 static diff --git a/Debug/Core/Src/system_stm32f4xx.cyclo b/Debug/Core/Src/system_stm32f4xx.cyclo new file mode 100644 index 0000000..4cc0df9 --- /dev/null +++ b/Debug/Core/Src/system_stm32f4xx.cyclo @@ -0,0 +1,2 @@ +../Core/Src/system_stm32f4xx.c:167:6:SystemInit 1 +../Core/Src/system_stm32f4xx.c:220:6:SystemCoreClockUpdate 6 diff --git a/Debug/Core/Src/system_stm32f4xx.d b/Debug/Core/Src/system_stm32f4xx.d new file mode 100644 index 0000000..60d6202 --- /dev/null +++ b/Debug/Core/Src/system_stm32f4xx.d @@ -0,0 +1,57 @@ +Core/Src/system_stm32f4xx.o: ../Core/Src/system_stm32f4xx.c \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Core/Src/system_stm32f4xx.o b/Debug/Core/Src/system_stm32f4xx.o new file mode 100644 index 0000000..3404dfa Binary files /dev/null and b/Debug/Core/Src/system_stm32f4xx.o differ diff --git a/Debug/Core/Src/system_stm32f4xx.su b/Debug/Core/Src/system_stm32f4xx.su new file mode 100644 index 0000000..96f1cd4 --- /dev/null +++ b/Debug/Core/Src/system_stm32f4xx.su @@ -0,0 +1,2 @@ +../Core/Src/system_stm32f4xx.c:167:6:SystemInit 4 static +../Core/Src/system_stm32f4xx.c:220:6:SystemCoreClockUpdate 32 static diff --git a/Debug/Core/Startup/startup_stm32f405rgtx.d b/Debug/Core/Startup/startup_stm32f405rgtx.d new file mode 100644 index 0000000..625ffc5 --- /dev/null +++ b/Debug/Core/Startup/startup_stm32f405rgtx.d @@ -0,0 +1,2 @@ +Core/Startup/startup_stm32f405rgtx.o: \ + ../Core/Startup/startup_stm32f405rgtx.s diff --git a/Debug/Core/Startup/startup_stm32f405rgtx.o b/Debug/Core/Startup/startup_stm32f405rgtx.o new file mode 100644 index 0000000..6897669 Binary files /dev/null and b/Debug/Core/Startup/startup_stm32f405rgtx.o differ diff --git a/Debug/Core/Startup/subdir.mk b/Debug/Core/Startup/subdir.mk new file mode 100644 index 0000000..162cb38 --- /dev/null +++ b/Debug/Core/Startup/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (14.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Core/Startup/startup_stm32f405rgtx.s + +OBJS += \ +./Core/Startup/startup_stm32f405rgtx.o + +S_DEPS += \ +./Core/Startup/startup_stm32f405rgtx.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/Startup/%.o: ../Core/Startup/%.s Core/Startup/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" "$<" + +clean: clean-Core-2f-Startup + +clean-Core-2f-Startup: + -$(RM) ./Core/Startup/startup_stm32f405rgtx.d ./Core/Startup/startup_stm32f405rgtx.o + +.PHONY: clean-Core-2f-Startup + diff --git a/Debug/Core/ThreadSafe/newlib_lock_glue.cyclo b/Debug/Core/ThreadSafe/newlib_lock_glue.cyclo new file mode 100644 index 0000000..d0380d7 --- /dev/null +++ b/Debug/Core/ThreadSafe/newlib_lock_glue.cyclo @@ -0,0 +1,17 @@ +../Core/ThreadSafe/newlib_lock_glue.c:46:13:Error_Handler 1 +../Core/ThreadSafe/stm32_lock.h:279:20:stm32_lock_init 3 +../Core/ThreadSafe/stm32_lock.h:293:20:stm32_lock_acquire 3 +../Core/ThreadSafe/stm32_lock.h:304:20:stm32_lock_release 3 +/Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/arm-none-eabi/include/sys/lock.h:41:13:__retarget_lock_init 1 +/Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/arm-none-eabi/include/sys/lock.h:43:13:__retarget_lock_init_recursive 3 +/Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/arm-none-eabi/include/sys/lock.h:45:13:__retarget_lock_close 1 +/Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/arm-none-eabi/include/sys/lock.h:47:13:__retarget_lock_close_recursive 1 +/Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/arm-none-eabi/include/sys/lock.h:49:13:__retarget_lock_acquire 2 +/Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/arm-none-eabi/include/sys/lock.h:51:13:__retarget_lock_acquire_recursive 2 +/Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/arm-none-eabi/include/sys/lock.h:53:12:__retarget_lock_try_acquire 1 +/Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/arm-none-eabi/include/sys/lock.h:55:12:__retarget_lock_try_acquire_recursive 1 +/Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/arm-none-eabi/include/sys/lock.h:58:13:__retarget_lock_release 2 +/Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/arm-none-eabi/include/sys/lock.h:60:13:__retarget_lock_release_recursive 2 +../Core/ThreadSafe/newlib_lock_glue.c:363:5:__cxa_guard_acquire 5 +../Core/ThreadSafe/newlib_lock_glue.c:399:6:__cxa_guard_abort 3 +../Core/ThreadSafe/newlib_lock_glue.c:420:6:__cxa_guard_release 2 diff --git a/Debug/Core/ThreadSafe/newlib_lock_glue.d b/Debug/Core/ThreadSafe/newlib_lock_glue.d new file mode 100644 index 0000000..f3d7fe2 --- /dev/null +++ b/Debug/Core/ThreadSafe/newlib_lock_glue.d @@ -0,0 +1,24 @@ +Core/ThreadSafe/newlib_lock_glue.o: ../Core/ThreadSafe/newlib_lock_glue.c \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h ../Core/ThreadSafe/stm32_lock.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Core/ThreadSafe/stm32_lock.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: diff --git a/Debug/Core/ThreadSafe/newlib_lock_glue.o b/Debug/Core/ThreadSafe/newlib_lock_glue.o new file mode 100644 index 0000000..1df886d Binary files /dev/null and b/Debug/Core/ThreadSafe/newlib_lock_glue.o differ diff --git a/Debug/Core/ThreadSafe/newlib_lock_glue.su b/Debug/Core/ThreadSafe/newlib_lock_glue.su new file mode 100644 index 0000000..aca200e --- /dev/null +++ b/Debug/Core/ThreadSafe/newlib_lock_glue.su @@ -0,0 +1,17 @@ +../Core/ThreadSafe/newlib_lock_glue.c:46:13:Error_Handler 4 static +../Core/ThreadSafe/stm32_lock.h:279:20:stm32_lock_init 24 static,ignoring_inline_asm +../Core/ThreadSafe/stm32_lock.h:293:20:stm32_lock_acquire 24 static,ignoring_inline_asm +../Core/ThreadSafe/stm32_lock.h:304:20:stm32_lock_release 24 static,ignoring_inline_asm +/Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/arm-none-eabi/include/sys/lock.h:41:13:__retarget_lock_init 16 static +/Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/arm-none-eabi/include/sys/lock.h:43:13:__retarget_lock_init_recursive 16 static,ignoring_inline_asm +/Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/arm-none-eabi/include/sys/lock.h:45:13:__retarget_lock_close 16 static +/Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/arm-none-eabi/include/sys/lock.h:47:13:__retarget_lock_close_recursive 16 static +/Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/arm-none-eabi/include/sys/lock.h:49:13:__retarget_lock_acquire 16 static,ignoring_inline_asm +/Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/arm-none-eabi/include/sys/lock.h:51:13:__retarget_lock_acquire_recursive 16 static,ignoring_inline_asm +/Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/arm-none-eabi/include/sys/lock.h:53:12:__retarget_lock_try_acquire 16 static +/Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/arm-none-eabi/include/sys/lock.h:55:12:__retarget_lock_try_acquire_recursive 16 static +/Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/arm-none-eabi/include/sys/lock.h:58:13:__retarget_lock_release 16 static,ignoring_inline_asm +/Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/arm-none-eabi/include/sys/lock.h:60:13:__retarget_lock_release_recursive 16 static,ignoring_inline_asm +../Core/ThreadSafe/newlib_lock_glue.c:363:5:__cxa_guard_acquire 32 static,ignoring_inline_asm +../Core/ThreadSafe/newlib_lock_glue.c:399:6:__cxa_guard_abort 16 static,ignoring_inline_asm +../Core/ThreadSafe/newlib_lock_glue.c:420:6:__cxa_guard_release 24 static,ignoring_inline_asm diff --git a/Debug/Core/ThreadSafe/subdir.mk b/Debug/Core/ThreadSafe/subdir.mk new file mode 100644 index 0000000..afb761c --- /dev/null +++ b/Debug/Core/ThreadSafe/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (14.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Core/ThreadSafe/newlib_lock_glue.c + +OBJS += \ +./Core/ThreadSafe/newlib_lock_glue.o + +C_DEPS += \ +./Core/ThreadSafe/newlib_lock_glue.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/ThreadSafe/%.o Core/ThreadSafe/%.su Core/ThreadSafe/%.cyclo: ../Core/ThreadSafe/%.c Core/ThreadSafe/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F405xx -DSTM32_THREAD_SAFE_STRATEGY=4 -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../Core/ThreadSafe -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Core-2f-ThreadSafe + +clean-Core-2f-ThreadSafe: + -$(RM) ./Core/ThreadSafe/newlib_lock_glue.cyclo ./Core/ThreadSafe/newlib_lock_glue.d ./Core/ThreadSafe/newlib_lock_glue.o ./Core/ThreadSafe/newlib_lock_glue.su + +.PHONY: clean-Core-2f-ThreadSafe + diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.cyclo b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.cyclo new file mode 100644 index 0000000..c8c31fa --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.cyclo @@ -0,0 +1,27 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:157:19:HAL_Init 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:190:19:HAL_DeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:219:13:HAL_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:230:13:HAL_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:253:26:HAL_InitTick 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:312:13:HAL_IncTick 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:323:17:HAL_GetTick 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:332:10:HAL_GetTickPrio 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:341:19:HAL_SetTickFreq 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:374:21:HAL_GetTickFreq 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:390:13:HAL_Delay 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:416:13:HAL_SuspendTick 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:432:13:HAL_ResumeTick 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:442:10:HAL_GetHalVersion 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:451:10:HAL_GetREVID 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:460:10:HAL_GetDEVID 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:469:6:HAL_DBGMCU_EnableDBGSleepMode 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:478:6:HAL_DBGMCU_DisableDBGSleepMode 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:487:6:HAL_DBGMCU_EnableDBGStopMode 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:496:6:HAL_DBGMCU_DisableDBGStopMode 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:505:6:HAL_DBGMCU_EnableDBGStandbyMode 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:514:6:HAL_DBGMCU_DisableDBGStandbyMode 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:525:6:HAL_EnableCompensationCell 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:536:6:HAL_DisableCompensationCell 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:545:10:HAL_GetUIDw0 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:554:10:HAL_GetUIDw1 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:563:10:HAL_GetUIDw2 1 diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d new file mode 100644 index 0000000..223de20 --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d @@ -0,0 +1,58 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o new file mode 100644 index 0000000..f57e6f6 Binary files /dev/null and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su new file mode 100644 index 0000000..fb2a723 --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su @@ -0,0 +1,27 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:157:19:HAL_Init 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:190:19:HAL_DeInit 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:219:13:HAL_MspInit 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:230:13:HAL_MspDeInit 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:253:26:HAL_InitTick 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:312:13:HAL_IncTick 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:323:17:HAL_GetTick 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:332:10:HAL_GetTickPrio 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:341:19:HAL_SetTickFreq 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:374:21:HAL_GetTickFreq 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:390:13:HAL_Delay 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:416:13:HAL_SuspendTick 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:432:13:HAL_ResumeTick 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:442:10:HAL_GetHalVersion 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:451:10:HAL_GetREVID 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:460:10:HAL_GetDEVID 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:469:6:HAL_DBGMCU_EnableDBGSleepMode 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:478:6:HAL_DBGMCU_DisableDBGSleepMode 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:487:6:HAL_DBGMCU_EnableDBGStopMode 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:496:6:HAL_DBGMCU_DisableDBGStopMode 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:505:6:HAL_DBGMCU_EnableDBGStandbyMode 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:514:6:HAL_DBGMCU_DisableDBGStandbyMode 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:525:6:HAL_EnableCompensationCell 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:536:6:HAL_DisableCompensationCell 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:545:10:HAL_GetUIDw0 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:554:10:HAL_GetUIDw1 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:563:10:HAL_GetUIDw2 4 static diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.cyclo b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.cyclo new file mode 100644 index 0000000..f86fc0a --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.cyclo @@ -0,0 +1,38 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:275:19:HAL_CAN_Init 62 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:460:19:HAL_CAN_DeInit 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:507:13:HAL_CAN_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:523:13:HAL_CAN_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:559:19:HAL_CAN_RegisterCallback 21 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:702:19:HAL_CAN_UnRegisterCallback 20 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:840:19:HAL_CAN_ConfigFilter 22 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1036:19:HAL_CAN_Start 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1088:19:HAL_CAN_Stop 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1143:19:HAL_CAN_RequestSleep 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1174:19:HAL_CAN_WakeUp 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1221:10:HAL_CAN_IsSleepActive 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1252:19:HAL_CAN_AddTxMessage 18 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1352:19:HAL_CAN_AbortTxRequest 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1401:10:HAL_CAN_GetTxMailboxesFreeLevel 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1444:10:HAL_CAN_IsTxMessagePending 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1476:10:HAL_CAN_GetTxTimestamp 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1510:19:HAL_CAN_GetRxMessage 11 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1610:10:HAL_CAN_GetRxFifoFillLevel 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1663:19:HAL_CAN_ActivateNotification 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1696:19:HAL_CAN_DeactivateNotification 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1727:6:HAL_CAN_IRQHandler 51 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2138:13:HAL_CAN_TxMailbox0CompleteCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2155:13:HAL_CAN_TxMailbox1CompleteCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2172:13:HAL_CAN_TxMailbox2CompleteCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2189:13:HAL_CAN_TxMailbox0AbortCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2206:13:HAL_CAN_TxMailbox1AbortCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2223:13:HAL_CAN_TxMailbox2AbortCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2240:13:HAL_CAN_RxFifo0MsgPendingCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2257:13:HAL_CAN_RxFifo0FullCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2274:13:HAL_CAN_RxFifo1MsgPendingCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2291:13:HAL_CAN_RxFifo1FullCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2308:13:HAL_CAN_SleepCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2324:13:HAL_CAN_WakeUpFromRxMsgCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2341:13:HAL_CAN_ErrorCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2378:22:HAL_CAN_GetState 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2413:10:HAL_CAN_GetError 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2425:19:HAL_CAN_ResetError 3 diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.d new file mode 100644 index 0000000..314697e --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.d @@ -0,0 +1,58 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o new file mode 100644 index 0000000..9deb965 Binary files /dev/null and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.su b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.su new file mode 100644 index 0000000..9d84eef --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.su @@ -0,0 +1,38 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:275:19:HAL_CAN_Init 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:460:19:HAL_CAN_DeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:507:13:HAL_CAN_MspInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:523:13:HAL_CAN_MspDeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:559:19:HAL_CAN_RegisterCallback 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:702:19:HAL_CAN_UnRegisterCallback 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:840:19:HAL_CAN_ConfigFilter 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1036:19:HAL_CAN_Start 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1088:19:HAL_CAN_Stop 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1143:19:HAL_CAN_RequestSleep 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1174:19:HAL_CAN_WakeUp 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1221:10:HAL_CAN_IsSleepActive 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1252:19:HAL_CAN_AddTxMessage 40 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1352:19:HAL_CAN_AbortTxRequest 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1401:10:HAL_CAN_GetTxMailboxesFreeLevel 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1444:10:HAL_CAN_IsTxMessagePending 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1476:10:HAL_CAN_GetTxTimestamp 40 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1510:19:HAL_CAN_GetRxMessage 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1610:10:HAL_CAN_GetRxFifoFillLevel 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1663:19:HAL_CAN_ActivateNotification 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1696:19:HAL_CAN_DeactivateNotification 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:1727:6:HAL_CAN_IRQHandler 48 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2138:13:HAL_CAN_TxMailbox0CompleteCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2155:13:HAL_CAN_TxMailbox1CompleteCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2172:13:HAL_CAN_TxMailbox2CompleteCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2189:13:HAL_CAN_TxMailbox0AbortCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2206:13:HAL_CAN_TxMailbox1AbortCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2223:13:HAL_CAN_TxMailbox2AbortCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2240:13:HAL_CAN_RxFifo0MsgPendingCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2257:13:HAL_CAN_RxFifo0FullCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2274:13:HAL_CAN_RxFifo1MsgPendingCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2291:13:HAL_CAN_RxFifo1FullCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2308:13:HAL_CAN_SleepCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2324:13:HAL_CAN_WakeUpFromRxMsgCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2341:13:HAL_CAN_ErrorCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2378:22:HAL_CAN_GetState 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2413:10:HAL_CAN_GetError 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c:2425:19:HAL_CAN_ResetError 24 static diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.cyclo b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.cyclo new file mode 100644 index 0000000..feff917 --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.cyclo @@ -0,0 +1,35 @@ +../Drivers/CMSIS/Include/core_cm4.h:1653:22:__NVIC_SetPriorityGrouping 1 +../Drivers/CMSIS/Include/core_cm4.h:1672:26:__NVIC_GetPriorityGrouping 1 +../Drivers/CMSIS/Include/core_cm4.h:1684:22:__NVIC_EnableIRQ 2 +../Drivers/CMSIS/Include/core_cm4.h:1722:22:__NVIC_DisableIRQ 2 +../Drivers/CMSIS/Include/core_cm4.h:1741:26:__NVIC_GetPendingIRQ 2 +../Drivers/CMSIS/Include/core_cm4.h:1760:22:__NVIC_SetPendingIRQ 2 +../Drivers/CMSIS/Include/core_cm4.h:1775:22:__NVIC_ClearPendingIRQ 2 +../Drivers/CMSIS/Include/core_cm4.h:1792:26:__NVIC_GetActive 2 +../Drivers/CMSIS/Include/core_cm4.h:1814:22:__NVIC_SetPriority 2 +../Drivers/CMSIS/Include/core_cm4.h:1836:26:__NVIC_GetPriority 2 +../Drivers/CMSIS/Include/core_cm4.h:1861:26:NVIC_EncodePriority 2 +../Drivers/CMSIS/Include/core_cm4.h:1888:22:NVIC_DecodePriority 2 +../Drivers/CMSIS/Include/core_cm4.h:1938:34:__NVIC_SystemReset 1 +../Drivers/CMSIS/Include/core_cm4.h:2022:26:SysTick_Config 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:141:6:HAL_NVIC_SetPriorityGrouping 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:163:6:HAL_NVIC_SetPriority 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:185:6:HAL_NVIC_EnableIRQ 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:201:6:HAL_NVIC_DisableIRQ 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:214:6:HAL_NVIC_SystemReset 0 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:227:10:HAL_SYSTICK_Config 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:256:6:HAL_MPU_Disable 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:279:6:HAL_MPU_Enable 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:296:6:HAL_MPU_EnableRegion 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:312:6:HAL_MPU_DisableRegion 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:330:6:HAL_MPU_ConfigRegion 57 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:368:6:HAL_CORTEX_ClearEvent 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:378:10:HAL_NVIC_GetPriorityGrouping 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:405:6:HAL_NVIC_GetPriority 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:420:6:HAL_NVIC_SetPendingIRQ 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:438:10:HAL_NVIC_GetPendingIRQ 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:454:6:HAL_NVIC_ClearPendingIRQ 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:471:10:HAL_NVIC_GetActive 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:488:6:HAL_SYSTICK_CLKSourceConfig 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:506:6:HAL_SYSTICK_IRQHandler 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:515:13:HAL_SYSTICK_Callback 1 diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d new file mode 100644 index 0000000..995dc2b --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d @@ -0,0 +1,58 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o new file mode 100644 index 0000000..5649acd Binary files /dev/null and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su new file mode 100644 index 0000000..985c480 --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su @@ -0,0 +1,35 @@ +../Drivers/CMSIS/Include/core_cm4.h:1653:22:__NVIC_SetPriorityGrouping 24 static +../Drivers/CMSIS/Include/core_cm4.h:1672:26:__NVIC_GetPriorityGrouping 4 static +../Drivers/CMSIS/Include/core_cm4.h:1684:22:__NVIC_EnableIRQ 16 static,ignoring_inline_asm +../Drivers/CMSIS/Include/core_cm4.h:1722:22:__NVIC_DisableIRQ 16 static,ignoring_inline_asm +../Drivers/CMSIS/Include/core_cm4.h:1741:26:__NVIC_GetPendingIRQ 16 static +../Drivers/CMSIS/Include/core_cm4.h:1760:22:__NVIC_SetPendingIRQ 16 static +../Drivers/CMSIS/Include/core_cm4.h:1775:22:__NVIC_ClearPendingIRQ 16 static +../Drivers/CMSIS/Include/core_cm4.h:1792:26:__NVIC_GetActive 16 static +../Drivers/CMSIS/Include/core_cm4.h:1814:22:__NVIC_SetPriority 16 static +../Drivers/CMSIS/Include/core_cm4.h:1836:26:__NVIC_GetPriority 16 static +../Drivers/CMSIS/Include/core_cm4.h:1861:26:NVIC_EncodePriority 40 static +../Drivers/CMSIS/Include/core_cm4.h:1888:22:NVIC_DecodePriority 40 static +../Drivers/CMSIS/Include/core_cm4.h:1938:34:__NVIC_SystemReset 4 static,ignoring_inline_asm +../Drivers/CMSIS/Include/core_cm4.h:2022:26:SysTick_Config 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:141:6:HAL_NVIC_SetPriorityGrouping 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:163:6:HAL_NVIC_SetPriority 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:185:6:HAL_NVIC_EnableIRQ 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:201:6:HAL_NVIC_DisableIRQ 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:214:6:HAL_NVIC_SystemReset 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:227:10:HAL_SYSTICK_Config 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:256:6:HAL_MPU_Disable 4 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:279:6:HAL_MPU_Enable 16 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:296:6:HAL_MPU_EnableRegion 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:312:6:HAL_MPU_DisableRegion 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:330:6:HAL_MPU_ConfigRegion 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:368:6:HAL_CORTEX_ClearEvent 4 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:378:10:HAL_NVIC_GetPriorityGrouping 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:405:6:HAL_NVIC_GetPriority 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:420:6:HAL_NVIC_SetPendingIRQ 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:438:10:HAL_NVIC_GetPendingIRQ 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:454:6:HAL_NVIC_ClearPendingIRQ 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:471:10:HAL_NVIC_GetActive 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:488:6:HAL_SYSTICK_CLKSourceConfig 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:506:6:HAL_SYSTICK_IRQHandler 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:515:13:HAL_SYSTICK_Callback 4 static diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.cyclo b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.cyclo new file mode 100644 index 0000000..5702c2b --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.cyclo @@ -0,0 +1,15 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:170:19:HAL_DMA_Init 67 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:309:19:HAL_DMA_DeInit 19 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:407:19:HAL_DMA_Start 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:451:19:HAL_DMA_Start_IT 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:513:19:HAL_DMA_Abort 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:580:19:HAL_DMA_Abort_IT 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:610:19:HAL_DMA_PollForTransfer 15 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:746:6:HAL_DMA_IRQHandler 32 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:967:19:HAL_DMA_RegisterCallback 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1029:19:HAL_DMA_UnRegisterCallback 10 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1114:22:HAL_DMA_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1125:10:HAL_DMA_GetError 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1151:13:DMA_SetConfig 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1185:17:DMA_CalcBaseAndBitshift 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1213:26:DMA_CheckFifoParam 15 diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d new file mode 100644 index 0000000..a0798bf --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d @@ -0,0 +1,58 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o new file mode 100644 index 0000000..9a691b7 Binary files /dev/null and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su new file mode 100644 index 0000000..6c24b90 --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su @@ -0,0 +1,15 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:170:19:HAL_DMA_Init 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:309:19:HAL_DMA_DeInit 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:407:19:HAL_DMA_Start 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:451:19:HAL_DMA_Start_IT 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:513:19:HAL_DMA_Abort 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:580:19:HAL_DMA_Abort_IT 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:610:19:HAL_DMA_PollForTransfer 48 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:746:6:HAL_DMA_IRQHandler 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:967:19:HAL_DMA_RegisterCallback 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1029:19:HAL_DMA_UnRegisterCallback 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1114:22:HAL_DMA_GetState 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1125:10:HAL_DMA_GetError 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1151:13:DMA_SetConfig 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1185:17:DMA_CalcBaseAndBitshift 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1213:26:DMA_CheckFifoParam 24 static diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.cyclo b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.cyclo new file mode 100644 index 0000000..30598fb --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.cyclo @@ -0,0 +1,4 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:100:19:HAL_DMAEx_MultiBufferStart 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:154:19:HAL_DMAEx_MultiBufferStart_IT 266 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:239:19:HAL_DMAEx_ChangeMemory 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:276:13:DMA_MultiBufferSetConfig 2 diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d new file mode 100644 index 0000000..fe978db --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d @@ -0,0 +1,58 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o new file mode 100644 index 0000000..1ebeaba Binary files /dev/null and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su new file mode 100644 index 0000000..9b2268b --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su @@ -0,0 +1,4 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:100:19:HAL_DMAEx_MultiBufferStart 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:154:19:HAL_DMAEx_MultiBufferStart_IT 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:239:19:HAL_DMAEx_ChangeMemory 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:276:13:DMA_MultiBufferSetConfig 24 static diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.cyclo b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.cyclo new file mode 100644 index 0000000..e01c097 --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.cyclo @@ -0,0 +1,9 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:142:19:HAL_EXTI_SetConfigLine 26 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:237:19:HAL_EXTI_GetConfigLine 14 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:316:19:HAL_EXTI_ClearConfigLine 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:369:19:HAL_EXTI_RegisterCallback 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:394:19:HAL_EXTI_GetHandle 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:434:6:HAL_EXTI_IRQHandler 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:466:10:HAL_EXTI_GetPending 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:498:6:HAL_EXTI_ClearPending 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:522:6:HAL_EXTI_GenerateSWI 6 diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d new file mode 100644 index 0000000..dcdf540 --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d @@ -0,0 +1,58 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o new file mode 100644 index 0000000..394656a Binary files /dev/null and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su new file mode 100644 index 0000000..8a14ca5 --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su @@ -0,0 +1,9 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:142:19:HAL_EXTI_SetConfigLine 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:237:19:HAL_EXTI_GetConfigLine 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:316:19:HAL_EXTI_ClearConfigLine 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:369:19:HAL_EXTI_RegisterCallback 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:394:19:HAL_EXTI_GetHandle 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:434:6:HAL_EXTI_IRQHandler 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:466:10:HAL_EXTI_GetPending 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:498:6:HAL_EXTI_ClearPending 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:522:6:HAL_EXTI_GenerateSWI 24 static diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.cyclo b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.cyclo new file mode 100644 index 0000000..a3dc5eb --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.cyclo @@ -0,0 +1,17 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:161:19:HAL_FLASH_Program 10 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:219:19:HAL_FLASH_Program_IT 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:263:6:HAL_FLASH_IRQHandler 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:383:13:HAL_FLASH_EndOfOperationCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:400:13:HAL_FLASH_OperationErrorCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:432:19:HAL_FLASH_Unlock 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:456:19:HAL_FLASH_Lock 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:468:19:HAL_FLASH_OB_Unlock 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:488:19:HAL_FLASH_OB_Lock 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:500:19:HAL_FLASH_OB_Launch 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:537:10:HAL_FLASH_GetError 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:551:19:FLASH_WaitForLastOperation 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:611:13:FLASH_Program_DoubleWord 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:645:13:FLASH_Program_Word 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:670:13:FLASH_Program_HalfWord 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:695:13:FLASH_Program_Byte 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:712:13:FLASH_SetErrorCode 6 diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d new file mode 100644 index 0000000..58f33bb --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d @@ -0,0 +1,58 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o new file mode 100644 index 0000000..5105b1e Binary files /dev/null and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su new file mode 100644 index 0000000..3f33f48 --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su @@ -0,0 +1,17 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:161:19:HAL_FLASH_Program 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:219:19:HAL_FLASH_Program_IT 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:263:6:HAL_FLASH_IRQHandler 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:383:13:HAL_FLASH_EndOfOperationCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:400:13:HAL_FLASH_OperationErrorCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:432:19:HAL_FLASH_Unlock 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:456:19:HAL_FLASH_Lock 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:468:19:HAL_FLASH_OB_Unlock 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:488:19:HAL_FLASH_OB_Lock 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:500:19:HAL_FLASH_OB_Launch 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:537:10:HAL_FLASH_GetError 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:551:19:FLASH_WaitForLastOperation 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:611:13:FLASH_Program_DoubleWord 24 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:645:13:FLASH_Program_Word 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:670:13:FLASH_Program_HalfWord 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:695:13:FLASH_Program_Byte 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:712:13:FLASH_SetErrorCode 4 static diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.cyclo b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.cyclo new file mode 100644 index 0000000..6a62ffd --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.cyclo @@ -0,0 +1,16 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:160:19:HAL_FLASHEx_Erase 10 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:231:19:HAL_FLASHEx_Erase_IT 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:281:19:HAL_FLASHEx_OBProgram 10 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:340:6:HAL_FLASHEx_OBGetConfig 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:948:13:FLASH_MassErase 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:977:6:FLASH_Erase_Sector 20 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1027:26:FLASH_OB_EnableWRP 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1063:26:FLASH_OB_DisableWRP 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1157:26:FLASH_OB_RDP_LevelConfig 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1191:26:FLASH_OB_UserConfig 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1226:26:FLASH_OB_BOR_LevelConfig 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1244:16:FLASH_OB_GetUser 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1254:17:FLASH_OB_GetWRP 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1268:16:FLASH_OB_GetRDP 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1296:16:FLASH_OB_GetBOR 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1306:6:FLASH_FlushCaches 3 diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d new file mode 100644 index 0000000..f3bf77e --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d @@ -0,0 +1,58 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o new file mode 100644 index 0000000..1790c16 Binary files /dev/null and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su new file mode 100644 index 0000000..629e80d --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su @@ -0,0 +1,16 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:160:19:HAL_FLASHEx_Erase 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:231:19:HAL_FLASHEx_Erase_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:281:19:HAL_FLASHEx_OBProgram 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:340:6:HAL_FLASHEx_OBGetConfig 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:948:13:FLASH_MassErase 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:977:6:FLASH_Erase_Sector 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1027:26:FLASH_OB_EnableWRP 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1063:26:FLASH_OB_DisableWRP 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1157:26:FLASH_OB_RDP_LevelConfig 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1191:26:FLASH_OB_UserConfig 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1226:26:FLASH_OB_BOR_LevelConfig 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1244:16:FLASH_OB_GetUser 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1254:17:FLASH_OB_GetWRP 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1268:16:FLASH_OB_GetRDP 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1296:16:FLASH_OB_GetBOR 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1306:6:FLASH_FlushCaches 4 static diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.cyclo b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d new file mode 100644 index 0000000..c405e10 --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d @@ -0,0 +1,58 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o new file mode 100644 index 0000000..f1ff828 Binary files /dev/null and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.su b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.cyclo b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.cyclo new file mode 100644 index 0000000..36bcf18 --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.cyclo @@ -0,0 +1,8 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:164:6:HAL_GPIO_Init 84 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:294:6:HAL_GPIO_DeInit 21 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:375:15:HAL_GPIO_ReadPin 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:410:6:HAL_GPIO_WritePin 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:433:6:HAL_GPIO_TogglePin 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:458:19:HAL_GPIO_LockPin 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:492:6:HAL_GPIO_EXTI_IRQHandler 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:507:13:HAL_GPIO_EXTI_Callback 1 diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d new file mode 100644 index 0000000..9281fb5 --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d @@ -0,0 +1,58 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o new file mode 100644 index 0000000..7dd2aee Binary files /dev/null and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su new file mode 100644 index 0000000..2ae1321 --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su @@ -0,0 +1,8 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:164:6:HAL_GPIO_Init 40 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:294:6:HAL_GPIO_DeInit 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:375:15:HAL_GPIO_ReadPin 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:410:6:HAL_GPIO_WritePin 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:433:6:HAL_GPIO_TogglePin 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:458:19:HAL_GPIO_LockPin 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:492:6:HAL_GPIO_EXTI_IRQHandler 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:507:13:HAL_GPIO_EXTI_Callback 16 static diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.cyclo b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.cyclo new file mode 100644 index 0000000..40f5c55 --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.cyclo @@ -0,0 +1,17 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:90:6:HAL_PWR_DeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:108:6:HAL_PWR_EnableBkUpAccess 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:128:6:HAL_PWR_DisableBkUpAccess 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:275:6:HAL_PWR_ConfigPVD 20 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:318:6:HAL_PWR_EnablePVD 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:327:6:HAL_PWR_DisablePVD 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:341:6:HAL_PWR_EnableWakeUpPin 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:359:6:HAL_PWR_DisableWakeUpPin 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:391:6:HAL_PWR_EnterSLEEPMode 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:445:6:HAL_PWR_EnterSTOPMode 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:488:6:HAL_PWR_EnterSTANDBYMode 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:509:6:HAL_PWR_PVD_IRQHandler 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:526:13:HAL_PWR_PVDCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:541:6:HAL_PWR_EnableSleepOnExit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:553:6:HAL_PWR_DisableSleepOnExit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:565:6:HAL_PWR_EnableSEVOnPend 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:577:6:HAL_PWR_DisableSEVOnPend 1 diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d new file mode 100644 index 0000000..3ce4d19 --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d @@ -0,0 +1,58 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o new file mode 100644 index 0000000..e3e9b7e Binary files /dev/null and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su new file mode 100644 index 0000000..4eb40e8 --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su @@ -0,0 +1,17 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:90:6:HAL_PWR_DeInit 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:108:6:HAL_PWR_EnableBkUpAccess 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:128:6:HAL_PWR_DisableBkUpAccess 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:275:6:HAL_PWR_ConfigPVD 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:318:6:HAL_PWR_EnablePVD 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:327:6:HAL_PWR_DisablePVD 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:341:6:HAL_PWR_EnableWakeUpPin 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:359:6:HAL_PWR_DisableWakeUpPin 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:391:6:HAL_PWR_EnterSLEEPMode 16 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:445:6:HAL_PWR_EnterSTOPMode 16 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:488:6:HAL_PWR_EnterSTANDBYMode 4 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:509:6:HAL_PWR_PVD_IRQHandler 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:526:13:HAL_PWR_PVDCallback 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:541:6:HAL_PWR_EnableSleepOnExit 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:553:6:HAL_PWR_DisableSleepOnExit 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:565:6:HAL_PWR_EnableSEVOnPend 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:577:6:HAL_PWR_DisableSEVOnPend 4 static diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.cyclo b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.cyclo new file mode 100644 index 0000000..ea37da3 --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.cyclo @@ -0,0 +1,6 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:141:19:HAL_PWREx_EnableBkUpReg 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:165:19:HAL_PWREx_DisableBkUpReg 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:189:6:HAL_PWREx_EnableFlashPowerDown 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:198:6:HAL_PWREx_DisableFlashPowerDown 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:211:10:HAL_PWREx_GetVoltageRange 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:232:19:HAL_PWREx_ControlVoltageScaling 5 diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d new file mode 100644 index 0000000..39a0de8 --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d @@ -0,0 +1,58 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o new file mode 100644 index 0000000..84943ab Binary files /dev/null and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su new file mode 100644 index 0000000..cd686a1 --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su @@ -0,0 +1,6 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:141:19:HAL_PWREx_EnableBkUpReg 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:165:19:HAL_PWREx_DisableBkUpReg 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:189:6:HAL_PWREx_EnableFlashPowerDown 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:198:6:HAL_PWREx_DisableFlashPowerDown 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:211:10:HAL_PWREx_GetVoltageRange 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:232:19:HAL_PWREx_ControlVoltageScaling 32 static diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.cyclo b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.cyclo new file mode 100644 index 0000000..c6417e0 --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.cyclo @@ -0,0 +1,14 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:200:26:HAL_RCC_DeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:219:26:HAL_RCC_OscConfig 88 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:591:19:HAL_RCC_ClockConfig 53 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:775:6:HAL_RCC_MCOConfig 17 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:841:6:HAL_RCC_EnableCSS 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:850:6:HAL_RCC_DisableCSS 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:885:17:HAL_RCC_GetSysClockFreq 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:943:10:HAL_RCC_GetHCLKFreq 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:954:10:HAL_RCC_GetPCLK1Freq 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:966:10:HAL_RCC_GetPCLK2Freq 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:979:13:HAL_RCC_GetOscConfig 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:1058:6:HAL_RCC_GetClockConfig 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:1084:6:HAL_RCC_NMI_IRQHandler 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:1101:13:HAL_RCC_CSSCallback 1 diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d new file mode 100644 index 0000000..9b9285a --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d @@ -0,0 +1,58 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o new file mode 100644 index 0000000..edd400f Binary files /dev/null and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su new file mode 100644 index 0000000..41041c7 --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su @@ -0,0 +1,14 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:200:26:HAL_RCC_DeInit 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:219:26:HAL_RCC_OscConfig 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:591:19:HAL_RCC_ClockConfig 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:775:6:HAL_RCC_MCOConfig 56 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:841:6:HAL_RCC_EnableCSS 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:850:6:HAL_RCC_DisableCSS 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:885:17:HAL_RCC_GetSysClockFreq 96 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:943:10:HAL_RCC_GetHCLKFreq 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:954:10:HAL_RCC_GetPCLK1Freq 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:966:10:HAL_RCC_GetPCLK2Freq 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:979:13:HAL_RCC_GetOscConfig 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:1058:6:HAL_RCC_GetClockConfig 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:1084:6:HAL_RCC_NMI_IRQHandler 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:1101:13:HAL_RCC_CSSCallback 4 static diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.cyclo b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.cyclo new file mode 100644 index 0000000..1a319d9 --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.cyclo @@ -0,0 +1,6 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2551:19:HAL_RCCEx_PeriphCLKConfig 54 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2680:6:HAL_RCCEx_GetPeriphCLKConfig 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2718:10:HAL_RCCEx_GetPeriphCLKFreq 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2846:19:HAL_RCCEx_EnablePLLI2S 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2929:19:HAL_RCCEx_DisablePLLI2S 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:3186:19:HAL_RCC_DeInit 12 diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d new file mode 100644 index 0000000..5a4a9d2 --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d @@ -0,0 +1,58 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o new file mode 100644 index 0000000..2c13eac Binary files /dev/null and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su new file mode 100644 index 0000000..d093158 --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su @@ -0,0 +1,6 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2551:19:HAL_RCCEx_PeriphCLKConfig 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2680:6:HAL_RCCEx_GetPeriphCLKConfig 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2718:10:HAL_RCCEx_GetPeriphCLKFreq 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2846:19:HAL_RCCEx_EnablePLLI2S 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2929:19:HAL_RCCEx_DisablePLLI2S 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:3186:19:HAL_RCC_DeInit 16 static diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.cyclo b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.cyclo new file mode 100644 index 0000000..302a522 --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.cyclo @@ -0,0 +1,119 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:266:19:HAL_TIM_Base_Init 33 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:326:19:HAL_TIM_Base_DeInit 17 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:369:13:HAL_TIM_Base_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:384:13:HAL_TIM_Base_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:400:19:HAL_TIM_Base_Start 25 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:439:19:HAL_TIM_Base_Stop 17 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:459:19:HAL_TIM_Base_Start_IT 25 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:501:19:HAL_TIM_Base_Stop_IT 17 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:526:19:HAL_TIM_Base_Start_DMA 23 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:595:19:HAL_TIM_Base_Stop_DMA 11 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:650:19:HAL_TIM_OC_Init 33 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:710:19:HAL_TIM_OC_DeInit 17 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:753:13:HAL_TIM_OC_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:768:13:HAL_TIM_OC_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:789:19:HAL_TIM_OC_Start 64 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:843:19:HAL_TIM_OC_Stop 55 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:878:19:HAL_TIM_OC_Start_IT 69 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:971:19:HAL_TIM_OC_Stop_IT 60 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1048:19:HAL_TIM_OC_Start_DMA 79 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1212:19:HAL_TIM_OC_Stop_DMA 60 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1315:19:HAL_TIM_PWM_Init 33 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1375:19:HAL_TIM_PWM_DeInit 17 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1418:13:HAL_TIM_PWM_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1433:13:HAL_TIM_PWM_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1454:19:HAL_TIM_PWM_Start 64 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1508:19:HAL_TIM_PWM_Stop 55 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1543:19:HAL_TIM_PWM_Start_IT 69 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1636:19:HAL_TIM_PWM_Stop_IT 60 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1713:19:HAL_TIM_PWM_Start_DMA 79 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1876:19:HAL_TIM_PWM_Stop_DMA 60 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1979:19:HAL_TIM_IC_Init 33 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2039:19:HAL_TIM_IC_DeInit 17 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2082:13:HAL_TIM_IC_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2097:13:HAL_TIM_IC_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2118:19:HAL_TIM_IC_Start 68 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2170:19:HAL_TIM_IC_Stop 53 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2200:19:HAL_TIM_IC_Start_IT 73 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2292:19:HAL_TIM_IC_Stop_IT 58 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2364:19:HAL_TIM_IC_Start_DMA 86 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2523:19:HAL_TIM_IC_Stop_DMA 64 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2628:19:HAL_TIM_OnePulse_Init 35 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2697:19:HAL_TIM_OnePulse_DeInit 17 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2742:13:HAL_TIM_OnePulse_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2757:13:HAL_TIM_OnePulse_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2777:19:HAL_TIM_OnePulse_Start 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2834:19:HAL_TIM_OnePulse_Stop 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2877:19:HAL_TIM_OnePulse_Start_IT 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2940:19:HAL_TIM_OnePulse_Stop_IT 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3019:19:HAL_TIM_Encoder_Init 50 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3134:19:HAL_TIM_Encoder_DeInit 17 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3179:13:HAL_TIM_Encoder_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3194:13:HAL_TIM_Encoder_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3214:19:HAL_TIM_Encoder_Start 21 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3308:19:HAL_TIM_Encoder_Stop 21 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3368:19:HAL_TIM_Encoder_Start_IT 21 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3468:19:HAL_TIM_Encoder_Stop_IT 21 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3533:19:HAL_TIM_Encoder_Start_DMA 40 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3746:19:HAL_TIM_Encoder_Stop_DMA 21 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3823:6:HAL_TIM_IRQHandler 21 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4041:19:HAL_TIM_OC_ConfigChannel 51 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4120:19:HAL_TIM_IC_ConfigChannel 49 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4219:19:HAL_TIM_PWM_ConfigChannel 49 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4333:19:HAL_TIM_OnePulse_ConfigChannel 52 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4481:19:HAL_TIM_DMABurst_WriteStart 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4534:19:HAL_TIM_DMABurst_MultiWriteStart 71 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4718:19:HAL_TIM_DMABurst_WriteStop 16 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4819:19:HAL_TIM_DMABurst_ReadStart 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4870:19:HAL_TIM_DMABurst_MultiReadStart 71 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5054:19:HAL_TIM_DMABurst_ReadStop 16 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5137:19:HAL_TIM_GenerateEvent 18 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5174:19:HAL_TIM_ConfigOCrefClear 29 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5304:19:HAL_TIM_ConfigClockSource 128 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5458:19:HAL_TIM_ConfigTI1Input 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5490:19:HAL_TIM_SlaveConfigSynchro 24 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5530:19:HAL_TIM_SlaveConfigSynchro_IT 24 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5573:10:HAL_TIM_ReadCapturedValue 37 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5657:13:HAL_TIM_PeriodElapsedCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5672:13:HAL_TIM_PeriodElapsedHalfCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5687:13:HAL_TIM_OC_DelayElapsedCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5702:13:HAL_TIM_IC_CaptureCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5717:13:HAL_TIM_IC_CaptureHalfCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5732:13:HAL_TIM_PWM_PulseFinishedCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5747:13:HAL_TIM_PWM_PulseFinishedHalfCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5762:13:HAL_TIM_TriggerCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5777:13:HAL_TIM_TriggerHalfCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5792:13:HAL_TIM_ErrorCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6339:22:HAL_TIM_Base_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6349:22:HAL_TIM_OC_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6359:22:HAL_TIM_PWM_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6369:22:HAL_TIM_IC_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6379:22:HAL_TIM_OnePulse_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6389:22:HAL_TIM_Encoder_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6399:23:HAL_TIM_GetActiveChannel 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6417:29:HAL_TIM_GetChannelState 48 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6434:30:HAL_TIM_DMABurstState 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6459:6:TIM_DMAError 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6502:13:TIM_DMADelayPulseCplt 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6561:6:TIM_DMADelayPulseHalfCplt 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6600:6:TIM_DMACaptureCplt 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6663:6:TIM_DMACaptureHalfCplt 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6702:13:TIM_DMAPeriodElapsedCplt 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6723:13:TIM_DMAPeriodElapsedHalfCplt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6739:13:TIM_DMATriggerCplt 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6760:13:TIM_DMATriggerHalfCplt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6777:6:TIM_Base_SetConfig 21 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6829:13:TIM_OC1_SetConfig 11 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6905:6:TIM_OC2_SetConfig 11 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6981:13:TIM_OC3_SetConfig 11 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7056:13:TIM_OC4_SetConfig 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7117:26:TIM_SlaveTimer_SetConfig 87 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7251:6:TIM_TI1_SetConfig 10 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7298:13:TIM_TI1_ConfigInputStage 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7341:13:TIM_TI2_SetConfig 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7381:13:TIM_TI2_ConfigInputStage 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7424:13:TIM_TI3_SetConfig 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7472:13:TIM_TI4_SetConfig 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7515:13:TIM_ITRx_SetConfig 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7545:6:TIM_ETR_SetConfig 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7575:6:TIM_CCxChannelCmd 18 diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d new file mode 100644 index 0000000..2a238f0 --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d @@ -0,0 +1,58 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o new file mode 100644 index 0000000..3eb2919 Binary files /dev/null and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.su b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.su new file mode 100644 index 0000000..f4fb564 --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.su @@ -0,0 +1,119 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:266:19:HAL_TIM_Base_Init 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:326:19:HAL_TIM_Base_DeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:369:13:HAL_TIM_Base_MspInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:384:13:HAL_TIM_Base_MspDeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:400:19:HAL_TIM_Base_Start 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:439:19:HAL_TIM_Base_Stop 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:459:19:HAL_TIM_Base_Start_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:501:19:HAL_TIM_Base_Stop_IT 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:526:19:HAL_TIM_Base_Start_DMA 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:595:19:HAL_TIM_Base_Stop_DMA 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:650:19:HAL_TIM_OC_Init 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:710:19:HAL_TIM_OC_DeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:753:13:HAL_TIM_OC_MspInit 16 static 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+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6702:13:TIM_DMAPeriodElapsedCplt 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6723:13:TIM_DMAPeriodElapsedHalfCplt 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6739:13:TIM_DMATriggerCplt 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6760:13:TIM_DMATriggerHalfCplt 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6777:6:TIM_Base_SetConfig 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6829:13:TIM_OC1_SetConfig 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6905:6:TIM_OC2_SetConfig 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6981:13:TIM_OC3_SetConfig 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7056:13:TIM_OC4_SetConfig 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7117:26:TIM_SlaveTimer_SetConfig 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7251:6:TIM_TI1_SetConfig 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7298:13:TIM_TI1_ConfigInputStage 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7341:13:TIM_TI2_SetConfig 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7381:13:TIM_TI2_ConfigInputStage 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7424:13:TIM_TI3_SetConfig 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7472:13:TIM_TI4_SetConfig 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7515:13:TIM_ITRx_SetConfig 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7545:6:TIM_ETR_SetConfig 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7575:6:TIM_CCxChannelCmd 32 static diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.cyclo b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.cyclo new file mode 100644 index 0000000..3867439 --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.cyclo @@ -0,0 +1,42 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:138:19:HAL_TIMEx_HallSensor_Init 33 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:240:19:HAL_TIMEx_HallSensor_DeInit 17 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:285:13:HAL_TIMEx_HallSensor_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:300:13:HAL_TIMEx_HallSensor_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:315:19:HAL_TIMEx_HallSensor_Start 20 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:369:19:HAL_TIMEx_HallSensor_Stop 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:397:19:HAL_TIMEx_HallSensor_Start_IT 20 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:454:19:HAL_TIMEx_HallSensor_Stop_IT 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:487:19:HAL_TIMEx_HallSensor_Start_DMA 23 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:563:19:HAL_TIMEx_HallSensor_Stop_DMA 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:625:19:HAL_TIMEx_OCN_Start 25 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:676:19:HAL_TIMEx_OCN_Stop 16 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:708:19:HAL_TIMEx_OCN_Start_IT 30 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:795:19:HAL_TIMEx_OCN_Stop_IT 22 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:870:19:HAL_TIMEx_OCN_Start_DMA 39 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1008:19:HAL_TIMEx_OCN_Stop_DMA 21 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1098:19:HAL_TIMEx_PWMN_Start 25 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1148:19:HAL_TIMEx_PWMN_Stop 16 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1180:19:HAL_TIMEx_PWMN_Start_IT 30 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1266:19:HAL_TIMEx_PWMN_Stop_IT 22 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1341:19:HAL_TIMEx_PWMN_Start_DMA 39 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1479:19:HAL_TIMEx_PWMN_Stop_DMA 21 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1570:19:HAL_TIMEx_OnePulseN_Start 14 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1619:19:HAL_TIMEx_OnePulseN_Stop 14 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1658:19:HAL_TIMEx_OnePulseN_Start_IT 14 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1713:19:HAL_TIMEx_OnePulseN_Stop_IT 14 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1792:19:HAL_TIMEx_ConfigCommutEvent 13 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1848:19:HAL_TIMEx_ConfigCommutEvent_IT 13 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1905:19:HAL_TIMEx_ConfigCommutEvent_DMA 13 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1954:19:HAL_TIMEx_MasterConfigSynchronization 28 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2015:19:HAL_TIMEx_ConfigBreakDeadTime 19 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2091:19:HAL_TIMEx_RemapConfig 15 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2147:13:HAL_TIMEx_CommutCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2161:13:HAL_TIMEx_CommutHalfCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2176:13:HAL_TIMEx_BreakCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2209:22:HAL_TIMEx_HallSensor_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2224:29:HAL_TIMEx_GetChannelNState 12 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2253:6:TIMEx_DMACommutationCplt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2272:6:TIMEx_DMACommutationHalfCplt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2292:13:TIM_DMADelayPulseNCplt 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2342:13:TIM_DMAErrorCCxN 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2387:13:TIM_CCxNChannelCmd 1 diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d new file mode 100644 index 0000000..03c321d --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d @@ -0,0 +1,58 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o new file mode 100644 index 0000000..e8b1c3e Binary files /dev/null and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su new file mode 100644 index 0000000..1dd929f --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su @@ -0,0 +1,42 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:138:19:HAL_TIMEx_HallSensor_Init 48 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:240:19:HAL_TIMEx_HallSensor_DeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:285:13:HAL_TIMEx_HallSensor_MspInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:300:13:HAL_TIMEx_HallSensor_MspDeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:315:19:HAL_TIMEx_HallSensor_Start 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:369:19:HAL_TIMEx_HallSensor_Stop 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:397:19:HAL_TIMEx_HallSensor_Start_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:454:19:HAL_TIMEx_HallSensor_Stop_IT 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:487:19:HAL_TIMEx_HallSensor_Start_DMA 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:563:19:HAL_TIMEx_HallSensor_Stop_DMA 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:625:19:HAL_TIMEx_OCN_Start 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:676:19:HAL_TIMEx_OCN_Stop 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:708:19:HAL_TIMEx_OCN_Start_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:795:19:HAL_TIMEx_OCN_Stop_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:870:19:HAL_TIMEx_OCN_Start_DMA 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1008:19:HAL_TIMEx_OCN_Stop_DMA 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1098:19:HAL_TIMEx_PWMN_Start 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1148:19:HAL_TIMEx_PWMN_Stop 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1180:19:HAL_TIMEx_PWMN_Start_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1266:19:HAL_TIMEx_PWMN_Stop_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1341:19:HAL_TIMEx_PWMN_Start_DMA 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1479:19:HAL_TIMEx_PWMN_Stop_DMA 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1570:19:HAL_TIMEx_OnePulseN_Start 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1619:19:HAL_TIMEx_OnePulseN_Stop 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1658:19:HAL_TIMEx_OnePulseN_Start_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1713:19:HAL_TIMEx_OnePulseN_Stop_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1792:19:HAL_TIMEx_ConfigCommutEvent 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1848:19:HAL_TIMEx_ConfigCommutEvent_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1905:19:HAL_TIMEx_ConfigCommutEvent_DMA 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1954:19:HAL_TIMEx_MasterConfigSynchronization 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2015:19:HAL_TIMEx_ConfigBreakDeadTime 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2091:19:HAL_TIMEx_RemapConfig 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2147:13:HAL_TIMEx_CommutCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2161:13:HAL_TIMEx_CommutHalfCpltCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2176:13:HAL_TIMEx_BreakCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2209:22:HAL_TIMEx_HallSensor_GetState 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2224:29:HAL_TIMEx_GetChannelNState 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2253:6:TIMEx_DMACommutationCplt 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2272:6:TIMEx_DMACommutationHalfCplt 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2292:13:TIM_DMADelayPulseNCplt 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2342:13:TIM_DMAErrorCCxN 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2387:13:TIM_CCxNChannelCmd 32 static diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk new file mode 100644 index 0000000..c77e4db --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk @@ -0,0 +1,72 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (14.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c + +OBJS += \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + +C_DEPS += \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/STM32F4xx_HAL_Driver/Src/%.o Drivers/STM32F4xx_HAL_Driver/Src/%.su Drivers/STM32F4xx_HAL_Driver/Src/%.cyclo: ../Drivers/STM32F4xx_HAL_Driver/Src/%.c Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F405xx -DSTM32_THREAD_SAFE_STRATEGY=4 -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../Core/ThreadSafe -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Drivers-2f-STM32F4xx_HAL_Driver-2f-Src + +clean-Drivers-2f-STM32F4xx_HAL_Driver-2f-Src: + -$(RM) ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su + +.PHONY: clean-Drivers-2f-STM32F4xx_HAL_Driver-2f-Src + diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.cyclo b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.cyclo new file mode 100644 index 0000000..2b65de2 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.cyclo @@ -0,0 +1,83 @@ +../Drivers/CMSIS/Include/core_cm4.h:1814:22:__NVIC_SetPriority 2 +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:159:6:SysTick_Handler 2 +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:174:22:SVC_Setup 1 +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:198:12:osKernelInitialize 3 +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:222:12:osKernelGetInfo 5 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b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.d new file mode 100644 index 0000000..1bca156 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.d @@ -0,0 +1,94 @@ +Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o: \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + 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../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + 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+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o new file mode 100644 index 0000000..2515034 Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o differ diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.su new file mode 100644 index 0000000..ec910ea --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.su @@ -0,0 +1,83 @@ +../Drivers/CMSIS/Include/core_cm4.h:1814:22:__NVIC_SetPriority 16 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:159:6:SysTick_Handler 8 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:174:22:SVC_Setup 8 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:198:12:osKernelInitialize 16 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:222:12:osKernelGetInfo 24 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:240:17:osKernelGetState 16 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:265:12:osKernelStart 16 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:288:9:osKernelLock 16 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:315:9:osKernelUnlock 16 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:347:9:osKernelRestoreLock 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:383:10:osKernelGetTickCount 16 static,ignoring_inline_asm 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static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:533:17:osThreadGetState 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:555:10:osThreadGetStackSpace 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:568:12:osThreadSetPriority 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:586:14:osThreadGetPriority 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:599:12:osThreadYield 16 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:613:12:osThreadSuspend 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:631:12:osThreadResume 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:650:18:osThreadExit 8 static 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+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:1693:20:osMessageQueueNew 48 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:1750:12:osMessageQueuePut 40 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:1791:12:osMessageQueueGet 40 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:1832:10:osMessageQueueGetCapacity 24 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:1846:10:osMessageQueueGetMsgSize 24 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:1860:10:osMessageQueueGetCount 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:1877:10:osMessageQueueGetSpace 48 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:1900:12:osMessageQueueReset 32 static,ignoring_inline_asm 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+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:2283:10:osMemoryPoolGetSpace 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:2311:12:osMemoryPoolDelete 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:2357:14:CreateBlock 24 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:2374:14:AllocBlock 24 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:2391:13:FreeBlock 24 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:2459:13:vApplicationGetIdleTaskMemory 24 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c:2473:13:vApplicationGetTimerTaskMemory 24 static diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/subdir.mk b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/subdir.mk new file mode 100644 index 0000000..4dc3547 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (14.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c + +OBJS += \ +./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + +C_DEPS += \ +./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/%.o Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/%.su Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/%.cyclo: ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/%.c Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F405xx -DSTM32_THREAD_SAFE_STRATEGY=4 -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../Core/ThreadSafe -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-CMSIS_RTOS_V2 + +clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-CMSIS_RTOS_V2: + -$(RM) ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.d ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.su + +.PHONY: clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-CMSIS_RTOS_V2 + diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.cyclo b/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.d b/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.d new file mode 100644 index 0000000..917ef11 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.d @@ -0,0 +1,22 @@ +Middlewares/Third_Party/FreeRTOS/Source/croutine.o: \ + ../Middlewares/Third_Party/FreeRTOS/Source/croutine.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h: diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.o new file mode 100644 index 0000000..b2a44df Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.o differ diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.cyclo b/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.cyclo new file mode 100644 index 0000000..ccd2657 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.cyclo @@ -0,0 +1,15 @@ +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:93:21:xEventGroupCreateStatic 4 +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:145:21:xEventGroupCreate 2 +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:191:13:xEventGroupSync 12 +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:311:13:xEventGroupWaitBits 17 +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:461:13:xEventGroupClearBits 3 +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:490:13:xEventGroupClearBitsFromISR 1 +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:503:13:xEventGroupGetBitsFromISR 1 +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:519:13:xEventGroupSetBits 9 +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:613:6:vEventGroupDelete 4 +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:657:6:vEventGroupSetBitsCallback 1 +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:665:6:vEventGroupClearBitsCallback 1 +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:671:19:prvTestWaitCondition 4 +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:708:13:xEventGroupSetBitsFromISR 1 +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:723:14:uxEventGroupGetNumber 2 +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:745:7:vEventGroupSetNumber 1 diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.d b/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.d new file mode 100644 index 0000000..a2c9c62 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.d @@ -0,0 +1,28 @@ +Middlewares/Third_Party/FreeRTOS/Source/event_groups.o: \ + ../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + 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+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.o new file mode 100644 index 0000000..828dbcd Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.o differ diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.su new file mode 100644 index 0000000..55187d2 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.su @@ -0,0 +1,15 @@ +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:93:21:xEventGroupCreateStatic 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:145:21:xEventGroupCreate 16 static +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:191:13:xEventGroupSync 56 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:311:13:xEventGroupWaitBits 72 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:461:13:xEventGroupClearBits 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:490:13:xEventGroupClearBitsFromISR 24 static +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:503:13:xEventGroupGetBitsFromISR 40 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:519:13:xEventGroupSetBits 64 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:613:6:vEventGroupDelete 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:657:6:vEventGroupSetBitsCallback 16 static +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:665:6:vEventGroupClearBitsCallback 16 static +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:671:19:prvTestWaitCondition 32 static +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:708:13:xEventGroupSetBitsFromISR 32 static +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:723:14:uxEventGroupGetNumber 24 static +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:745:7:vEventGroupSetNumber 16 static diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.cyclo b/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.cyclo new file mode 100644 index 0000000..8d6cdb0 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.cyclo @@ -0,0 +1,5 @@ +../Middlewares/Third_Party/FreeRTOS/Source/list.c:37:6:vListInitialise 1 +../Middlewares/Third_Party/FreeRTOS/Source/list.c:62:6:vListInitialiseItem 1 +../Middlewares/Third_Party/FreeRTOS/Source/list.c:74:6:vListInsertEnd 1 +../Middlewares/Third_Party/FreeRTOS/Source/list.c:103:6:vListInsert 3 +../Middlewares/Third_Party/FreeRTOS/Source/list.c:170:13:uxListRemove 2 diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.d b/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.d new file mode 100644 index 0000000..a46554b --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.d @@ -0,0 +1,18 @@ +Middlewares/Third_Party/FreeRTOS/Source/list.o: \ + ../Middlewares/Third_Party/FreeRTOS/Source/list.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.o new file mode 100644 index 0000000..958bd8a Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.o differ diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.su new file mode 100644 index 0000000..85c9323 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.su @@ -0,0 +1,5 @@ +../Middlewares/Third_Party/FreeRTOS/Source/list.c:37:6:vListInitialise 16 static +../Middlewares/Third_Party/FreeRTOS/Source/list.c:62:6:vListInitialiseItem 16 static +../Middlewares/Third_Party/FreeRTOS/Source/list.c:74:6:vListInsertEnd 24 static +../Middlewares/Third_Party/FreeRTOS/Source/list.c:103:6:vListInsert 24 static +../Middlewares/Third_Party/FreeRTOS/Source/list.c:170:13:uxListRemove 24 static diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.cyclo b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.cyclo new file mode 100644 index 0000000..1ca2981 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.cyclo @@ -0,0 +1,13 @@ +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:187:14:pxPortInitialiseStack 1 +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:217:13:prvTaskExitError 3 +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:242:6:SVC_Handler 1 +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:261:13:prvPortStartFirstTask 1 +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:287:12:xPortStartScheduler 5 +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:395:6:vPortEndScheduler 2 +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:403:6:vPortEnterCritical 3 +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:420:6:vPortExitCritical 3 +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:431:6:PendSV_Handler 1 +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:488:6:xPortSysTickHandler 2 +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:679:30:vPortSetupTimerInterrupt 1 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../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o new file mode 100644 index 0000000..f121c7a Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o differ diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.su new file mode 100644 index 0000000..2bfa56c --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.su @@ -0,0 +1,13 @@ +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:187:14:pxPortInitialiseStack 24 static +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:217:13:prvTaskExitError 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:242:6:SVC_Handler 0 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:261:13:prvPortStartFirstTask 0 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:287:12:xPortStartScheduler 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:395:6:vPortEndScheduler 16 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:403:6:vPortEnterCritical 16 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:420:6:vPortExitCritical 16 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:431:6:PendSV_Handler 0 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:488:6:xPortSysTickHandler 16 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:679:30:vPortSetupTimerInterrupt 4 static +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:701:13:vPortEnableVFP 0 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c:717:7:vPortValidateInterruptPriority 24 static,ignoring_inline_asm diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/subdir.mk b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/subdir.mk new file mode 100644 index 0000000..90b7257 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (14.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c + +OBJS += \ +./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o + +C_DEPS += \ +./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/%.o Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/%.su Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/%.cyclo: ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/%.c Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F405xx -DSTM32_THREAD_SAFE_STRATEGY=4 -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../Core/ThreadSafe -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-portable-2f-GCC-2f-ARM_CM4F + +clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-portable-2f-GCC-2f-ARM_CM4F: + -$(RM) ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.d ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.su + +.PHONY: clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-portable-2f-GCC-2f-ARM_CM4F + diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.cyclo b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.cyclo new file mode 100644 index 0000000..0fae04d --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.cyclo @@ -0,0 +1,8 @@ +../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:115:7:pvPortMalloc 15 +../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:266:6:vPortFree 6 +../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:315:8:xPortGetFreeHeapSize 1 +../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:321:8:xPortGetMinimumEverFreeHeapSize 1 +../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:327:6:vPortInitialiseBlocks 1 +../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:333:13:prvHeapInit 2 +../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:381:13:prvInsertBlockIntoFreeList 6 +../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:442:6:vPortGetHeapStats 5 diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.d b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.d new file mode 100644 index 0000000..3239dc9 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.d @@ -0,0 +1,20 @@ +Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o: \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o new file mode 100644 index 0000000..91bbc34 Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o differ diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.su new file mode 100644 index 0000000..03dea47 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.su @@ -0,0 +1,8 @@ +../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:115:7:pvPortMalloc 48 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:266:6:vPortFree 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:315:8:xPortGetFreeHeapSize 4 static +../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:321:8:xPortGetMinimumEverFreeHeapSize 4 static +../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:327:6:vPortInitialiseBlocks 4 static +../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:333:13:prvHeapInit 24 static +../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:381:13:prvInsertBlockIntoFreeList 24 static +../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:442:6:vPortGetHeapStats 32 static diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk new file mode 100644 index 0000000..370a730 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (14.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c + +OBJS += \ +./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + +C_DEPS += \ +./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/%.o Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/%.su Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/%.cyclo: ../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/%.c Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F405xx -DSTM32_THREAD_SAFE_STRATEGY=4 -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../Core/ThreadSafe -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-portable-2f-MemMang + +clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-portable-2f-MemMang: + -$(RM) ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.d ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.su + +.PHONY: clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-portable-2f-MemMang + diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.cyclo b/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.cyclo new file mode 100644 index 0000000..cb09ef0 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.cyclo @@ -0,0 +1,40 @@ +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:255:12:xQueueGenericReset 5 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:310:16:xQueueGenericCreateStatic 11 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:368:16:xQueueGenericCreate 3 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:422:13:prvInitialiseNewQueue 2 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:466:14:prvInitialiseMutex 2 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:496:16:xQueueCreateMutex 1 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:512:16:xQueueCreateMutexStatic 1 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:532:15:xQueueGetMutexHolder 2 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:563:15:xQueueGetMutexHolderFromISR 3 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:589:13:xQueueGiveMutexRecursive 4 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:644:13:xQueueTakeMutexRecursive 4 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:686:16:xQueueCreateCountingSemaphoreStatic 4 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:714:16:xQueueCreateCountingSemaphore 4 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:740:12:xQueueGenericSend 23 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:950:12:xQueueGenericSendFromISR 14 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1112:12:xQueueGiveFromISR 11 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1277:12:xQueueReceive 19 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1418:12:xQueueSemaphoreTake 21 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1636:12:xQueuePeek 19 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1785:12:xQueueReceiveFromISR 10 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1876:12:xQueuePeekFromISR 7 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1930:13:uxQueueMessagesWaiting 2 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1946:13:uxQueueSpacesAvailable 2 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1963:13:uxQueueMessagesWaitingFromISR 2 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1975:6:vQueueDelete 3 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2019:14:uxQueueGetQueueNumber 1 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2029:7:vQueueSetQueueNumber 1 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2039:10:ucQueueGetQueueType 1 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2049:21:prvGetDisinheritPriorityAfterTimeout 2 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2074:19:prvCopyDataToQueue 8 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2153:13:prvCopyDataFromQueue 3 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2171:13:prvUnlockQueue 7 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2291:19:prvIsQueueEmpty 2 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2312:12:xQueueIsQueueEmptyFromISR 3 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2331:19:prvIsQueueFull 2 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2352:12:xQueueIsQueueFullFromISR 3 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2648:7:vQueueAddToRegistry 3 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2677:14:pcQueueGetName 3 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2705:7:vQueueUnregisterQueue 3 +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2737:7:vQueueWaitForMessageRestricted 4 diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.d b/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.d new file mode 100644 index 0000000..23ff8db --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.d @@ -0,0 +1,24 @@ +Middlewares/Third_Party/FreeRTOS/Source/queue.o: \ + ../Middlewares/Third_Party/FreeRTOS/Source/queue.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.o new file mode 100644 index 0000000..802f0b9 Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.o differ diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.su new file mode 100644 index 0000000..c246712 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.su @@ -0,0 +1,40 @@ +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:255:12:xQueueGenericReset 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:310:16:xQueueGenericCreateStatic 64 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:368:16:xQueueGenericCreate 48 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:422:13:prvInitialiseNewQueue 24 static +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:466:14:prvInitialiseMutex 16 static +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:496:16:xQueueCreateMutex 32 static +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:512:16:xQueueCreateMutexStatic 40 static +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:532:15:xQueueGetMutexHolder 24 static +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:563:15:xQueueGetMutexHolderFromISR 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:589:13:xQueueGiveMutexRecursive 40 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:644:13:xQueueTakeMutexRecursive 40 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:686:16:xQueueCreateCountingSemaphoreStatic 48 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:714:16:xQueueCreateCountingSemaphore 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:740:12:xQueueGenericSend 64 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:950:12:xQueueGenericSendFromISR 72 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1112:12:xQueueGiveFromISR 64 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1277:12:xQueueReceive 56 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1418:12:xQueueSemaphoreTake 64 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1636:12:xQueuePeek 64 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1785:12:xQueueReceiveFromISR 64 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1876:12:xQueuePeekFromISR 56 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1930:13:uxQueueMessagesWaiting 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1946:13:uxQueueSpacesAvailable 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1963:13:uxQueueMessagesWaitingFromISR 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1975:6:vQueueDelete 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2019:14:uxQueueGetQueueNumber 16 static +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2029:7:vQueueSetQueueNumber 16 static +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2039:10:ucQueueGetQueueType 16 static +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2049:21:prvGetDisinheritPriorityAfterTimeout 24 static +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2074:19:prvCopyDataToQueue 32 static +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2153:13:prvCopyDataFromQueue 16 static +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2171:13:prvUnlockQueue 24 static +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2291:19:prvIsQueueEmpty 24 static +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2312:12:xQueueIsQueueEmptyFromISR 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2331:19:prvIsQueueFull 24 static +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2352:12:xQueueIsQueueFullFromISR 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2648:7:vQueueAddToRegistry 24 static +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2677:14:pcQueueGetName 24 static +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2705:7:vQueueUnregisterQueue 24 static +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2737:7:vQueueWaitForMessageRestricted 32 static diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.cyclo b/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.cyclo new file mode 100644 index 0000000..8992bd9 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.cyclo @@ -0,0 +1,25 @@ +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:219:23:xStreamBufferGenericCreate 7 +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:283:23:xStreamBufferGenericCreateStatic 10 +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:359:6:vStreamBufferDelete 3 +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:392:12:xStreamBufferReset 4 +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:441:12:xStreamBufferSetTriggerLevel 4 +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:470:8:xStreamBufferSpacesAvailable 3 +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:494:8:xStreamBufferBytesAvailable 2 +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:506:8:xStreamBufferSend 13 +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:610:8:xStreamBufferSendFromISR 7 +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:661:15:prvWriteMessageToBuffer 5 +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:713:8:xStreamBufferReceive 11 +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:817:8:xStreamBufferNextMessageLengthBytes 5 +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:861:8:xStreamBufferReceiveFromISR 7 +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:918:15:prvReadMessageFromBuffer 3 +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:970:12:xStreamBufferIsEmpty 3 +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:993:12:xStreamBufferIsFull 4 +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1028:12:xStreamBufferSendCompletedFromISR 3 +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1058:12:xStreamBufferReceiveCompletedFromISR 3 +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1088:15:prvWriteBytesToBuffer 6 +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1134:15:prvReadBytesFromBuffer 7 +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1189:15:prvBytesInBuffer 2 +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1209:13:prvInitialiseNewStreamBuffer 2 +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1237:14:uxStreamBufferGetStreamBufferNumber 1 +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1247:7:vStreamBufferSetStreamBufferNumber 1 +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1257:10:ucStreamBufferGetStreamBufferType 1 diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.d b/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.d new file mode 100644 index 0000000..c5439ea --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.d @@ -0,0 +1,22 @@ +Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o: \ + ../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h: diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o new file mode 100644 index 0000000..19c1138 Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o differ diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.su new file mode 100644 index 0000000..f4fca78 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.su @@ -0,0 +1,25 @@ +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:219:23:xStreamBufferGenericCreate 56 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:283:23:xStreamBufferGenericCreateStatic 72 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:359:6:vStreamBufferDelete 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:392:12:xStreamBufferReset 40 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:441:12:xStreamBufferSetTriggerLevel 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:470:8:xStreamBufferSpacesAvailable 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:494:8:xStreamBufferBytesAvailable 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:506:8:xStreamBufferSend 72 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:610:8:xStreamBufferSendFromISR 72 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:661:15:prvWriteMessageToBuffer 32 static +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:713:8:xStreamBufferReceive 64 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:817:8:xStreamBufferNextMessageLengthBytes 48 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:861:8:xStreamBufferReceiveFromISR 72 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:918:15:prvReadMessageFromBuffer 40 static +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:970:12:xStreamBufferIsEmpty 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:993:12:xStreamBufferIsFull 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1028:12:xStreamBufferSendCompletedFromISR 56 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1058:12:xStreamBufferReceiveCompletedFromISR 56 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1088:15:prvWriteBytesToBuffer 48 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1134:15:prvReadBytesFromBuffer 48 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1189:15:prvBytesInBuffer 24 static +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1209:13:prvInitialiseNewStreamBuffer 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1237:14:uxStreamBufferGetStreamBufferNumber 16 static +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1247:7:vStreamBufferSetStreamBufferNumber 16 static +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1257:10:ucStreamBufferGetStreamBufferType 16 static diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/subdir.mk b/Debug/Middlewares/Third_Party/FreeRTOS/Source/subdir.mk new file mode 100644 index 0000000..3294f24 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/subdir.mk @@ -0,0 +1,45 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (14.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/FreeRTOS/Source/croutine.c \ +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c \ +../Middlewares/Third_Party/FreeRTOS/Source/list.c \ +../Middlewares/Third_Party/FreeRTOS/Source/queue.c \ +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c \ +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c \ +../Middlewares/Third_Party/FreeRTOS/Source/timers.c + +OBJS += \ +./Middlewares/Third_Party/FreeRTOS/Source/croutine.o \ +./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o \ +./Middlewares/Third_Party/FreeRTOS/Source/list.o \ +./Middlewares/Third_Party/FreeRTOS/Source/queue.o \ +./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o \ +./Middlewares/Third_Party/FreeRTOS/Source/tasks.o \ +./Middlewares/Third_Party/FreeRTOS/Source/timers.o + +C_DEPS += \ +./Middlewares/Third_Party/FreeRTOS/Source/croutine.d \ +./Middlewares/Third_Party/FreeRTOS/Source/event_groups.d \ +./Middlewares/Third_Party/FreeRTOS/Source/list.d \ +./Middlewares/Third_Party/FreeRTOS/Source/queue.d \ +./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.d \ +./Middlewares/Third_Party/FreeRTOS/Source/tasks.d \ +./Middlewares/Third_Party/FreeRTOS/Source/timers.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/FreeRTOS/Source/%.o Middlewares/Third_Party/FreeRTOS/Source/%.su Middlewares/Third_Party/FreeRTOS/Source/%.cyclo: ../Middlewares/Third_Party/FreeRTOS/Source/%.c Middlewares/Third_Party/FreeRTOS/Source/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F405xx -DSTM32_THREAD_SAFE_STRATEGY=4 -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../Core/ThreadSafe -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source + +clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source: + -$(RM) ./Middlewares/Third_Party/FreeRTOS/Source/croutine.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/croutine.d ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o ./Middlewares/Third_Party/FreeRTOS/Source/croutine.su ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.d ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.su ./Middlewares/Third_Party/FreeRTOS/Source/list.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/list.d ./Middlewares/Third_Party/FreeRTOS/Source/list.o ./Middlewares/Third_Party/FreeRTOS/Source/list.su ./Middlewares/Third_Party/FreeRTOS/Source/queue.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/queue.d ./Middlewares/Third_Party/FreeRTOS/Source/queue.o ./Middlewares/Third_Party/FreeRTOS/Source/queue.su ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.d ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.su ./Middlewares/Third_Party/FreeRTOS/Source/tasks.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/tasks.d ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o ./Middlewares/Third_Party/FreeRTOS/Source/tasks.su ./Middlewares/Third_Party/FreeRTOS/Source/timers.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/timers.d ./Middlewares/Third_Party/FreeRTOS/Source/timers.o ./Middlewares/Third_Party/FreeRTOS/Source/timers.su + +.PHONY: clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source + diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.cyclo b/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.cyclo new file mode 100644 index 0000000..1447c70 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.cyclo @@ -0,0 +1,62 @@ +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:581:15:xTaskCreateStatic 6 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:733:13:xTaskCreate 4 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:824:13:prvInitialiseNewTask 7 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1077:13:prvAddNewTaskToReadyList 8 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1162:7:vTaskDelete 7 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1257:7:vTaskDelayUntil 11 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1341:7:vTaskDelay 4 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1386:13:eTaskGetState 10 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1478:14:uxTaskPriorityGet 2 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1500:14:uxTaskPriorityGetFromISR 2 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1540:7:vTaskPrioritySet 14 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1704:7:vTaskSuspend 9 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1805:20:prvTaskIsTaskSuspended 5 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1851:7:vTaskResume 7 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1905:13:xTaskResumeFromISR 6 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1975:6:vTaskStartScheduler 5 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2099:6:vTaskEndScheduler 1 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2110:6:vTaskSuspendAll 1 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2194:12:xTaskResumeAll 12 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2304:12:xTaskGetTickCount 1 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2319:12:xTaskGetTickCountFromISR 1 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2350:13:uxTaskGetNumberOfTasks 1 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2358:7:pcTaskGetName 3 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2505:14:uxTaskGetSystemState 4 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2609:12:xTaskCatchUpTicks 2 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2707:12:xTaskIncrementTick 12 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2989:6:vTaskSwitchContext 5 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3064:6:vTaskPlaceOnEventList 2 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3081:6:vTaskPlaceOnUnorderedEventList 3 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3107:7:vTaskPlaceOnEventListRestricted 3 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3138:12:xTaskRemoveFromEventList 5 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3206:6:vTaskRemoveFromUnorderedEventList 5 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3254:6:vTaskSetTimeOutState 2 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3266:6:vTaskInternalSetTimeOutState 1 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3274:12:xTaskCheckForTimeOut 7 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3337:6:vTaskMissedYield 1 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3345:14:uxTaskGetTaskNumber 2 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3368:7:vTaskSetTaskNumber 2 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3392:8:prvIdleTask 2 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3607:13:prvInitialiseTaskLists 2 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3639:13:prvCheckTasksWaitingTermination 2 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3670:7:vTaskGetInfo 7 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3766:21:prvListTasksWithinSingleList 5 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3799:32:prvTaskCheckFreeStackSpace 2 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3859:14:uxTaskGetStackHighWaterMark 2 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3887:14:prvDeleteTCB 4 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3943:13:prvResetNextTaskUnblockTime 2 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3969:15:xTaskGetCurrentTaskHandle 1 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3986:13:xTaskGetSchedulerState 3 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4014:13:xTaskPriorityInherit 7 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4104:13:xTaskPriorityDisinherit 7 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4184:7:vTaskPriorityDisinheritAfterTimeout 10 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4602:12:uxTaskResetEventItemValue 1 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4618:15:pvTaskIncrementMutexHeldCount 2 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4635:11:ulTaskNotifyTake 5 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4703:13:xTaskNotifyWait 5 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4783:13:xTaskGenericNotify 14 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4897:13:xTaskGenericNotifyFromISR 16 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:5026:7:vTaskNotifyGiveFromISR 8 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:5112:13:xTaskNotifyStateClear 3 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:5143:11:ulTaskNotifyValueClear 2 +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:5177:13:prvAddCurrentTaskToDelayedList 5 diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.d b/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.d new file mode 100644 index 0000000..953067b --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.d @@ -0,0 +1,26 @@ +Middlewares/Third_Party/FreeRTOS/Source/tasks.o: \ + ../Middlewares/Third_Party/FreeRTOS/Source/tasks.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h: diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.o new file mode 100644 index 0000000..a714f20 Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.o differ diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.su new file mode 100644 index 0000000..dcc662e --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.su @@ -0,0 +1,62 @@ +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:581:15:xTaskCreateStatic 64 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:733:13:xTaskCreate 56 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:824:13:prvInitialiseNewTask 40 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1077:13:prvAddNewTaskToReadyList 16 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1162:7:vTaskDelete 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1257:7:vTaskDelayUntil 48 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1341:7:vTaskDelay 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1386:13:eTaskGetState 40 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1478:14:uxTaskPriorityGet 24 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1500:14:uxTaskPriorityGetFromISR 40 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1540:7:vTaskPrioritySet 40 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1704:7:vTaskSuspend 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1805:20:prvTaskIsTaskSuspended 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1851:7:vTaskResume 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1905:13:xTaskResumeFromISR 48 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1975:6:vTaskStartScheduler 48 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2099:6:vTaskEndScheduler 16 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2110:6:vTaskSuspendAll 4 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2194:12:xTaskResumeAll 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2304:12:xTaskGetTickCount 16 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2319:12:xTaskGetTickCountFromISR 16 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2350:13:uxTaskGetNumberOfTasks 4 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2358:7:pcTaskGetName 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2505:14:uxTaskGetSystemState 32 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2609:12:xTaskCatchUpTicks 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2707:12:xTaskIncrementTick 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2989:6:vTaskSwitchContext 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3064:6:vTaskPlaceOnEventList 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3081:6:vTaskPlaceOnUnorderedEventList 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3107:7:vTaskPlaceOnEventListRestricted 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3138:12:xTaskRemoveFromEventList 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3206:6:vTaskRemoveFromUnorderedEventList 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3254:6:vTaskSetTimeOutState 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3266:6:vTaskInternalSetTimeOutState 16 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3274:12:xTaskCheckForTimeOut 40 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3337:6:vTaskMissedYield 4 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3345:14:uxTaskGetTaskNumber 24 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3368:7:vTaskSetTaskNumber 24 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3392:8:prvIdleTask 16 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3607:13:prvInitialiseTaskLists 16 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3639:13:prvCheckTasksWaitingTermination 16 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3670:7:vTaskGetInfo 32 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3766:21:prvListTasksWithinSingleList 48 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3799:32:prvTaskCheckFreeStackSpace 24 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3859:14:uxTaskGetStackHighWaterMark 32 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3887:14:prvDeleteTCB 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3943:13:prvResetNextTaskUnblockTime 16 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3969:15:xTaskGetCurrentTaskHandle 16 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3986:13:xTaskGetSchedulerState 16 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4014:13:xTaskPriorityInherit 24 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4104:13:xTaskPriorityDisinherit 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4184:7:vTaskPriorityDisinheritAfterTimeout 40 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4602:12:uxTaskResetEventItemValue 16 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4618:15:pvTaskIncrementMutexHeldCount 4 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4635:11:ulTaskNotifyTake 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4703:13:xTaskNotifyWait 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4783:13:xTaskGenericNotify 48 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4897:13:xTaskGenericNotifyFromISR 64 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:5026:7:vTaskNotifyGiveFromISR 48 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:5112:13:xTaskNotifyStateClear 24 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:5143:11:ulTaskNotifyValueClear 24 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:5177:13:prvAddCurrentTaskToDelayedList 24 static diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.cyclo b/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.cyclo new file mode 100644 index 0000000..036afef --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.cyclo @@ -0,0 +1,27 @@ +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:227:12:xTimerCreateTimerTask 4 +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:282:16:xTimerCreate 2 +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:309:16:xTimerCreateStatic 4 +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:349:13:prvInitialiseNewTimer 4 +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:381:12:xTimerGenericCommand 5 +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:424:14:xTimerGetTimerDaemonTaskHandle 2 +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:433:12:xTimerGetPeriod 2 +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:442:6:vTimerSetReloadMode 3 +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:462:13:uxTimerGetReloadMode 3 +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:487:12:xTimerGetExpiryTime 2 +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:498:14:pcTimerGetName 2 +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:507:13:prvProcessExpiredTimer 4 +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:548:8:prvTimerTask 1 +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:584:13:prvProcessTimerOrBlockTask 7 +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:644:19:prvGetNextExpireTime 3 +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:670:19:prvSampleTimeNow 2 +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:693:19:prvInsertTimerInActiveList 5 +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:734:13:prvProcessReceivedCommands 15 +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:882:13:prvSwitchTimerLists 5 +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:941:13:prvCheckForValidListAndQueue 3 +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:992:12:xTimerIsTimerActive 3 +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:1017:7:pvTimerGetTimerID 2 +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:1034:6:vTimerSetTimerID 2 +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:1050:13:xTimerPendFunctionCallFromISR 1 +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:1074:13:xTimerPendFunctionCall 2 +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:1103:14:uxTimerGetTimerNumber 1 +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:1113:7:vTimerSetTimerNumber 1 diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.d b/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.d new file mode 100644 index 0000000..221036f --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.d @@ -0,0 +1,26 @@ +Middlewares/Third_Party/FreeRTOS/Source/timers.o: \ + ../Middlewares/Third_Party/FreeRTOS/Source/timers.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.o new file mode 100644 index 0000000..7a262e3 Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.o differ diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.su new file mode 100644 index 0000000..3b652bc --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.su @@ -0,0 +1,27 @@ +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:227:12:xTimerCreateTimerTask 48 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:282:16:xTimerCreate 40 static +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:309:16:xTimerCreateStatic 48 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:349:13:prvInitialiseNewTimer 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:381:12:xTimerGenericCommand 48 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:424:14:xTimerGetTimerDaemonTaskHandle 16 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:433:12:xTimerGetPeriod 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:442:6:vTimerSetReloadMode 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:462:13:uxTimerGetReloadMode 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:487:12:xTimerGetExpiryTime 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:498:14:pcTimerGetName 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:507:13:prvProcessExpiredTimer 40 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:548:8:prvTimerTask 24 static +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:584:13:prvProcessTimerOrBlockTask 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:644:19:prvGetNextExpireTime 24 static +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:670:19:prvSampleTimeNow 24 static +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:693:19:prvInsertTimerInActiveList 32 static +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:734:13:prvProcessReceivedCommands 64 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:882:13:prvSwitchTimerLists 40 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:941:13:prvCheckForValidListAndQueue 16 static +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:992:12:xTimerIsTimerActive 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:1017:7:pvTimerGetTimerID 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:1034:6:vTimerSetTimerID 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:1050:13:xTimerPendFunctionCallFromISR 48 static +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:1074:13:xTimerPendFunctionCall 48 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:1103:14:uxTimerGetTimerNumber 16 static +../Middlewares/Third_Party/FreeRTOS/Source/timers.c:1113:7:vTimerSetTimerNumber 16 static diff --git a/Debug/can_logger.elf b/Debug/can_logger.elf new file mode 100755 index 0000000..46d9fde Binary files /dev/null and b/Debug/can_logger.elf differ diff --git a/Debug/can_logger.list b/Debug/can_logger.list new file mode 100644 index 0000000..90e5163 --- /dev/null +++ b/Debug/can_logger.list @@ -0,0 +1,15690 @@ + +can_logger.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 00000188 08000000 08000000 00001000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 00005a4c 08000190 08000190 00001190 2**4 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 00000180 08005bdc 08005bdc 00006bdc 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 08005d5c 08005d5c 00007060 2**0 + CONTENTS, READONLY + 4 .ARM 00000008 08005d5c 08005d5c 00006d5c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 5 .preinit_array 00000000 08005d64 08005d64 00007060 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000004 08005d64 08005d64 00006d64 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 7 .fini_array 00000004 08005d68 08005d68 00006d68 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 8 .data 00000060 20000000 08005d6c 00007000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .ccmram 00000000 10000000 10000000 00007060 2**0 + CONTENTS + 10 .bss 00004c68 20000060 20000060 00007060 2**2 + ALLOC + 11 ._user_heap_stack 00000600 20004cc8 20004cc8 00007060 2**0 + ALLOC + 12 .ARM.attributes 00000030 00000000 00000000 00007060 2**0 + CONTENTS, READONLY + 13 .debug_info 00016399 00000000 00000000 00007090 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 14 .debug_abbrev 000033aa 00000000 00000000 0001d429 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 15 .debug_aranges 00001398 00000000 00000000 000207d8 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 16 .debug_rnglists 00000f1d 00000000 00000000 00021b70 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 17 .debug_macro 00003316 00000000 00000000 00022a8d 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_line 000183ed 00000000 00000000 00025da3 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_str 000cc536 00000000 00000000 0003e190 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 20 .comment 00000043 00000000 00000000 0010a6c6 2**0 + CONTENTS, READONLY + 21 .debug_frame 0000519c 00000000 00000000 0010a70c 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 22 .debug_line_str 000000ba 00000000 00000000 0010f8a8 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +Disassembly of section .text: + +08000190 <__do_global_dtors_aux>: + 8000190: b510 push {r4, lr} + 8000192: 4c05 ldr r4, [pc, #20] @ (80001a8 <__do_global_dtors_aux+0x18>) + 8000194: 7823 ldrb r3, [r4, #0] + 8000196: b933 cbnz r3, 80001a6 <__do_global_dtors_aux+0x16> + 8000198: 4b04 ldr r3, [pc, #16] @ (80001ac <__do_global_dtors_aux+0x1c>) + 800019a: b113 cbz r3, 80001a2 <__do_global_dtors_aux+0x12> + 800019c: 4804 ldr r0, [pc, #16] @ (80001b0 <__do_global_dtors_aux+0x20>) + 800019e: f3af 8000 nop.w + 80001a2: 2301 movs r3, #1 + 80001a4: 7023 strb r3, [r4, #0] + 80001a6: bd10 pop {r4, pc} + 80001a8: 20000060 .word 0x20000060 + 80001ac: 00000000 .word 0x00000000 + 80001b0: 08005bc4 .word 0x08005bc4 + +080001b4 : + 80001b4: b508 push {r3, lr} + 80001b6: 4b03 ldr r3, [pc, #12] @ (80001c4 ) + 80001b8: b11b cbz r3, 80001c2 + 80001ba: 4903 ldr r1, [pc, #12] @ (80001c8 ) + 80001bc: 4803 ldr r0, [pc, #12] @ (80001cc ) + 80001be: f3af 8000 nop.w + 80001c2: bd08 pop {r3, pc} + 80001c4: 00000000 .word 0x00000000 + 80001c8: 20000064 .word 0x20000064 + 80001cc: 08005bc4 .word 0x08005bc4 + +080001d0 <__aeabi_uldivmod>: + 80001d0: b953 cbnz r3, 80001e8 <__aeabi_uldivmod+0x18> + 80001d2: b94a cbnz r2, 80001e8 <__aeabi_uldivmod+0x18> + 80001d4: 2900 cmp r1, #0 + 80001d6: bf08 it eq + 80001d8: 2800 cmpeq r0, #0 + 80001da: bf1c itt ne + 80001dc: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff + 80001e0: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff + 80001e4: f000 b988 b.w 80004f8 <__aeabi_idiv0> + 80001e8: f1ad 0c08 sub.w ip, sp, #8 + 80001ec: e96d ce04 strd ip, lr, [sp, #-16]! + 80001f0: f000 f806 bl 8000200 <__udivmoddi4> + 80001f4: f8dd e004 ldr.w lr, [sp, #4] + 80001f8: e9dd 2302 ldrd r2, r3, [sp, #8] + 80001fc: b004 add sp, #16 + 80001fe: 4770 bx lr + +08000200 <__udivmoddi4>: + 8000200: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 8000204: 9d08 ldr r5, [sp, #32] + 8000206: 460f mov r7, r1 + 8000208: 4604 mov r4, r0 + 800020a: 468c mov ip, r1 + 800020c: 2b00 cmp r3, #0 + 800020e: d148 bne.n 80002a2 <__udivmoddi4+0xa2> + 8000210: 428a cmp r2, r1 + 8000212: 4616 mov r6, r2 + 8000214: d961 bls.n 80002da <__udivmoddi4+0xda> + 8000216: fab2 f382 clz r3, r2 + 800021a: b14b cbz r3, 8000230 <__udivmoddi4+0x30> + 800021c: f1c3 0220 rsb r2, r3, #32 + 8000220: fa01 fc03 lsl.w ip, r1, r3 + 8000224: fa20 f202 lsr.w r2, r0, r2 + 8000228: 409e lsls r6, r3 + 800022a: ea42 0c0c orr.w ip, r2, ip + 800022e: 409c lsls r4, r3 + 8000230: ea4f 4e16 mov.w lr, r6, lsr #16 + 8000234: b2b7 uxth r7, r6 + 8000236: fbbc f1fe udiv r1, ip, lr + 800023a: 0c22 lsrs r2, r4, #16 + 800023c: fb0e cc11 mls ip, lr, r1, ip + 8000240: ea42 420c orr.w r2, r2, ip, lsl #16 + 8000244: fb01 f007 mul.w r0, r1, r7 + 8000248: 4290 cmp r0, r2 + 800024a: d909 bls.n 8000260 <__udivmoddi4+0x60> + 800024c: 18b2 adds r2, r6, r2 + 800024e: f101 3cff add.w ip, r1, #4294967295 @ 0xffffffff + 8000252: f080 80ee bcs.w 8000432 <__udivmoddi4+0x232> + 8000256: 4290 cmp r0, r2 + 8000258: f240 80eb bls.w 8000432 <__udivmoddi4+0x232> + 800025c: 3902 subs r1, #2 + 800025e: 4432 add r2, r6 + 8000260: 1a12 subs r2, r2, r0 + 8000262: b2a4 uxth r4, r4 + 8000264: fbb2 f0fe udiv r0, r2, lr + 8000268: fb0e 2210 mls r2, lr, r0, r2 + 800026c: ea44 4402 orr.w r4, r4, r2, lsl #16 + 8000270: fb00 f707 mul.w r7, r0, r7 + 8000274: 42a7 cmp r7, r4 + 8000276: d909 bls.n 800028c <__udivmoddi4+0x8c> + 8000278: 1934 adds r4, r6, r4 + 800027a: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff + 800027e: f080 80da bcs.w 8000436 <__udivmoddi4+0x236> + 8000282: 42a7 cmp r7, r4 + 8000284: f240 80d7 bls.w 8000436 <__udivmoddi4+0x236> + 8000288: 4434 add r4, r6 + 800028a: 3802 subs r0, #2 + 800028c: ea40 4001 orr.w r0, r0, r1, lsl #16 + 8000290: 1be4 subs r4, r4, r7 + 8000292: 2100 movs r1, #0 + 8000294: b11d cbz r5, 800029e <__udivmoddi4+0x9e> + 8000296: 40dc lsrs r4, r3 + 8000298: 2300 movs r3, #0 + 800029a: e9c5 4300 strd r4, r3, [r5] + 800029e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 80002a2: 428b cmp r3, r1 + 80002a4: d906 bls.n 80002b4 <__udivmoddi4+0xb4> + 80002a6: b10d cbz r5, 80002ac <__udivmoddi4+0xac> + 80002a8: e9c5 0100 strd r0, r1, [r5] + 80002ac: 2100 movs r1, #0 + 80002ae: 4608 mov r0, r1 + 80002b0: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 80002b4: fab3 f183 clz r1, r3 + 80002b8: 2900 cmp r1, #0 + 80002ba: d148 bne.n 800034e <__udivmoddi4+0x14e> + 80002bc: 42bb cmp r3, r7 + 80002be: d302 bcc.n 80002c6 <__udivmoddi4+0xc6> + 80002c0: 4282 cmp r2, r0 + 80002c2: f200 8107 bhi.w 80004d4 <__udivmoddi4+0x2d4> + 80002c6: 1a84 subs r4, r0, r2 + 80002c8: eb67 0203 sbc.w r2, r7, r3 + 80002cc: 2001 movs r0, #1 + 80002ce: 4694 mov ip, r2 + 80002d0: 2d00 cmp r5, #0 + 80002d2: d0e4 beq.n 800029e <__udivmoddi4+0x9e> + 80002d4: e9c5 4c00 strd r4, ip, [r5] + 80002d8: e7e1 b.n 800029e <__udivmoddi4+0x9e> + 80002da: 2a00 cmp r2, #0 + 80002dc: f000 8092 beq.w 8000404 <__udivmoddi4+0x204> + 80002e0: fab2 f382 clz r3, r2 + 80002e4: 2b00 cmp r3, #0 + 80002e6: f040 80a8 bne.w 800043a <__udivmoddi4+0x23a> + 80002ea: 1a8a subs r2, r1, r2 + 80002ec: ea4f 4e16 mov.w lr, r6, lsr #16 + 80002f0: fa1f fc86 uxth.w ip, r6 + 80002f4: 2101 movs r1, #1 + 80002f6: 0c20 lsrs r0, r4, #16 + 80002f8: fbb2 f7fe udiv r7, r2, lr + 80002fc: fb0e 2217 mls r2, lr, r7, r2 + 8000300: ea40 4202 orr.w r2, r0, r2, lsl #16 + 8000304: fb0c f007 mul.w r0, ip, r7 + 8000308: 4290 cmp r0, r2 + 800030a: d907 bls.n 800031c <__udivmoddi4+0x11c> + 800030c: 18b2 adds r2, r6, r2 + 800030e: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff + 8000312: d202 bcs.n 800031a <__udivmoddi4+0x11a> + 8000314: 4290 cmp r0, r2 + 8000316: f200 80e2 bhi.w 80004de <__udivmoddi4+0x2de> + 800031a: 4647 mov r7, r8 + 800031c: 1a12 subs r2, r2, r0 + 800031e: b2a4 uxth r4, r4 + 8000320: fbb2 f0fe udiv r0, r2, lr + 8000324: fb0e 2210 mls r2, lr, r0, r2 + 8000328: ea44 4402 orr.w r4, r4, r2, lsl #16 + 800032c: fb0c fc00 mul.w ip, ip, r0 + 8000330: 45a4 cmp ip, r4 + 8000332: d907 bls.n 8000344 <__udivmoddi4+0x144> + 8000334: 1934 adds r4, r6, r4 + 8000336: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff + 800033a: d202 bcs.n 8000342 <__udivmoddi4+0x142> + 800033c: 45a4 cmp ip, r4 + 800033e: f200 80cb bhi.w 80004d8 <__udivmoddi4+0x2d8> + 8000342: 4610 mov r0, r2 + 8000344: eba4 040c sub.w r4, r4, ip + 8000348: ea40 4007 orr.w r0, r0, r7, lsl #16 + 800034c: e7a2 b.n 8000294 <__udivmoddi4+0x94> + 800034e: f1c1 0620 rsb r6, r1, #32 + 8000352: 408b lsls r3, r1 + 8000354: fa22 fc06 lsr.w ip, r2, r6 + 8000358: ea4c 0c03 orr.w ip, ip, r3 + 800035c: fa07 f401 lsl.w r4, r7, r1 + 8000360: fa20 f306 lsr.w r3, r0, r6 + 8000364: 40f7 lsrs r7, r6 + 8000366: ea4f 491c mov.w r9, ip, lsr #16 + 800036a: 4323 orrs r3, r4 + 800036c: fa00 f801 lsl.w r8, r0, r1 + 8000370: fa1f fe8c uxth.w lr, ip + 8000374: fbb7 f0f9 udiv r0, r7, r9 + 8000378: 0c1c lsrs r4, r3, #16 + 800037a: fb09 7710 mls r7, r9, r0, r7 + 800037e: ea44 4407 orr.w r4, r4, r7, lsl #16 + 8000382: fb00 f70e mul.w r7, r0, lr + 8000386: 42a7 cmp r7, r4 + 8000388: fa02 f201 lsl.w r2, r2, r1 + 800038c: d90a bls.n 80003a4 <__udivmoddi4+0x1a4> + 800038e: eb1c 0404 adds.w r4, ip, r4 + 8000392: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff + 8000396: f080 809b bcs.w 80004d0 <__udivmoddi4+0x2d0> + 800039a: 42a7 cmp r7, r4 + 800039c: f240 8098 bls.w 80004d0 <__udivmoddi4+0x2d0> + 80003a0: 3802 subs r0, #2 + 80003a2: 4464 add r4, ip + 80003a4: 1be4 subs r4, r4, r7 + 80003a6: b29f uxth r7, r3 + 80003a8: fbb4 f3f9 udiv r3, r4, r9 + 80003ac: fb09 4413 mls r4, r9, r3, r4 + 80003b0: ea47 4404 orr.w r4, r7, r4, lsl #16 + 80003b4: fb03 fe0e mul.w lr, r3, lr + 80003b8: 45a6 cmp lr, r4 + 80003ba: d909 bls.n 80003d0 <__udivmoddi4+0x1d0> + 80003bc: eb1c 0404 adds.w r4, ip, r4 + 80003c0: f103 37ff add.w r7, r3, #4294967295 @ 0xffffffff + 80003c4: f080 8082 bcs.w 80004cc <__udivmoddi4+0x2cc> + 80003c8: 45a6 cmp lr, r4 + 80003ca: d97f bls.n 80004cc <__udivmoddi4+0x2cc> + 80003cc: 3b02 subs r3, #2 + 80003ce: 4464 add r4, ip + 80003d0: ea43 4000 orr.w r0, r3, r0, lsl #16 + 80003d4: eba4 040e sub.w r4, r4, lr + 80003d8: fba0 e702 umull lr, r7, r0, r2 + 80003dc: 42bc cmp r4, r7 + 80003de: 4673 mov r3, lr + 80003e0: 46b9 mov r9, r7 + 80003e2: d363 bcc.n 80004ac <__udivmoddi4+0x2ac> + 80003e4: d060 beq.n 80004a8 <__udivmoddi4+0x2a8> + 80003e6: b15d cbz r5, 8000400 <__udivmoddi4+0x200> + 80003e8: ebb8 0203 subs.w r2, r8, r3 + 80003ec: eb64 0409 sbc.w r4, r4, r9 + 80003f0: fa04 f606 lsl.w r6, r4, r6 + 80003f4: fa22 f301 lsr.w r3, r2, r1 + 80003f8: 431e orrs r6, r3 + 80003fa: 40cc lsrs r4, r1 + 80003fc: e9c5 6400 strd r6, r4, [r5] + 8000400: 2100 movs r1, #0 + 8000402: e74c b.n 800029e <__udivmoddi4+0x9e> + 8000404: 0862 lsrs r2, r4, #1 + 8000406: 0848 lsrs r0, r1, #1 + 8000408: ea42 71c1 orr.w r1, r2, r1, lsl #31 + 800040c: 0c0b lsrs r3, r1, #16 + 800040e: ea43 4300 orr.w r3, r3, r0, lsl #16 + 8000412: b28a uxth r2, r1 + 8000414: ea42 4203 orr.w r2, r2, r3, lsl #16 + 8000418: fbb3 f1f6 udiv r1, r3, r6 + 800041c: 07e4 lsls r4, r4, #31 + 800041e: 46b4 mov ip, r6 + 8000420: 4637 mov r7, r6 + 8000422: 46b6 mov lr, r6 + 8000424: 231f movs r3, #31 + 8000426: fbb0 f0f6 udiv r0, r0, r6 + 800042a: 1bd2 subs r2, r2, r7 + 800042c: ea41 4100 orr.w r1, r1, r0, lsl #16 + 8000430: e761 b.n 80002f6 <__udivmoddi4+0xf6> + 8000432: 4661 mov r1, ip + 8000434: e714 b.n 8000260 <__udivmoddi4+0x60> + 8000436: 4610 mov r0, r2 + 8000438: e728 b.n 800028c <__udivmoddi4+0x8c> + 800043a: f1c3 0120 rsb r1, r3, #32 + 800043e: fa20 f201 lsr.w r2, r0, r1 + 8000442: 409e lsls r6, r3 + 8000444: fa27 f101 lsr.w r1, r7, r1 + 8000448: 409f lsls r7, r3 + 800044a: 433a orrs r2, r7 + 800044c: ea4f 4e16 mov.w lr, r6, lsr #16 + 8000450: fa1f fc86 uxth.w ip, r6 + 8000454: fbb1 f7fe udiv r7, r1, lr + 8000458: fb0e 1017 mls r0, lr, r7, r1 + 800045c: 0c11 lsrs r1, r2, #16 + 800045e: ea41 4100 orr.w r1, r1, r0, lsl #16 + 8000462: fb07 f80c mul.w r8, r7, ip + 8000466: 4588 cmp r8, r1 + 8000468: fa04 f403 lsl.w r4, r4, r3 + 800046c: d93a bls.n 80004e4 <__udivmoddi4+0x2e4> + 800046e: 1871 adds r1, r6, r1 + 8000470: f107 30ff add.w r0, r7, #4294967295 @ 0xffffffff + 8000474: d201 bcs.n 800047a <__udivmoddi4+0x27a> + 8000476: 4588 cmp r8, r1 + 8000478: d81f bhi.n 80004ba <__udivmoddi4+0x2ba> + 800047a: eba1 0108 sub.w r1, r1, r8 + 800047e: fbb1 f8fe udiv r8, r1, lr + 8000482: fb08 f70c mul.w r7, r8, ip + 8000486: fb0e 1118 mls r1, lr, r8, r1 + 800048a: b292 uxth r2, r2 + 800048c: ea42 4201 orr.w r2, r2, r1, lsl #16 + 8000490: 42ba cmp r2, r7 + 8000492: d22f bcs.n 80004f4 <__udivmoddi4+0x2f4> + 8000494: 18b2 adds r2, r6, r2 + 8000496: f108 31ff add.w r1, r8, #4294967295 @ 0xffffffff + 800049a: d2c6 bcs.n 800042a <__udivmoddi4+0x22a> + 800049c: 42ba cmp r2, r7 + 800049e: d2c4 bcs.n 800042a <__udivmoddi4+0x22a> + 80004a0: f1a8 0102 sub.w r1, r8, #2 + 80004a4: 4432 add r2, r6 + 80004a6: e7c0 b.n 800042a <__udivmoddi4+0x22a> + 80004a8: 45f0 cmp r8, lr + 80004aa: d29c bcs.n 80003e6 <__udivmoddi4+0x1e6> + 80004ac: ebbe 0302 subs.w r3, lr, r2 + 80004b0: eb67 070c sbc.w r7, r7, ip + 80004b4: 3801 subs r0, #1 + 80004b6: 46b9 mov r9, r7 + 80004b8: e795 b.n 80003e6 <__udivmoddi4+0x1e6> + 80004ba: eba6 0808 sub.w r8, r6, r8 + 80004be: 4441 add r1, r8 + 80004c0: 1eb8 subs r0, r7, #2 + 80004c2: fbb1 f8fe udiv r8, r1, lr + 80004c6: fb08 f70c mul.w r7, r8, ip + 80004ca: e7dc b.n 8000486 <__udivmoddi4+0x286> + 80004cc: 463b mov r3, r7 + 80004ce: e77f b.n 80003d0 <__udivmoddi4+0x1d0> + 80004d0: 4650 mov r0, sl + 80004d2: e767 b.n 80003a4 <__udivmoddi4+0x1a4> + 80004d4: 4608 mov r0, r1 + 80004d6: e6fb b.n 80002d0 <__udivmoddi4+0xd0> + 80004d8: 4434 add r4, r6 + 80004da: 3802 subs r0, #2 + 80004dc: e732 b.n 8000344 <__udivmoddi4+0x144> + 80004de: 3f02 subs r7, #2 + 80004e0: 4432 add r2, r6 + 80004e2: e71b b.n 800031c <__udivmoddi4+0x11c> + 80004e4: eba1 0108 sub.w r1, r1, r8 + 80004e8: 4638 mov r0, r7 + 80004ea: fbb1 f8fe udiv r8, r1, lr + 80004ee: fb08 f70c mul.w r7, r8, ip + 80004f2: e7c8 b.n 8000486 <__udivmoddi4+0x286> + 80004f4: 4641 mov r1, r8 + 80004f6: e798 b.n 800042a <__udivmoddi4+0x22a> + +080004f8 <__aeabi_idiv0>: + 80004f8: 4770 bx lr + 80004fa: bf00 nop + +080004fc
: +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + 80004fc: b580 push {r7, lr} + 80004fe: af00 add r7, sp, #0 + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 8000500: f000 fbe0 bl 8000cc4 + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 8000504: f000 f81a bl 800053c + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 8000508: f000 f8de bl 80006c8 + MX_CAN1_Init(); + 800050c: f000 f874 bl 80005f8 + MX_CAN2_Init(); + 8000510: f000 f8a6 bl 8000660 + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /* Init scheduler */ + osKernelInitialize(); + 8000514: f002 fcbc bl 8002e90 + /* add queues, ... */ + /* USER CODE END RTOS_QUEUES */ + + /* Create the thread(s) */ + /* creation of defaultTask */ + defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes); + 8000518: 4a05 ldr r2, [pc, #20] @ (8000530 ) + 800051a: 2100 movs r1, #0 + 800051c: 4805 ldr r0, [pc, #20] @ (8000534 ) + 800051e: f002 fd01 bl 8002f24 + 8000522: 4603 mov r3, r0 + 8000524: 4a04 ldr r2, [pc, #16] @ (8000538 ) + 8000526: 6013 str r3, [r2, #0] + /* USER CODE BEGIN RTOS_EVENTS */ + /* add events, ... */ + /* USER CODE END RTOS_EVENTS */ + + /* Start scheduler */ + osKernelStart(); + 8000528: f002 fcd6 bl 8002ed8 + + /* We should never get here as control is now taken by the scheduler */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + 800052c: bf00 nop + 800052e: e7fd b.n 800052c + 8000530: 08005d20 .word 0x08005d20 + 8000534: 08000809 .word 0x08000809 + 8000538: 20000144 .word 0x20000144 + +0800053c : +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 800053c: b580 push {r7, lr} + 800053e: b094 sub sp, #80 @ 0x50 + 8000540: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 8000542: f107 0320 add.w r3, r7, #32 + 8000546: 2230 movs r2, #48 @ 0x30 + 8000548: 2100 movs r1, #0 + 800054a: 4618 mov r0, r3 + 800054c: f005 fa58 bl 8005a00 + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 8000550: f107 030c add.w r3, r7, #12 + 8000554: 2200 movs r2, #0 + 8000556: 601a str r2, [r3, #0] + 8000558: 605a str r2, [r3, #4] + 800055a: 609a str r2, [r3, #8] + 800055c: 60da str r2, [r3, #12] + 800055e: 611a str r2, [r3, #16] + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + 8000560: 2300 movs r3, #0 + 8000562: 60bb str r3, [r7, #8] + 8000564: 4b22 ldr r3, [pc, #136] @ (80005f0 ) + 8000566: 6c1b ldr r3, [r3, #64] @ 0x40 + 8000568: 4a21 ldr r2, [pc, #132] @ (80005f0 ) + 800056a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 800056e: 6413 str r3, [r2, #64] @ 0x40 + 8000570: 4b1f ldr r3, [pc, #124] @ (80005f0 ) + 8000572: 6c1b ldr r3, [r3, #64] @ 0x40 + 8000574: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8000578: 60bb str r3, [r7, #8] + 800057a: 68bb ldr r3, [r7, #8] + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 800057c: 2300 movs r3, #0 + 800057e: 607b str r3, [r7, #4] + 8000580: 4b1c ldr r3, [pc, #112] @ (80005f4 ) + 8000582: 681b ldr r3, [r3, #0] + 8000584: 4a1b ldr r2, [pc, #108] @ (80005f4 ) + 8000586: f443 4380 orr.w r3, r3, #16384 @ 0x4000 + 800058a: 6013 str r3, [r2, #0] + 800058c: 4b19 ldr r3, [pc, #100] @ (80005f4 ) + 800058e: 681b ldr r3, [r3, #0] + 8000590: f403 4380 and.w r3, r3, #16384 @ 0x4000 + 8000594: 607b str r3, [r7, #4] + 8000596: 687b ldr r3, [r7, #4] + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + 8000598: 2302 movs r3, #2 + 800059a: 623b str r3, [r7, #32] + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + 800059c: 2301 movs r3, #1 + 800059e: 62fb str r3, [r7, #44] @ 0x2c + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 80005a0: 2310 movs r3, #16 + 80005a2: 633b str r3, [r7, #48] @ 0x30 + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + 80005a4: 2300 movs r3, #0 + 80005a6: 63bb str r3, [r7, #56] @ 0x38 + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 80005a8: f107 0320 add.w r3, r7, #32 + 80005ac: 4618 mov r0, r3 + 80005ae: f001 fa9d bl 8001aec + 80005b2: 4603 mov r3, r0 + 80005b4: 2b00 cmp r3, #0 + 80005b6: d001 beq.n 80005bc + { + Error_Handler(); + 80005b8: f000 f940 bl 800083c + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 80005bc: 230f movs r3, #15 + 80005be: 60fb str r3, [r7, #12] + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + 80005c0: 2300 movs r3, #0 + 80005c2: 613b str r3, [r7, #16] + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 80005c4: 2300 movs r3, #0 + 80005c6: 617b str r3, [r7, #20] + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 80005c8: 2300 movs r3, #0 + 80005ca: 61bb str r3, [r7, #24] + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 80005cc: 2300 movs r3, #0 + 80005ce: 61fb str r3, [r7, #28] + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + 80005d0: f107 030c add.w r3, r7, #12 + 80005d4: 2100 movs r1, #0 + 80005d6: 4618 mov r0, r3 + 80005d8: f001 fdb4 bl 8002144 + 80005dc: 4603 mov r3, r0 + 80005de: 2b00 cmp r3, #0 + 80005e0: d001 beq.n 80005e6 + { + Error_Handler(); + 80005e2: f000 f92b bl 800083c + } +} + 80005e6: bf00 nop + 80005e8: 3750 adds r7, #80 @ 0x50 + 80005ea: 46bd mov sp, r7 + 80005ec: bd80 pop {r7, pc} + 80005ee: bf00 nop + 80005f0: 40023800 .word 0x40023800 + 80005f4: 40007000 .word 0x40007000 + +080005f8 : + * @brief CAN1 Initialization Function + * @param None + * @retval None + */ +static void MX_CAN1_Init(void) +{ + 80005f8: b580 push {r7, lr} + 80005fa: af00 add r7, sp, #0 + /* USER CODE END CAN1_Init 0 */ + + /* USER CODE BEGIN CAN1_Init 1 */ + + /* USER CODE END CAN1_Init 1 */ + hcan1.Instance = CAN1; + 80005fc: 4b16 ldr r3, [pc, #88] @ (8000658 ) + 80005fe: 4a17 ldr r2, [pc, #92] @ (800065c ) + 8000600: 601a str r2, [r3, #0] + hcan1.Init.Prescaler = 16; + 8000602: 4b15 ldr r3, [pc, #84] @ (8000658 ) + 8000604: 2210 movs r2, #16 + 8000606: 605a str r2, [r3, #4] + hcan1.Init.Mode = CAN_MODE_NORMAL; + 8000608: 4b13 ldr r3, [pc, #76] @ (8000658 ) + 800060a: 2200 movs r2, #0 + 800060c: 609a str r2, [r3, #8] + hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ; + 800060e: 4b12 ldr r3, [pc, #72] @ (8000658 ) + 8000610: 2200 movs r2, #0 + 8000612: 60da str r2, [r3, #12] + hcan1.Init.TimeSeg1 = CAN_BS1_1TQ; + 8000614: 4b10 ldr r3, [pc, #64] @ (8000658 ) + 8000616: 2200 movs r2, #0 + 8000618: 611a str r2, [r3, #16] + hcan1.Init.TimeSeg2 = CAN_BS2_1TQ; + 800061a: 4b0f ldr r3, [pc, #60] @ (8000658 ) + 800061c: 2200 movs r2, #0 + 800061e: 615a str r2, [r3, #20] + hcan1.Init.TimeTriggeredMode = DISABLE; + 8000620: 4b0d ldr r3, [pc, #52] @ (8000658 ) + 8000622: 2200 movs r2, #0 + 8000624: 761a strb r2, [r3, #24] + hcan1.Init.AutoBusOff = DISABLE; + 8000626: 4b0c ldr r3, [pc, #48] @ (8000658 ) + 8000628: 2200 movs r2, #0 + 800062a: 765a strb r2, [r3, #25] + hcan1.Init.AutoWakeUp = DISABLE; + 800062c: 4b0a ldr r3, [pc, #40] @ (8000658 ) + 800062e: 2200 movs r2, #0 + 8000630: 769a strb r2, [r3, #26] + hcan1.Init.AutoRetransmission = DISABLE; + 8000632: 4b09 ldr r3, [pc, #36] @ (8000658 ) + 8000634: 2200 movs r2, #0 + 8000636: 76da strb r2, [r3, #27] + hcan1.Init.ReceiveFifoLocked = DISABLE; + 8000638: 4b07 ldr r3, [pc, #28] @ (8000658 ) + 800063a: 2200 movs r2, #0 + 800063c: 771a strb r2, [r3, #28] + hcan1.Init.TransmitFifoPriority = DISABLE; + 800063e: 4b06 ldr r3, [pc, #24] @ (8000658 ) + 8000640: 2200 movs r2, #0 + 8000642: 775a strb r2, [r3, #29] + if (HAL_CAN_Init(&hcan1) != HAL_OK) + 8000644: 4804 ldr r0, [pc, #16] @ (8000658 ) + 8000646: f000 fb7f bl 8000d48 + 800064a: 4603 mov r3, r0 + 800064c: 2b00 cmp r3, #0 + 800064e: d001 beq.n 8000654 + { + Error_Handler(); + 8000650: f000 f8f4 bl 800083c + } + /* USER CODE BEGIN CAN1_Init 2 */ + + /* USER CODE END CAN1_Init 2 */ + +} + 8000654: bf00 nop + 8000656: bd80 pop {r7, pc} + 8000658: 2000007c .word 0x2000007c + 800065c: 40006400 .word 0x40006400 + +08000660 : + * @brief CAN2 Initialization Function + * @param None + * @retval None + */ +static void MX_CAN2_Init(void) +{ + 8000660: b580 push {r7, lr} + 8000662: af00 add r7, sp, #0 + /* USER CODE END CAN2_Init 0 */ + + /* USER CODE BEGIN CAN2_Init 1 */ + + /* USER CODE END CAN2_Init 1 */ + hcan2.Instance = CAN2; + 8000664: 4b16 ldr r3, [pc, #88] @ (80006c0 ) + 8000666: 4a17 ldr r2, [pc, #92] @ (80006c4 ) + 8000668: 601a str r2, [r3, #0] + hcan2.Init.Prescaler = 16; + 800066a: 4b15 ldr r3, [pc, #84] @ (80006c0 ) + 800066c: 2210 movs r2, #16 + 800066e: 605a str r2, [r3, #4] + hcan2.Init.Mode = CAN_MODE_NORMAL; + 8000670: 4b13 ldr r3, [pc, #76] @ (80006c0 ) + 8000672: 2200 movs r2, #0 + 8000674: 609a str r2, [r3, #8] + hcan2.Init.SyncJumpWidth = CAN_SJW_1TQ; + 8000676: 4b12 ldr r3, [pc, #72] @ (80006c0 ) + 8000678: 2200 movs r2, #0 + 800067a: 60da str r2, [r3, #12] + hcan2.Init.TimeSeg1 = CAN_BS1_1TQ; + 800067c: 4b10 ldr r3, [pc, #64] @ (80006c0 ) + 800067e: 2200 movs r2, #0 + 8000680: 611a str r2, [r3, #16] + hcan2.Init.TimeSeg2 = CAN_BS2_1TQ; + 8000682: 4b0f ldr r3, [pc, #60] @ (80006c0 ) + 8000684: 2200 movs r2, #0 + 8000686: 615a str r2, [r3, #20] + hcan2.Init.TimeTriggeredMode = DISABLE; + 8000688: 4b0d ldr r3, [pc, #52] @ (80006c0 ) + 800068a: 2200 movs r2, #0 + 800068c: 761a strb r2, [r3, #24] + hcan2.Init.AutoBusOff = DISABLE; + 800068e: 4b0c ldr r3, [pc, #48] @ (80006c0 ) + 8000690: 2200 movs r2, #0 + 8000692: 765a strb r2, [r3, #25] + hcan2.Init.AutoWakeUp = DISABLE; + 8000694: 4b0a ldr r3, [pc, #40] @ (80006c0 ) + 8000696: 2200 movs r2, #0 + 8000698: 769a strb r2, [r3, #26] + hcan2.Init.AutoRetransmission = DISABLE; + 800069a: 4b09 ldr r3, [pc, #36] @ (80006c0 ) + 800069c: 2200 movs r2, #0 + 800069e: 76da strb r2, [r3, #27] + hcan2.Init.ReceiveFifoLocked = DISABLE; + 80006a0: 4b07 ldr r3, [pc, #28] @ (80006c0 ) + 80006a2: 2200 movs r2, #0 + 80006a4: 771a strb r2, [r3, #28] + hcan2.Init.TransmitFifoPriority = DISABLE; + 80006a6: 4b06 ldr r3, [pc, #24] @ (80006c0 ) + 80006a8: 2200 movs r2, #0 + 80006aa: 775a strb r2, [r3, #29] + if (HAL_CAN_Init(&hcan2) != HAL_OK) + 80006ac: 4804 ldr r0, [pc, #16] @ (80006c0 ) + 80006ae: f000 fb4b bl 8000d48 + 80006b2: 4603 mov r3, r0 + 80006b4: 2b00 cmp r3, #0 + 80006b6: d001 beq.n 80006bc + { + Error_Handler(); + 80006b8: f000 f8c0 bl 800083c + } + /* USER CODE BEGIN CAN2_Init 2 */ + + /* USER CODE END CAN2_Init 2 */ + +} + 80006bc: bf00 nop + 80006be: bd80 pop {r7, pc} + 80006c0: 200000e0 .word 0x200000e0 + 80006c4: 40006800 .word 0x40006800 + +080006c8 : + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + 80006c8: b580 push {r7, lr} + 80006ca: b08a sub sp, #40 @ 0x28 + 80006cc: af00 add r7, sp, #0 + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 80006ce: f107 0314 add.w r3, r7, #20 + 80006d2: 2200 movs r2, #0 + 80006d4: 601a str r2, [r3, #0] + 80006d6: 605a str r2, [r3, #4] + 80006d8: 609a str r2, [r3, #8] + 80006da: 60da str r2, [r3, #12] + 80006dc: 611a str r2, [r3, #16] + /* USER CODE BEGIN MX_GPIO_Init_1 */ + + /* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + 80006de: 2300 movs r3, #0 + 80006e0: 613b str r3, [r7, #16] + 80006e2: 4b43 ldr r3, [pc, #268] @ (80007f0 ) + 80006e4: 6b1b ldr r3, [r3, #48] @ 0x30 + 80006e6: 4a42 ldr r2, [pc, #264] @ (80007f0 ) + 80006e8: f043 0304 orr.w r3, r3, #4 + 80006ec: 6313 str r3, [r2, #48] @ 0x30 + 80006ee: 4b40 ldr r3, [pc, #256] @ (80007f0 ) + 80006f0: 6b1b ldr r3, [r3, #48] @ 0x30 + 80006f2: f003 0304 and.w r3, r3, #4 + 80006f6: 613b str r3, [r7, #16] + 80006f8: 693b ldr r3, [r7, #16] + __HAL_RCC_GPIOH_CLK_ENABLE(); + 80006fa: 2300 movs r3, #0 + 80006fc: 60fb str r3, [r7, #12] + 80006fe: 4b3c ldr r3, [pc, #240] @ (80007f0 ) + 8000700: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000702: 4a3b ldr r2, [pc, #236] @ (80007f0 ) + 8000704: f043 0380 orr.w r3, r3, #128 @ 0x80 + 8000708: 6313 str r3, [r2, #48] @ 0x30 + 800070a: 4b39 ldr r3, [pc, #228] @ (80007f0 ) + 800070c: 6b1b ldr r3, [r3, #48] @ 0x30 + 800070e: f003 0380 and.w r3, r3, #128 @ 0x80 + 8000712: 60fb str r3, [r7, #12] + 8000714: 68fb ldr r3, [r7, #12] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8000716: 2300 movs r3, #0 + 8000718: 60bb str r3, [r7, #8] + 800071a: 4b35 ldr r3, [pc, #212] @ (80007f0 ) + 800071c: 6b1b ldr r3, [r3, #48] @ 0x30 + 800071e: 4a34 ldr r2, [pc, #208] @ (80007f0 ) + 8000720: f043 0301 orr.w r3, r3, #1 + 8000724: 6313 str r3, [r2, #48] @ 0x30 + 8000726: 4b32 ldr r3, [pc, #200] @ (80007f0 ) + 8000728: 6b1b ldr r3, [r3, #48] @ 0x30 + 800072a: f003 0301 and.w r3, r3, #1 + 800072e: 60bb str r3, [r7, #8] + 8000730: 68bb ldr r3, [r7, #8] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8000732: 2300 movs r3, #0 + 8000734: 607b str r3, [r7, #4] + 8000736: 4b2e ldr r3, [pc, #184] @ (80007f0 ) + 8000738: 6b1b ldr r3, [r3, #48] @ 0x30 + 800073a: 4a2d ldr r2, [pc, #180] @ (80007f0 ) + 800073c: f043 0302 orr.w r3, r3, #2 + 8000740: 6313 str r3, [r2, #48] @ 0x30 + 8000742: 4b2b ldr r3, [pc, #172] @ (80007f0 ) + 8000744: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000746: f003 0302 and.w r3, r3, #2 + 800074a: 607b str r3, [r7, #4] + 800074c: 687b ldr r3, [r7, #4] + __HAL_RCC_GPIOD_CLK_ENABLE(); + 800074e: 2300 movs r3, #0 + 8000750: 603b str r3, [r7, #0] + 8000752: 4b27 ldr r3, [pc, #156] @ (80007f0 ) + 8000754: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000756: 4a26 ldr r2, [pc, #152] @ (80007f0 ) + 8000758: f043 0308 orr.w r3, r3, #8 + 800075c: 6313 str r3, [r2, #48] @ 0x30 + 800075e: 4b24 ldr r3, [pc, #144] @ (80007f0 ) + 8000760: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000762: f003 0308 and.w r3, r3, #8 + 8000766: 603b str r3, [r7, #0] + 8000768: 683b ldr r3, [r7, #0] + + /*Configure GPIO pins : PC13 PC14 PC15 PC0 + PC1 PC2 PC3 PC4 + PC5 PC6 PC7 PC8 + PC9 PC10 PC11 PC12 */ + GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15|GPIO_PIN_0 + 800076a: f64f 73ff movw r3, #65535 @ 0xffff + 800076e: 617b str r3, [r7, #20] + |GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4 + |GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8 + |GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 8000770: 2303 movs r3, #3 + 8000772: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000774: 2300 movs r3, #0 + 8000776: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 8000778: f107 0314 add.w r3, r7, #20 + 800077c: 4619 mov r1, r3 + 800077e: 481d ldr r0, [pc, #116] @ (80007f4 ) + 8000780: f000 fee0 bl 8001544 + + /*Configure GPIO pins : PH0 PH1 */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; + 8000784: 2303 movs r3, #3 + 8000786: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 8000788: 2303 movs r3, #3 + 800078a: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800078c: 2300 movs r3, #0 + 800078e: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + 8000790: f107 0314 add.w r3, r7, #20 + 8000794: 4619 mov r1, r3 + 8000796: 4818 ldr r0, [pc, #96] @ (80007f8 ) + 8000798: f000 fed4 bl 8001544 + + /*Configure GPIO pins : PA0 PA1 PA2 PA3 + PA4 PA5 PA6 PA7 + PA8 PA9 PA10 PA11 + PA12 PA13 PA14 PA15 */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + 800079c: f64f 73ff movw r3, #65535 @ 0xffff + 80007a0: 617b str r3, [r7, #20] + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7 + |GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 80007a2: 2303 movs r3, #3 + 80007a4: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80007a6: 2300 movs r3, #0 + 80007a8: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80007aa: f107 0314 add.w r3, r7, #20 + 80007ae: 4619 mov r1, r3 + 80007b0: 4812 ldr r0, [pc, #72] @ (80007fc ) + 80007b2: f000 fec7 bl 8001544 + + /*Configure GPIO pins : PB0 PB1 PB2 PB10 + PB11 PB14 PB15 PB3 + PB4 PB5 PB6 PB7 */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10 + 80007b6: f64c 43ff movw r3, #52479 @ 0xccff + 80007ba: 617b str r3, [r7, #20] + |GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_15|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 80007bc: 2303 movs r3, #3 + 80007be: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80007c0: 2300 movs r3, #0 + 80007c2: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 80007c4: f107 0314 add.w r3, r7, #20 + 80007c8: 4619 mov r1, r3 + 80007ca: 480d ldr r0, [pc, #52] @ (8000800 ) + 80007cc: f000 feba bl 8001544 + + /*Configure GPIO pin : PD2 */ + GPIO_InitStruct.Pin = GPIO_PIN_2; + 80007d0: 2304 movs r3, #4 + 80007d2: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 80007d4: 2303 movs r3, #3 + 80007d6: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80007d8: 2300 movs r3, #0 + 80007da: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + 80007dc: f107 0314 add.w r3, r7, #20 + 80007e0: 4619 mov r1, r3 + 80007e2: 4808 ldr r0, [pc, #32] @ (8000804 ) + 80007e4: f000 feae bl 8001544 + + /* USER CODE BEGIN MX_GPIO_Init_2 */ + + /* USER CODE END MX_GPIO_Init_2 */ +} + 80007e8: bf00 nop + 80007ea: 3728 adds r7, #40 @ 0x28 + 80007ec: 46bd mov sp, r7 + 80007ee: bd80 pop {r7, pc} + 80007f0: 40023800 .word 0x40023800 + 80007f4: 40020800 .word 0x40020800 + 80007f8: 40021c00 .word 0x40021c00 + 80007fc: 40020000 .word 0x40020000 + 8000800: 40020400 .word 0x40020400 + 8000804: 40020c00 .word 0x40020c00 + +08000808 : + * @param argument: Not used + * @retval None + */ +/* USER CODE END Header_StartDefaultTask */ +void StartDefaultTask(void *argument) +{ + 8000808: b580 push {r7, lr} + 800080a: b082 sub sp, #8 + 800080c: af00 add r7, sp, #0 + 800080e: 6078 str r0, [r7, #4] + /* USER CODE BEGIN 5 */ + /* Infinite loop */ + for(;;) + { + osDelay(1); + 8000810: 2001 movs r0, #1 + 8000812: f002 fc19 bl 8003048 + 8000816: e7fb b.n 8000810 + +08000818 : + * a global variable "uwTick" used as application time base. + * @param htim : TIM handle + * @retval None + */ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + 8000818: b580 push {r7, lr} + 800081a: b082 sub sp, #8 + 800081c: af00 add r7, sp, #0 + 800081e: 6078 str r0, [r7, #4] + /* USER CODE BEGIN Callback 0 */ + + /* USER CODE END Callback 0 */ + if (htim->Instance == TIM6) + 8000820: 687b ldr r3, [r7, #4] + 8000822: 681b ldr r3, [r3, #0] + 8000824: 4a04 ldr r2, [pc, #16] @ (8000838 ) + 8000826: 4293 cmp r3, r2 + 8000828: d101 bne.n 800082e + { + HAL_IncTick(); + 800082a: f000 fa6d bl 8000d08 + } + /* USER CODE BEGIN Callback 1 */ + + /* USER CODE END Callback 1 */ +} + 800082e: bf00 nop + 8000830: 3708 adds r7, #8 + 8000832: 46bd mov sp, r7 + 8000834: bd80 pop {r7, pc} + 8000836: bf00 nop + 8000838: 40001000 .word 0x40001000 + +0800083c : +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + 800083c: b480 push {r7} + 800083e: af00 add r7, sp, #0 + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); + 8000840: b672 cpsid i +} + 8000842: bf00 nop + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + 8000844: bf00 nop + 8000846: e7fd b.n 8000844 + +08000848 : + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + 8000848: b480 push {r7} + 800084a: b083 sub sp, #12 + 800084c: af00 add r7, sp, #0 + 800084e: 6078 str r0, [r7, #4] + 8000850: 6039 str r1, [r7, #0] + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} + 8000852: bf00 nop + 8000854: 370c adds r7, #12 + 8000856: 46bd mov sp, r7 + 8000858: f85d 7b04 ldr.w r7, [sp], #4 + 800085c: 4770 bx lr + ... + +08000860 : +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 8000860: b580 push {r7, lr} + 8000862: b082 sub sp, #8 + 8000864: af00 add r7, sp, #0 + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8000866: 2300 movs r3, #0 + 8000868: 607b str r3, [r7, #4] + 800086a: 4b12 ldr r3, [pc, #72] @ (80008b4 ) + 800086c: 6c5b ldr r3, [r3, #68] @ 0x44 + 800086e: 4a11 ldr r2, [pc, #68] @ (80008b4 ) + 8000870: f443 4380 orr.w r3, r3, #16384 @ 0x4000 + 8000874: 6453 str r3, [r2, #68] @ 0x44 + 8000876: 4b0f ldr r3, [pc, #60] @ (80008b4 ) + 8000878: 6c5b ldr r3, [r3, #68] @ 0x44 + 800087a: f403 4380 and.w r3, r3, #16384 @ 0x4000 + 800087e: 607b str r3, [r7, #4] + 8000880: 687b ldr r3, [r7, #4] + __HAL_RCC_PWR_CLK_ENABLE(); + 8000882: 2300 movs r3, #0 + 8000884: 603b str r3, [r7, #0] + 8000886: 4b0b ldr r3, [pc, #44] @ (80008b4 ) + 8000888: 6c1b ldr r3, [r3, #64] @ 0x40 + 800088a: 4a0a ldr r2, [pc, #40] @ (80008b4 ) + 800088c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8000890: 6413 str r3, [r2, #64] @ 0x40 + 8000892: 4b08 ldr r3, [pc, #32] @ (80008b4 ) + 8000894: 6c1b ldr r3, [r3, #64] @ 0x40 + 8000896: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 800089a: 603b str r3, [r7, #0] + 800089c: 683b ldr r3, [r7, #0] + + /* System interrupt init*/ + /* PendSV_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); + 800089e: 2200 movs r2, #0 + 80008a0: 210f movs r1, #15 + 80008a2: f06f 0001 mvn.w r0, #1 + 80008a6: f000 fe09 bl 80014bc + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 80008aa: bf00 nop + 80008ac: 3708 adds r7, #8 + 80008ae: 46bd mov sp, r7 + 80008b0: bd80 pop {r7, pc} + 80008b2: bf00 nop + 80008b4: 40023800 .word 0x40023800 + +080008b8 : + * This function configures the hardware resources used in this example + * @param hcan: CAN handle pointer + * @retval None + */ +void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) +{ + 80008b8: b580 push {r7, lr} + 80008ba: b08c sub sp, #48 @ 0x30 + 80008bc: af00 add r7, sp, #0 + 80008be: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 80008c0: f107 031c add.w r3, r7, #28 + 80008c4: 2200 movs r2, #0 + 80008c6: 601a str r2, [r3, #0] + 80008c8: 605a str r2, [r3, #4] + 80008ca: 609a str r2, [r3, #8] + 80008cc: 60da str r2, [r3, #12] + 80008ce: 611a str r2, [r3, #16] + if(hcan->Instance==CAN1) + 80008d0: 687b ldr r3, [r7, #4] + 80008d2: 681b ldr r3, [r3, #0] + 80008d4: 4a43 ldr r2, [pc, #268] @ (80009e4 ) + 80008d6: 4293 cmp r3, r2 + 80008d8: d136 bne.n 8000948 + { + /* USER CODE BEGIN CAN1_MspInit 0 */ + + /* USER CODE END CAN1_MspInit 0 */ + /* Peripheral clock enable */ + HAL_RCC_CAN1_CLK_ENABLED++; + 80008da: 4b43 ldr r3, [pc, #268] @ (80009e8 ) + 80008dc: 681b ldr r3, [r3, #0] + 80008de: 3301 adds r3, #1 + 80008e0: 4a41 ldr r2, [pc, #260] @ (80009e8 ) + 80008e2: 6013 str r3, [r2, #0] + if(HAL_RCC_CAN1_CLK_ENABLED==1){ + 80008e4: 4b40 ldr r3, [pc, #256] @ (80009e8 ) + 80008e6: 681b ldr r3, [r3, #0] + 80008e8: 2b01 cmp r3, #1 + 80008ea: d10d bne.n 8000908 + __HAL_RCC_CAN1_CLK_ENABLE(); + 80008ec: 2300 movs r3, #0 + 80008ee: 61bb str r3, [r7, #24] + 80008f0: 4b3e ldr r3, [pc, #248] @ (80009ec ) + 80008f2: 6c1b ldr r3, [r3, #64] @ 0x40 + 80008f4: 4a3d ldr r2, [pc, #244] @ (80009ec ) + 80008f6: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 + 80008fa: 6413 str r3, [r2, #64] @ 0x40 + 80008fc: 4b3b ldr r3, [pc, #236] @ (80009ec ) + 80008fe: 6c1b ldr r3, [r3, #64] @ 0x40 + 8000900: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8000904: 61bb str r3, [r7, #24] + 8000906: 69bb ldr r3, [r7, #24] + } + + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8000908: 2300 movs r3, #0 + 800090a: 617b str r3, [r7, #20] + 800090c: 4b37 ldr r3, [pc, #220] @ (80009ec ) + 800090e: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000910: 4a36 ldr r2, [pc, #216] @ (80009ec ) + 8000912: f043 0302 orr.w r3, r3, #2 + 8000916: 6313 str r3, [r2, #48] @ 0x30 + 8000918: 4b34 ldr r3, [pc, #208] @ (80009ec ) + 800091a: 6b1b ldr r3, [r3, #48] @ 0x30 + 800091c: f003 0302 and.w r3, r3, #2 + 8000920: 617b str r3, [r7, #20] + 8000922: 697b ldr r3, [r7, #20] + /**CAN1 GPIO Configuration + PB8 ------> CAN1_RX + PB9 ------> CAN1_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; + 8000924: f44f 7340 mov.w r3, #768 @ 0x300 + 8000928: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800092a: 2302 movs r3, #2 + 800092c: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800092e: 2300 movs r3, #0 + 8000930: 627b str r3, [r7, #36] @ 0x24 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8000932: 2303 movs r3, #3 + 8000934: 62bb str r3, [r7, #40] @ 0x28 + GPIO_InitStruct.Alternate = GPIO_AF9_CAN1; + 8000936: 2309 movs r3, #9 + 8000938: 62fb str r3, [r7, #44] @ 0x2c + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 800093a: f107 031c add.w r3, r7, #28 + 800093e: 4619 mov r1, r3 + 8000940: 482b ldr r0, [pc, #172] @ (80009f0 ) + 8000942: f000 fdff bl 8001544 + /* USER CODE BEGIN CAN2_MspInit 1 */ + + /* USER CODE END CAN2_MspInit 1 */ + } + +} + 8000946: e048 b.n 80009da + else if(hcan->Instance==CAN2) + 8000948: 687b ldr r3, [r7, #4] + 800094a: 681b ldr r3, [r3, #0] + 800094c: 4a29 ldr r2, [pc, #164] @ (80009f4 ) + 800094e: 4293 cmp r3, r2 + 8000950: d143 bne.n 80009da + __HAL_RCC_CAN2_CLK_ENABLE(); + 8000952: 2300 movs r3, #0 + 8000954: 613b str r3, [r7, #16] + 8000956: 4b25 ldr r3, [pc, #148] @ (80009ec ) + 8000958: 6c1b ldr r3, [r3, #64] @ 0x40 + 800095a: 4a24 ldr r2, [pc, #144] @ (80009ec ) + 800095c: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 + 8000960: 6413 str r3, [r2, #64] @ 0x40 + 8000962: 4b22 ldr r3, [pc, #136] @ (80009ec ) + 8000964: 6c1b ldr r3, [r3, #64] @ 0x40 + 8000966: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 + 800096a: 613b str r3, [r7, #16] + 800096c: 693b ldr r3, [r7, #16] + HAL_RCC_CAN1_CLK_ENABLED++; + 800096e: 4b1e ldr r3, [pc, #120] @ (80009e8 ) + 8000970: 681b ldr r3, [r3, #0] + 8000972: 3301 adds r3, #1 + 8000974: 4a1c ldr r2, [pc, #112] @ (80009e8 ) + 8000976: 6013 str r3, [r2, #0] + if(HAL_RCC_CAN1_CLK_ENABLED==1){ + 8000978: 4b1b ldr r3, [pc, #108] @ (80009e8 ) + 800097a: 681b ldr r3, [r3, #0] + 800097c: 2b01 cmp r3, #1 + 800097e: d10d bne.n 800099c + __HAL_RCC_CAN1_CLK_ENABLE(); + 8000980: 2300 movs r3, #0 + 8000982: 60fb str r3, [r7, #12] + 8000984: 4b19 ldr r3, [pc, #100] @ (80009ec ) + 8000986: 6c1b ldr r3, [r3, #64] @ 0x40 + 8000988: 4a18 ldr r2, [pc, #96] @ (80009ec ) + 800098a: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 + 800098e: 6413 str r3, [r2, #64] @ 0x40 + 8000990: 4b16 ldr r3, [pc, #88] @ (80009ec ) + 8000992: 6c1b ldr r3, [r3, #64] @ 0x40 + 8000994: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8000998: 60fb str r3, [r7, #12] + 800099a: 68fb ldr r3, [r7, #12] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 800099c: 2300 movs r3, #0 + 800099e: 60bb str r3, [r7, #8] + 80009a0: 4b12 ldr r3, [pc, #72] @ (80009ec ) + 80009a2: 6b1b ldr r3, [r3, #48] @ 0x30 + 80009a4: 4a11 ldr r2, [pc, #68] @ (80009ec ) + 80009a6: f043 0302 orr.w r3, r3, #2 + 80009aa: 6313 str r3, [r2, #48] @ 0x30 + 80009ac: 4b0f ldr r3, [pc, #60] @ (80009ec ) + 80009ae: 6b1b ldr r3, [r3, #48] @ 0x30 + 80009b0: f003 0302 and.w r3, r3, #2 + 80009b4: 60bb str r3, [r7, #8] + 80009b6: 68bb ldr r3, [r7, #8] + GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13; + 80009b8: f44f 5340 mov.w r3, #12288 @ 0x3000 + 80009bc: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 80009be: 2302 movs r3, #2 + 80009c0: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80009c2: 2300 movs r3, #0 + 80009c4: 627b str r3, [r7, #36] @ 0x24 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 80009c6: 2303 movs r3, #3 + 80009c8: 62bb str r3, [r7, #40] @ 0x28 + GPIO_InitStruct.Alternate = GPIO_AF9_CAN2; + 80009ca: 2309 movs r3, #9 + 80009cc: 62fb str r3, [r7, #44] @ 0x2c + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 80009ce: f107 031c add.w r3, r7, #28 + 80009d2: 4619 mov r1, r3 + 80009d4: 4806 ldr r0, [pc, #24] @ (80009f0 ) + 80009d6: f000 fdb5 bl 8001544 +} + 80009da: bf00 nop + 80009dc: 3730 adds r7, #48 @ 0x30 + 80009de: 46bd mov sp, r7 + 80009e0: bd80 pop {r7, pc} + 80009e2: bf00 nop + 80009e4: 40006400 .word 0x40006400 + 80009e8: 20000148 .word 0x20000148 + 80009ec: 40023800 .word 0x40023800 + 80009f0: 40020400 .word 0x40020400 + 80009f4: 40006800 .word 0x40006800 + +080009f8 : + * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). + * @param TickPriority: Tick interrupt priority. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 80009f8: b580 push {r7, lr} + 80009fa: b08e sub sp, #56 @ 0x38 + 80009fc: af00 add r7, sp, #0 + 80009fe: 6078 str r0, [r7, #4] + RCC_ClkInitTypeDef clkconfig; + uint32_t uwTimclock, uwAPB1Prescaler = 0U; + 8000a00: 2300 movs r3, #0 + 8000a02: 62fb str r3, [r7, #44] @ 0x2c + + uint32_t uwPrescalerValue = 0U; + 8000a04: 2300 movs r3, #0 + 8000a06: 62bb str r3, [r7, #40] @ 0x28 + uint32_t pFLatency; + + HAL_StatusTypeDef status; + + /* Enable TIM6 clock */ + __HAL_RCC_TIM6_CLK_ENABLE(); + 8000a08: 2300 movs r3, #0 + 8000a0a: 60fb str r3, [r7, #12] + 8000a0c: 4b33 ldr r3, [pc, #204] @ (8000adc ) + 8000a0e: 6c1b ldr r3, [r3, #64] @ 0x40 + 8000a10: 4a32 ldr r2, [pc, #200] @ (8000adc ) + 8000a12: f043 0310 orr.w r3, r3, #16 + 8000a16: 6413 str r3, [r2, #64] @ 0x40 + 8000a18: 4b30 ldr r3, [pc, #192] @ (8000adc ) + 8000a1a: 6c1b ldr r3, [r3, #64] @ 0x40 + 8000a1c: f003 0310 and.w r3, r3, #16 + 8000a20: 60fb str r3, [r7, #12] + 8000a22: 68fb ldr r3, [r7, #12] + + /* Get clock configuration */ + HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); + 8000a24: f107 0210 add.w r2, r7, #16 + 8000a28: f107 0314 add.w r3, r7, #20 + 8000a2c: 4611 mov r1, r2 + 8000a2e: 4618 mov r0, r3 + 8000a30: f001 fdfa bl 8002628 + + /* Get APB1 prescaler */ + uwAPB1Prescaler = clkconfig.APB1CLKDivider; + 8000a34: 6a3b ldr r3, [r7, #32] + 8000a36: 62fb str r3, [r7, #44] @ 0x2c + /* Compute TIM6 clock */ + if (uwAPB1Prescaler == RCC_HCLK_DIV1) + 8000a38: 6afb ldr r3, [r7, #44] @ 0x2c + 8000a3a: 2b00 cmp r3, #0 + 8000a3c: d103 bne.n 8000a46 + { + uwTimclock = HAL_RCC_GetPCLK1Freq(); + 8000a3e: f001 fddf bl 8002600 + 8000a42: 6378 str r0, [r7, #52] @ 0x34 + 8000a44: e004 b.n 8000a50 + } + else + { + uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq(); + 8000a46: f001 fddb bl 8002600 + 8000a4a: 4603 mov r3, r0 + 8000a4c: 005b lsls r3, r3, #1 + 8000a4e: 637b str r3, [r7, #52] @ 0x34 + } + + /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */ + uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); + 8000a50: 6b7b ldr r3, [r7, #52] @ 0x34 + 8000a52: 4a23 ldr r2, [pc, #140] @ (8000ae0 ) + 8000a54: fba2 2303 umull r2, r3, r2, r3 + 8000a58: 0c9b lsrs r3, r3, #18 + 8000a5a: 3b01 subs r3, #1 + 8000a5c: 62bb str r3, [r7, #40] @ 0x28 + + /* Initialize TIM6 */ + htim6.Instance = TIM6; + 8000a5e: 4b21 ldr r3, [pc, #132] @ (8000ae4 ) + 8000a60: 4a21 ldr r2, [pc, #132] @ (8000ae8 ) + 8000a62: 601a str r2, [r3, #0] + * Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base. + * Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + * ClockDivision = 0 + * Counter direction = Up + */ + htim6.Init.Period = (1000000U / 1000U) - 1U; + 8000a64: 4b1f ldr r3, [pc, #124] @ (8000ae4 ) + 8000a66: f240 32e7 movw r2, #999 @ 0x3e7 + 8000a6a: 60da str r2, [r3, #12] + htim6.Init.Prescaler = uwPrescalerValue; + 8000a6c: 4a1d ldr r2, [pc, #116] @ (8000ae4 ) + 8000a6e: 6abb ldr r3, [r7, #40] @ 0x28 + 8000a70: 6053 str r3, [r2, #4] + htim6.Init.ClockDivision = 0; + 8000a72: 4b1c ldr r3, [pc, #112] @ (8000ae4 ) + 8000a74: 2200 movs r2, #0 + 8000a76: 611a str r2, [r3, #16] + htim6.Init.CounterMode = TIM_COUNTERMODE_UP; + 8000a78: 4b1a ldr r3, [pc, #104] @ (8000ae4 ) + 8000a7a: 2200 movs r2, #0 + 8000a7c: 609a str r2, [r3, #8] + htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 8000a7e: 4b19 ldr r3, [pc, #100] @ (8000ae4 ) + 8000a80: 2200 movs r2, #0 + 8000a82: 619a str r2, [r3, #24] + + status = HAL_TIM_Base_Init(&htim6); + 8000a84: 4817 ldr r0, [pc, #92] @ (8000ae4 ) + 8000a86: f001 fe01 bl 800268c + 8000a8a: 4603 mov r3, r0 + 8000a8c: f887 3033 strb.w r3, [r7, #51] @ 0x33 + if (status == HAL_OK) + 8000a90: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 + 8000a94: 2b00 cmp r3, #0 + 8000a96: d11b bne.n 8000ad0 + { + + /* Start the TIM time Base generation in interrupt mode */ + status = HAL_TIM_Base_Start_IT(&htim6); + 8000a98: 4812 ldr r0, [pc, #72] @ (8000ae4 ) + 8000a9a: f001 ff1d bl 80028d8 + 8000a9e: 4603 mov r3, r0 + 8000aa0: f887 3033 strb.w r3, [r7, #51] @ 0x33 + if (status == HAL_OK) + 8000aa4: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 + 8000aa8: 2b00 cmp r3, #0 + 8000aaa: d111 bne.n 8000ad0 + { + /* Enable the TIM6 global Interrupt */ + HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); + 8000aac: 2036 movs r0, #54 @ 0x36 + 8000aae: f000 fd31 bl 8001514 + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 8000ab2: 687b ldr r3, [r7, #4] + 8000ab4: 2b0f cmp r3, #15 + 8000ab6: d808 bhi.n 8000aca + { + /* Configure the TIM IRQ priority */ + HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority, 0U); + 8000ab8: 2200 movs r2, #0 + 8000aba: 6879 ldr r1, [r7, #4] + 8000abc: 2036 movs r0, #54 @ 0x36 + 8000abe: f000 fcfd bl 80014bc + uwTickPrio = TickPriority; + 8000ac2: 4a0a ldr r2, [pc, #40] @ (8000aec ) + 8000ac4: 687b ldr r3, [r7, #4] + 8000ac6: 6013 str r3, [r2, #0] + 8000ac8: e002 b.n 8000ad0 + } + else + { + status = HAL_ERROR; + 8000aca: 2301 movs r3, #1 + 8000acc: f887 3033 strb.w r3, [r7, #51] @ 0x33 + } + } + } + + /* Return function status */ + return status; + 8000ad0: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 +} + 8000ad4: 4618 mov r0, r3 + 8000ad6: 3738 adds r7, #56 @ 0x38 + 8000ad8: 46bd mov sp, r7 + 8000ada: bd80 pop {r7, pc} + 8000adc: 40023800 .word 0x40023800 + 8000ae0: 431bde83 .word 0x431bde83 + 8000ae4: 2000014c .word 0x2000014c + 8000ae8: 40001000 .word 0x40001000 + 8000aec: 20000004 .word 0x20000004 + +08000af0 : +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + 8000af0: b480 push {r7} + 8000af2: af00 add r7, sp, #0 + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + 8000af4: bf00 nop + 8000af6: e7fd b.n 8000af4 + +08000af8 : + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + 8000af8: b480 push {r7} + 8000afa: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 8000afc: bf00 nop + 8000afe: e7fd b.n 8000afc + +08000b00 : + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + 8000b00: b480 push {r7} + 8000b02: af00 add r7, sp, #0 + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + 8000b04: bf00 nop + 8000b06: e7fd b.n 8000b04 + +08000b08 : + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + 8000b08: b480 push {r7} + 8000b0a: af00 add r7, sp, #0 + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + 8000b0c: bf00 nop + 8000b0e: e7fd b.n 8000b0c + +08000b10 : + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + 8000b10: b480 push {r7} + 8000b12: af00 add r7, sp, #0 + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + 8000b14: bf00 nop + 8000b16: e7fd b.n 8000b14 + +08000b18 : + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + 8000b18: b480 push {r7} + 8000b1a: af00 add r7, sp, #0 + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + 8000b1c: bf00 nop + 8000b1e: 46bd mov sp, r7 + 8000b20: f85d 7b04 ldr.w r7, [sp], #4 + 8000b24: 4770 bx lr + ... + +08000b28 : + +/** + * @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts. + */ +void TIM6_DAC_IRQHandler(void) +{ + 8000b28: b580 push {r7, lr} + 8000b2a: af00 add r7, sp, #0 + /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ + + /* USER CODE END TIM6_DAC_IRQn 0 */ + HAL_TIM_IRQHandler(&htim6); + 8000b2c: 4802 ldr r0, [pc, #8] @ (8000b38 ) + 8000b2e: f001 ff99 bl 8002a64 + /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ + + /* USER CODE END TIM6_DAC_IRQn 1 */ +} + 8000b32: bf00 nop + 8000b34: bd80 pop {r7, pc} + 8000b36: bf00 nop + 8000b38: 2000014c .word 0x2000014c + +08000b3c : + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + 8000b3c: b480 push {r7} + 8000b3e: af00 add r7, sp, #0 + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + 8000b40: 4b06 ldr r3, [pc, #24] @ (8000b5c ) + 8000b42: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8000b46: 4a05 ldr r2, [pc, #20] @ (8000b5c ) + 8000b48: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 + 8000b4c: f8c2 3088 str.w r3, [r2, #136] @ 0x88 + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + 8000b50: bf00 nop + 8000b52: 46bd mov sp, r7 + 8000b54: f85d 7b04 ldr.w r7, [sp], #4 + 8000b58: 4770 bx lr + 8000b5a: bf00 nop + 8000b5c: e000ed00 .word 0xe000ed00 + +08000b60 : + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + 8000b60: f8df d034 ldr.w sp, [pc, #52] @ 8000b98 + +/* Call the clock system initialization function.*/ + bl SystemInit + 8000b64: f7ff ffea bl 8000b3c + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + 8000b68: 480c ldr r0, [pc, #48] @ (8000b9c ) + ldr r1, =_edata + 8000b6a: 490d ldr r1, [pc, #52] @ (8000ba0 ) + ldr r2, =_sidata + 8000b6c: 4a0d ldr r2, [pc, #52] @ (8000ba4 ) + movs r3, #0 + 8000b6e: 2300 movs r3, #0 + b LoopCopyDataInit + 8000b70: e002 b.n 8000b78 + +08000b72 : + +CopyDataInit: + ldr r4, [r2, r3] + 8000b72: 58d4 ldr r4, [r2, r3] + str r4, [r0, r3] + 8000b74: 50c4 str r4, [r0, r3] + adds r3, r3, #4 + 8000b76: 3304 adds r3, #4 + +08000b78 : + +LoopCopyDataInit: + adds r4, r0, r3 + 8000b78: 18c4 adds r4, r0, r3 + cmp r4, r1 + 8000b7a: 428c cmp r4, r1 + bcc CopyDataInit + 8000b7c: d3f9 bcc.n 8000b72 + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + 8000b7e: 4a0a ldr r2, [pc, #40] @ (8000ba8 ) + ldr r4, =_ebss + 8000b80: 4c0a ldr r4, [pc, #40] @ (8000bac ) + movs r3, #0 + 8000b82: 2300 movs r3, #0 + b LoopFillZerobss + 8000b84: e001 b.n 8000b8a + +08000b86 : + +FillZerobss: + str r3, [r2] + 8000b86: 6013 str r3, [r2, #0] + adds r2, r2, #4 + 8000b88: 3204 adds r2, #4 + +08000b8a : + +LoopFillZerobss: + cmp r2, r4 + 8000b8a: 42a2 cmp r2, r4 + bcc FillZerobss + 8000b8c: d3fb bcc.n 8000b86 + +/* Call static constructors */ + bl __libc_init_array + 8000b8e: f004 ff3f bl 8005a10 <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 8000b92: f7ff fcb3 bl 80004fc
+ bx lr + 8000b96: 4770 bx lr + ldr sp, =_estack /* set stack pointer */ + 8000b98: 20020000 .word 0x20020000 + ldr r0, =_sdata + 8000b9c: 20000000 .word 0x20000000 + ldr r1, =_edata + 8000ba0: 20000060 .word 0x20000060 + ldr r2, =_sidata + 8000ba4: 08005d6c .word 0x08005d6c + ldr r2, =_sbss + 8000ba8: 20000060 .word 0x20000060 + ldr r4, =_ebss + 8000bac: 20004cc8 .word 0x20004cc8 + +08000bb0 : + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 8000bb0: e7fe b.n 8000bb0 + +08000bb2 : +/** + * @brief Acquire STM32 lock + * @param lock The lock to acquire + */ +static inline void stm32_lock_acquire(LockingData_t *lock) +{ + 8000bb2: b580 push {r7, lr} + 8000bb4: b084 sub sp, #16 + 8000bb6: af00 add r7, sp, #0 + 8000bb8: 6078 str r0, [r7, #4] + STM32_LOCK_BLOCK_IF_NULL_ARGUMENT(lock); + 8000bba: 687b ldr r3, [r7, #4] + 8000bbc: 2b00 cmp r3, #0 + 8000bbe: d105 bne.n 8000bcc + __ASM volatile ("cpsid i" : : : "memory"); + 8000bc0: b672 cpsid i +} + 8000bc2: bf00 nop + 8000bc4: f7ff fe3a bl 800083c + 8000bc8: bf00 nop + 8000bca: e7fd b.n 8000bc8 + STM32_LOCK_ASSERT_VALID_NESTING_LEVEL(lock); + 8000bcc: 687b ldr r3, [r7, #4] + 8000bce: 7a1b ldrb r3, [r3, #8] + 8000bd0: 2b01 cmp r3, #1 + 8000bd2: d905 bls.n 8000be0 + __ASM volatile ("cpsid i" : : : "memory"); + 8000bd4: b672 cpsid i +} + 8000bd6: bf00 nop + 8000bd8: f7ff fe30 bl 800083c + 8000bdc: bf00 nop + 8000bde: e7fd b.n 8000bdc + lock->basepri[lock->nesting_level++] = taskENTER_CRITICAL_FROM_ISR(); + 8000be0: 687b ldr r3, [r7, #4] + 8000be2: 7a1b ldrb r3, [r3, #8] + 8000be4: 1c5a adds r2, r3, #1 + 8000be6: b2d1 uxtb r1, r2 + 8000be8: 687a ldr r2, [r7, #4] + 8000bea: 7211 strb r1, [r2, #8] + 8000bec: 4619 mov r1, r3 + +portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) +{ +uint32_t ulOriginalBASEPRI, ulNewBASEPRI; + + __asm volatile + 8000bee: f3ef 8211 mrs r2, BASEPRI + 8000bf2: f04f 0350 mov.w r3, #80 @ 0x50 + 8000bf6: f383 8811 msr BASEPRI, r3 + 8000bfa: f3bf 8f6f isb sy + 8000bfe: f3bf 8f4f dsb sy + 8000c02: 60fa str r2, [r7, #12] + 8000c04: 60bb str r3, [r7, #8] + :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); + + /* This return will not be reached but is necessary to prevent compiler + warnings. */ + return ulOriginalBASEPRI; + 8000c06: 68fa ldr r2, [r7, #12] + 8000c08: 687b ldr r3, [r7, #4] + 8000c0a: f843 2021 str.w r2, [r3, r1, lsl #2] +} + 8000c0e: bf00 nop + 8000c10: 3710 adds r7, #16 + 8000c12: 46bd mov sp, r7 + 8000c14: bd80 pop {r7, pc} + +08000c16 : +/** + * @brief Release STM32 lock + * @param lock The lock to release + */ +static inline void stm32_lock_release(LockingData_t *lock) +{ + 8000c16: b580 push {r7, lr} + 8000c18: b084 sub sp, #16 + 8000c1a: af00 add r7, sp, #0 + 8000c1c: 6078 str r0, [r7, #4] + STM32_LOCK_BLOCK_IF_NULL_ARGUMENT(lock); + 8000c1e: 687b ldr r3, [r7, #4] + 8000c20: 2b00 cmp r3, #0 + 8000c22: d105 bne.n 8000c30 + __ASM volatile ("cpsid i" : : : "memory"); + 8000c24: b672 cpsid i +} + 8000c26: bf00 nop + 8000c28: f7ff fe08 bl 800083c + 8000c2c: bf00 nop + 8000c2e: e7fd b.n 8000c2c + lock->nesting_level--; + 8000c30: 687b ldr r3, [r7, #4] + 8000c32: 7a1b ldrb r3, [r3, #8] + 8000c34: 3b01 subs r3, #1 + 8000c36: b2da uxtb r2, r3 + 8000c38: 687b ldr r3, [r7, #4] + 8000c3a: 721a strb r2, [r3, #8] + STM32_LOCK_ASSERT_VALID_NESTING_LEVEL(lock); + 8000c3c: 687b ldr r3, [r7, #4] + 8000c3e: 7a1b ldrb r3, [r3, #8] + 8000c40: 2b01 cmp r3, #1 + 8000c42: d905 bls.n 8000c50 + __ASM volatile ("cpsid i" : : : "memory"); + 8000c44: b672 cpsid i +} + 8000c46: bf00 nop + 8000c48: f7ff fdf8 bl 800083c + 8000c4c: bf00 nop + 8000c4e: e7fd b.n 8000c4c + taskEXIT_CRITICAL_FROM_ISR(lock->basepri[lock->nesting_level]); + 8000c50: 687b ldr r3, [r7, #4] + 8000c52: 7a1b ldrb r3, [r3, #8] + 8000c54: 461a mov r2, r3 + 8000c56: 687b ldr r3, [r7, #4] + 8000c58: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8000c5c: 60fb str r3, [r7, #12] +} +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) +{ + __asm volatile + 8000c5e: 68fb ldr r3, [r7, #12] + 8000c60: f383 8811 msr BASEPRI, r3 + ( + " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory" + ); +} + 8000c64: bf00 nop +} + 8000c66: bf00 nop + 8000c68: 3710 adds r7, #16 + 8000c6a: 46bd mov sp, r7 + 8000c6c: bd80 pop {r7, pc} + +08000c6e <__retarget_lock_acquire_recursive>: +/** + * @brief Acquire recursive lock + * @param lock The lock + */ +void __retarget_lock_acquire_recursive(_LOCK_T lock) +{ + 8000c6e: b580 push {r7, lr} + 8000c70: b082 sub sp, #8 + 8000c72: af00 add r7, sp, #0 + 8000c74: 6078 str r0, [r7, #4] + STM32_LOCK_BLOCK_IF_NULL_ARGUMENT(lock); + 8000c76: 687b ldr r3, [r7, #4] + 8000c78: 2b00 cmp r3, #0 + 8000c7a: d105 bne.n 8000c88 <__retarget_lock_acquire_recursive+0x1a> + __ASM volatile ("cpsid i" : : : "memory"); + 8000c7c: b672 cpsid i +} + 8000c7e: bf00 nop + 8000c80: f7ff fddc bl 800083c + 8000c84: bf00 nop + 8000c86: e7fd b.n 8000c84 <__retarget_lock_acquire_recursive+0x16> + stm32_lock_acquire(STM32_LOCK_PARAMETER(lock)); + 8000c88: 687b ldr r3, [r7, #4] + 8000c8a: 4618 mov r0, r3 + 8000c8c: f7ff ff91 bl 8000bb2 +} + 8000c90: bf00 nop + 8000c92: 3708 adds r7, #8 + 8000c94: 46bd mov sp, r7 + 8000c96: bd80 pop {r7, pc} + +08000c98 <__retarget_lock_release_recursive>: +/** + * @brief Release recursive lock + * @param lock The lock + */ +void __retarget_lock_release_recursive(_LOCK_T lock) +{ + 8000c98: b580 push {r7, lr} + 8000c9a: b082 sub sp, #8 + 8000c9c: af00 add r7, sp, #0 + 8000c9e: 6078 str r0, [r7, #4] + STM32_LOCK_BLOCK_IF_NULL_ARGUMENT(lock); + 8000ca0: 687b ldr r3, [r7, #4] + 8000ca2: 2b00 cmp r3, #0 + 8000ca4: d105 bne.n 8000cb2 <__retarget_lock_release_recursive+0x1a> + __ASM volatile ("cpsid i" : : : "memory"); + 8000ca6: b672 cpsid i +} + 8000ca8: bf00 nop + 8000caa: f7ff fdc7 bl 800083c + 8000cae: bf00 nop + 8000cb0: e7fd b.n 8000cae <__retarget_lock_release_recursive+0x16> + stm32_lock_release(STM32_LOCK_PARAMETER(lock)); + 8000cb2: 687b ldr r3, [r7, #4] + 8000cb4: 4618 mov r0, r3 + 8000cb6: f7ff ffae bl 8000c16 +} + 8000cba: bf00 nop + 8000cbc: 3708 adds r7, #8 + 8000cbe: 46bd mov sp, r7 + 8000cc0: bd80 pop {r7, pc} + ... + +08000cc4 : + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 8000cc4: b580 push {r7, lr} + 8000cc6: af00 add r7, sp, #0 + /* Configure Flash prefetch, Instruction cache, Data cache */ +#if (INSTRUCTION_CACHE_ENABLE != 0U) + __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); + 8000cc8: 4b0e ldr r3, [pc, #56] @ (8000d04 ) + 8000cca: 681b ldr r3, [r3, #0] + 8000ccc: 4a0d ldr r2, [pc, #52] @ (8000d04 ) + 8000cce: f443 7300 orr.w r3, r3, #512 @ 0x200 + 8000cd2: 6013 str r3, [r2, #0] +#endif /* INSTRUCTION_CACHE_ENABLE */ + +#if (DATA_CACHE_ENABLE != 0U) + __HAL_FLASH_DATA_CACHE_ENABLE(); + 8000cd4: 4b0b ldr r3, [pc, #44] @ (8000d04 ) + 8000cd6: 681b ldr r3, [r3, #0] + 8000cd8: 4a0a ldr r2, [pc, #40] @ (8000d04 ) + 8000cda: f443 6380 orr.w r3, r3, #1024 @ 0x400 + 8000cde: 6013 str r3, [r2, #0] +#endif /* DATA_CACHE_ENABLE */ + +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); + 8000ce0: 4b08 ldr r3, [pc, #32] @ (8000d04 ) + 8000ce2: 681b ldr r3, [r3, #0] + 8000ce4: 4a07 ldr r2, [pc, #28] @ (8000d04 ) + 8000ce6: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8000cea: 6013 str r3, [r2, #0] +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 8000cec: 2003 movs r0, #3 + 8000cee: f000 fbc5 bl 800147c + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + HAL_InitTick(TICK_INT_PRIORITY); + 8000cf2: 200f movs r0, #15 + 8000cf4: f7ff fe80 bl 80009f8 + + /* Init the low level hardware */ + HAL_MspInit(); + 8000cf8: f7ff fdb2 bl 8000860 + + /* Return function status */ + return HAL_OK; + 8000cfc: 2300 movs r3, #0 +} + 8000cfe: 4618 mov r0, r3 + 8000d00: bd80 pop {r7, pc} + 8000d02: bf00 nop + 8000d04: 40023c00 .word 0x40023c00 + +08000d08 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + 8000d08: b480 push {r7} + 8000d0a: af00 add r7, sp, #0 + uwTick += uwTickFreq; + 8000d0c: 4b06 ldr r3, [pc, #24] @ (8000d28 ) + 8000d0e: 781b ldrb r3, [r3, #0] + 8000d10: 461a mov r2, r3 + 8000d12: 4b06 ldr r3, [pc, #24] @ (8000d2c ) + 8000d14: 681b ldr r3, [r3, #0] + 8000d16: 4413 add r3, r2 + 8000d18: 4a04 ldr r2, [pc, #16] @ (8000d2c ) + 8000d1a: 6013 str r3, [r2, #0] +} + 8000d1c: bf00 nop + 8000d1e: 46bd mov sp, r7 + 8000d20: f85d 7b04 ldr.w r7, [sp], #4 + 8000d24: 4770 bx lr + 8000d26: bf00 nop + 8000d28: 20000008 .word 0x20000008 + 8000d2c: 200001a0 .word 0x200001a0 + +08000d30 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + 8000d30: b480 push {r7} + 8000d32: af00 add r7, sp, #0 + return uwTick; + 8000d34: 4b03 ldr r3, [pc, #12] @ (8000d44 ) + 8000d36: 681b ldr r3, [r3, #0] +} + 8000d38: 4618 mov r0, r3 + 8000d3a: 46bd mov sp, r7 + 8000d3c: f85d 7b04 ldr.w r7, [sp], #4 + 8000d40: 4770 bx lr + 8000d42: bf00 nop + 8000d44: 200001a0 .word 0x200001a0 + +08000d48 : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) +{ + 8000d48: b580 push {r7, lr} + 8000d4a: b084 sub sp, #16 + 8000d4c: af00 add r7, sp, #0 + 8000d4e: 6078 str r0, [r7, #4] + uint32_t tickstart; + + /* Check CAN handle */ + if (hcan == NULL) + 8000d50: 687b ldr r3, [r7, #4] + 8000d52: 2b00 cmp r3, #0 + 8000d54: d101 bne.n 8000d5a + { + return HAL_ERROR; + 8000d56: 2301 movs r3, #1 + 8000d58: e243 b.n 80011e2 + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + 8000d5a: 687b ldr r3, [r7, #4] + 8000d5c: 681b ldr r3, [r3, #0] + 8000d5e: 4a93 ldr r2, [pc, #588] @ (8000fac ) + 8000d60: 4293 cmp r3, r2 + 8000d62: d009 beq.n 8000d78 + 8000d64: 687b ldr r3, [r7, #4] + 8000d66: 681b ldr r3, [r3, #0] + 8000d68: 4a91 ldr r2, [pc, #580] @ (8000fb0 ) + 8000d6a: 4293 cmp r3, r2 + 8000d6c: d004 beq.n 8000d78 + 8000d6e: f44f 718f mov.w r1, #286 @ 0x11e + 8000d72: 4890 ldr r0, [pc, #576] @ (8000fb4 ) + 8000d74: f7ff fd68 bl 8000848 + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode)); + 8000d78: 687b ldr r3, [r7, #4] + 8000d7a: 7e1b ldrb r3, [r3, #24] + 8000d7c: 2b00 cmp r3, #0 + 8000d7e: d008 beq.n 8000d92 + 8000d80: 687b ldr r3, [r7, #4] + 8000d82: 7e1b ldrb r3, [r3, #24] + 8000d84: 2b01 cmp r3, #1 + 8000d86: d004 beq.n 8000d92 + 8000d88: f240 111f movw r1, #287 @ 0x11f + 8000d8c: 4889 ldr r0, [pc, #548] @ (8000fb4 ) + 8000d8e: f7ff fd5b bl 8000848 + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff)); + 8000d92: 687b ldr r3, [r7, #4] + 8000d94: 7e5b ldrb r3, [r3, #25] + 8000d96: 2b00 cmp r3, #0 + 8000d98: d008 beq.n 8000dac + 8000d9a: 687b ldr r3, [r7, #4] + 8000d9c: 7e5b ldrb r3, [r3, #25] + 8000d9e: 2b01 cmp r3, #1 + 8000da0: d004 beq.n 8000dac + 8000da2: f44f 7190 mov.w r1, #288 @ 0x120 + 8000da6: 4883 ldr r0, [pc, #524] @ (8000fb4 ) + 8000da8: f7ff fd4e bl 8000848 + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp)); + 8000dac: 687b ldr r3, [r7, #4] + 8000dae: 7e9b ldrb r3, [r3, #26] + 8000db0: 2b00 cmp r3, #0 + 8000db2: d008 beq.n 8000dc6 + 8000db4: 687b ldr r3, [r7, #4] + 8000db6: 7e9b ldrb r3, [r3, #26] + 8000db8: 2b01 cmp r3, #1 + 8000dba: d004 beq.n 8000dc6 + 8000dbc: f240 1121 movw r1, #289 @ 0x121 + 8000dc0: 487c ldr r0, [pc, #496] @ (8000fb4 ) + 8000dc2: f7ff fd41 bl 8000848 + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission)); + 8000dc6: 687b ldr r3, [r7, #4] + 8000dc8: 7edb ldrb r3, [r3, #27] + 8000dca: 2b00 cmp r3, #0 + 8000dcc: d008 beq.n 8000de0 + 8000dce: 687b ldr r3, [r7, #4] + 8000dd0: 7edb ldrb r3, [r3, #27] + 8000dd2: 2b01 cmp r3, #1 + 8000dd4: d004 beq.n 8000de0 + 8000dd6: f44f 7191 mov.w r1, #290 @ 0x122 + 8000dda: 4876 ldr r0, [pc, #472] @ (8000fb4 ) + 8000ddc: f7ff fd34 bl 8000848 + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked)); + 8000de0: 687b ldr r3, [r7, #4] + 8000de2: 7f1b ldrb r3, [r3, #28] + 8000de4: 2b00 cmp r3, #0 + 8000de6: d008 beq.n 8000dfa + 8000de8: 687b ldr r3, [r7, #4] + 8000dea: 7f1b ldrb r3, [r3, #28] + 8000dec: 2b01 cmp r3, #1 + 8000dee: d004 beq.n 8000dfa + 8000df0: f240 1123 movw r1, #291 @ 0x123 + 8000df4: 486f ldr r0, [pc, #444] @ (8000fb4 ) + 8000df6: f7ff fd27 bl 8000848 + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority)); + 8000dfa: 687b ldr r3, [r7, #4] + 8000dfc: 7f5b ldrb r3, [r3, #29] + 8000dfe: 2b00 cmp r3, #0 + 8000e00: d008 beq.n 8000e14 + 8000e02: 687b ldr r3, [r7, #4] + 8000e04: 7f5b ldrb r3, [r3, #29] + 8000e06: 2b01 cmp r3, #1 + 8000e08: d004 beq.n 8000e14 + 8000e0a: f44f 7192 mov.w r1, #292 @ 0x124 + 8000e0e: 4869 ldr r0, [pc, #420] @ (8000fb4 ) + 8000e10: f7ff fd1a bl 8000848 + assert_param(IS_CAN_MODE(hcan->Init.Mode)); + 8000e14: 687b ldr r3, [r7, #4] + 8000e16: 689b ldr r3, [r3, #8] + 8000e18: 2b00 cmp r3, #0 + 8000e1a: d013 beq.n 8000e44 + 8000e1c: 687b ldr r3, [r7, #4] + 8000e1e: 689b ldr r3, [r3, #8] + 8000e20: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8000e24: d00e beq.n 8000e44 + 8000e26: 687b ldr r3, [r7, #4] + 8000e28: 689b ldr r3, [r3, #8] + 8000e2a: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 + 8000e2e: d009 beq.n 8000e44 + 8000e30: 687b ldr r3, [r7, #4] + 8000e32: 689b ldr r3, [r3, #8] + 8000e34: f1b3 4f40 cmp.w r3, #3221225472 @ 0xc0000000 + 8000e38: d004 beq.n 8000e44 + 8000e3a: f240 1125 movw r1, #293 @ 0x125 + 8000e3e: 485d ldr r0, [pc, #372] @ (8000fb4 ) + 8000e40: f7ff fd02 bl 8000848 + assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth)); + 8000e44: 687b ldr r3, [r7, #4] + 8000e46: 68db ldr r3, [r3, #12] + 8000e48: 2b00 cmp r3, #0 + 8000e4a: d013 beq.n 8000e74 + 8000e4c: 687b ldr r3, [r7, #4] + 8000e4e: 68db ldr r3, [r3, #12] + 8000e50: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 + 8000e54: d00e beq.n 8000e74 + 8000e56: 687b ldr r3, [r7, #4] + 8000e58: 68db ldr r3, [r3, #12] + 8000e5a: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 + 8000e5e: d009 beq.n 8000e74 + 8000e60: 687b ldr r3, [r7, #4] + 8000e62: 68db ldr r3, [r3, #12] + 8000e64: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 + 8000e68: d004 beq.n 8000e74 + 8000e6a: f44f 7193 mov.w r1, #294 @ 0x126 + 8000e6e: 4851 ldr r0, [pc, #324] @ (8000fb4 ) + 8000e70: f7ff fcea bl 8000848 + assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1)); + 8000e74: 687b ldr r3, [r7, #4] + 8000e76: 691b ldr r3, [r3, #16] + 8000e78: 2b00 cmp r3, #0 + 8000e7a: d04f beq.n 8000f1c + 8000e7c: 687b ldr r3, [r7, #4] + 8000e7e: 691b ldr r3, [r3, #16] + 8000e80: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8000e84: d04a beq.n 8000f1c + 8000e86: 687b ldr r3, [r7, #4] + 8000e88: 691b ldr r3, [r3, #16] + 8000e8a: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 + 8000e8e: d045 beq.n 8000f1c + 8000e90: 687b ldr r3, [r7, #4] + 8000e92: 691b ldr r3, [r3, #16] + 8000e94: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 + 8000e98: d040 beq.n 8000f1c + 8000e9a: 687b ldr r3, [r7, #4] + 8000e9c: 691b ldr r3, [r3, #16] + 8000e9e: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 + 8000ea2: d03b beq.n 8000f1c + 8000ea4: 687b ldr r3, [r7, #4] + 8000ea6: 691b ldr r3, [r3, #16] + 8000ea8: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 + 8000eac: d036 beq.n 8000f1c + 8000eae: 687b ldr r3, [r7, #4] + 8000eb0: 691b ldr r3, [r3, #16] + 8000eb2: f5b3 2fc0 cmp.w r3, #393216 @ 0x60000 + 8000eb6: d031 beq.n 8000f1c + 8000eb8: 687b ldr r3, [r7, #4] + 8000eba: 691b ldr r3, [r3, #16] + 8000ebc: f5b3 2fe0 cmp.w r3, #458752 @ 0x70000 + 8000ec0: d02c beq.n 8000f1c + 8000ec2: 687b ldr r3, [r7, #4] + 8000ec4: 691b ldr r3, [r3, #16] + 8000ec6: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 + 8000eca: d027 beq.n 8000f1c + 8000ecc: 687b ldr r3, [r7, #4] + 8000ece: 691b ldr r3, [r3, #16] + 8000ed0: f5b3 2f10 cmp.w r3, #589824 @ 0x90000 + 8000ed4: d022 beq.n 8000f1c + 8000ed6: 687b ldr r3, [r7, #4] + 8000ed8: 691b ldr r3, [r3, #16] + 8000eda: f5b3 2f20 cmp.w r3, #655360 @ 0xa0000 + 8000ede: d01d beq.n 8000f1c + 8000ee0: 687b ldr r3, [r7, #4] + 8000ee2: 691b ldr r3, [r3, #16] + 8000ee4: f5b3 2f30 cmp.w r3, #720896 @ 0xb0000 + 8000ee8: d018 beq.n 8000f1c + 8000eea: 687b ldr r3, [r7, #4] + 8000eec: 691b ldr r3, [r3, #16] + 8000eee: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 + 8000ef2: d013 beq.n 8000f1c + 8000ef4: 687b ldr r3, [r7, #4] + 8000ef6: 691b ldr r3, [r3, #16] + 8000ef8: f5b3 2f50 cmp.w r3, #851968 @ 0xd0000 + 8000efc: d00e beq.n 8000f1c + 8000efe: 687b ldr r3, [r7, #4] + 8000f00: 691b ldr r3, [r3, #16] + 8000f02: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 + 8000f06: d009 beq.n 8000f1c + 8000f08: 687b ldr r3, [r7, #4] + 8000f0a: 691b ldr r3, [r3, #16] + 8000f0c: f5b3 2f70 cmp.w r3, #983040 @ 0xf0000 + 8000f10: d004 beq.n 8000f1c + 8000f12: f240 1127 movw r1, #295 @ 0x127 + 8000f16: 4827 ldr r0, [pc, #156] @ (8000fb4 ) + 8000f18: f7ff fc96 bl 8000848 + assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2)); + 8000f1c: 687b ldr r3, [r7, #4] + 8000f1e: 695b ldr r3, [r3, #20] + 8000f20: 2b00 cmp r3, #0 + 8000f22: d027 beq.n 8000f74 + 8000f24: 687b ldr r3, [r7, #4] + 8000f26: 695b ldr r3, [r3, #20] + 8000f28: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 + 8000f2c: d022 beq.n 8000f74 + 8000f2e: 687b ldr r3, [r7, #4] + 8000f30: 695b ldr r3, [r3, #20] + 8000f32: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 + 8000f36: d01d beq.n 8000f74 + 8000f38: 687b ldr r3, [r7, #4] + 8000f3a: 695b ldr r3, [r3, #20] + 8000f3c: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 + 8000f40: d018 beq.n 8000f74 + 8000f42: 687b ldr r3, [r7, #4] + 8000f44: 695b ldr r3, [r3, #20] + 8000f46: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 + 8000f4a: d013 beq.n 8000f74 + 8000f4c: 687b ldr r3, [r7, #4] + 8000f4e: 695b ldr r3, [r3, #20] + 8000f50: f5b3 0fa0 cmp.w r3, #5242880 @ 0x500000 + 8000f54: d00e beq.n 8000f74 + 8000f56: 687b ldr r3, [r7, #4] + 8000f58: 695b ldr r3, [r3, #20] + 8000f5a: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 + 8000f5e: d009 beq.n 8000f74 + 8000f60: 687b ldr r3, [r7, #4] + 8000f62: 695b ldr r3, [r3, #20] + 8000f64: f5b3 0fe0 cmp.w r3, #7340032 @ 0x700000 + 8000f68: d004 beq.n 8000f74 + 8000f6a: f44f 7194 mov.w r1, #296 @ 0x128 + 8000f6e: 4811 ldr r0, [pc, #68] @ (8000fb4 ) + 8000f70: f7ff fc6a bl 8000848 + assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); + 8000f74: 687b ldr r3, [r7, #4] + 8000f76: 685b ldr r3, [r3, #4] + 8000f78: 2b00 cmp r3, #0 + 8000f7a: d004 beq.n 8000f86 + 8000f7c: 687b ldr r3, [r7, #4] + 8000f7e: 685b ldr r3, [r3, #4] + 8000f80: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 8000f84: d904 bls.n 8000f90 + 8000f86: f240 1129 movw r1, #297 @ 0x129 + 8000f8a: 480a ldr r0, [pc, #40] @ (8000fb4 ) + 8000f8c: f7ff fc5c bl 8000848 + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + if (hcan->State == HAL_CAN_STATE_RESET) + 8000f90: 687b ldr r3, [r7, #4] + 8000f92: f893 3020 ldrb.w r3, [r3, #32] + 8000f96: b2db uxtb r3, r3 + 8000f98: 2b00 cmp r3, #0 + 8000f9a: d13d bne.n 8001018 + { + /* Reset callbacks to legacy functions */ + hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; /* Legacy weak RxFifo0MsgPendingCallback */ + 8000f9c: 687b ldr r3, [r7, #4] + 8000f9e: 4a06 ldr r2, [pc, #24] @ (8000fb8 ) + 8000fa0: 641a str r2, [r3, #64] @ 0x40 + hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; /* Legacy weak RxFifo0FullCallback */ + 8000fa2: 687b ldr r3, [r7, #4] + 8000fa4: 4a05 ldr r2, [pc, #20] @ (8000fbc ) + 8000fa6: 645a str r2, [r3, #68] @ 0x44 + 8000fa8: e00a b.n 8000fc0 + 8000faa: bf00 nop + 8000fac: 40006400 .word 0x40006400 + 8000fb0: 40006800 .word 0x40006800 + 8000fb4: 08005be8 .word 0x08005be8 + 8000fb8: 08001295 .word 0x08001295 + 8000fbc: 080012a9 .word 0x080012a9 + hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; /* Legacy weak RxFifo1MsgPendingCallback */ + 8000fc0: 687b ldr r3, [r7, #4] + 8000fc2: 4a8a ldr r2, [pc, #552] @ (80011ec ) + 8000fc4: 649a str r2, [r3, #72] @ 0x48 + hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; /* Legacy weak RxFifo1FullCallback */ + 8000fc6: 687b ldr r3, [r7, #4] + 8000fc8: 4a89 ldr r2, [pc, #548] @ (80011f0 ) + 8000fca: 64da str r2, [r3, #76] @ 0x4c + hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; /* Legacy weak TxMailbox0CompleteCallback */ + 8000fcc: 687b ldr r3, [r7, #4] + 8000fce: 4a89 ldr r2, [pc, #548] @ (80011f4 ) + 8000fd0: 629a str r2, [r3, #40] @ 0x28 + hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; /* Legacy weak TxMailbox1CompleteCallback */ + 8000fd2: 687b ldr r3, [r7, #4] + 8000fd4: 4a88 ldr r2, [pc, #544] @ (80011f8 ) + 8000fd6: 62da str r2, [r3, #44] @ 0x2c + hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; /* Legacy weak TxMailbox2CompleteCallback */ + 8000fd8: 687b ldr r3, [r7, #4] + 8000fda: 4a88 ldr r2, [pc, #544] @ (80011fc ) + 8000fdc: 631a str r2, [r3, #48] @ 0x30 + hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; /* Legacy weak TxMailbox0AbortCallback */ + 8000fde: 687b ldr r3, [r7, #4] + 8000fe0: 4a87 ldr r2, [pc, #540] @ (8001200 ) + 8000fe2: 635a str r2, [r3, #52] @ 0x34 + hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; /* Legacy weak TxMailbox1AbortCallback */ + 8000fe4: 687b ldr r3, [r7, #4] + 8000fe6: 4a87 ldr r2, [pc, #540] @ (8001204 ) + 8000fe8: 639a str r2, [r3, #56] @ 0x38 + hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; /* Legacy weak TxMailbox2AbortCallback */ + 8000fea: 687b ldr r3, [r7, #4] + 8000fec: 4a86 ldr r2, [pc, #536] @ (8001208 ) + 8000fee: 63da str r2, [r3, #60] @ 0x3c + hcan->SleepCallback = HAL_CAN_SleepCallback; /* Legacy weak SleepCallback */ + 8000ff0: 687b ldr r3, [r7, #4] + 8000ff2: 4a86 ldr r2, [pc, #536] @ (800120c ) + 8000ff4: 651a str r2, [r3, #80] @ 0x50 + hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; /* Legacy weak WakeUpFromRxMsgCallback */ + 8000ff6: 687b ldr r3, [r7, #4] + 8000ff8: 4a85 ldr r2, [pc, #532] @ (8001210 ) + 8000ffa: 655a str r2, [r3, #84] @ 0x54 + hcan->ErrorCallback = HAL_CAN_ErrorCallback; /* Legacy weak ErrorCallback */ + 8000ffc: 687b ldr r3, [r7, #4] + 8000ffe: 4a85 ldr r2, [pc, #532] @ (8001214 ) + 8001000: 659a str r2, [r3, #88] @ 0x58 + + if (hcan->MspInitCallback == NULL) + 8001002: 687b ldr r3, [r7, #4] + 8001004: 6ddb ldr r3, [r3, #92] @ 0x5c + 8001006: 2b00 cmp r3, #0 + 8001008: d102 bne.n 8001010 + { + hcan->MspInitCallback = HAL_CAN_MspInit; /* Legacy weak MspInit */ + 800100a: 687b ldr r3, [r7, #4] + 800100c: 4a82 ldr r2, [pc, #520] @ (8001218 ) + 800100e: 65da str r2, [r3, #92] @ 0x5c + } + + /* Init the low level hardware: CLOCK, NVIC */ + hcan->MspInitCallback(hcan); + 8001010: 687b ldr r3, [r7, #4] + 8001012: 6ddb ldr r3, [r3, #92] @ 0x5c + 8001014: 6878 ldr r0, [r7, #4] + 8001016: 4798 blx r3 + HAL_CAN_MspInit(hcan); + } +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + 8001018: 687b ldr r3, [r7, #4] + 800101a: 681b ldr r3, [r3, #0] + 800101c: 681a ldr r2, [r3, #0] + 800101e: 687b ldr r3, [r7, #4] + 8001020: 681b ldr r3, [r3, #0] + 8001022: f042 0201 orr.w r2, r2, #1 + 8001026: 601a str r2, [r3, #0] + + /* Get tick */ + tickstart = HAL_GetTick(); + 8001028: f7ff fe82 bl 8000d30 + 800102c: 60f8 str r0, [r7, #12] + + /* Wait initialisation acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) + 800102e: e012 b.n 8001056 + { + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + 8001030: f7ff fe7e bl 8000d30 + 8001034: 4602 mov r2, r0 + 8001036: 68fb ldr r3, [r7, #12] + 8001038: 1ad3 subs r3, r2, r3 + 800103a: 2b0a cmp r3, #10 + 800103c: d90b bls.n 8001056 + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + 800103e: 687b ldr r3, [r7, #4] + 8001040: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001042: f443 3200 orr.w r2, r3, #131072 @ 0x20000 + 8001046: 687b ldr r3, [r7, #4] + 8001048: 625a str r2, [r3, #36] @ 0x24 + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + 800104a: 687b ldr r3, [r7, #4] + 800104c: 2205 movs r2, #5 + 800104e: f883 2020 strb.w r2, [r3, #32] + + return HAL_ERROR; + 8001052: 2301 movs r3, #1 + 8001054: e0c5 b.n 80011e2 + while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) + 8001056: 687b ldr r3, [r7, #4] + 8001058: 681b ldr r3, [r3, #0] + 800105a: 685b ldr r3, [r3, #4] + 800105c: f003 0301 and.w r3, r3, #1 + 8001060: 2b00 cmp r3, #0 + 8001062: d0e5 beq.n 8001030 + } + } + + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + 8001064: 687b ldr r3, [r7, #4] + 8001066: 681b ldr r3, [r3, #0] + 8001068: 681a ldr r2, [r3, #0] + 800106a: 687b ldr r3, [r7, #4] + 800106c: 681b ldr r3, [r3, #0] + 800106e: f022 0202 bic.w r2, r2, #2 + 8001072: 601a str r2, [r3, #0] + + /* Get tick */ + tickstart = HAL_GetTick(); + 8001074: f7ff fe5c bl 8000d30 + 8001078: 60f8 str r0, [r7, #12] + + /* Check Sleep mode leave acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + 800107a: e012 b.n 80010a2 + { + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + 800107c: f7ff fe58 bl 8000d30 + 8001080: 4602 mov r2, r0 + 8001082: 68fb ldr r3, [r7, #12] + 8001084: 1ad3 subs r3, r2, r3 + 8001086: 2b0a cmp r3, #10 + 8001088: d90b bls.n 80010a2 + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + 800108a: 687b ldr r3, [r7, #4] + 800108c: 6a5b ldr r3, [r3, #36] @ 0x24 + 800108e: f443 3200 orr.w r2, r3, #131072 @ 0x20000 + 8001092: 687b ldr r3, [r7, #4] + 8001094: 625a str r2, [r3, #36] @ 0x24 + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + 8001096: 687b ldr r3, [r7, #4] + 8001098: 2205 movs r2, #5 + 800109a: f883 2020 strb.w r2, [r3, #32] + + return HAL_ERROR; + 800109e: 2301 movs r3, #1 + 80010a0: e09f b.n 80011e2 + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + 80010a2: 687b ldr r3, [r7, #4] + 80010a4: 681b ldr r3, [r3, #0] + 80010a6: 685b ldr r3, [r3, #4] + 80010a8: f003 0302 and.w r3, r3, #2 + 80010ac: 2b00 cmp r3, #0 + 80010ae: d1e5 bne.n 800107c + } + } + + /* Set the time triggered communication mode */ + if (hcan->Init.TimeTriggeredMode == ENABLE) + 80010b0: 687b ldr r3, [r7, #4] + 80010b2: 7e1b ldrb r3, [r3, #24] + 80010b4: 2b01 cmp r3, #1 + 80010b6: d108 bne.n 80010ca + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); + 80010b8: 687b ldr r3, [r7, #4] + 80010ba: 681b ldr r3, [r3, #0] + 80010bc: 681a ldr r2, [r3, #0] + 80010be: 687b ldr r3, [r7, #4] + 80010c0: 681b ldr r3, [r3, #0] + 80010c2: f042 0280 orr.w r2, r2, #128 @ 0x80 + 80010c6: 601a str r2, [r3, #0] + 80010c8: e007 b.n 80010da + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); + 80010ca: 687b ldr r3, [r7, #4] + 80010cc: 681b ldr r3, [r3, #0] + 80010ce: 681a ldr r2, [r3, #0] + 80010d0: 687b ldr r3, [r7, #4] + 80010d2: 681b ldr r3, [r3, #0] + 80010d4: f022 0280 bic.w r2, r2, #128 @ 0x80 + 80010d8: 601a str r2, [r3, #0] + } + + /* Set the automatic bus-off management */ + if (hcan->Init.AutoBusOff == ENABLE) + 80010da: 687b ldr r3, [r7, #4] + 80010dc: 7e5b ldrb r3, [r3, #25] + 80010de: 2b01 cmp r3, #1 + 80010e0: d108 bne.n 80010f4 + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); + 80010e2: 687b ldr r3, [r7, #4] + 80010e4: 681b ldr r3, [r3, #0] + 80010e6: 681a ldr r2, [r3, #0] + 80010e8: 687b ldr r3, [r7, #4] + 80010ea: 681b ldr r3, [r3, #0] + 80010ec: f042 0240 orr.w r2, r2, #64 @ 0x40 + 80010f0: 601a str r2, [r3, #0] + 80010f2: e007 b.n 8001104 + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); + 80010f4: 687b ldr r3, [r7, #4] + 80010f6: 681b ldr r3, [r3, #0] + 80010f8: 681a ldr r2, [r3, #0] + 80010fa: 687b ldr r3, [r7, #4] + 80010fc: 681b ldr r3, [r3, #0] + 80010fe: f022 0240 bic.w r2, r2, #64 @ 0x40 + 8001102: 601a str r2, [r3, #0] + } + + /* Set the automatic wake-up mode */ + if (hcan->Init.AutoWakeUp == ENABLE) + 8001104: 687b ldr r3, [r7, #4] + 8001106: 7e9b ldrb r3, [r3, #26] + 8001108: 2b01 cmp r3, #1 + 800110a: d108 bne.n 800111e + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); + 800110c: 687b ldr r3, [r7, #4] + 800110e: 681b ldr r3, [r3, #0] + 8001110: 681a ldr r2, [r3, #0] + 8001112: 687b ldr r3, [r7, #4] + 8001114: 681b ldr r3, [r3, #0] + 8001116: f042 0220 orr.w r2, r2, #32 + 800111a: 601a str r2, [r3, #0] + 800111c: e007 b.n 800112e + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); + 800111e: 687b ldr r3, [r7, #4] + 8001120: 681b ldr r3, [r3, #0] + 8001122: 681a ldr r2, [r3, #0] + 8001124: 687b ldr r3, [r7, #4] + 8001126: 681b ldr r3, [r3, #0] + 8001128: f022 0220 bic.w r2, r2, #32 + 800112c: 601a str r2, [r3, #0] + } + + /* Set the automatic retransmission */ + if (hcan->Init.AutoRetransmission == ENABLE) + 800112e: 687b ldr r3, [r7, #4] + 8001130: 7edb ldrb r3, [r3, #27] + 8001132: 2b01 cmp r3, #1 + 8001134: d108 bne.n 8001148 + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); + 8001136: 687b ldr r3, [r7, #4] + 8001138: 681b ldr r3, [r3, #0] + 800113a: 681a ldr r2, [r3, #0] + 800113c: 687b ldr r3, [r7, #4] + 800113e: 681b ldr r3, [r3, #0] + 8001140: f022 0210 bic.w r2, r2, #16 + 8001144: 601a str r2, [r3, #0] + 8001146: e007 b.n 8001158 + } + else + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); + 8001148: 687b ldr r3, [r7, #4] + 800114a: 681b ldr r3, [r3, #0] + 800114c: 681a ldr r2, [r3, #0] + 800114e: 687b ldr r3, [r7, #4] + 8001150: 681b ldr r3, [r3, #0] + 8001152: f042 0210 orr.w r2, r2, #16 + 8001156: 601a str r2, [r3, #0] + } + + /* Set the receive FIFO locked mode */ + if (hcan->Init.ReceiveFifoLocked == ENABLE) + 8001158: 687b ldr r3, [r7, #4] + 800115a: 7f1b ldrb r3, [r3, #28] + 800115c: 2b01 cmp r3, #1 + 800115e: d108 bne.n 8001172 + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + 8001160: 687b ldr r3, [r7, #4] + 8001162: 681b ldr r3, [r3, #0] + 8001164: 681a ldr r2, [r3, #0] + 8001166: 687b ldr r3, [r7, #4] + 8001168: 681b ldr r3, [r3, #0] + 800116a: f042 0208 orr.w r2, r2, #8 + 800116e: 601a str r2, [r3, #0] + 8001170: e007 b.n 8001182 + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + 8001172: 687b ldr r3, [r7, #4] + 8001174: 681b ldr r3, [r3, #0] + 8001176: 681a ldr r2, [r3, #0] + 8001178: 687b ldr r3, [r7, #4] + 800117a: 681b ldr r3, [r3, #0] + 800117c: f022 0208 bic.w r2, r2, #8 + 8001180: 601a str r2, [r3, #0] + } + + /* Set the transmit FIFO priority */ + if (hcan->Init.TransmitFifoPriority == ENABLE) + 8001182: 687b ldr r3, [r7, #4] + 8001184: 7f5b ldrb r3, [r3, #29] + 8001186: 2b01 cmp r3, #1 + 8001188: d108 bne.n 800119c + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + 800118a: 687b ldr r3, [r7, #4] + 800118c: 681b ldr r3, [r3, #0] + 800118e: 681a ldr r2, [r3, #0] + 8001190: 687b ldr r3, [r7, #4] + 8001192: 681b ldr r3, [r3, #0] + 8001194: f042 0204 orr.w r2, r2, #4 + 8001198: 601a str r2, [r3, #0] + 800119a: e007 b.n 80011ac + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + 800119c: 687b ldr r3, [r7, #4] + 800119e: 681b ldr r3, [r3, #0] + 80011a0: 681a ldr r2, [r3, #0] + 80011a2: 687b ldr r3, [r7, #4] + 80011a4: 681b ldr r3, [r3, #0] + 80011a6: f022 0204 bic.w r2, r2, #4 + 80011aa: 601a str r2, [r3, #0] + } + + /* Set the bit timing register */ + WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | + 80011ac: 687b ldr r3, [r7, #4] + 80011ae: 689a ldr r2, [r3, #8] + 80011b0: 687b ldr r3, [r7, #4] + 80011b2: 68db ldr r3, [r3, #12] + 80011b4: 431a orrs r2, r3 + 80011b6: 687b ldr r3, [r7, #4] + 80011b8: 691b ldr r3, [r3, #16] + 80011ba: 431a orrs r2, r3 + 80011bc: 687b ldr r3, [r7, #4] + 80011be: 695b ldr r3, [r3, #20] + 80011c0: ea42 0103 orr.w r1, r2, r3 + 80011c4: 687b ldr r3, [r7, #4] + 80011c6: 685b ldr r3, [r3, #4] + 80011c8: 1e5a subs r2, r3, #1 + 80011ca: 687b ldr r3, [r7, #4] + 80011cc: 681b ldr r3, [r3, #0] + 80011ce: 430a orrs r2, r1 + 80011d0: 61da str r2, [r3, #28] + hcan->Init.TimeSeg1 | + hcan->Init.TimeSeg2 | + (hcan->Init.Prescaler - 1U))); + + /* Initialize the error code */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + 80011d2: 687b ldr r3, [r7, #4] + 80011d4: 2200 movs r2, #0 + 80011d6: 625a str r2, [r3, #36] @ 0x24 + + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_READY; + 80011d8: 687b ldr r3, [r7, #4] + 80011da: 2201 movs r2, #1 + 80011dc: f883 2020 strb.w r2, [r3, #32] + + /* Return function status */ + return HAL_OK; + 80011e0: 2300 movs r3, #0 +} + 80011e2: 4618 mov r0, r3 + 80011e4: 3710 adds r7, #16 + 80011e6: 46bd mov sp, r7 + 80011e8: bd80 pop {r7, pc} + 80011ea: bf00 nop + 80011ec: 080012bd .word 0x080012bd + 80011f0: 080012d1 .word 0x080012d1 + 80011f4: 0800121d .word 0x0800121d + 80011f8: 08001231 .word 0x08001231 + 80011fc: 08001245 .word 0x08001245 + 8001200: 08001259 .word 0x08001259 + 8001204: 0800126d .word 0x0800126d + 8001208: 08001281 .word 0x08001281 + 800120c: 080012e5 .word 0x080012e5 + 8001210: 080012f9 .word 0x080012f9 + 8001214: 0800130d .word 0x0800130d + 8001218: 080008b9 .word 0x080008b9 + +0800121c : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) +{ + 800121c: b480 push {r7} + 800121e: b083 sub sp, #12 + 8001220: af00 add r7, sp, #0 + 8001222: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the + user file + */ +} + 8001224: bf00 nop + 8001226: 370c adds r7, #12 + 8001228: 46bd mov sp, r7 + 800122a: f85d 7b04 ldr.w r7, [sp], #4 + 800122e: 4770 bx lr + +08001230 : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) +{ + 8001230: b480 push {r7} + 8001232: b083 sub sp, #12 + 8001234: af00 add r7, sp, #0 + 8001236: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the + user file + */ +} + 8001238: bf00 nop + 800123a: 370c adds r7, #12 + 800123c: 46bd mov sp, r7 + 800123e: f85d 7b04 ldr.w r7, [sp], #4 + 8001242: 4770 bx lr + +08001244 : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) +{ + 8001244: b480 push {r7} + 8001246: b083 sub sp, #12 + 8001248: af00 add r7, sp, #0 + 800124a: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the + user file + */ +} + 800124c: bf00 nop + 800124e: 370c adds r7, #12 + 8001250: 46bd mov sp, r7 + 8001252: f85d 7b04 ldr.w r7, [sp], #4 + 8001256: 4770 bx lr + +08001258 : + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) +{ + 8001258: b480 push {r7} + 800125a: b083 sub sp, #12 + 800125c: af00 add r7, sp, #0 + 800125e: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0AbortCallback could be implemented in the + user file + */ +} + 8001260: bf00 nop + 8001262: 370c adds r7, #12 + 8001264: 46bd mov sp, r7 + 8001266: f85d 7b04 ldr.w r7, [sp], #4 + 800126a: 4770 bx lr + +0800126c : + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) +{ + 800126c: b480 push {r7} + 800126e: b083 sub sp, #12 + 8001270: af00 add r7, sp, #0 + 8001272: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1AbortCallback could be implemented in the + user file + */ +} + 8001274: bf00 nop + 8001276: 370c adds r7, #12 + 8001278: 46bd mov sp, r7 + 800127a: f85d 7b04 ldr.w r7, [sp], #4 + 800127e: 4770 bx lr + +08001280 : + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) +{ + 8001280: b480 push {r7} + 8001282: b083 sub sp, #12 + 8001284: af00 add r7, sp, #0 + 8001286: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2AbortCallback could be implemented in the + user file + */ +} + 8001288: bf00 nop + 800128a: 370c adds r7, #12 + 800128c: 46bd mov sp, r7 + 800128e: f85d 7b04 ldr.w r7, [sp], #4 + 8001292: 4770 bx lr + +08001294 : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + 8001294: b480 push {r7} + 8001296: b083 sub sp, #12 + 8001298: af00 add r7, sp, #0 + 800129a: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the + user file + */ +} + 800129c: bf00 nop + 800129e: 370c adds r7, #12 + 80012a0: 46bd mov sp, r7 + 80012a2: f85d 7b04 ldr.w r7, [sp], #4 + 80012a6: 4770 bx lr + +080012a8 : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) +{ + 80012a8: b480 push {r7} + 80012aa: b083 sub sp, #12 + 80012ac: af00 add r7, sp, #0 + 80012ae: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0FullCallback could be implemented in the user + file + */ +} + 80012b0: bf00 nop + 80012b2: 370c adds r7, #12 + 80012b4: 46bd mov sp, r7 + 80012b6: f85d 7b04 ldr.w r7, [sp], #4 + 80012ba: 4770 bx lr + +080012bc : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + 80012bc: b480 push {r7} + 80012be: b083 sub sp, #12 + 80012c0: af00 add r7, sp, #0 + 80012c2: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the + user file + */ +} + 80012c4: bf00 nop + 80012c6: 370c adds r7, #12 + 80012c8: 46bd mov sp, r7 + 80012ca: f85d 7b04 ldr.w r7, [sp], #4 + 80012ce: 4770 bx lr + +080012d0 : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) +{ + 80012d0: b480 push {r7} + 80012d2: b083 sub sp, #12 + 80012d4: af00 add r7, sp, #0 + 80012d6: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1FullCallback could be implemented in the user + file + */ +} + 80012d8: bf00 nop + 80012da: 370c adds r7, #12 + 80012dc: 46bd mov sp, r7 + 80012de: f85d 7b04 ldr.w r7, [sp], #4 + 80012e2: 4770 bx lr + +080012e4 : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) +{ + 80012e4: b480 push {r7} + 80012e6: b083 sub sp, #12 + 80012e8: af00 add r7, sp, #0 + 80012ea: 6078 str r0, [r7, #4] + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_SleepCallback could be implemented in the user file + */ +} + 80012ec: bf00 nop + 80012ee: 370c adds r7, #12 + 80012f0: 46bd mov sp, r7 + 80012f2: f85d 7b04 ldr.w r7, [sp], #4 + 80012f6: 4770 bx lr + +080012f8 : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) +{ + 80012f8: b480 push {r7} + 80012fa: b083 sub sp, #12 + 80012fc: af00 add r7, sp, #0 + 80012fe: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the + user file + */ +} + 8001300: bf00 nop + 8001302: 370c adds r7, #12 + 8001304: 46bd mov sp, r7 + 8001306: f85d 7b04 ldr.w r7, [sp], #4 + 800130a: 4770 bx lr + +0800130c : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) +{ + 800130c: b480 push {r7} + 800130e: b083 sub sp, #12 + 8001310: af00 add r7, sp, #0 + 8001312: 6078 str r0, [r7, #4] + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_ErrorCallback could be implemented in the user file + */ +} + 8001314: bf00 nop + 8001316: 370c adds r7, #12 + 8001318: 46bd mov sp, r7 + 800131a: f85d 7b04 ldr.w r7, [sp], #4 + 800131e: 4770 bx lr + +08001320 <__NVIC_SetPriorityGrouping>: + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8001320: b480 push {r7} + 8001322: b085 sub sp, #20 + 8001324: af00 add r7, sp, #0 + 8001326: 6078 str r0, [r7, #4] + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8001328: 687b ldr r3, [r7, #4] + 800132a: f003 0307 and.w r3, r3, #7 + 800132e: 60fb str r3, [r7, #12] + + reg_value = SCB->AIRCR; /* read old register configuration */ + 8001330: 4b0c ldr r3, [pc, #48] @ (8001364 <__NVIC_SetPriorityGrouping+0x44>) + 8001332: 68db ldr r3, [r3, #12] + 8001334: 60bb str r3, [r7, #8] + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + 8001336: 68ba ldr r2, [r7, #8] + 8001338: f64f 03ff movw r3, #63743 @ 0xf8ff + 800133c: 4013 ands r3, r2 + 800133e: 60bb str r3, [r7, #8] + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + 8001340: 68fb ldr r3, [r7, #12] + 8001342: 021a lsls r2, r3, #8 + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 8001344: 68bb ldr r3, [r7, #8] + 8001346: 4313 orrs r3, r2 + reg_value = (reg_value | + 8001348: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 + 800134c: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 8001350: 60bb str r3, [r7, #8] + SCB->AIRCR = reg_value; + 8001352: 4a04 ldr r2, [pc, #16] @ (8001364 <__NVIC_SetPriorityGrouping+0x44>) + 8001354: 68bb ldr r3, [r7, #8] + 8001356: 60d3 str r3, [r2, #12] +} + 8001358: bf00 nop + 800135a: 3714 adds r7, #20 + 800135c: 46bd mov sp, r7 + 800135e: f85d 7b04 ldr.w r7, [sp], #4 + 8001362: 4770 bx lr + 8001364: e000ed00 .word 0xe000ed00 + +08001368 <__NVIC_GetPriorityGrouping>: + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + 8001368: b480 push {r7} + 800136a: af00 add r7, sp, #0 + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + 800136c: 4b04 ldr r3, [pc, #16] @ (8001380 <__NVIC_GetPriorityGrouping+0x18>) + 800136e: 68db ldr r3, [r3, #12] + 8001370: 0a1b lsrs r3, r3, #8 + 8001372: f003 0307 and.w r3, r3, #7 +} + 8001376: 4618 mov r0, r3 + 8001378: 46bd mov sp, r7 + 800137a: f85d 7b04 ldr.w r7, [sp], #4 + 800137e: 4770 bx lr + 8001380: e000ed00 .word 0xe000ed00 + +08001384 <__NVIC_EnableIRQ>: + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8001384: b480 push {r7} + 8001386: b083 sub sp, #12 + 8001388: af00 add r7, sp, #0 + 800138a: 4603 mov r3, r0 + 800138c: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 800138e: f997 3007 ldrsb.w r3, [r7, #7] + 8001392: 2b00 cmp r3, #0 + 8001394: db0b blt.n 80013ae <__NVIC_EnableIRQ+0x2a> + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 8001396: 79fb ldrb r3, [r7, #7] + 8001398: f003 021f and.w r2, r3, #31 + 800139c: 4907 ldr r1, [pc, #28] @ (80013bc <__NVIC_EnableIRQ+0x38>) + 800139e: f997 3007 ldrsb.w r3, [r7, #7] + 80013a2: 095b lsrs r3, r3, #5 + 80013a4: 2001 movs r0, #1 + 80013a6: fa00 f202 lsl.w r2, r0, r2 + 80013aa: f841 2023 str.w r2, [r1, r3, lsl #2] + __COMPILER_BARRIER(); + } +} + 80013ae: bf00 nop + 80013b0: 370c adds r7, #12 + 80013b2: 46bd mov sp, r7 + 80013b4: f85d 7b04 ldr.w r7, [sp], #4 + 80013b8: 4770 bx lr + 80013ba: bf00 nop + 80013bc: e000e100 .word 0xe000e100 + +080013c0 <__NVIC_SetPriority>: + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + 80013c0: b480 push {r7} + 80013c2: b083 sub sp, #12 + 80013c4: af00 add r7, sp, #0 + 80013c6: 4603 mov r3, r0 + 80013c8: 6039 str r1, [r7, #0] + 80013ca: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 80013cc: f997 3007 ldrsb.w r3, [r7, #7] + 80013d0: 2b00 cmp r3, #0 + 80013d2: db0a blt.n 80013ea <__NVIC_SetPriority+0x2a> + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 80013d4: 683b ldr r3, [r7, #0] + 80013d6: b2da uxtb r2, r3 + 80013d8: 490c ldr r1, [pc, #48] @ (800140c <__NVIC_SetPriority+0x4c>) + 80013da: f997 3007 ldrsb.w r3, [r7, #7] + 80013de: 0112 lsls r2, r2, #4 + 80013e0: b2d2 uxtb r2, r2 + 80013e2: 440b add r3, r1 + 80013e4: f883 2300 strb.w r2, [r3, #768] @ 0x300 + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + 80013e8: e00a b.n 8001400 <__NVIC_SetPriority+0x40> + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 80013ea: 683b ldr r3, [r7, #0] + 80013ec: b2da uxtb r2, r3 + 80013ee: 4908 ldr r1, [pc, #32] @ (8001410 <__NVIC_SetPriority+0x50>) + 80013f0: 79fb ldrb r3, [r7, #7] + 80013f2: f003 030f and.w r3, r3, #15 + 80013f6: 3b04 subs r3, #4 + 80013f8: 0112 lsls r2, r2, #4 + 80013fa: b2d2 uxtb r2, r2 + 80013fc: 440b add r3, r1 + 80013fe: 761a strb r2, [r3, #24] +} + 8001400: bf00 nop + 8001402: 370c adds r7, #12 + 8001404: 46bd mov sp, r7 + 8001406: f85d 7b04 ldr.w r7, [sp], #4 + 800140a: 4770 bx lr + 800140c: e000e100 .word 0xe000e100 + 8001410: e000ed00 .word 0xe000ed00 + +08001414 : + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8001414: b480 push {r7} + 8001416: b089 sub sp, #36 @ 0x24 + 8001418: af00 add r7, sp, #0 + 800141a: 60f8 str r0, [r7, #12] + 800141c: 60b9 str r1, [r7, #8] + 800141e: 607a str r2, [r7, #4] + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8001420: 68fb ldr r3, [r7, #12] + 8001422: f003 0307 and.w r3, r3, #7 + 8001426: 61fb str r3, [r7, #28] + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + 8001428: 69fb ldr r3, [r7, #28] + 800142a: f1c3 0307 rsb r3, r3, #7 + 800142e: 2b04 cmp r3, #4 + 8001430: bf28 it cs + 8001432: 2304 movcs r3, #4 + 8001434: 61bb str r3, [r7, #24] + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + 8001436: 69fb ldr r3, [r7, #28] + 8001438: 3304 adds r3, #4 + 800143a: 2b06 cmp r3, #6 + 800143c: d902 bls.n 8001444 + 800143e: 69fb ldr r3, [r7, #28] + 8001440: 3b03 subs r3, #3 + 8001442: e000 b.n 8001446 + 8001444: 2300 movs r3, #0 + 8001446: 617b str r3, [r7, #20] + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8001448: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 800144c: 69bb ldr r3, [r7, #24] + 800144e: fa02 f303 lsl.w r3, r2, r3 + 8001452: 43da mvns r2, r3 + 8001454: 68bb ldr r3, [r7, #8] + 8001456: 401a ands r2, r3 + 8001458: 697b ldr r3, [r7, #20] + 800145a: 409a lsls r2, r3 + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 800145c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff + 8001460: 697b ldr r3, [r7, #20] + 8001462: fa01 f303 lsl.w r3, r1, r3 + 8001466: 43d9 mvns r1, r3 + 8001468: 687b ldr r3, [r7, #4] + 800146a: 400b ands r3, r1 + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 800146c: 4313 orrs r3, r2 + ); +} + 800146e: 4618 mov r0, r3 + 8001470: 3724 adds r7, #36 @ 0x24 + 8001472: 46bd mov sp, r7 + 8001474: f85d 7b04 ldr.w r7, [sp], #4 + 8001478: 4770 bx lr + ... + +0800147c : + * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 800147c: b580 push {r7, lr} + 800147e: b082 sub sp, #8 + 8001480: af00 add r7, sp, #0 + 8001482: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + 8001484: 687b ldr r3, [r7, #4] + 8001486: 2b07 cmp r3, #7 + 8001488: d00f beq.n 80014aa + 800148a: 687b ldr r3, [r7, #4] + 800148c: 2b06 cmp r3, #6 + 800148e: d00c beq.n 80014aa + 8001490: 687b ldr r3, [r7, #4] + 8001492: 2b05 cmp r3, #5 + 8001494: d009 beq.n 80014aa + 8001496: 687b ldr r3, [r7, #4] + 8001498: 2b04 cmp r3, #4 + 800149a: d006 beq.n 80014aa + 800149c: 687b ldr r3, [r7, #4] + 800149e: 2b03 cmp r3, #3 + 80014a0: d003 beq.n 80014aa + 80014a2: 2190 movs r1, #144 @ 0x90 + 80014a4: 4804 ldr r0, [pc, #16] @ (80014b8 ) + 80014a6: f7ff f9cf bl 8000848 + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); + 80014aa: 6878 ldr r0, [r7, #4] + 80014ac: f7ff ff38 bl 8001320 <__NVIC_SetPriorityGrouping> +} + 80014b0: bf00 nop + 80014b2: 3708 adds r7, #8 + 80014b4: 46bd mov sp, r7 + 80014b6: bd80 pop {r7, pc} + 80014b8: 08005c20 .word 0x08005c20 + +080014bc : + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 80014bc: b580 push {r7, lr} + 80014be: b086 sub sp, #24 + 80014c0: af00 add r7, sp, #0 + 80014c2: 4603 mov r3, r0 + 80014c4: 60b9 str r1, [r7, #8] + 80014c6: 607a str r2, [r7, #4] + 80014c8: 73fb strb r3, [r7, #15] + uint32_t prioritygroup = 0x00U; + 80014ca: 2300 movs r3, #0 + 80014cc: 617b str r3, [r7, #20] + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + 80014ce: 687b ldr r3, [r7, #4] + 80014d0: 2b0f cmp r3, #15 + 80014d2: d903 bls.n 80014dc + 80014d4: 21a8 movs r1, #168 @ 0xa8 + 80014d6: 480e ldr r0, [pc, #56] @ (8001510 ) + 80014d8: f7ff f9b6 bl 8000848 + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + 80014dc: 68bb ldr r3, [r7, #8] + 80014de: 2b0f cmp r3, #15 + 80014e0: d903 bls.n 80014ea + 80014e2: 21a9 movs r1, #169 @ 0xa9 + 80014e4: 480a ldr r0, [pc, #40] @ (8001510 ) + 80014e6: f7ff f9af bl 8000848 + + prioritygroup = NVIC_GetPriorityGrouping(); + 80014ea: f7ff ff3d bl 8001368 <__NVIC_GetPriorityGrouping> + 80014ee: 6178 str r0, [r7, #20] + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 80014f0: 687a ldr r2, [r7, #4] + 80014f2: 68b9 ldr r1, [r7, #8] + 80014f4: 6978 ldr r0, [r7, #20] + 80014f6: f7ff ff8d bl 8001414 + 80014fa: 4602 mov r2, r0 + 80014fc: f997 300f ldrsb.w r3, [r7, #15] + 8001500: 4611 mov r1, r2 + 8001502: 4618 mov r0, r3 + 8001504: f7ff ff5c bl 80013c0 <__NVIC_SetPriority> +} + 8001508: bf00 nop + 800150a: 3718 adds r7, #24 + 800150c: 46bd mov sp, r7 + 800150e: bd80 pop {r7, pc} + 8001510: 08005c20 .word 0x08005c20 + +08001514 : + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8001514: b580 push {r7, lr} + 8001516: b082 sub sp, #8 + 8001518: af00 add r7, sp, #0 + 800151a: 4603 mov r3, r0 + 800151c: 71fb strb r3, [r7, #7] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + 800151e: f997 3007 ldrsb.w r3, [r7, #7] + 8001522: 2b00 cmp r3, #0 + 8001524: da03 bge.n 800152e + 8001526: 21bc movs r1, #188 @ 0xbc + 8001528: 4805 ldr r0, [pc, #20] @ (8001540 ) + 800152a: f7ff f98d bl 8000848 + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); + 800152e: f997 3007 ldrsb.w r3, [r7, #7] + 8001532: 4618 mov r0, r3 + 8001534: f7ff ff26 bl 8001384 <__NVIC_EnableIRQ> +} + 8001538: bf00 nop + 800153a: 3708 adds r7, #8 + 800153c: 46bd mov sp, r7 + 800153e: bd80 pop {r7, pc} + 8001540: 08005c20 .word 0x08005c20 + +08001544 : + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + 8001544: b580 push {r7, lr} + 8001546: b088 sub sp, #32 + 8001548: af00 add r7, sp, #0 + 800154a: 6078 str r0, [r7, #4] + 800154c: 6039 str r1, [r7, #0] + uint32_t position; + uint32_t ioposition = 0x00U; + 800154e: 2300 movs r3, #0 + 8001550: 617b str r3, [r7, #20] + uint32_t iocurrent = 0x00U; + 8001552: 2300 movs r3, #0 + 8001554: 613b str r3, [r7, #16] + uint32_t temp = 0x00U; + 8001556: 2300 movs r3, #0 + 8001558: 61bb str r3, [r7, #24] + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + 800155a: 687b ldr r3, [r7, #4] + 800155c: 4a38 ldr r2, [pc, #224] @ (8001640 ) + 800155e: 4293 cmp r3, r2 + 8001560: d023 beq.n 80015aa + 8001562: 687b ldr r3, [r7, #4] + 8001564: 4a37 ldr r2, [pc, #220] @ (8001644 ) + 8001566: 4293 cmp r3, r2 + 8001568: d01f beq.n 80015aa + 800156a: 687b ldr r3, [r7, #4] + 800156c: 4a36 ldr r2, [pc, #216] @ (8001648 ) + 800156e: 4293 cmp r3, r2 + 8001570: d01b beq.n 80015aa + 8001572: 687b ldr r3, [r7, #4] + 8001574: 4a35 ldr r2, [pc, #212] @ (800164c ) + 8001576: 4293 cmp r3, r2 + 8001578: d017 beq.n 80015aa + 800157a: 687b ldr r3, [r7, #4] + 800157c: 4a34 ldr r2, [pc, #208] @ (8001650 ) + 800157e: 4293 cmp r3, r2 + 8001580: d013 beq.n 80015aa + 8001582: 687b ldr r3, [r7, #4] + 8001584: 4a33 ldr r2, [pc, #204] @ (8001654 ) + 8001586: 4293 cmp r3, r2 + 8001588: d00f beq.n 80015aa + 800158a: 687b ldr r3, [r7, #4] + 800158c: 4a32 ldr r2, [pc, #200] @ (8001658 ) + 800158e: 4293 cmp r3, r2 + 8001590: d00b beq.n 80015aa + 8001592: 687b ldr r3, [r7, #4] + 8001594: 4a31 ldr r2, [pc, #196] @ (800165c ) + 8001596: 4293 cmp r3, r2 + 8001598: d007 beq.n 80015aa + 800159a: 687b ldr r3, [r7, #4] + 800159c: 4a30 ldr r2, [pc, #192] @ (8001660 ) + 800159e: 4293 cmp r3, r2 + 80015a0: d003 beq.n 80015aa + 80015a2: 21ac movs r1, #172 @ 0xac + 80015a4: 482f ldr r0, [pc, #188] @ (8001664 ) + 80015a6: f7ff f94f bl 8000848 + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + 80015aa: 683b ldr r3, [r7, #0] + 80015ac: 681b ldr r3, [r3, #0] + 80015ae: b29b uxth r3, r3 + 80015b0: 2b00 cmp r3, #0 + 80015b2: d004 beq.n 80015be + 80015b4: 683b ldr r3, [r7, #0] + 80015b6: 681b ldr r3, [r3, #0] + 80015b8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 80015bc: d303 bcc.n 80015c6 + 80015be: 21ad movs r1, #173 @ 0xad + 80015c0: 4828 ldr r0, [pc, #160] @ (8001664 ) + 80015c2: f7ff f941 bl 8000848 + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + 80015c6: 683b ldr r3, [r7, #0] + 80015c8: 685b ldr r3, [r3, #4] + 80015ca: 2b00 cmp r3, #0 + 80015cc: d035 beq.n 800163a + 80015ce: 683b ldr r3, [r7, #0] + 80015d0: 685b ldr r3, [r3, #4] + 80015d2: 2b01 cmp r3, #1 + 80015d4: d031 beq.n 800163a + 80015d6: 683b ldr r3, [r7, #0] + 80015d8: 685b ldr r3, [r3, #4] + 80015da: 2b11 cmp r3, #17 + 80015dc: d02d beq.n 800163a + 80015de: 683b ldr r3, [r7, #0] + 80015e0: 685b ldr r3, [r3, #4] + 80015e2: 2b02 cmp r3, #2 + 80015e4: d029 beq.n 800163a + 80015e6: 683b ldr r3, [r7, #0] + 80015e8: 685b ldr r3, [r3, #4] + 80015ea: 2b12 cmp r3, #18 + 80015ec: d025 beq.n 800163a + 80015ee: 683b ldr r3, [r7, #0] + 80015f0: 685b ldr r3, [r3, #4] + 80015f2: f5b3 1f88 cmp.w r3, #1114112 @ 0x110000 + 80015f6: d020 beq.n 800163a + 80015f8: 683b ldr r3, [r7, #0] + 80015fa: 685b ldr r3, [r3, #4] + 80015fc: f5b3 1f04 cmp.w r3, #2162688 @ 0x210000 + 8001600: d01b beq.n 800163a + 8001602: 683b ldr r3, [r7, #0] + 8001604: 685b ldr r3, [r3, #4] + 8001606: f5b3 1f44 cmp.w r3, #3211264 @ 0x310000 + 800160a: d016 beq.n 800163a + 800160c: 683b ldr r3, [r7, #0] + 800160e: 685b ldr r3, [r3, #4] + 8001610: f5b3 1f90 cmp.w r3, #1179648 @ 0x120000 + 8001614: d011 beq.n 800163a + 8001616: 683b ldr r3, [r7, #0] + 8001618: 685b ldr r3, [r3, #4] + 800161a: f5b3 1f08 cmp.w r3, #2228224 @ 0x220000 + 800161e: d00c beq.n 800163a + 8001620: 683b ldr r3, [r7, #0] + 8001622: 685b ldr r3, [r3, #4] + 8001624: f5b3 1f48 cmp.w r3, #3276800 @ 0x320000 + 8001628: d007 beq.n 800163a + 800162a: 683b ldr r3, [r7, #0] + 800162c: 685b ldr r3, [r3, #4] + 800162e: 2b03 cmp r3, #3 + 8001630: d003 beq.n 800163a + 8001632: 21ae movs r1, #174 @ 0xae + 8001634: 480b ldr r0, [pc, #44] @ (8001664 ) + 8001636: f7ff f907 bl 8000848 + + /* Configure the port pins */ + for(position = 0U; position < GPIO_NUMBER; position++) + 800163a: 2300 movs r3, #0 + 800163c: 61fb str r3, [r7, #28] + 800163e: e235 b.n 8001aac + 8001640: 40020000 .word 0x40020000 + 8001644: 40020400 .word 0x40020400 + 8001648: 40020800 .word 0x40020800 + 800164c: 40020c00 .word 0x40020c00 + 8001650: 40021000 .word 0x40021000 + 8001654: 40021400 .word 0x40021400 + 8001658: 40021800 .word 0x40021800 + 800165c: 40021c00 .word 0x40021c00 + 8001660: 40022000 .word 0x40022000 + 8001664: 08005c5c .word 0x08005c5c + { + /* Get the IO position */ + ioposition = 0x01U << position; + 8001668: 2201 movs r2, #1 + 800166a: 69fb ldr r3, [r7, #28] + 800166c: fa02 f303 lsl.w r3, r2, r3 + 8001670: 617b str r3, [r7, #20] + /* Get the current IO position */ + iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; + 8001672: 683b ldr r3, [r7, #0] + 8001674: 681b ldr r3, [r3, #0] + 8001676: 697a ldr r2, [r7, #20] + 8001678: 4013 ands r3, r2 + 800167a: 613b str r3, [r7, #16] + + if(iocurrent == ioposition) + 800167c: 693a ldr r2, [r7, #16] + 800167e: 697b ldr r3, [r7, #20] + 8001680: 429a cmp r2, r3 + 8001682: f040 8210 bne.w 8001aa6 + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ + 8001686: 683b ldr r3, [r7, #0] + 8001688: 685b ldr r3, [r3, #4] + 800168a: f003 0303 and.w r3, r3, #3 + 800168e: 2b01 cmp r3, #1 + 8001690: d005 beq.n 800169e + (GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + 8001692: 683b ldr r3, [r7, #0] + 8001694: 685b ldr r3, [r3, #4] + 8001696: f003 0303 and.w r3, r3, #3 + if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ + 800169a: 2b02 cmp r3, #2 + 800169c: d144 bne.n 8001728 + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + 800169e: 683b ldr r3, [r7, #0] + 80016a0: 68db ldr r3, [r3, #12] + 80016a2: 2b00 cmp r3, #0 + 80016a4: d00f beq.n 80016c6 + 80016a6: 683b ldr r3, [r7, #0] + 80016a8: 68db ldr r3, [r3, #12] + 80016aa: 2b01 cmp r3, #1 + 80016ac: d00b beq.n 80016c6 + 80016ae: 683b ldr r3, [r7, #0] + 80016b0: 68db ldr r3, [r3, #12] + 80016b2: 2b02 cmp r3, #2 + 80016b4: d007 beq.n 80016c6 + 80016b6: 683b ldr r3, [r7, #0] + 80016b8: 68db ldr r3, [r3, #12] + 80016ba: 2b03 cmp r3, #3 + 80016bc: d003 beq.n 80016c6 + 80016be: 21c0 movs r1, #192 @ 0xc0 + 80016c0: 488d ldr r0, [pc, #564] @ (80018f8 ) + 80016c2: f7ff f8c1 bl 8000848 + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + 80016c6: 687b ldr r3, [r7, #4] + 80016c8: 689b ldr r3, [r3, #8] + 80016ca: 61bb str r3, [r7, #24] + temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); + 80016cc: 69fb ldr r3, [r7, #28] + 80016ce: 005b lsls r3, r3, #1 + 80016d0: 2203 movs r2, #3 + 80016d2: fa02 f303 lsl.w r3, r2, r3 + 80016d6: 43db mvns r3, r3 + 80016d8: 69ba ldr r2, [r7, #24] + 80016da: 4013 ands r3, r2 + 80016dc: 61bb str r3, [r7, #24] + temp |= (GPIO_Init->Speed << (position * 2U)); + 80016de: 683b ldr r3, [r7, #0] + 80016e0: 68da ldr r2, [r3, #12] + 80016e2: 69fb ldr r3, [r7, #28] + 80016e4: 005b lsls r3, r3, #1 + 80016e6: fa02 f303 lsl.w r3, r2, r3 + 80016ea: 69ba ldr r2, [r7, #24] + 80016ec: 4313 orrs r3, r2 + 80016ee: 61bb str r3, [r7, #24] + GPIOx->OSPEEDR = temp; + 80016f0: 687b ldr r3, [r7, #4] + 80016f2: 69ba ldr r2, [r7, #24] + 80016f4: 609a str r2, [r3, #8] + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + 80016f6: 687b ldr r3, [r7, #4] + 80016f8: 685b ldr r3, [r3, #4] + 80016fa: 61bb str r3, [r7, #24] + temp &= ~(GPIO_OTYPER_OT_0 << position) ; + 80016fc: 2201 movs r2, #1 + 80016fe: 69fb ldr r3, [r7, #28] + 8001700: fa02 f303 lsl.w r3, r2, r3 + 8001704: 43db mvns r3, r3 + 8001706: 69ba ldr r2, [r7, #24] + 8001708: 4013 ands r3, r2 + 800170a: 61bb str r3, [r7, #24] + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + 800170c: 683b ldr r3, [r7, #0] + 800170e: 685b ldr r3, [r3, #4] + 8001710: 091b lsrs r3, r3, #4 + 8001712: f003 0201 and.w r2, r3, #1 + 8001716: 69fb ldr r3, [r7, #28] + 8001718: fa02 f303 lsl.w r3, r2, r3 + 800171c: 69ba ldr r2, [r7, #24] + 800171e: 4313 orrs r3, r2 + 8001720: 61bb str r3, [r7, #24] + GPIOx->OTYPER = temp; + 8001722: 687b ldr r3, [r7, #4] + 8001724: 69ba ldr r2, [r7, #24] + 8001726: 605a str r2, [r3, #4] + } + + if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + 8001728: 683b ldr r3, [r7, #0] + 800172a: 685b ldr r3, [r3, #4] + 800172c: f003 0303 and.w r3, r3, #3 + 8001730: 2b03 cmp r3, #3 + 8001732: d027 beq.n 8001784 + { + /* Check the parameters */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + 8001734: 683b ldr r3, [r7, #0] + 8001736: 689b ldr r3, [r3, #8] + 8001738: 2b00 cmp r3, #0 + 800173a: d00b beq.n 8001754 + 800173c: 683b ldr r3, [r7, #0] + 800173e: 689b ldr r3, [r3, #8] + 8001740: 2b01 cmp r3, #1 + 8001742: d007 beq.n 8001754 + 8001744: 683b ldr r3, [r7, #0] + 8001746: 689b ldr r3, [r3, #8] + 8001748: 2b02 cmp r3, #2 + 800174a: d003 beq.n 8001754 + 800174c: 21d1 movs r1, #209 @ 0xd1 + 800174e: 486a ldr r0, [pc, #424] @ (80018f8 ) + 8001750: f7ff f87a bl 8000848 + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + 8001754: 687b ldr r3, [r7, #4] + 8001756: 68db ldr r3, [r3, #12] + 8001758: 61bb str r3, [r7, #24] + temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); + 800175a: 69fb ldr r3, [r7, #28] + 800175c: 005b lsls r3, r3, #1 + 800175e: 2203 movs r2, #3 + 8001760: fa02 f303 lsl.w r3, r2, r3 + 8001764: 43db mvns r3, r3 + 8001766: 69ba ldr r2, [r7, #24] + 8001768: 4013 ands r3, r2 + 800176a: 61bb str r3, [r7, #24] + temp |= ((GPIO_Init->Pull) << (position * 2U)); + 800176c: 683b ldr r3, [r7, #0] + 800176e: 689a ldr r2, [r3, #8] + 8001770: 69fb ldr r3, [r7, #28] + 8001772: 005b lsls r3, r3, #1 + 8001774: fa02 f303 lsl.w r3, r2, r3 + 8001778: 69ba ldr r2, [r7, #24] + 800177a: 4313 orrs r3, r2 + 800177c: 61bb str r3, [r7, #24] + GPIOx->PUPDR = temp; + 800177e: 687b ldr r3, [r7, #4] + 8001780: 69ba ldr r2, [r7, #24] + 8001782: 60da str r2, [r3, #12] + } + + /* In case of Alternate function mode selection */ + if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + 8001784: 683b ldr r3, [r7, #0] + 8001786: 685b ldr r3, [r3, #4] + 8001788: f003 0303 and.w r3, r3, #3 + 800178c: 2b02 cmp r3, #2 + 800178e: f040 80b5 bne.w 80018fc + { + /* Check the Alternate function parameter */ + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + 8001792: 683b ldr r3, [r7, #0] + 8001794: 691b ldr r3, [r3, #16] + 8001796: 2b00 cmp r3, #0 + 8001798: f000 8089 beq.w 80018ae + 800179c: 683b ldr r3, [r7, #0] + 800179e: 691b ldr r3, [r3, #16] + 80017a0: 2b09 cmp r3, #9 + 80017a2: f000 8084 beq.w 80018ae + 80017a6: 683b ldr r3, [r7, #0] + 80017a8: 691b ldr r3, [r3, #16] + 80017aa: 2b00 cmp r3, #0 + 80017ac: d07f beq.n 80018ae + 80017ae: 683b ldr r3, [r7, #0] + 80017b0: 691b ldr r3, [r3, #16] + 80017b2: 2b00 cmp r3, #0 + 80017b4: d07b beq.n 80018ae + 80017b6: 683b ldr r3, [r7, #0] + 80017b8: 691b ldr r3, [r3, #16] + 80017ba: 2b00 cmp r3, #0 + 80017bc: d077 beq.n 80018ae + 80017be: 683b ldr r3, [r7, #0] + 80017c0: 691b ldr r3, [r3, #16] + 80017c2: 2b00 cmp r3, #0 + 80017c4: d073 beq.n 80018ae + 80017c6: 683b ldr r3, [r7, #0] + 80017c8: 691b ldr r3, [r3, #16] + 80017ca: 2b01 cmp r3, #1 + 80017cc: d06f beq.n 80018ae + 80017ce: 683b ldr r3, [r7, #0] + 80017d0: 691b ldr r3, [r3, #16] + 80017d2: 2b01 cmp r3, #1 + 80017d4: d06b beq.n 80018ae + 80017d6: 683b ldr r3, [r7, #0] + 80017d8: 691b ldr r3, [r3, #16] + 80017da: 2b02 cmp r3, #2 + 80017dc: d067 beq.n 80018ae + 80017de: 683b ldr r3, [r7, #0] + 80017e0: 691b ldr r3, [r3, #16] + 80017e2: 2b02 cmp r3, #2 + 80017e4: d063 beq.n 80018ae + 80017e6: 683b ldr r3, [r7, #0] + 80017e8: 691b ldr r3, [r3, #16] + 80017ea: 2b02 cmp r3, #2 + 80017ec: d05f beq.n 80018ae + 80017ee: 683b ldr r3, [r7, #0] + 80017f0: 691b ldr r3, [r3, #16] + 80017f2: 2b03 cmp r3, #3 + 80017f4: d05b beq.n 80018ae + 80017f6: 683b ldr r3, [r7, #0] + 80017f8: 691b ldr r3, [r3, #16] + 80017fa: 2b04 cmp r3, #4 + 80017fc: d057 beq.n 80018ae + 80017fe: 683b ldr r3, [r7, #0] + 8001800: 691b ldr r3, [r3, #16] + 8001802: 2b04 cmp r3, #4 + 8001804: d053 beq.n 80018ae + 8001806: 683b ldr r3, [r7, #0] + 8001808: 691b ldr r3, [r3, #16] + 800180a: 2b04 cmp r3, #4 + 800180c: d04f beq.n 80018ae + 800180e: 683b ldr r3, [r7, #0] + 8001810: 691b ldr r3, [r3, #16] + 8001812: 2b05 cmp r3, #5 + 8001814: d04b beq.n 80018ae + 8001816: 683b ldr r3, [r7, #0] + 8001818: 691b ldr r3, [r3, #16] + 800181a: 2b05 cmp r3, #5 + 800181c: d047 beq.n 80018ae + 800181e: 683b ldr r3, [r7, #0] + 8001820: 691b ldr r3, [r3, #16] + 8001822: 2b09 cmp r3, #9 + 8001824: d043 beq.n 80018ae + 8001826: 683b ldr r3, [r7, #0] + 8001828: 691b ldr r3, [r3, #16] + 800182a: 2b06 cmp r3, #6 + 800182c: d03f beq.n 80018ae + 800182e: 683b ldr r3, [r7, #0] + 8001830: 691b ldr r3, [r3, #16] + 8001832: 2b09 cmp r3, #9 + 8001834: d03b beq.n 80018ae + 8001836: 683b ldr r3, [r7, #0] + 8001838: 691b ldr r3, [r3, #16] + 800183a: 2b07 cmp r3, #7 + 800183c: d037 beq.n 80018ae + 800183e: 683b ldr r3, [r7, #0] + 8001840: 691b ldr r3, [r3, #16] + 8001842: 2b07 cmp r3, #7 + 8001844: d033 beq.n 80018ae + 8001846: 683b ldr r3, [r7, #0] + 8001848: 691b ldr r3, [r3, #16] + 800184a: 2b07 cmp r3, #7 + 800184c: d02f beq.n 80018ae + 800184e: 683b ldr r3, [r7, #0] + 8001850: 691b ldr r3, [r3, #16] + 8001852: 2b08 cmp r3, #8 + 8001854: d02b beq.n 80018ae + 8001856: 683b ldr r3, [r7, #0] + 8001858: 691b ldr r3, [r3, #16] + 800185a: 2b08 cmp r3, #8 + 800185c: d027 beq.n 80018ae + 800185e: 683b ldr r3, [r7, #0] + 8001860: 691b ldr r3, [r3, #16] + 8001862: 2b08 cmp r3, #8 + 8001864: d023 beq.n 80018ae + 8001866: 683b ldr r3, [r7, #0] + 8001868: 691b ldr r3, [r3, #16] + 800186a: 2b09 cmp r3, #9 + 800186c: d01f beq.n 80018ae + 800186e: 683b ldr r3, [r7, #0] + 8001870: 691b ldr r3, [r3, #16] + 8001872: 2b09 cmp r3, #9 + 8001874: d01b beq.n 80018ae + 8001876: 683b ldr r3, [r7, #0] + 8001878: 691b ldr r3, [r3, #16] + 800187a: 2b0a cmp r3, #10 + 800187c: d017 beq.n 80018ae + 800187e: 683b ldr r3, [r7, #0] + 8001880: 691b ldr r3, [r3, #16] + 8001882: 2b0a cmp r3, #10 + 8001884: d013 beq.n 80018ae + 8001886: 683b ldr r3, [r7, #0] + 8001888: 691b ldr r3, [r3, #16] + 800188a: 2b0c cmp r3, #12 + 800188c: d00f beq.n 80018ae + 800188e: 683b ldr r3, [r7, #0] + 8001890: 691b ldr r3, [r3, #16] + 8001892: 2b0c cmp r3, #12 + 8001894: d00b beq.n 80018ae + 8001896: 683b ldr r3, [r7, #0] + 8001898: 691b ldr r3, [r3, #16] + 800189a: 2b0c cmp r3, #12 + 800189c: d007 beq.n 80018ae + 800189e: 683b ldr r3, [r7, #0] + 80018a0: 691b ldr r3, [r3, #16] + 80018a2: 2b0f cmp r3, #15 + 80018a4: d003 beq.n 80018ae + 80018a6: 21de movs r1, #222 @ 0xde + 80018a8: 4813 ldr r0, [pc, #76] @ (80018f8 ) + 80018aa: f7fe ffcd bl 8000848 + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3U]; + 80018ae: 69fb ldr r3, [r7, #28] + 80018b0: 08da lsrs r2, r3, #3 + 80018b2: 687b ldr r3, [r7, #4] + 80018b4: 3208 adds r2, #8 + 80018b6: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80018ba: 61bb str r3, [r7, #24] + temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; + 80018bc: 69fb ldr r3, [r7, #28] + 80018be: f003 0307 and.w r3, r3, #7 + 80018c2: 009b lsls r3, r3, #2 + 80018c4: 220f movs r2, #15 + 80018c6: fa02 f303 lsl.w r3, r2, r3 + 80018ca: 43db mvns r3, r3 + 80018cc: 69ba ldr r2, [r7, #24] + 80018ce: 4013 ands r3, r2 + 80018d0: 61bb str r3, [r7, #24] + temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); + 80018d2: 683b ldr r3, [r7, #0] + 80018d4: 691a ldr r2, [r3, #16] + 80018d6: 69fb ldr r3, [r7, #28] + 80018d8: f003 0307 and.w r3, r3, #7 + 80018dc: 009b lsls r3, r3, #2 + 80018de: fa02 f303 lsl.w r3, r2, r3 + 80018e2: 69ba ldr r2, [r7, #24] + 80018e4: 4313 orrs r3, r2 + 80018e6: 61bb str r3, [r7, #24] + GPIOx->AFR[position >> 3U] = temp; + 80018e8: 69fb ldr r3, [r7, #28] + 80018ea: 08da lsrs r2, r3, #3 + 80018ec: 687b ldr r3, [r7, #4] + 80018ee: 3208 adds r2, #8 + 80018f0: 69b9 ldr r1, [r7, #24] + 80018f2: f843 1022 str.w r1, [r3, r2, lsl #2] + 80018f6: e001 b.n 80018fc + 80018f8: 08005c5c .word 0x08005c5c + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + 80018fc: 687b ldr r3, [r7, #4] + 80018fe: 681b ldr r3, [r3, #0] + 8001900: 61bb str r3, [r7, #24] + temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); + 8001902: 69fb ldr r3, [r7, #28] + 8001904: 005b lsls r3, r3, #1 + 8001906: 2203 movs r2, #3 + 8001908: fa02 f303 lsl.w r3, r2, r3 + 800190c: 43db mvns r3, r3 + 800190e: 69ba ldr r2, [r7, #24] + 8001910: 4013 ands r3, r2 + 8001912: 61bb str r3, [r7, #24] + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + 8001914: 683b ldr r3, [r7, #0] + 8001916: 685b ldr r3, [r3, #4] + 8001918: f003 0203 and.w r2, r3, #3 + 800191c: 69fb ldr r3, [r7, #28] + 800191e: 005b lsls r3, r3, #1 + 8001920: fa02 f303 lsl.w r3, r2, r3 + 8001924: 69ba ldr r2, [r7, #24] + 8001926: 4313 orrs r3, r2 + 8001928: 61bb str r3, [r7, #24] + GPIOx->MODER = temp; + 800192a: 687b ldr r3, [r7, #4] + 800192c: 69ba ldr r2, [r7, #24] + 800192e: 601a str r2, [r3, #0] + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if((GPIO_Init->Mode & EXTI_MODE) != 0x00U) + 8001930: 683b ldr r3, [r7, #0] + 8001932: 685b ldr r3, [r3, #4] + 8001934: f403 3340 and.w r3, r3, #196608 @ 0x30000 + 8001938: 2b00 cmp r3, #0 + 800193a: f000 80b4 beq.w 8001aa6 + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 800193e: 2300 movs r3, #0 + 8001940: 60fb str r3, [r7, #12] + 8001942: 4b5f ldr r3, [pc, #380] @ (8001ac0 ) + 8001944: 6c5b ldr r3, [r3, #68] @ 0x44 + 8001946: 4a5e ldr r2, [pc, #376] @ (8001ac0 ) + 8001948: f443 4380 orr.w r3, r3, #16384 @ 0x4000 + 800194c: 6453 str r3, [r2, #68] @ 0x44 + 800194e: 4b5c ldr r3, [pc, #368] @ (8001ac0 ) + 8001950: 6c5b ldr r3, [r3, #68] @ 0x44 + 8001952: f403 4380 and.w r3, r3, #16384 @ 0x4000 + 8001956: 60fb str r3, [r7, #12] + 8001958: 68fb ldr r3, [r7, #12] + + temp = SYSCFG->EXTICR[position >> 2U]; + 800195a: 4a5a ldr r2, [pc, #360] @ (8001ac4 ) + 800195c: 69fb ldr r3, [r7, #28] + 800195e: 089b lsrs r3, r3, #2 + 8001960: 3302 adds r3, #2 + 8001962: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8001966: 61bb str r3, [r7, #24] + temp &= ~(0x0FU << (4U * (position & 0x03U))); + 8001968: 69fb ldr r3, [r7, #28] + 800196a: f003 0303 and.w r3, r3, #3 + 800196e: 009b lsls r3, r3, #2 + 8001970: 220f movs r2, #15 + 8001972: fa02 f303 lsl.w r3, r2, r3 + 8001976: 43db mvns r3, r3 + 8001978: 69ba ldr r2, [r7, #24] + 800197a: 4013 ands r3, r2 + 800197c: 61bb str r3, [r7, #24] + temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); + 800197e: 687b ldr r3, [r7, #4] + 8001980: 4a51 ldr r2, [pc, #324] @ (8001ac8 ) + 8001982: 4293 cmp r3, r2 + 8001984: d02b beq.n 80019de + 8001986: 687b ldr r3, [r7, #4] + 8001988: 4a50 ldr r2, [pc, #320] @ (8001acc ) + 800198a: 4293 cmp r3, r2 + 800198c: d025 beq.n 80019da + 800198e: 687b ldr r3, [r7, #4] + 8001990: 4a4f ldr r2, [pc, #316] @ (8001ad0 ) + 8001992: 4293 cmp r3, r2 + 8001994: d01f beq.n 80019d6 + 8001996: 687b ldr r3, [r7, #4] + 8001998: 4a4e ldr r2, [pc, #312] @ (8001ad4 ) + 800199a: 4293 cmp r3, r2 + 800199c: d019 beq.n 80019d2 + 800199e: 687b ldr r3, [r7, #4] + 80019a0: 4a4d ldr r2, [pc, #308] @ (8001ad8 ) + 80019a2: 4293 cmp r3, r2 + 80019a4: d013 beq.n 80019ce + 80019a6: 687b ldr r3, [r7, #4] + 80019a8: 4a4c ldr r2, [pc, #304] @ (8001adc ) + 80019aa: 4293 cmp r3, r2 + 80019ac: d00d beq.n 80019ca + 80019ae: 687b ldr r3, [r7, #4] + 80019b0: 4a4b ldr r2, [pc, #300] @ (8001ae0 ) + 80019b2: 4293 cmp r3, r2 + 80019b4: d007 beq.n 80019c6 + 80019b6: 687b ldr r3, [r7, #4] + 80019b8: 4a4a ldr r2, [pc, #296] @ (8001ae4 ) + 80019ba: 4293 cmp r3, r2 + 80019bc: d101 bne.n 80019c2 + 80019be: 2307 movs r3, #7 + 80019c0: e00e b.n 80019e0 + 80019c2: 2308 movs r3, #8 + 80019c4: e00c b.n 80019e0 + 80019c6: 2306 movs r3, #6 + 80019c8: e00a b.n 80019e0 + 80019ca: 2305 movs r3, #5 + 80019cc: e008 b.n 80019e0 + 80019ce: 2304 movs r3, #4 + 80019d0: e006 b.n 80019e0 + 80019d2: 2303 movs r3, #3 + 80019d4: e004 b.n 80019e0 + 80019d6: 2302 movs r3, #2 + 80019d8: e002 b.n 80019e0 + 80019da: 2301 movs r3, #1 + 80019dc: e000 b.n 80019e0 + 80019de: 2300 movs r3, #0 + 80019e0: 69fa ldr r2, [r7, #28] + 80019e2: f002 0203 and.w r2, r2, #3 + 80019e6: 0092 lsls r2, r2, #2 + 80019e8: 4093 lsls r3, r2 + 80019ea: 69ba ldr r2, [r7, #24] + 80019ec: 4313 orrs r3, r2 + 80019ee: 61bb str r3, [r7, #24] + SYSCFG->EXTICR[position >> 2U] = temp; + 80019f0: 4934 ldr r1, [pc, #208] @ (8001ac4 ) + 80019f2: 69fb ldr r3, [r7, #28] + 80019f4: 089b lsrs r3, r3, #2 + 80019f6: 3302 adds r3, #2 + 80019f8: 69ba ldr r2, [r7, #24] + 80019fa: f841 2023 str.w r2, [r1, r3, lsl #2] + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + 80019fe: 4b3a ldr r3, [pc, #232] @ (8001ae8 ) + 8001a00: 689b ldr r3, [r3, #8] + 8001a02: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 8001a04: 693b ldr r3, [r7, #16] + 8001a06: 43db mvns r3, r3 + 8001a08: 69ba ldr r2, [r7, #24] + 8001a0a: 4013 ands r3, r2 + 8001a0c: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) + 8001a0e: 683b ldr r3, [r7, #0] + 8001a10: 685b ldr r3, [r3, #4] + 8001a12: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 8001a16: 2b00 cmp r3, #0 + 8001a18: d003 beq.n 8001a22 + { + temp |= iocurrent; + 8001a1a: 69ba ldr r2, [r7, #24] + 8001a1c: 693b ldr r3, [r7, #16] + 8001a1e: 4313 orrs r3, r2 + 8001a20: 61bb str r3, [r7, #24] + } + EXTI->RTSR = temp; + 8001a22: 4a31 ldr r2, [pc, #196] @ (8001ae8 ) + 8001a24: 69bb ldr r3, [r7, #24] + 8001a26: 6093 str r3, [r2, #8] + + temp = EXTI->FTSR; + 8001a28: 4b2f ldr r3, [pc, #188] @ (8001ae8 ) + 8001a2a: 68db ldr r3, [r3, #12] + 8001a2c: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 8001a2e: 693b ldr r3, [r7, #16] + 8001a30: 43db mvns r3, r3 + 8001a32: 69ba ldr r2, [r7, #24] + 8001a34: 4013 ands r3, r2 + 8001a36: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) + 8001a38: 683b ldr r3, [r7, #0] + 8001a3a: 685b ldr r3, [r3, #4] + 8001a3c: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 8001a40: 2b00 cmp r3, #0 + 8001a42: d003 beq.n 8001a4c + { + temp |= iocurrent; + 8001a44: 69ba ldr r2, [r7, #24] + 8001a46: 693b ldr r3, [r7, #16] + 8001a48: 4313 orrs r3, r2 + 8001a4a: 61bb str r3, [r7, #24] + } + EXTI->FTSR = temp; + 8001a4c: 4a26 ldr r2, [pc, #152] @ (8001ae8 ) + 8001a4e: 69bb ldr r3, [r7, #24] + 8001a50: 60d3 str r3, [r2, #12] + + temp = EXTI->EMR; + 8001a52: 4b25 ldr r3, [pc, #148] @ (8001ae8 ) + 8001a54: 685b ldr r3, [r3, #4] + 8001a56: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 8001a58: 693b ldr r3, [r7, #16] + 8001a5a: 43db mvns r3, r3 + 8001a5c: 69ba ldr r2, [r7, #24] + 8001a5e: 4013 ands r3, r2 + 8001a60: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & EXTI_EVT) != 0x00U) + 8001a62: 683b ldr r3, [r7, #0] + 8001a64: 685b ldr r3, [r3, #4] + 8001a66: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8001a6a: 2b00 cmp r3, #0 + 8001a6c: d003 beq.n 8001a76 + { + temp |= iocurrent; + 8001a6e: 69ba ldr r2, [r7, #24] + 8001a70: 693b ldr r3, [r7, #16] + 8001a72: 4313 orrs r3, r2 + 8001a74: 61bb str r3, [r7, #24] + } + EXTI->EMR = temp; + 8001a76: 4a1c ldr r2, [pc, #112] @ (8001ae8 ) + 8001a78: 69bb ldr r3, [r7, #24] + 8001a7a: 6053 str r3, [r2, #4] + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + 8001a7c: 4b1a ldr r3, [pc, #104] @ (8001ae8 ) + 8001a7e: 681b ldr r3, [r3, #0] + 8001a80: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 8001a82: 693b ldr r3, [r7, #16] + 8001a84: 43db mvns r3, r3 + 8001a86: 69ba ldr r2, [r7, #24] + 8001a88: 4013 ands r3, r2 + 8001a8a: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & EXTI_IT) != 0x00U) + 8001a8c: 683b ldr r3, [r7, #0] + 8001a8e: 685b ldr r3, [r3, #4] + 8001a90: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8001a94: 2b00 cmp r3, #0 + 8001a96: d003 beq.n 8001aa0 + { + temp |= iocurrent; + 8001a98: 69ba ldr r2, [r7, #24] + 8001a9a: 693b ldr r3, [r7, #16] + 8001a9c: 4313 orrs r3, r2 + 8001a9e: 61bb str r3, [r7, #24] + } + EXTI->IMR = temp; + 8001aa0: 4a11 ldr r2, [pc, #68] @ (8001ae8 ) + 8001aa2: 69bb ldr r3, [r7, #24] + 8001aa4: 6013 str r3, [r2, #0] + for(position = 0U; position < GPIO_NUMBER; position++) + 8001aa6: 69fb ldr r3, [r7, #28] + 8001aa8: 3301 adds r3, #1 + 8001aaa: 61fb str r3, [r7, #28] + 8001aac: 69fb ldr r3, [r7, #28] + 8001aae: 2b0f cmp r3, #15 + 8001ab0: f67f adda bls.w 8001668 + } + } + } +} + 8001ab4: bf00 nop + 8001ab6: bf00 nop + 8001ab8: 3720 adds r7, #32 + 8001aba: 46bd mov sp, r7 + 8001abc: bd80 pop {r7, pc} + 8001abe: bf00 nop + 8001ac0: 40023800 .word 0x40023800 + 8001ac4: 40013800 .word 0x40013800 + 8001ac8: 40020000 .word 0x40020000 + 8001acc: 40020400 .word 0x40020400 + 8001ad0: 40020800 .word 0x40020800 + 8001ad4: 40020c00 .word 0x40020c00 + 8001ad8: 40021000 .word 0x40021000 + 8001adc: 40021400 .word 0x40021400 + 8001ae0: 40021800 .word 0x40021800 + 8001ae4: 40021c00 .word 0x40021c00 + 8001ae8: 40013c00 .word 0x40013c00 + +08001aec : + * supported by this API. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 8001aec: b580 push {r7, lr} + 8001aee: b086 sub sp, #24 + 8001af0: af00 add r7, sp, #0 + 8001af2: 6078 str r0, [r7, #4] + uint32_t tickstart; + uint32_t pll_config; + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + 8001af4: 687b ldr r3, [r7, #4] + 8001af6: 2b00 cmp r3, #0 + 8001af8: d101 bne.n 8001afe + { + return HAL_ERROR; + 8001afa: 2301 movs r3, #1 + 8001afc: e318 b.n 8002130 + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + 8001afe: 687b ldr r3, [r7, #4] + 8001b00: 681b ldr r3, [r3, #0] + 8001b02: 2b0f cmp r3, #15 + 8001b04: d903 bls.n 8001b0e + 8001b06: 21e6 movs r1, #230 @ 0xe6 + 8001b08: 4897 ldr r0, [pc, #604] @ (8001d68 ) + 8001b0a: f7fe fe9d bl 8000848 + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 8001b0e: 687b ldr r3, [r7, #4] + 8001b10: 681b ldr r3, [r3, #0] + 8001b12: f003 0301 and.w r3, r3, #1 + 8001b16: 2b00 cmp r3, #0 + 8001b18: f000 8088 beq.w 8001c2c + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + 8001b1c: 687b ldr r3, [r7, #4] + 8001b1e: 685b ldr r3, [r3, #4] + 8001b20: 2b00 cmp r3, #0 + 8001b22: d00d beq.n 8001b40 + 8001b24: 687b ldr r3, [r7, #4] + 8001b26: 685b ldr r3, [r3, #4] + 8001b28: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8001b2c: d008 beq.n 8001b40 + 8001b2e: 687b ldr r3, [r7, #4] + 8001b30: 685b ldr r3, [r3, #4] + 8001b32: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 + 8001b36: d003 beq.n 8001b40 + 8001b38: 21eb movs r1, #235 @ 0xeb + 8001b3a: 488b ldr r0, [pc, #556] @ (8001d68 ) + 8001b3c: f7fe fe84 bl 8000848 + /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \ + 8001b40: 4b8a ldr r3, [pc, #552] @ (8001d6c ) + 8001b42: 689b ldr r3, [r3, #8] + 8001b44: f003 030c and.w r3, r3, #12 + 8001b48: 2b04 cmp r3, #4 + 8001b4a: d00c beq.n 8001b66 + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) + 8001b4c: 4b87 ldr r3, [pc, #540] @ (8001d6c ) + 8001b4e: 689b ldr r3, [r3, #8] + 8001b50: f003 030c and.w r3, r3, #12 + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \ + 8001b54: 2b08 cmp r3, #8 + 8001b56: d112 bne.n 8001b7e + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) + 8001b58: 4b84 ldr r3, [pc, #528] @ (8001d6c ) + 8001b5a: 685b ldr r3, [r3, #4] + 8001b5c: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 8001b60: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 + 8001b64: d10b bne.n 8001b7e + { + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8001b66: 4b81 ldr r3, [pc, #516] @ (8001d6c ) + 8001b68: 681b ldr r3, [r3, #0] + 8001b6a: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8001b6e: 2b00 cmp r3, #0 + 8001b70: d05b beq.n 8001c2a + 8001b72: 687b ldr r3, [r7, #4] + 8001b74: 685b ldr r3, [r3, #4] + 8001b76: 2b00 cmp r3, #0 + 8001b78: d157 bne.n 8001c2a + { + return HAL_ERROR; + 8001b7a: 2301 movs r3, #1 + 8001b7c: e2d8 b.n 8002130 + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 8001b7e: 687b ldr r3, [r7, #4] + 8001b80: 685b ldr r3, [r3, #4] + 8001b82: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8001b86: d106 bne.n 8001b96 + 8001b88: 4b78 ldr r3, [pc, #480] @ (8001d6c ) + 8001b8a: 681b ldr r3, [r3, #0] + 8001b8c: 4a77 ldr r2, [pc, #476] @ (8001d6c ) + 8001b8e: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8001b92: 6013 str r3, [r2, #0] + 8001b94: e01d b.n 8001bd2 + 8001b96: 687b ldr r3, [r7, #4] + 8001b98: 685b ldr r3, [r3, #4] + 8001b9a: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 + 8001b9e: d10c bne.n 8001bba + 8001ba0: 4b72 ldr r3, [pc, #456] @ (8001d6c ) + 8001ba2: 681b ldr r3, [r3, #0] + 8001ba4: 4a71 ldr r2, [pc, #452] @ (8001d6c ) + 8001ba6: f443 2380 orr.w r3, r3, #262144 @ 0x40000 + 8001baa: 6013 str r3, [r2, #0] + 8001bac: 4b6f ldr r3, [pc, #444] @ (8001d6c ) + 8001bae: 681b ldr r3, [r3, #0] + 8001bb0: 4a6e ldr r2, [pc, #440] @ (8001d6c ) + 8001bb2: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8001bb6: 6013 str r3, [r2, #0] + 8001bb8: e00b b.n 8001bd2 + 8001bba: 4b6c ldr r3, [pc, #432] @ (8001d6c ) + 8001bbc: 681b ldr r3, [r3, #0] + 8001bbe: 4a6b ldr r2, [pc, #428] @ (8001d6c ) + 8001bc0: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 8001bc4: 6013 str r3, [r2, #0] + 8001bc6: 4b69 ldr r3, [pc, #420] @ (8001d6c ) + 8001bc8: 681b ldr r3, [r3, #0] + 8001bca: 4a68 ldr r2, [pc, #416] @ (8001d6c ) + 8001bcc: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 8001bd0: 6013 str r3, [r2, #0] + + /* Check the HSE State */ + if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) + 8001bd2: 687b ldr r3, [r7, #4] + 8001bd4: 685b ldr r3, [r3, #4] + 8001bd6: 2b00 cmp r3, #0 + 8001bd8: d013 beq.n 8001c02 + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001bda: f7ff f8a9 bl 8000d30 + 8001bde: 6138 str r0, [r7, #16] + + /* Wait till HSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 8001be0: e008 b.n 8001bf4 + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 8001be2: f7ff f8a5 bl 8000d30 + 8001be6: 4602 mov r2, r0 + 8001be8: 693b ldr r3, [r7, #16] + 8001bea: 1ad3 subs r3, r2, r3 + 8001bec: 2b64 cmp r3, #100 @ 0x64 + 8001bee: d901 bls.n 8001bf4 + { + return HAL_TIMEOUT; + 8001bf0: 2303 movs r3, #3 + 8001bf2: e29d b.n 8002130 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 8001bf4: 4b5d ldr r3, [pc, #372] @ (8001d6c ) + 8001bf6: 681b ldr r3, [r3, #0] + 8001bf8: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8001bfc: 2b00 cmp r3, #0 + 8001bfe: d0f0 beq.n 8001be2 + 8001c00: e014 b.n 8001c2c + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001c02: f7ff f895 bl 8000d30 + 8001c06: 6138 str r0, [r7, #16] + + /* Wait till HSE is bypassed or disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 8001c08: e008 b.n 8001c1c + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 8001c0a: f7ff f891 bl 8000d30 + 8001c0e: 4602 mov r2, r0 + 8001c10: 693b ldr r3, [r7, #16] + 8001c12: 1ad3 subs r3, r2, r3 + 8001c14: 2b64 cmp r3, #100 @ 0x64 + 8001c16: d901 bls.n 8001c1c + { + return HAL_TIMEOUT; + 8001c18: 2303 movs r3, #3 + 8001c1a: e289 b.n 8002130 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 8001c1c: 4b53 ldr r3, [pc, #332] @ (8001d6c ) + 8001c1e: 681b ldr r3, [r3, #0] + 8001c20: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8001c24: 2b00 cmp r3, #0 + 8001c26: d1f0 bne.n 8001c0a + 8001c28: e000 b.n 8001c2c + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8001c2a: bf00 nop + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 8001c2c: 687b ldr r3, [r7, #4] + 8001c2e: 681b ldr r3, [r3, #0] + 8001c30: f003 0302 and.w r3, r3, #2 + 8001c34: 2b00 cmp r3, #0 + 8001c36: d079 beq.n 8001d2c + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + 8001c38: 687b ldr r3, [r7, #4] + 8001c3a: 68db ldr r3, [r3, #12] + 8001c3c: 2b00 cmp r3, #0 + 8001c3e: d008 beq.n 8001c52 + 8001c40: 687b ldr r3, [r7, #4] + 8001c42: 68db ldr r3, [r3, #12] + 8001c44: 2b01 cmp r3, #1 + 8001c46: d004 beq.n 8001c52 + 8001c48: f240 111d movw r1, #285 @ 0x11d + 8001c4c: 4846 ldr r0, [pc, #280] @ (8001d68 ) + 8001c4e: f7fe fdfb bl 8000848 + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + 8001c52: 687b ldr r3, [r7, #4] + 8001c54: 691b ldr r3, [r3, #16] + 8001c56: 2b1f cmp r3, #31 + 8001c58: d904 bls.n 8001c64 + 8001c5a: f44f 718f mov.w r1, #286 @ 0x11e + 8001c5e: 4842 ldr r0, [pc, #264] @ (8001d68 ) + 8001c60: f7fe fdf2 bl 8000848 + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || \ + 8001c64: 4b41 ldr r3, [pc, #260] @ (8001d6c ) + 8001c66: 689b ldr r3, [r3, #8] + 8001c68: f003 030c and.w r3, r3, #12 + 8001c6c: 2b00 cmp r3, #0 + 8001c6e: d00b beq.n 8001c88 + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) + 8001c70: 4b3e ldr r3, [pc, #248] @ (8001d6c ) + 8001c72: 689b ldr r3, [r3, #8] + 8001c74: f003 030c and.w r3, r3, #12 + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || \ + 8001c78: 2b08 cmp r3, #8 + 8001c7a: d11c bne.n 8001cb6 + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) + 8001c7c: 4b3b ldr r3, [pc, #236] @ (8001d6c ) + 8001c7e: 685b ldr r3, [r3, #4] + 8001c80: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 8001c84: 2b00 cmp r3, #0 + 8001c86: d116 bne.n 8001cb6 + { + /* When HSI is used as system clock it will not disabled */ + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 8001c88: 4b38 ldr r3, [pc, #224] @ (8001d6c ) + 8001c8a: 681b ldr r3, [r3, #0] + 8001c8c: f003 0302 and.w r3, r3, #2 + 8001c90: 2b00 cmp r3, #0 + 8001c92: d005 beq.n 8001ca0 + 8001c94: 687b ldr r3, [r7, #4] + 8001c96: 68db ldr r3, [r3, #12] + 8001c98: 2b01 cmp r3, #1 + 8001c9a: d001 beq.n 8001ca0 + { + return HAL_ERROR; + 8001c9c: 2301 movs r3, #1 + 8001c9e: e247 b.n 8002130 + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8001ca0: 4b32 ldr r3, [pc, #200] @ (8001d6c ) + 8001ca2: 681b ldr r3, [r3, #0] + 8001ca4: f023 02f8 bic.w r2, r3, #248 @ 0xf8 + 8001ca8: 687b ldr r3, [r7, #4] + 8001caa: 691b ldr r3, [r3, #16] + 8001cac: 00db lsls r3, r3, #3 + 8001cae: 492f ldr r1, [pc, #188] @ (8001d6c ) + 8001cb0: 4313 orrs r3, r2 + 8001cb2: 600b str r3, [r1, #0] + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 8001cb4: e03a b.n 8001d2c + } + } + else + { + /* Check the HSI State */ + if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) + 8001cb6: 687b ldr r3, [r7, #4] + 8001cb8: 68db ldr r3, [r3, #12] + 8001cba: 2b00 cmp r3, #0 + 8001cbc: d020 beq.n 8001d00 + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + 8001cbe: 4b2c ldr r3, [pc, #176] @ (8001d70 ) + 8001cc0: 2201 movs r2, #1 + 8001cc2: 601a str r2, [r3, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8001cc4: f7ff f834 bl 8000d30 + 8001cc8: 6138 str r0, [r7, #16] + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 8001cca: e008 b.n 8001cde + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 8001ccc: f7ff f830 bl 8000d30 + 8001cd0: 4602 mov r2, r0 + 8001cd2: 693b ldr r3, [r7, #16] + 8001cd4: 1ad3 subs r3, r2, r3 + 8001cd6: 2b02 cmp r3, #2 + 8001cd8: d901 bls.n 8001cde + { + return HAL_TIMEOUT; + 8001cda: 2303 movs r3, #3 + 8001cdc: e228 b.n 8002130 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 8001cde: 4b23 ldr r3, [pc, #140] @ (8001d6c ) + 8001ce0: 681b ldr r3, [r3, #0] + 8001ce2: f003 0302 and.w r3, r3, #2 + 8001ce6: 2b00 cmp r3, #0 + 8001ce8: d0f0 beq.n 8001ccc + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8001cea: 4b20 ldr r3, [pc, #128] @ (8001d6c ) + 8001cec: 681b ldr r3, [r3, #0] + 8001cee: f023 02f8 bic.w r2, r3, #248 @ 0xf8 + 8001cf2: 687b ldr r3, [r7, #4] + 8001cf4: 691b ldr r3, [r3, #16] + 8001cf6: 00db lsls r3, r3, #3 + 8001cf8: 491c ldr r1, [pc, #112] @ (8001d6c ) + 8001cfa: 4313 orrs r3, r2 + 8001cfc: 600b str r3, [r1, #0] + 8001cfe: e015 b.n 8001d2c + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + 8001d00: 4b1b ldr r3, [pc, #108] @ (8001d70 ) + 8001d02: 2200 movs r2, #0 + 8001d04: 601a str r2, [r3, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8001d06: f7ff f813 bl 8000d30 + 8001d0a: 6138 str r0, [r7, #16] + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 8001d0c: e008 b.n 8001d20 + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 8001d0e: f7ff f80f bl 8000d30 + 8001d12: 4602 mov r2, r0 + 8001d14: 693b ldr r3, [r7, #16] + 8001d16: 1ad3 subs r3, r2, r3 + 8001d18: 2b02 cmp r3, #2 + 8001d1a: d901 bls.n 8001d20 + { + return HAL_TIMEOUT; + 8001d1c: 2303 movs r3, #3 + 8001d1e: e207 b.n 8002130 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 8001d20: 4b12 ldr r3, [pc, #72] @ (8001d6c ) + 8001d22: 681b ldr r3, [r3, #0] + 8001d24: f003 0302 and.w r3, r3, #2 + 8001d28: 2b00 cmp r3, #0 + 8001d2a: d1f0 bne.n 8001d0e + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 8001d2c: 687b ldr r3, [r7, #4] + 8001d2e: 681b ldr r3, [r3, #0] + 8001d30: f003 0308 and.w r3, r3, #8 + 8001d34: 2b00 cmp r3, #0 + 8001d36: d045 beq.n 8001dc4 + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + 8001d38: 687b ldr r3, [r7, #4] + 8001d3a: 695b ldr r3, [r3, #20] + 8001d3c: 2b00 cmp r3, #0 + 8001d3e: d008 beq.n 8001d52 + 8001d40: 687b ldr r3, [r7, #4] + 8001d42: 695b ldr r3, [r3, #20] + 8001d44: 2b01 cmp r3, #1 + 8001d46: d004 beq.n 8001d52 + 8001d48: f44f 71af mov.w r1, #350 @ 0x15e + 8001d4c: 4806 ldr r0, [pc, #24] @ (8001d68 ) + 8001d4e: f7fe fd7b bl 8000848 + + /* Check the LSI State */ + if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) + 8001d52: 687b ldr r3, [r7, #4] + 8001d54: 695b ldr r3, [r3, #20] + 8001d56: 2b00 cmp r3, #0 + 8001d58: d01e beq.n 8001d98 + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + 8001d5a: 4b06 ldr r3, [pc, #24] @ (8001d74 ) + 8001d5c: 2201 movs r2, #1 + 8001d5e: 601a str r2, [r3, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8001d60: f7fe ffe6 bl 8000d30 + 8001d64: 6138 str r0, [r7, #16] + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 8001d66: e010 b.n 8001d8a + 8001d68: 08005c98 .word 0x08005c98 + 8001d6c: 40023800 .word 0x40023800 + 8001d70: 42470000 .word 0x42470000 + 8001d74: 42470e80 .word 0x42470e80 + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 8001d78: f7fe ffda bl 8000d30 + 8001d7c: 4602 mov r2, r0 + 8001d7e: 693b ldr r3, [r7, #16] + 8001d80: 1ad3 subs r3, r2, r3 + 8001d82: 2b02 cmp r3, #2 + 8001d84: d901 bls.n 8001d8a + { + return HAL_TIMEOUT; + 8001d86: 2303 movs r3, #3 + 8001d88: e1d2 b.n 8002130 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 8001d8a: 4b5e ldr r3, [pc, #376] @ (8001f04 ) + 8001d8c: 6f5b ldr r3, [r3, #116] @ 0x74 + 8001d8e: f003 0302 and.w r3, r3, #2 + 8001d92: 2b00 cmp r3, #0 + 8001d94: d0f0 beq.n 8001d78 + 8001d96: e015 b.n 8001dc4 + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + 8001d98: 4b5b ldr r3, [pc, #364] @ (8001f08 ) + 8001d9a: 2200 movs r2, #0 + 8001d9c: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001d9e: f7fe ffc7 bl 8000d30 + 8001da2: 6138 str r0, [r7, #16] + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 8001da4: e008 b.n 8001db8 + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 8001da6: f7fe ffc3 bl 8000d30 + 8001daa: 4602 mov r2, r0 + 8001dac: 693b ldr r3, [r7, #16] + 8001dae: 1ad3 subs r3, r2, r3 + 8001db0: 2b02 cmp r3, #2 + 8001db2: d901 bls.n 8001db8 + { + return HAL_TIMEOUT; + 8001db4: 2303 movs r3, #3 + 8001db6: e1bb b.n 8002130 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 8001db8: 4b52 ldr r3, [pc, #328] @ (8001f04 ) + 8001dba: 6f5b ldr r3, [r3, #116] @ 0x74 + 8001dbc: f003 0302 and.w r3, r3, #2 + 8001dc0: 2b00 cmp r3, #0 + 8001dc2: d1f0 bne.n 8001da6 + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 8001dc4: 687b ldr r3, [r7, #4] + 8001dc6: 681b ldr r3, [r3, #0] + 8001dc8: f003 0304 and.w r3, r3, #4 + 8001dcc: 2b00 cmp r3, #0 + 8001dce: f000 80b0 beq.w 8001f32 + { + FlagStatus pwrclkchanged = RESET; + 8001dd2: 2300 movs r3, #0 + 8001dd4: 75fb strb r3, [r7, #23] + + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + 8001dd6: 687b ldr r3, [r7, #4] + 8001dd8: 689b ldr r3, [r3, #8] + 8001dda: 2b00 cmp r3, #0 + 8001ddc: d00c beq.n 8001df8 + 8001dde: 687b ldr r3, [r7, #4] + 8001de0: 689b ldr r3, [r3, #8] + 8001de2: 2b01 cmp r3, #1 + 8001de4: d008 beq.n 8001df8 + 8001de6: 687b ldr r3, [r7, #4] + 8001de8: 689b ldr r3, [r3, #8] + 8001dea: 2b05 cmp r3, #5 + 8001dec: d004 beq.n 8001df8 + 8001dee: f44f 71c5 mov.w r1, #394 @ 0x18a + 8001df2: 4846 ldr r0, [pc, #280] @ (8001f0c ) + 8001df4: f7fe fd28 bl 8000848 + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + 8001df8: 4b42 ldr r3, [pc, #264] @ (8001f04 ) + 8001dfa: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001dfc: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001e00: 2b00 cmp r3, #0 + 8001e02: d10f bne.n 8001e24 + { + __HAL_RCC_PWR_CLK_ENABLE(); + 8001e04: 2300 movs r3, #0 + 8001e06: 60bb str r3, [r7, #8] + 8001e08: 4b3e ldr r3, [pc, #248] @ (8001f04 ) + 8001e0a: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001e0c: 4a3d ldr r2, [pc, #244] @ (8001f04 ) + 8001e0e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8001e12: 6413 str r3, [r2, #64] @ 0x40 + 8001e14: 4b3b ldr r3, [pc, #236] @ (8001f04 ) + 8001e16: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001e18: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001e1c: 60bb str r3, [r7, #8] + 8001e1e: 68bb ldr r3, [r7, #8] + pwrclkchanged = SET; + 8001e20: 2301 movs r3, #1 + 8001e22: 75fb strb r3, [r7, #23] + } + + if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8001e24: 4b3a ldr r3, [pc, #232] @ (8001f10 ) + 8001e26: 681b ldr r3, [r3, #0] + 8001e28: f403 7380 and.w r3, r3, #256 @ 0x100 + 8001e2c: 2b00 cmp r3, #0 + 8001e2e: d118 bne.n 8001e62 + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + 8001e30: 4b37 ldr r3, [pc, #220] @ (8001f10 ) + 8001e32: 681b ldr r3, [r3, #0] + 8001e34: 4a36 ldr r2, [pc, #216] @ (8001f10 ) + 8001e36: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8001e3a: 6013 str r3, [r2, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 8001e3c: f7fe ff78 bl 8000d30 + 8001e40: 6138 str r0, [r7, #16] + + while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8001e42: e008 b.n 8001e56 + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 8001e44: f7fe ff74 bl 8000d30 + 8001e48: 4602 mov r2, r0 + 8001e4a: 693b ldr r3, [r7, #16] + 8001e4c: 1ad3 subs r3, r2, r3 + 8001e4e: 2b02 cmp r3, #2 + 8001e50: d901 bls.n 8001e56 + { + return HAL_TIMEOUT; + 8001e52: 2303 movs r3, #3 + 8001e54: e16c b.n 8002130 + while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8001e56: 4b2e ldr r3, [pc, #184] @ (8001f10 ) + 8001e58: 681b ldr r3, [r3, #0] + 8001e5a: f403 7380 and.w r3, r3, #256 @ 0x100 + 8001e5e: 2b00 cmp r3, #0 + 8001e60: d0f0 beq.n 8001e44 + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 8001e62: 687b ldr r3, [r7, #4] + 8001e64: 689b ldr r3, [r3, #8] + 8001e66: 2b01 cmp r3, #1 + 8001e68: d106 bne.n 8001e78 + 8001e6a: 4b26 ldr r3, [pc, #152] @ (8001f04 ) + 8001e6c: 6f1b ldr r3, [r3, #112] @ 0x70 + 8001e6e: 4a25 ldr r2, [pc, #148] @ (8001f04 ) + 8001e70: f043 0301 orr.w r3, r3, #1 + 8001e74: 6713 str r3, [r2, #112] @ 0x70 + 8001e76: e01c b.n 8001eb2 + 8001e78: 687b ldr r3, [r7, #4] + 8001e7a: 689b ldr r3, [r3, #8] + 8001e7c: 2b05 cmp r3, #5 + 8001e7e: d10c bne.n 8001e9a + 8001e80: 4b20 ldr r3, [pc, #128] @ (8001f04 ) + 8001e82: 6f1b ldr r3, [r3, #112] @ 0x70 + 8001e84: 4a1f ldr r2, [pc, #124] @ (8001f04 ) + 8001e86: f043 0304 orr.w r3, r3, #4 + 8001e8a: 6713 str r3, [r2, #112] @ 0x70 + 8001e8c: 4b1d ldr r3, [pc, #116] @ (8001f04 ) + 8001e8e: 6f1b ldr r3, [r3, #112] @ 0x70 + 8001e90: 4a1c ldr r2, [pc, #112] @ (8001f04 ) + 8001e92: f043 0301 orr.w r3, r3, #1 + 8001e96: 6713 str r3, [r2, #112] @ 0x70 + 8001e98: e00b b.n 8001eb2 + 8001e9a: 4b1a ldr r3, [pc, #104] @ (8001f04 ) + 8001e9c: 6f1b ldr r3, [r3, #112] @ 0x70 + 8001e9e: 4a19 ldr r2, [pc, #100] @ (8001f04 ) + 8001ea0: f023 0301 bic.w r3, r3, #1 + 8001ea4: 6713 str r3, [r2, #112] @ 0x70 + 8001ea6: 4b17 ldr r3, [pc, #92] @ (8001f04 ) + 8001ea8: 6f1b ldr r3, [r3, #112] @ 0x70 + 8001eaa: 4a16 ldr r2, [pc, #88] @ (8001f04 ) + 8001eac: f023 0304 bic.w r3, r3, #4 + 8001eb0: 6713 str r3, [r2, #112] @ 0x70 + /* Check the LSE State */ + if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) + 8001eb2: 687b ldr r3, [r7, #4] + 8001eb4: 689b ldr r3, [r3, #8] + 8001eb6: 2b00 cmp r3, #0 + 8001eb8: d015 beq.n 8001ee6 + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8001eba: f7fe ff39 bl 8000d30 + 8001ebe: 6138 str r0, [r7, #16] + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8001ec0: e00a b.n 8001ed8 + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8001ec2: f7fe ff35 bl 8000d30 + 8001ec6: 4602 mov r2, r0 + 8001ec8: 693b ldr r3, [r7, #16] + 8001eca: 1ad3 subs r3, r2, r3 + 8001ecc: f241 3288 movw r2, #5000 @ 0x1388 + 8001ed0: 4293 cmp r3, r2 + 8001ed2: d901 bls.n 8001ed8 + { + return HAL_TIMEOUT; + 8001ed4: 2303 movs r3, #3 + 8001ed6: e12b b.n 8002130 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8001ed8: 4b0a ldr r3, [pc, #40] @ (8001f04 ) + 8001eda: 6f1b ldr r3, [r3, #112] @ 0x70 + 8001edc: f003 0302 and.w r3, r3, #2 + 8001ee0: 2b00 cmp r3, #0 + 8001ee2: d0ee beq.n 8001ec2 + 8001ee4: e01c b.n 8001f20 + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001ee6: f7fe ff23 bl 8000d30 + 8001eea: 6138 str r0, [r7, #16] + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 8001eec: e012 b.n 8001f14 + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8001eee: f7fe ff1f bl 8000d30 + 8001ef2: 4602 mov r2, r0 + 8001ef4: 693b ldr r3, [r7, #16] + 8001ef6: 1ad3 subs r3, r2, r3 + 8001ef8: f241 3288 movw r2, #5000 @ 0x1388 + 8001efc: 4293 cmp r3, r2 + 8001efe: d909 bls.n 8001f14 + { + return HAL_TIMEOUT; + 8001f00: 2303 movs r3, #3 + 8001f02: e115 b.n 8002130 + 8001f04: 40023800 .word 0x40023800 + 8001f08: 42470e80 .word 0x42470e80 + 8001f0c: 08005c98 .word 0x08005c98 + 8001f10: 40007000 .word 0x40007000 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 8001f14: 4b88 ldr r3, [pc, #544] @ (8002138 ) + 8001f16: 6f1b ldr r3, [r3, #112] @ 0x70 + 8001f18: f003 0302 and.w r3, r3, #2 + 8001f1c: 2b00 cmp r3, #0 + 8001f1e: d1e6 bne.n 8001eee + } + } + } + + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + 8001f20: 7dfb ldrb r3, [r7, #23] + 8001f22: 2b01 cmp r3, #1 + 8001f24: d105 bne.n 8001f32 + { + __HAL_RCC_PWR_CLK_DISABLE(); + 8001f26: 4b84 ldr r3, [pc, #528] @ (8002138 ) + 8001f28: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001f2a: 4a83 ldr r2, [pc, #524] @ (8002138 ) + 8001f2c: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8001f30: 6413 str r3, [r2, #64] @ 0x40 + } + } + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + 8001f32: 687b ldr r3, [r7, #4] + 8001f34: 699b ldr r3, [r3, #24] + 8001f36: 2b00 cmp r3, #0 + 8001f38: d00c beq.n 8001f54 + 8001f3a: 687b ldr r3, [r7, #4] + 8001f3c: 699b ldr r3, [r3, #24] + 8001f3e: 2b01 cmp r3, #1 + 8001f40: d008 beq.n 8001f54 + 8001f42: 687b ldr r3, [r7, #4] + 8001f44: 699b ldr r3, [r3, #24] + 8001f46: 2b02 cmp r3, #2 + 8001f48: d004 beq.n 8001f54 + 8001f4a: f240 11cd movw r1, #461 @ 0x1cd + 8001f4e: 487b ldr r0, [pc, #492] @ (800213c ) + 8001f50: f7fe fc7a bl 8000848 + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 8001f54: 687b ldr r3, [r7, #4] + 8001f56: 699b ldr r3, [r3, #24] + 8001f58: 2b00 cmp r3, #0 + 8001f5a: f000 80e8 beq.w 800212e + { + /* Check if the PLL is used as system clock or not */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + 8001f5e: 4b76 ldr r3, [pc, #472] @ (8002138 ) + 8001f60: 689b ldr r3, [r3, #8] + 8001f62: f003 030c and.w r3, r3, #12 + 8001f66: 2b08 cmp r3, #8 + 8001f68: f000 80a9 beq.w 80020be + { + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 8001f6c: 687b ldr r3, [r7, #4] + 8001f6e: 699b ldr r3, [r3, #24] + 8001f70: 2b02 cmp r3, #2 + 8001f72: f040 808d bne.w 8002090 + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + 8001f76: 687b ldr r3, [r7, #4] + 8001f78: 69db ldr r3, [r3, #28] + 8001f7a: 2b00 cmp r3, #0 + 8001f7c: d009 beq.n 8001f92 + 8001f7e: 687b ldr r3, [r7, #4] + 8001f80: 69db ldr r3, [r3, #28] + 8001f82: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 + 8001f86: d004 beq.n 8001f92 + 8001f88: f44f 71eb mov.w r1, #470 @ 0x1d6 + 8001f8c: 486b ldr r0, [pc, #428] @ (800213c ) + 8001f8e: f7fe fc5b bl 8000848 + assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); + 8001f92: 687b ldr r3, [r7, #4] + 8001f94: 6a1b ldr r3, [r3, #32] + 8001f96: 2b01 cmp r3, #1 + 8001f98: d903 bls.n 8001fa2 + 8001f9a: 687b ldr r3, [r7, #4] + 8001f9c: 6a1b ldr r3, [r3, #32] + 8001f9e: 2b3f cmp r3, #63 @ 0x3f + 8001fa0: d904 bls.n 8001fac + 8001fa2: f240 11d7 movw r1, #471 @ 0x1d7 + 8001fa6: 4865 ldr r0, [pc, #404] @ (800213c ) + 8001fa8: f7fe fc4e bl 8000848 + assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); + 8001fac: 687b ldr r3, [r7, #4] + 8001fae: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001fb0: 2b31 cmp r3, #49 @ 0x31 + 8001fb2: d904 bls.n 8001fbe + 8001fb4: 687b ldr r3, [r7, #4] + 8001fb6: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001fb8: f5b3 7fd8 cmp.w r3, #432 @ 0x1b0 + 8001fbc: d904 bls.n 8001fc8 + 8001fbe: f44f 71ec mov.w r1, #472 @ 0x1d8 + 8001fc2: 485e ldr r0, [pc, #376] @ (800213c ) + 8001fc4: f7fe fc40 bl 8000848 + assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + 8001fc8: 687b ldr r3, [r7, #4] + 8001fca: 6a9b ldr r3, [r3, #40] @ 0x28 + 8001fcc: 2b02 cmp r3, #2 + 8001fce: d010 beq.n 8001ff2 + 8001fd0: 687b ldr r3, [r7, #4] + 8001fd2: 6a9b ldr r3, [r3, #40] @ 0x28 + 8001fd4: 2b04 cmp r3, #4 + 8001fd6: d00c beq.n 8001ff2 + 8001fd8: 687b ldr r3, [r7, #4] + 8001fda: 6a9b ldr r3, [r3, #40] @ 0x28 + 8001fdc: 2b06 cmp r3, #6 + 8001fde: d008 beq.n 8001ff2 + 8001fe0: 687b ldr r3, [r7, #4] + 8001fe2: 6a9b ldr r3, [r3, #40] @ 0x28 + 8001fe4: 2b08 cmp r3, #8 + 8001fe6: d004 beq.n 8001ff2 + 8001fe8: f240 11d9 movw r1, #473 @ 0x1d9 + 8001fec: 4853 ldr r0, [pc, #332] @ (800213c ) + 8001fee: f7fe fc2b bl 8000848 + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); + 8001ff2: 687b ldr r3, [r7, #4] + 8001ff4: 6adb ldr r3, [r3, #44] @ 0x2c + 8001ff6: 2b01 cmp r3, #1 + 8001ff8: d903 bls.n 8002002 + 8001ffa: 687b ldr r3, [r7, #4] + 8001ffc: 6adb ldr r3, [r3, #44] @ 0x2c + 8001ffe: 2b0f cmp r3, #15 + 8002000: d904 bls.n 800200c + 8002002: f44f 71ed mov.w r1, #474 @ 0x1da + 8002006: 484d ldr r0, [pc, #308] @ (800213c ) + 8002008: f7fe fc1e bl 8000848 + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 800200c: 4b4c ldr r3, [pc, #304] @ (8002140 ) + 800200e: 2200 movs r2, #0 + 8002010: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8002012: f7fe fe8d bl 8000d30 + 8002016: 6138 str r0, [r7, #16] + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8002018: e008 b.n 800202c + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 800201a: f7fe fe89 bl 8000d30 + 800201e: 4602 mov r2, r0 + 8002020: 693b ldr r3, [r7, #16] + 8002022: 1ad3 subs r3, r2, r3 + 8002024: 2b02 cmp r3, #2 + 8002026: d901 bls.n 800202c + { + return HAL_TIMEOUT; + 8002028: 2303 movs r3, #3 + 800202a: e081 b.n 8002130 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 800202c: 4b42 ldr r3, [pc, #264] @ (8002138 ) + 800202e: 681b ldr r3, [r3, #0] + 8002030: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8002034: 2b00 cmp r3, #0 + 8002036: d1f0 bne.n 800201a + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ + 8002038: 687b ldr r3, [r7, #4] + 800203a: 69da ldr r2, [r3, #28] + 800203c: 687b ldr r3, [r7, #4] + 800203e: 6a1b ldr r3, [r3, #32] + 8002040: 431a orrs r2, r3 + 8002042: 687b ldr r3, [r7, #4] + 8002044: 6a5b ldr r3, [r3, #36] @ 0x24 + 8002046: 019b lsls r3, r3, #6 + 8002048: 431a orrs r2, r3 + 800204a: 687b ldr r3, [r7, #4] + 800204c: 6a9b ldr r3, [r3, #40] @ 0x28 + 800204e: 085b lsrs r3, r3, #1 + 8002050: 3b01 subs r3, #1 + 8002052: 041b lsls r3, r3, #16 + 8002054: 431a orrs r2, r3 + 8002056: 687b ldr r3, [r7, #4] + 8002058: 6adb ldr r3, [r3, #44] @ 0x2c + 800205a: 061b lsls r3, r3, #24 + 800205c: 4936 ldr r1, [pc, #216] @ (8002138 ) + 800205e: 4313 orrs r3, r2 + 8002060: 604b str r3, [r1, #4] + RCC_OscInitStruct->PLL.PLLM | \ + (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ + (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ + (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 8002062: 4b37 ldr r3, [pc, #220] @ (8002140 ) + 8002064: 2201 movs r2, #1 + 8002066: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8002068: f7fe fe62 bl 8000d30 + 800206c: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 800206e: e008 b.n 8002082 + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 8002070: f7fe fe5e bl 8000d30 + 8002074: 4602 mov r2, r0 + 8002076: 693b ldr r3, [r7, #16] + 8002078: 1ad3 subs r3, r2, r3 + 800207a: 2b02 cmp r3, #2 + 800207c: d901 bls.n 8002082 + { + return HAL_TIMEOUT; + 800207e: 2303 movs r3, #3 + 8002080: e056 b.n 8002130 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8002082: 4b2d ldr r3, [pc, #180] @ (8002138 ) + 8002084: 681b ldr r3, [r3, #0] + 8002086: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 800208a: 2b00 cmp r3, #0 + 800208c: d0f0 beq.n 8002070 + 800208e: e04e b.n 800212e + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8002090: 4b2b ldr r3, [pc, #172] @ (8002140 ) + 8002092: 2200 movs r2, #0 + 8002094: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8002096: f7fe fe4b bl 8000d30 + 800209a: 6138 str r0, [r7, #16] + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 800209c: e008 b.n 80020b0 + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 800209e: f7fe fe47 bl 8000d30 + 80020a2: 4602 mov r2, r0 + 80020a4: 693b ldr r3, [r7, #16] + 80020a6: 1ad3 subs r3, r2, r3 + 80020a8: 2b02 cmp r3, #2 + 80020aa: d901 bls.n 80020b0 + { + return HAL_TIMEOUT; + 80020ac: 2303 movs r3, #3 + 80020ae: e03f b.n 8002130 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 80020b0: 4b21 ldr r3, [pc, #132] @ (8002138 ) + 80020b2: 681b ldr r3, [r3, #0] + 80020b4: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 80020b8: 2b00 cmp r3, #0 + 80020ba: d1f0 bne.n 800209e + 80020bc: e037 b.n 800212e + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + 80020be: 687b ldr r3, [r7, #4] + 80020c0: 699b ldr r3, [r3, #24] + 80020c2: 2b01 cmp r3, #1 + 80020c4: d101 bne.n 80020ca + { + return HAL_ERROR; + 80020c6: 2301 movs r3, #1 + 80020c8: e032 b.n 8002130 + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->PLLCFGR; + 80020ca: 4b1b ldr r3, [pc, #108] @ (8002138 ) + 80020cc: 685b ldr r3, [r3, #4] + 80020ce: 60fb str r3, [r7, #12] + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) +#else + if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + 80020d0: 687b ldr r3, [r7, #4] + 80020d2: 699b ldr r3, [r3, #24] + 80020d4: 2b01 cmp r3, #1 + 80020d6: d028 beq.n 800212a + (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 80020d8: 68fb ldr r3, [r7, #12] + 80020da: f403 0280 and.w r2, r3, #4194304 @ 0x400000 + 80020de: 687b ldr r3, [r7, #4] + 80020e0: 69db ldr r3, [r3, #28] + if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + 80020e2: 429a cmp r2, r3 + 80020e4: d121 bne.n 800212a + (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || + 80020e6: 68fb ldr r3, [r7, #12] + 80020e8: f003 023f and.w r2, r3, #63 @ 0x3f + 80020ec: 687b ldr r3, [r7, #4] + 80020ee: 6a1b ldr r3, [r3, #32] + (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 80020f0: 429a cmp r2, r3 + 80020f2: d11a bne.n 800212a + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || + 80020f4: 68fa ldr r2, [r7, #12] + 80020f6: f647 73c0 movw r3, #32704 @ 0x7fc0 + 80020fa: 4013 ands r3, r2 + 80020fc: 687a ldr r2, [r7, #4] + 80020fe: 6a52 ldr r2, [r2, #36] @ 0x24 + 8002100: 0192 lsls r2, r2, #6 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || + 8002102: 4293 cmp r3, r2 + 8002104: d111 bne.n 800212a + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || + 8002106: 68fb ldr r3, [r7, #12] + 8002108: f403 3240 and.w r2, r3, #196608 @ 0x30000 + 800210c: 687b ldr r3, [r7, #4] + 800210e: 6a9b ldr r3, [r3, #40] @ 0x28 + 8002110: 085b lsrs r3, r3, #1 + 8002112: 3b01 subs r3, #1 + 8002114: 041b lsls r3, r3, #16 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || + 8002116: 429a cmp r2, r3 + 8002118: d107 bne.n 800212a + (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) + 800211a: 68fb ldr r3, [r7, #12] + 800211c: f003 6270 and.w r2, r3, #251658240 @ 0xf000000 + 8002120: 687b ldr r3, [r7, #4] + 8002122: 6adb ldr r3, [r3, #44] @ 0x2c + 8002124: 061b lsls r3, r3, #24 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || + 8002126: 429a cmp r2, r3 + 8002128: d001 beq.n 800212e +#endif /* RCC_PLLCFGR_PLLR */ + { + return HAL_ERROR; + 800212a: 2301 movs r3, #1 + 800212c: e000 b.n 8002130 + } + } + } + } + return HAL_OK; + 800212e: 2300 movs r3, #0 +} + 8002130: 4618 mov r0, r3 + 8002132: 3718 adds r7, #24 + 8002134: 46bd mov sp, r7 + 8002136: bd80 pop {r7, pc} + 8002138: 40023800 .word 0x40023800 + 800213c: 08005c98 .word 0x08005c98 + 8002140: 42470060 .word 0x42470060 + +08002144 : + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 8002144: b580 push {r7, lr} + 8002146: b084 sub sp, #16 + 8002148: af00 add r7, sp, #0 + 800214a: 6078 str r0, [r7, #4] + 800214c: 6039 str r1, [r7, #0] + uint32_t tickstart; + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + 800214e: 687b ldr r3, [r7, #4] + 8002150: 2b00 cmp r3, #0 + 8002152: d101 bne.n 8002158 + { + return HAL_ERROR; + 8002154: 2301 movs r3, #1 + 8002156: e174 b.n 8002442 + } + + /* Check the parameters */ + assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + 8002158: 687b ldr r3, [r7, #4] + 800215a: 681b ldr r3, [r3, #0] + 800215c: 2b00 cmp r3, #0 + 800215e: d003 beq.n 8002168 + 8002160: 687b ldr r3, [r7, #4] + 8002162: 681b ldr r3, [r3, #0] + 8002164: 2b0f cmp r3, #15 + 8002166: d904 bls.n 8002172 + 8002168: f240 215a movw r1, #602 @ 0x25a + 800216c: 487b ldr r0, [pc, #492] @ (800235c ) + 800216e: f7fe fb6b bl 8000848 + assert_param(IS_FLASH_LATENCY(FLatency)); + 8002172: 683b ldr r3, [r7, #0] + 8002174: 2b00 cmp r3, #0 + 8002176: d019 beq.n 80021ac + 8002178: 683b ldr r3, [r7, #0] + 800217a: 2b01 cmp r3, #1 + 800217c: d016 beq.n 80021ac + 800217e: 683b ldr r3, [r7, #0] + 8002180: 2b02 cmp r3, #2 + 8002182: d013 beq.n 80021ac + 8002184: 683b ldr r3, [r7, #0] + 8002186: 2b03 cmp r3, #3 + 8002188: d010 beq.n 80021ac + 800218a: 683b ldr r3, [r7, #0] + 800218c: 2b04 cmp r3, #4 + 800218e: d00d beq.n 80021ac + 8002190: 683b ldr r3, [r7, #0] + 8002192: 2b05 cmp r3, #5 + 8002194: d00a beq.n 80021ac + 8002196: 683b ldr r3, [r7, #0] + 8002198: 2b06 cmp r3, #6 + 800219a: d007 beq.n 80021ac + 800219c: 683b ldr r3, [r7, #0] + 800219e: 2b07 cmp r3, #7 + 80021a0: d004 beq.n 80021ac + 80021a2: f240 215b movw r1, #603 @ 0x25b + 80021a6: 486d ldr r0, [pc, #436] @ (800235c ) + 80021a8: f7fe fb4e bl 8000848 + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + 80021ac: 4b6c ldr r3, [pc, #432] @ (8002360 ) + 80021ae: 681b ldr r3, [r3, #0] + 80021b0: f003 0307 and.w r3, r3, #7 + 80021b4: 683a ldr r2, [r7, #0] + 80021b6: 429a cmp r2, r3 + 80021b8: d90c bls.n 80021d4 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 80021ba: 4b69 ldr r3, [pc, #420] @ (8002360 ) + 80021bc: 683a ldr r2, [r7, #0] + 80021be: b2d2 uxtb r2, r2 + 80021c0: 701a strb r2, [r3, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + 80021c2: 4b67 ldr r3, [pc, #412] @ (8002360 ) + 80021c4: 681b ldr r3, [r3, #0] + 80021c6: f003 0307 and.w r3, r3, #7 + 80021ca: 683a ldr r2, [r7, #0] + 80021cc: 429a cmp r2, r3 + 80021ce: d001 beq.n 80021d4 + { + return HAL_ERROR; + 80021d0: 2301 movs r3, #1 + 80021d2: e136 b.n 8002442 + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 80021d4: 687b ldr r3, [r7, #4] + 80021d6: 681b ldr r3, [r3, #0] + 80021d8: f003 0302 and.w r3, r3, #2 + 80021dc: 2b00 cmp r3, #0 + 80021de: d049 beq.n 8002274 + { + /* Set the highest APBx dividers in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 80021e0: 687b ldr r3, [r7, #4] + 80021e2: 681b ldr r3, [r3, #0] + 80021e4: f003 0304 and.w r3, r3, #4 + 80021e8: 2b00 cmp r3, #0 + 80021ea: d005 beq.n 80021f8 + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); + 80021ec: 4b5d ldr r3, [pc, #372] @ (8002364 ) + 80021ee: 689b ldr r3, [r3, #8] + 80021f0: 4a5c ldr r2, [pc, #368] @ (8002364 ) + 80021f2: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00 + 80021f6: 6093 str r3, [r2, #8] + } + + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 80021f8: 687b ldr r3, [r7, #4] + 80021fa: 681b ldr r3, [r3, #0] + 80021fc: f003 0308 and.w r3, r3, #8 + 8002200: 2b00 cmp r3, #0 + 8002202: d005 beq.n 8002210 + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); + 8002204: 4b57 ldr r3, [pc, #348] @ (8002364 ) + 8002206: 689b ldr r3, [r3, #8] + 8002208: 4a56 ldr r2, [pc, #344] @ (8002364 ) + 800220a: f443 4360 orr.w r3, r3, #57344 @ 0xe000 + 800220e: 6093 str r3, [r2, #8] + } + + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + 8002210: 687b ldr r3, [r7, #4] + 8002212: 689b ldr r3, [r3, #8] + 8002214: 2b00 cmp r3, #0 + 8002216: d024 beq.n 8002262 + 8002218: 687b ldr r3, [r7, #4] + 800221a: 689b ldr r3, [r3, #8] + 800221c: 2b80 cmp r3, #128 @ 0x80 + 800221e: d020 beq.n 8002262 + 8002220: 687b ldr r3, [r7, #4] + 8002222: 689b ldr r3, [r3, #8] + 8002224: 2b90 cmp r3, #144 @ 0x90 + 8002226: d01c beq.n 8002262 + 8002228: 687b ldr r3, [r7, #4] + 800222a: 689b ldr r3, [r3, #8] + 800222c: 2ba0 cmp r3, #160 @ 0xa0 + 800222e: d018 beq.n 8002262 + 8002230: 687b ldr r3, [r7, #4] + 8002232: 689b ldr r3, [r3, #8] + 8002234: 2bb0 cmp r3, #176 @ 0xb0 + 8002236: d014 beq.n 8002262 + 8002238: 687b ldr r3, [r7, #4] + 800223a: 689b ldr r3, [r3, #8] + 800223c: 2bc0 cmp r3, #192 @ 0xc0 + 800223e: d010 beq.n 8002262 + 8002240: 687b ldr r3, [r7, #4] + 8002242: 689b ldr r3, [r3, #8] + 8002244: 2bd0 cmp r3, #208 @ 0xd0 + 8002246: d00c beq.n 8002262 + 8002248: 687b ldr r3, [r7, #4] + 800224a: 689b ldr r3, [r3, #8] + 800224c: 2be0 cmp r3, #224 @ 0xe0 + 800224e: d008 beq.n 8002262 + 8002250: 687b ldr r3, [r7, #4] + 8002252: 689b ldr r3, [r3, #8] + 8002254: 2bf0 cmp r3, #240 @ 0xf0 + 8002256: d004 beq.n 8002262 + 8002258: f240 217e movw r1, #638 @ 0x27e + 800225c: 483f ldr r0, [pc, #252] @ (800235c ) + 800225e: f7fe faf3 bl 8000848 + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 8002262: 4b40 ldr r3, [pc, #256] @ (8002364 ) + 8002264: 689b ldr r3, [r3, #8] + 8002266: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 800226a: 687b ldr r3, [r7, #4] + 800226c: 689b ldr r3, [r3, #8] + 800226e: 493d ldr r1, [pc, #244] @ (8002364 ) + 8002270: 4313 orrs r3, r2 + 8002272: 608b str r3, [r1, #8] + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 8002274: 687b ldr r3, [r7, #4] + 8002276: 681b ldr r3, [r3, #0] + 8002278: f003 0301 and.w r3, r3, #1 + 800227c: 2b00 cmp r3, #0 + 800227e: d059 beq.n 8002334 + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + 8002280: 687b ldr r3, [r7, #4] + 8002282: 685b ldr r3, [r3, #4] + 8002284: 2b00 cmp r3, #0 + 8002286: d010 beq.n 80022aa + 8002288: 687b ldr r3, [r7, #4] + 800228a: 685b ldr r3, [r3, #4] + 800228c: 2b01 cmp r3, #1 + 800228e: d00c beq.n 80022aa + 8002290: 687b ldr r3, [r7, #4] + 8002292: 685b ldr r3, [r3, #4] + 8002294: 2b02 cmp r3, #2 + 8002296: d008 beq.n 80022aa + 8002298: 687b ldr r3, [r7, #4] + 800229a: 685b ldr r3, [r3, #4] + 800229c: 2b03 cmp r3, #3 + 800229e: d004 beq.n 80022aa + 80022a0: f240 2185 movw r1, #645 @ 0x285 + 80022a4: 482d ldr r0, [pc, #180] @ (800235c ) + 80022a6: f7fe facf bl 8000848 + + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 80022aa: 687b ldr r3, [r7, #4] + 80022ac: 685b ldr r3, [r3, #4] + 80022ae: 2b01 cmp r3, #1 + 80022b0: d107 bne.n 80022c2 + { + /* Check the HSE ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 80022b2: 4b2c ldr r3, [pc, #176] @ (8002364 ) + 80022b4: 681b ldr r3, [r3, #0] + 80022b6: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80022ba: 2b00 cmp r3, #0 + 80022bc: d119 bne.n 80022f2 + { + return HAL_ERROR; + 80022be: 2301 movs r3, #1 + 80022c0: e0bf b.n 8002442 + } + } + /* PLL is selected as System Clock Source */ + else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || + 80022c2: 687b ldr r3, [r7, #4] + 80022c4: 685b ldr r3, [r3, #4] + 80022c6: 2b02 cmp r3, #2 + 80022c8: d003 beq.n 80022d2 + (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)) + 80022ca: 687b ldr r3, [r7, #4] + 80022cc: 685b ldr r3, [r3, #4] + else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || + 80022ce: 2b03 cmp r3, #3 + 80022d0: d107 bne.n 80022e2 + { + /* Check the PLL ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 80022d2: 4b24 ldr r3, [pc, #144] @ (8002364 ) + 80022d4: 681b ldr r3, [r3, #0] + 80022d6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 80022da: 2b00 cmp r3, #0 + 80022dc: d109 bne.n 80022f2 + { + return HAL_ERROR; + 80022de: 2301 movs r3, #1 + 80022e0: e0af b.n 8002442 + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 80022e2: 4b20 ldr r3, [pc, #128] @ (8002364 ) + 80022e4: 681b ldr r3, [r3, #0] + 80022e6: f003 0302 and.w r3, r3, #2 + 80022ea: 2b00 cmp r3, #0 + 80022ec: d101 bne.n 80022f2 + { + return HAL_ERROR; + 80022ee: 2301 movs r3, #1 + 80022f0: e0a7 b.n 8002442 + } + } + + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + 80022f2: 4b1c ldr r3, [pc, #112] @ (8002364 ) + 80022f4: 689b ldr r3, [r3, #8] + 80022f6: f023 0203 bic.w r2, r3, #3 + 80022fa: 687b ldr r3, [r7, #4] + 80022fc: 685b ldr r3, [r3, #4] + 80022fe: 4919 ldr r1, [pc, #100] @ (8002364 ) + 8002300: 4313 orrs r3, r2 + 8002302: 608b str r3, [r1, #8] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8002304: f7fe fd14 bl 8000d30 + 8002308: 60f8 str r0, [r7, #12] + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 800230a: e00a b.n 8002322 + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 800230c: f7fe fd10 bl 8000d30 + 8002310: 4602 mov r2, r0 + 8002312: 68fb ldr r3, [r7, #12] + 8002314: 1ad3 subs r3, r2, r3 + 8002316: f241 3288 movw r2, #5000 @ 0x1388 + 800231a: 4293 cmp r3, r2 + 800231c: d901 bls.n 8002322 + { + return HAL_TIMEOUT; + 800231e: 2303 movs r3, #3 + 8002320: e08f b.n 8002442 + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 8002322: 4b10 ldr r3, [pc, #64] @ (8002364 ) + 8002324: 689b ldr r3, [r3, #8] + 8002326: f003 020c and.w r2, r3, #12 + 800232a: 687b ldr r3, [r7, #4] + 800232c: 685b ldr r3, [r3, #4] + 800232e: 009b lsls r3, r3, #2 + 8002330: 429a cmp r2, r3 + 8002332: d1eb bne.n 800230c + } + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + 8002334: 4b0a ldr r3, [pc, #40] @ (8002360 ) + 8002336: 681b ldr r3, [r3, #0] + 8002338: f003 0307 and.w r3, r3, #7 + 800233c: 683a ldr r2, [r7, #0] + 800233e: 429a cmp r2, r3 + 8002340: d212 bcs.n 8002368 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8002342: 4b07 ldr r3, [pc, #28] @ (8002360 ) + 8002344: 683a ldr r2, [r7, #0] + 8002346: b2d2 uxtb r2, r2 + 8002348: 701a strb r2, [r3, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + 800234a: 4b05 ldr r3, [pc, #20] @ (8002360 ) + 800234c: 681b ldr r3, [r3, #0] + 800234e: f003 0307 and.w r3, r3, #7 + 8002352: 683a ldr r2, [r7, #0] + 8002354: 429a cmp r2, r3 + 8002356: d007 beq.n 8002368 + { + return HAL_ERROR; + 8002358: 2301 movs r3, #1 + 800235a: e072 b.n 8002442 + 800235c: 08005c98 .word 0x08005c98 + 8002360: 40023c00 .word 0x40023c00 + 8002364: 40023800 .word 0x40023800 + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8002368: 687b ldr r3, [r7, #4] + 800236a: 681b ldr r3, [r3, #0] + 800236c: f003 0304 and.w r3, r3, #4 + 8002370: 2b00 cmp r3, #0 + 8002372: d025 beq.n 80023c0 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + 8002374: 687b ldr r3, [r7, #4] + 8002376: 68db ldr r3, [r3, #12] + 8002378: 2b00 cmp r3, #0 + 800237a: d018 beq.n 80023ae + 800237c: 687b ldr r3, [r7, #4] + 800237e: 68db ldr r3, [r3, #12] + 8002380: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 8002384: d013 beq.n 80023ae + 8002386: 687b ldr r3, [r7, #4] + 8002388: 68db ldr r3, [r3, #12] + 800238a: f5b3 5fa0 cmp.w r3, #5120 @ 0x1400 + 800238e: d00e beq.n 80023ae + 8002390: 687b ldr r3, [r7, #4] + 8002392: 68db ldr r3, [r3, #12] + 8002394: f5b3 5fc0 cmp.w r3, #6144 @ 0x1800 + 8002398: d009 beq.n 80023ae + 800239a: 687b ldr r3, [r7, #4] + 800239c: 68db ldr r3, [r3, #12] + 800239e: f5b3 5fe0 cmp.w r3, #7168 @ 0x1c00 + 80023a2: d004 beq.n 80023ae + 80023a4: f240 21c3 movw r1, #707 @ 0x2c3 + 80023a8: 4828 ldr r0, [pc, #160] @ (800244c ) + 80023aa: f7fe fa4d bl 8000848 + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 80023ae: 4b28 ldr r3, [pc, #160] @ (8002450 ) + 80023b0: 689b ldr r3, [r3, #8] + 80023b2: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00 + 80023b6: 687b ldr r3, [r7, #4] + 80023b8: 68db ldr r3, [r3, #12] + 80023ba: 4925 ldr r1, [pc, #148] @ (8002450 ) + 80023bc: 4313 orrs r3, r2 + 80023be: 608b str r3, [r1, #8] + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 80023c0: 687b ldr r3, [r7, #4] + 80023c2: 681b ldr r3, [r3, #0] + 80023c4: f003 0308 and.w r3, r3, #8 + 80023c8: 2b00 cmp r3, #0 + 80023ca: d026 beq.n 800241a + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + 80023cc: 687b ldr r3, [r7, #4] + 80023ce: 691b ldr r3, [r3, #16] + 80023d0: 2b00 cmp r3, #0 + 80023d2: d018 beq.n 8002406 + 80023d4: 687b ldr r3, [r7, #4] + 80023d6: 691b ldr r3, [r3, #16] + 80023d8: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 80023dc: d013 beq.n 8002406 + 80023de: 687b ldr r3, [r7, #4] + 80023e0: 691b ldr r3, [r3, #16] + 80023e2: f5b3 5fa0 cmp.w r3, #5120 @ 0x1400 + 80023e6: d00e beq.n 8002406 + 80023e8: 687b ldr r3, [r7, #4] + 80023ea: 691b ldr r3, [r3, #16] + 80023ec: f5b3 5fc0 cmp.w r3, #6144 @ 0x1800 + 80023f0: d009 beq.n 8002406 + 80023f2: 687b ldr r3, [r7, #4] + 80023f4: 691b ldr r3, [r3, #16] + 80023f6: f5b3 5fe0 cmp.w r3, #7168 @ 0x1c00 + 80023fa: d004 beq.n 8002406 + 80023fc: f240 21ca movw r1, #714 @ 0x2ca + 8002400: 4812 ldr r0, [pc, #72] @ (800244c ) + 8002402: f7fe fa21 bl 8000848 + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); + 8002406: 4b12 ldr r3, [pc, #72] @ (8002450 ) + 8002408: 689b ldr r3, [r3, #8] + 800240a: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 800240e: 687b ldr r3, [r7, #4] + 8002410: 691b ldr r3, [r3, #16] + 8002412: 00db lsls r3, r3, #3 + 8002414: 490e ldr r1, [pc, #56] @ (8002450 ) + 8002416: 4313 orrs r3, r2 + 8002418: 608b str r3, [r1, #8] + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; + 800241a: f000 f821 bl 8002460 + 800241e: 4602 mov r2, r0 + 8002420: 4b0b ldr r3, [pc, #44] @ (8002450 ) + 8002422: 689b ldr r3, [r3, #8] + 8002424: 091b lsrs r3, r3, #4 + 8002426: f003 030f and.w r3, r3, #15 + 800242a: 490a ldr r1, [pc, #40] @ (8002454 ) + 800242c: 5ccb ldrb r3, [r1, r3] + 800242e: fa22 f303 lsr.w r3, r2, r3 + 8002432: 4a09 ldr r2, [pc, #36] @ (8002458 ) + 8002434: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings */ + HAL_InitTick(uwTickPrio); + 8002436: 4b09 ldr r3, [pc, #36] @ (800245c ) + 8002438: 681b ldr r3, [r3, #0] + 800243a: 4618 mov r0, r3 + 800243c: f7fe fadc bl 80009f8 + + return HAL_OK; + 8002440: 2300 movs r3, #0 +} + 8002442: 4618 mov r0, r3 + 8002444: 3710 adds r7, #16 + 8002446: 46bd mov sp, r7 + 8002448: bd80 pop {r7, pc} + 800244a: bf00 nop + 800244c: 08005c98 .word 0x08005c98 + 8002450: 40023800 .word 0x40023800 + 8002454: 08005d44 .word 0x08005d44 + 8002458: 20000000 .word 0x20000000 + 800245c: 20000004 .word 0x20000004 + +08002460 : + * + * + * @retval SYSCLK frequency + */ +__weak uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 8002460: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} + 8002464: b090 sub sp, #64 @ 0x40 + 8002466: af00 add r7, sp, #0 + uint32_t pllm = 0U; + 8002468: 2300 movs r3, #0 + 800246a: 637b str r3, [r7, #52] @ 0x34 + uint32_t pllvco = 0U; + 800246c: 2300 movs r3, #0 + 800246e: 63fb str r3, [r7, #60] @ 0x3c + uint32_t pllp = 0U; + 8002470: 2300 movs r3, #0 + 8002472: 633b str r3, [r7, #48] @ 0x30 + uint32_t sysclockfreq = 0U; + 8002474: 2300 movs r3, #0 + 8002476: 63bb str r3, [r7, #56] @ 0x38 + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + 8002478: 4b58 ldr r3, [pc, #352] @ (80025dc ) + 800247a: 689b ldr r3, [r3, #8] + 800247c: f003 030c and.w r3, r3, #12 + 8002480: 2b08 cmp r3, #8 + 8002482: d00d beq.n 80024a0 + 8002484: 2b08 cmp r3, #8 + 8002486: f200 80a0 bhi.w 80025ca + 800248a: 2b00 cmp r3, #0 + 800248c: d002 beq.n 8002494 + 800248e: 2b04 cmp r3, #4 + 8002490: d003 beq.n 800249a + 8002492: e09a b.n 80025ca + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + { + sysclockfreq = HSI_VALUE; + 8002494: 4b52 ldr r3, [pc, #328] @ (80025e0 ) + 8002496: 63bb str r3, [r7, #56] @ 0x38 + break; + 8002498: e09a b.n 80025d0 + } + case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ + { + sysclockfreq = HSE_VALUE; + 800249a: 4b52 ldr r3, [pc, #328] @ (80025e4 ) + 800249c: 63bb str r3, [r7, #56] @ 0x38 + break; + 800249e: e097 b.n 80025d0 + } + case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */ + { + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLP */ + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + 80024a0: 4b4e ldr r3, [pc, #312] @ (80025dc ) + 80024a2: 685b ldr r3, [r3, #4] + 80024a4: f003 033f and.w r3, r3, #63 @ 0x3f + 80024a8: 637b str r3, [r7, #52] @ 0x34 + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + 80024aa: 4b4c ldr r3, [pc, #304] @ (80025dc ) + 80024ac: 685b ldr r3, [r3, #4] + 80024ae: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 80024b2: 2b00 cmp r3, #0 + 80024b4: d027 beq.n 8002506 + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + 80024b6: 4b49 ldr r3, [pc, #292] @ (80025dc ) + 80024b8: 685b ldr r3, [r3, #4] + 80024ba: 099b lsrs r3, r3, #6 + 80024bc: 2200 movs r2, #0 + 80024be: 623b str r3, [r7, #32] + 80024c0: 627a str r2, [r7, #36] @ 0x24 + 80024c2: 6a3b ldr r3, [r7, #32] + 80024c4: f3c3 0008 ubfx r0, r3, #0, #9 + 80024c8: 2100 movs r1, #0 + 80024ca: 4b46 ldr r3, [pc, #280] @ (80025e4 ) + 80024cc: fb03 f201 mul.w r2, r3, r1 + 80024d0: 2300 movs r3, #0 + 80024d2: fb00 f303 mul.w r3, r0, r3 + 80024d6: 4413 add r3, r2 + 80024d8: 4a42 ldr r2, [pc, #264] @ (80025e4 ) + 80024da: fba0 2102 umull r2, r1, r0, r2 + 80024de: 62f9 str r1, [r7, #44] @ 0x2c + 80024e0: 62ba str r2, [r7, #40] @ 0x28 + 80024e2: 6afa ldr r2, [r7, #44] @ 0x2c + 80024e4: 4413 add r3, r2 + 80024e6: 62fb str r3, [r7, #44] @ 0x2c + 80024e8: 6b7b ldr r3, [r7, #52] @ 0x34 + 80024ea: 2200 movs r2, #0 + 80024ec: 61bb str r3, [r7, #24] + 80024ee: 61fa str r2, [r7, #28] + 80024f0: e9d7 2306 ldrd r2, r3, [r7, #24] + 80024f4: e9d7 010a ldrd r0, r1, [r7, #40] @ 0x28 + 80024f8: f7fd fe6a bl 80001d0 <__aeabi_uldivmod> + 80024fc: 4602 mov r2, r0 + 80024fe: 460b mov r3, r1 + 8002500: 4613 mov r3, r2 + 8002502: 63fb str r3, [r7, #60] @ 0x3c + 8002504: e053 b.n 80025ae + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + 8002506: 4b35 ldr r3, [pc, #212] @ (80025dc ) + 8002508: 685b ldr r3, [r3, #4] + 800250a: 099b lsrs r3, r3, #6 + 800250c: 2200 movs r2, #0 + 800250e: 613b str r3, [r7, #16] + 8002510: 617a str r2, [r7, #20] + 8002512: 693b ldr r3, [r7, #16] + 8002514: f3c3 0a08 ubfx sl, r3, #0, #9 + 8002518: f04f 0b00 mov.w fp, #0 + 800251c: 4652 mov r2, sl + 800251e: 465b mov r3, fp + 8002520: f04f 0000 mov.w r0, #0 + 8002524: f04f 0100 mov.w r1, #0 + 8002528: 0159 lsls r1, r3, #5 + 800252a: ea41 61d2 orr.w r1, r1, r2, lsr #27 + 800252e: 0150 lsls r0, r2, #5 + 8002530: 4602 mov r2, r0 + 8002532: 460b mov r3, r1 + 8002534: ebb2 080a subs.w r8, r2, sl + 8002538: eb63 090b sbc.w r9, r3, fp + 800253c: f04f 0200 mov.w r2, #0 + 8002540: f04f 0300 mov.w r3, #0 + 8002544: ea4f 1389 mov.w r3, r9, lsl #6 + 8002548: ea43 6398 orr.w r3, r3, r8, lsr #26 + 800254c: ea4f 1288 mov.w r2, r8, lsl #6 + 8002550: ebb2 0408 subs.w r4, r2, r8 + 8002554: eb63 0509 sbc.w r5, r3, r9 + 8002558: f04f 0200 mov.w r2, #0 + 800255c: f04f 0300 mov.w r3, #0 + 8002560: 00eb lsls r3, r5, #3 + 8002562: ea43 7354 orr.w r3, r3, r4, lsr #29 + 8002566: 00e2 lsls r2, r4, #3 + 8002568: 4614 mov r4, r2 + 800256a: 461d mov r5, r3 + 800256c: eb14 030a adds.w r3, r4, sl + 8002570: 603b str r3, [r7, #0] + 8002572: eb45 030b adc.w r3, r5, fp + 8002576: 607b str r3, [r7, #4] + 8002578: f04f 0200 mov.w r2, #0 + 800257c: f04f 0300 mov.w r3, #0 + 8002580: e9d7 4500 ldrd r4, r5, [r7] + 8002584: 4629 mov r1, r5 + 8002586: 028b lsls r3, r1, #10 + 8002588: 4621 mov r1, r4 + 800258a: ea43 5391 orr.w r3, r3, r1, lsr #22 + 800258e: 4621 mov r1, r4 + 8002590: 028a lsls r2, r1, #10 + 8002592: 4610 mov r0, r2 + 8002594: 4619 mov r1, r3 + 8002596: 6b7b ldr r3, [r7, #52] @ 0x34 + 8002598: 2200 movs r2, #0 + 800259a: 60bb str r3, [r7, #8] + 800259c: 60fa str r2, [r7, #12] + 800259e: e9d7 2302 ldrd r2, r3, [r7, #8] + 80025a2: f7fd fe15 bl 80001d0 <__aeabi_uldivmod> + 80025a6: 4602 mov r2, r0 + 80025a8: 460b mov r3, r1 + 80025aa: 4613 mov r3, r2 + 80025ac: 63fb str r3, [r7, #60] @ 0x3c + } + pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U); + 80025ae: 4b0b ldr r3, [pc, #44] @ (80025dc ) + 80025b0: 685b ldr r3, [r3, #4] + 80025b2: 0c1b lsrs r3, r3, #16 + 80025b4: f003 0303 and.w r3, r3, #3 + 80025b8: 3301 adds r3, #1 + 80025ba: 005b lsls r3, r3, #1 + 80025bc: 633b str r3, [r7, #48] @ 0x30 + + sysclockfreq = pllvco / pllp; + 80025be: 6bfa ldr r2, [r7, #60] @ 0x3c + 80025c0: 6b3b ldr r3, [r7, #48] @ 0x30 + 80025c2: fbb2 f3f3 udiv r3, r2, r3 + 80025c6: 63bb str r3, [r7, #56] @ 0x38 + break; + 80025c8: e002 b.n 80025d0 + } + default: + { + sysclockfreq = HSI_VALUE; + 80025ca: 4b05 ldr r3, [pc, #20] @ (80025e0 ) + 80025cc: 63bb str r3, [r7, #56] @ 0x38 + break; + 80025ce: bf00 nop + } + } + return sysclockfreq; + 80025d0: 6bbb ldr r3, [r7, #56] @ 0x38 +} + 80025d2: 4618 mov r0, r3 + 80025d4: 3740 adds r7, #64 @ 0x40 + 80025d6: 46bd mov sp, r7 + 80025d8: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} + 80025dc: 40023800 .word 0x40023800 + 80025e0: 00f42400 .word 0x00f42400 + 80025e4: 017d7840 .word 0x017d7840 + +080025e8 : + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated within this function + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + 80025e8: b480 push {r7} + 80025ea: af00 add r7, sp, #0 + return SystemCoreClock; + 80025ec: 4b03 ldr r3, [pc, #12] @ (80025fc ) + 80025ee: 681b ldr r3, [r3, #0] +} + 80025f0: 4618 mov r0, r3 + 80025f2: 46bd mov sp, r7 + 80025f4: f85d 7b04 ldr.w r7, [sp], #4 + 80025f8: 4770 bx lr + 80025fa: bf00 nop + 80025fc: 20000000 .word 0x20000000 + +08002600 : + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + 8002600: b580 push {r7, lr} + 8002602: af00 add r7, sp, #0 + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); + 8002604: f7ff fff0 bl 80025e8 + 8002608: 4602 mov r2, r0 + 800260a: 4b05 ldr r3, [pc, #20] @ (8002620 ) + 800260c: 689b ldr r3, [r3, #8] + 800260e: 0a9b lsrs r3, r3, #10 + 8002610: f003 0307 and.w r3, r3, #7 + 8002614: 4903 ldr r1, [pc, #12] @ (8002624 ) + 8002616: 5ccb ldrb r3, [r1, r3] + 8002618: fa22 f303 lsr.w r3, r2, r3 +} + 800261c: 4618 mov r0, r3 + 800261e: bd80 pop {r7, pc} + 8002620: 40023800 .word 0x40023800 + 8002624: 08005d54 .word 0x08005d54 + +08002628 : + * will be configured. + * @param pFLatency Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + 8002628: b480 push {r7} + 800262a: b083 sub sp, #12 + 800262c: af00 add r7, sp, #0 + 800262e: 6078 str r0, [r7, #4] + 8002630: 6039 str r1, [r7, #0] + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + 8002632: 687b ldr r3, [r7, #4] + 8002634: 220f movs r2, #15 + 8002636: 601a str r2, [r3, #0] + + /* Get the SYSCLK configuration --------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + 8002638: 4b12 ldr r3, [pc, #72] @ (8002684 ) + 800263a: 689b ldr r3, [r3, #8] + 800263c: f003 0203 and.w r2, r3, #3 + 8002640: 687b ldr r3, [r7, #4] + 8002642: 605a str r2, [r3, #4] + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + 8002644: 4b0f ldr r3, [pc, #60] @ (8002684 ) + 8002646: 689b ldr r3, [r3, #8] + 8002648: f003 02f0 and.w r2, r3, #240 @ 0xf0 + 800264c: 687b ldr r3, [r7, #4] + 800264e: 609a str r2, [r3, #8] + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); + 8002650: 4b0c ldr r3, [pc, #48] @ (8002684 ) + 8002652: 689b ldr r3, [r3, #8] + 8002654: f403 52e0 and.w r2, r3, #7168 @ 0x1c00 + 8002658: 687b ldr r3, [r7, #4] + 800265a: 60da str r2, [r3, #12] + + /* Get the APB2 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U); + 800265c: 4b09 ldr r3, [pc, #36] @ (8002684 ) + 800265e: 689b ldr r3, [r3, #8] + 8002660: 08db lsrs r3, r3, #3 + 8002662: f403 52e0 and.w r2, r3, #7168 @ 0x1c00 + 8002666: 687b ldr r3, [r7, #4] + 8002668: 611a str r2, [r3, #16] + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); + 800266a: 4b07 ldr r3, [pc, #28] @ (8002688 ) + 800266c: 681b ldr r3, [r3, #0] + 800266e: f003 0207 and.w r2, r3, #7 + 8002672: 683b ldr r3, [r7, #0] + 8002674: 601a str r2, [r3, #0] +} + 8002676: bf00 nop + 8002678: 370c adds r7, #12 + 800267a: 46bd mov sp, r7 + 800267c: f85d 7b04 ldr.w r7, [sp], #4 + 8002680: 4770 bx lr + 8002682: bf00 nop + 8002684: 40023800 .word 0x40023800 + 8002688: 40023c00 .word 0x40023c00 + +0800268c : + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + 800268c: b580 push {r7, lr} + 800268e: b082 sub sp, #8 + 8002690: af00 add r7, sp, #0 + 8002692: 6078 str r0, [r7, #4] + /* Check the TIM handle allocation */ + if (htim == NULL) + 8002694: 687b ldr r3, [r7, #4] + 8002696: 2b00 cmp r3, #0 + 8002698: d101 bne.n 800269e + { + return HAL_ERROR; + 800269a: 2301 movs r3, #1 + 800269c: e0f2 b.n 8002884 + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + 800269e: 687b ldr r3, [r7, #4] + 80026a0: 681b ldr r3, [r3, #0] + 80026a2: 4a7a ldr r2, [pc, #488] @ (800288c ) + 80026a4: 4293 cmp r3, r2 + 80026a6: d045 beq.n 8002734 + 80026a8: 687b ldr r3, [r7, #4] + 80026aa: 681b ldr r3, [r3, #0] + 80026ac: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 80026b0: d040 beq.n 8002734 + 80026b2: 687b ldr r3, [r7, #4] + 80026b4: 681b ldr r3, [r3, #0] + 80026b6: 4a76 ldr r2, [pc, #472] @ (8002890 ) + 80026b8: 4293 cmp r3, r2 + 80026ba: d03b beq.n 8002734 + 80026bc: 687b ldr r3, [r7, #4] + 80026be: 681b ldr r3, [r3, #0] + 80026c0: 4a74 ldr r2, [pc, #464] @ (8002894 ) + 80026c2: 4293 cmp r3, r2 + 80026c4: d036 beq.n 8002734 + 80026c6: 687b ldr r3, [r7, #4] + 80026c8: 681b ldr r3, [r3, #0] + 80026ca: 4a73 ldr r2, [pc, #460] @ (8002898 ) + 80026cc: 4293 cmp r3, r2 + 80026ce: d031 beq.n 8002734 + 80026d0: 687b ldr r3, [r7, #4] + 80026d2: 681b ldr r3, [r3, #0] + 80026d4: 4a71 ldr r2, [pc, #452] @ (800289c ) + 80026d6: 4293 cmp r3, r2 + 80026d8: d02c beq.n 8002734 + 80026da: 687b ldr r3, [r7, #4] + 80026dc: 681b ldr r3, [r3, #0] + 80026de: 4a70 ldr r2, [pc, #448] @ (80028a0 ) + 80026e0: 4293 cmp r3, r2 + 80026e2: d027 beq.n 8002734 + 80026e4: 687b ldr r3, [r7, #4] + 80026e6: 681b ldr r3, [r3, #0] + 80026e8: 4a6e ldr r2, [pc, #440] @ (80028a4 ) + 80026ea: 4293 cmp r3, r2 + 80026ec: d022 beq.n 8002734 + 80026ee: 687b ldr r3, [r7, #4] + 80026f0: 681b ldr r3, [r3, #0] + 80026f2: 4a6d ldr r2, [pc, #436] @ (80028a8 ) + 80026f4: 4293 cmp r3, r2 + 80026f6: d01d beq.n 8002734 + 80026f8: 687b ldr r3, [r7, #4] + 80026fa: 681b ldr r3, [r3, #0] + 80026fc: 4a6b ldr r2, [pc, #428] @ (80028ac ) + 80026fe: 4293 cmp r3, r2 + 8002700: d018 beq.n 8002734 + 8002702: 687b ldr r3, [r7, #4] + 8002704: 681b ldr r3, [r3, #0] + 8002706: 4a6a ldr r2, [pc, #424] @ (80028b0 ) + 8002708: 4293 cmp r3, r2 + 800270a: d013 beq.n 8002734 + 800270c: 687b ldr r3, [r7, #4] + 800270e: 681b ldr r3, [r3, #0] + 8002710: 4a68 ldr r2, [pc, #416] @ (80028b4 ) + 8002712: 4293 cmp r3, r2 + 8002714: d00e beq.n 8002734 + 8002716: 687b ldr r3, [r7, #4] + 8002718: 681b ldr r3, [r3, #0] + 800271a: 4a67 ldr r2, [pc, #412] @ (80028b8 ) + 800271c: 4293 cmp r3, r2 + 800271e: d009 beq.n 8002734 + 8002720: 687b ldr r3, [r7, #4] + 8002722: 681b ldr r3, [r3, #0] + 8002724: 4a65 ldr r2, [pc, #404] @ (80028bc ) + 8002726: 4293 cmp r3, r2 + 8002728: d004 beq.n 8002734 + 800272a: f240 1113 movw r1, #275 @ 0x113 + 800272e: 4864 ldr r0, [pc, #400] @ (80028c0 ) + 8002730: f7fe f88a bl 8000848 + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + 8002734: 687b ldr r3, [r7, #4] + 8002736: 689b ldr r3, [r3, #8] + 8002738: 2b00 cmp r3, #0 + 800273a: d014 beq.n 8002766 + 800273c: 687b ldr r3, [r7, #4] + 800273e: 689b ldr r3, [r3, #8] + 8002740: 2b10 cmp r3, #16 + 8002742: d010 beq.n 8002766 + 8002744: 687b ldr r3, [r7, #4] + 8002746: 689b ldr r3, [r3, #8] + 8002748: 2b20 cmp r3, #32 + 800274a: d00c beq.n 8002766 + 800274c: 687b ldr r3, [r7, #4] + 800274e: 689b ldr r3, [r3, #8] + 8002750: 2b40 cmp r3, #64 @ 0x40 + 8002752: d008 beq.n 8002766 + 8002754: 687b ldr r3, [r7, #4] + 8002756: 689b ldr r3, [r3, #8] + 8002758: 2b60 cmp r3, #96 @ 0x60 + 800275a: d004 beq.n 8002766 + 800275c: f44f 718a mov.w r1, #276 @ 0x114 + 8002760: 4857 ldr r0, [pc, #348] @ (80028c0 ) + 8002762: f7fe f871 bl 8000848 + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + 8002766: 687b ldr r3, [r7, #4] + 8002768: 691b ldr r3, [r3, #16] + 800276a: 2b00 cmp r3, #0 + 800276c: d00e beq.n 800278c + 800276e: 687b ldr r3, [r7, #4] + 8002770: 691b ldr r3, [r3, #16] + 8002772: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 8002776: d009 beq.n 800278c + 8002778: 687b ldr r3, [r7, #4] + 800277a: 691b ldr r3, [r3, #16] + 800277c: f5b3 7f00 cmp.w r3, #512 @ 0x200 + 8002780: d004 beq.n 800278c + 8002782: f240 1115 movw r1, #277 @ 0x115 + 8002786: 484e ldr r0, [pc, #312] @ (80028c0 ) + 8002788: f7fe f85e bl 8000848 + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + 800278c: 687b ldr r3, [r7, #4] + 800278e: 681b ldr r3, [r3, #0] + 8002790: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8002794: d004 beq.n 80027a0 + 8002796: 687b ldr r3, [r7, #4] + 8002798: 681b ldr r3, [r3, #0] + 800279a: 4a3f ldr r2, [pc, #252] @ (8002898 ) + 800279c: 4293 cmp r3, r2 + 800279e: d101 bne.n 80027a4 + 80027a0: 2301 movs r3, #1 + 80027a2: e000 b.n 80027a6 + 80027a4: 2300 movs r3, #0 + 80027a6: 2b00 cmp r3, #0 + 80027a8: d10f bne.n 80027ca + 80027aa: 687b ldr r3, [r7, #4] + 80027ac: 68db ldr r3, [r3, #12] + 80027ae: 2b00 cmp r3, #0 + 80027b0: d006 beq.n 80027c0 + 80027b2: 687b ldr r3, [r7, #4] + 80027b4: 68db ldr r3, [r3, #12] + 80027b6: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 80027ba: d201 bcs.n 80027c0 + 80027bc: 2301 movs r3, #1 + 80027be: e000 b.n 80027c2 + 80027c0: 2300 movs r3, #0 + 80027c2: f003 0301 and.w r3, r3, #1 + 80027c6: b2db uxtb r3, r3 + 80027c8: e006 b.n 80027d8 + 80027ca: 687b ldr r3, [r7, #4] + 80027cc: 68db ldr r3, [r3, #12] + 80027ce: 2b00 cmp r3, #0 + 80027d0: bf14 ite ne + 80027d2: 2301 movne r3, #1 + 80027d4: 2300 moveq r3, #0 + 80027d6: b2db uxtb r3, r3 + 80027d8: 2b00 cmp r3, #0 + 80027da: d104 bne.n 80027e6 + 80027dc: f44f 718b mov.w r1, #278 @ 0x116 + 80027e0: 4837 ldr r0, [pc, #220] @ (80028c0 ) + 80027e2: f7fe f831 bl 8000848 + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + 80027e6: 687b ldr r3, [r7, #4] + 80027e8: 699b ldr r3, [r3, #24] + 80027ea: 2b00 cmp r3, #0 + 80027ec: d008 beq.n 8002800 + 80027ee: 687b ldr r3, [r7, #4] + 80027f0: 699b ldr r3, [r3, #24] + 80027f2: 2b80 cmp r3, #128 @ 0x80 + 80027f4: d004 beq.n 8002800 + 80027f6: f240 1117 movw r1, #279 @ 0x117 + 80027fa: 4831 ldr r0, [pc, #196] @ (80028c0 ) + 80027fc: f7fe f824 bl 8000848 + + if (htim->State == HAL_TIM_STATE_RESET) + 8002800: 687b ldr r3, [r7, #4] + 8002802: f893 303d ldrb.w r3, [r3, #61] @ 0x3d + 8002806: b2db uxtb r3, r3 + 8002808: 2b00 cmp r3, #0 + 800280a: d106 bne.n 800281a + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 800280c: 687b ldr r3, [r7, #4] + 800280e: 2200 movs r2, #0 + 8002810: f883 203c strb.w r2, [r3, #60] @ 0x3c + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); + 8002814: 6878 ldr r0, [r7, #4] + 8002816: f000 f855 bl 80028c4 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 800281a: 687b ldr r3, [r7, #4] + 800281c: 2202 movs r2, #2 + 800281e: f883 203d strb.w r2, [r3, #61] @ 0x3d + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 8002822: 687b ldr r3, [r7, #4] + 8002824: 681a ldr r2, [r3, #0] + 8002826: 687b ldr r3, [r7, #4] + 8002828: 3304 adds r3, #4 + 800282a: 4619 mov r1, r3 + 800282c: 4610 mov r0, r2 + 800282e: f000 fa31 bl 8002c94 + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 8002832: 687b ldr r3, [r7, #4] + 8002834: 2201 movs r2, #1 + 8002836: f883 2046 strb.w r2, [r3, #70] @ 0x46 + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 800283a: 687b ldr r3, [r7, #4] + 800283c: 2201 movs r2, #1 + 800283e: f883 203e strb.w r2, [r3, #62] @ 0x3e + 8002842: 687b ldr r3, [r7, #4] + 8002844: 2201 movs r2, #1 + 8002846: f883 203f strb.w r2, [r3, #63] @ 0x3f + 800284a: 687b ldr r3, [r7, #4] + 800284c: 2201 movs r2, #1 + 800284e: f883 2040 strb.w r2, [r3, #64] @ 0x40 + 8002852: 687b ldr r3, [r7, #4] + 8002854: 2201 movs r2, #1 + 8002856: f883 2041 strb.w r2, [r3, #65] @ 0x41 + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 800285a: 687b ldr r3, [r7, #4] + 800285c: 2201 movs r2, #1 + 800285e: f883 2042 strb.w r2, [r3, #66] @ 0x42 + 8002862: 687b ldr r3, [r7, #4] + 8002864: 2201 movs r2, #1 + 8002866: f883 2043 strb.w r2, [r3, #67] @ 0x43 + 800286a: 687b ldr r3, [r7, #4] + 800286c: 2201 movs r2, #1 + 800286e: f883 2044 strb.w r2, [r3, #68] @ 0x44 + 8002872: 687b ldr r3, [r7, #4] + 8002874: 2201 movs r2, #1 + 8002876: f883 2045 strb.w r2, [r3, #69] @ 0x45 + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 800287a: 687b ldr r3, [r7, #4] + 800287c: 2201 movs r2, #1 + 800287e: f883 203d strb.w r2, [r3, #61] @ 0x3d + + return HAL_OK; + 8002882: 2300 movs r3, #0 +} + 8002884: 4618 mov r0, r3 + 8002886: 3708 adds r7, #8 + 8002888: 46bd mov sp, r7 + 800288a: bd80 pop {r7, pc} + 800288c: 40010000 .word 0x40010000 + 8002890: 40000400 .word 0x40000400 + 8002894: 40000800 .word 0x40000800 + 8002898: 40000c00 .word 0x40000c00 + 800289c: 40001000 .word 0x40001000 + 80028a0: 40001400 .word 0x40001400 + 80028a4: 40010400 .word 0x40010400 + 80028a8: 40014000 .word 0x40014000 + 80028ac: 40014400 .word 0x40014400 + 80028b0: 40014800 .word 0x40014800 + 80028b4: 40001800 .word 0x40001800 + 80028b8: 40001c00 .word 0x40001c00 + 80028bc: 40002000 .word 0x40002000 + 80028c0: 08005cd0 .word 0x08005cd0 + +080028c4 : + * @brief Initializes the TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) +{ + 80028c4: b480 push {r7} + 80028c6: b083 sub sp, #12 + 80028c8: af00 add r7, sp, #0 + 80028ca: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspInit could be implemented in the user file + */ +} + 80028cc: bf00 nop + 80028ce: 370c adds r7, #12 + 80028d0: 46bd mov sp, r7 + 80028d2: f85d 7b04 ldr.w r7, [sp], #4 + 80028d6: 4770 bx lr + +080028d8 : + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + 80028d8: b580 push {r7, lr} + 80028da: b084 sub sp, #16 + 80028dc: af00 add r7, sp, #0 + 80028de: 6078 str r0, [r7, #4] + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + 80028e0: 687b ldr r3, [r7, #4] + 80028e2: 681b ldr r3, [r3, #0] + 80028e4: 4a51 ldr r2, [pc, #324] @ (8002a2c ) + 80028e6: 4293 cmp r3, r2 + 80028e8: d045 beq.n 8002976 + 80028ea: 687b ldr r3, [r7, #4] + 80028ec: 681b ldr r3, [r3, #0] + 80028ee: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 80028f2: d040 beq.n 8002976 + 80028f4: 687b ldr r3, [r7, #4] + 80028f6: 681b ldr r3, [r3, #0] + 80028f8: 4a4d ldr r2, [pc, #308] @ (8002a30 ) + 80028fa: 4293 cmp r3, r2 + 80028fc: d03b beq.n 8002976 + 80028fe: 687b ldr r3, [r7, #4] + 8002900: 681b ldr r3, [r3, #0] + 8002902: 4a4c ldr r2, [pc, #304] @ (8002a34 ) + 8002904: 4293 cmp r3, r2 + 8002906: d036 beq.n 8002976 + 8002908: 687b ldr r3, [r7, #4] + 800290a: 681b ldr r3, [r3, #0] + 800290c: 4a4a ldr r2, [pc, #296] @ (8002a38 ) + 800290e: 4293 cmp r3, r2 + 8002910: d031 beq.n 8002976 + 8002912: 687b ldr r3, [r7, #4] + 8002914: 681b ldr r3, [r3, #0] + 8002916: 4a49 ldr r2, [pc, #292] @ (8002a3c ) + 8002918: 4293 cmp r3, r2 + 800291a: d02c beq.n 8002976 + 800291c: 687b ldr r3, [r7, #4] + 800291e: 681b ldr r3, [r3, #0] + 8002920: 4a47 ldr r2, [pc, #284] @ (8002a40 ) + 8002922: 4293 cmp r3, r2 + 8002924: d027 beq.n 8002976 + 8002926: 687b ldr r3, [r7, #4] + 8002928: 681b ldr r3, [r3, #0] + 800292a: 4a46 ldr r2, [pc, #280] @ (8002a44 ) + 800292c: 4293 cmp r3, r2 + 800292e: d022 beq.n 8002976 + 8002930: 687b ldr r3, [r7, #4] + 8002932: 681b ldr r3, [r3, #0] + 8002934: 4a44 ldr r2, [pc, #272] @ (8002a48 ) + 8002936: 4293 cmp r3, r2 + 8002938: d01d beq.n 8002976 + 800293a: 687b ldr r3, [r7, #4] + 800293c: 681b ldr r3, [r3, #0] + 800293e: 4a43 ldr r2, [pc, #268] @ (8002a4c ) + 8002940: 4293 cmp r3, r2 + 8002942: d018 beq.n 8002976 + 8002944: 687b ldr r3, [r7, #4] + 8002946: 681b ldr r3, [r3, #0] + 8002948: 4a41 ldr r2, [pc, #260] @ (8002a50 ) + 800294a: 4293 cmp r3, r2 + 800294c: d013 beq.n 8002976 + 800294e: 687b ldr r3, [r7, #4] + 8002950: 681b ldr r3, [r3, #0] + 8002952: 4a40 ldr r2, [pc, #256] @ (8002a54 ) + 8002954: 4293 cmp r3, r2 + 8002956: d00e beq.n 8002976 + 8002958: 687b ldr r3, [r7, #4] + 800295a: 681b ldr r3, [r3, #0] + 800295c: 4a3e ldr r2, [pc, #248] @ (8002a58 ) + 800295e: 4293 cmp r3, r2 + 8002960: d009 beq.n 8002976 + 8002962: 687b ldr r3, [r7, #4] + 8002964: 681b ldr r3, [r3, #0] + 8002966: 4a3d ldr r2, [pc, #244] @ (8002a5c ) + 8002968: 4293 cmp r3, r2 + 800296a: d004 beq.n 8002976 + 800296c: f44f 71e8 mov.w r1, #464 @ 0x1d0 + 8002970: 483b ldr r0, [pc, #236] @ (8002a60 ) + 8002972: f7fd ff69 bl 8000848 + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + 8002976: 687b ldr r3, [r7, #4] + 8002978: f893 303d ldrb.w r3, [r3, #61] @ 0x3d + 800297c: b2db uxtb r3, r3 + 800297e: 2b01 cmp r3, #1 + 8002980: d001 beq.n 8002986 + { + return HAL_ERROR; + 8002982: 2301 movs r3, #1 + 8002984: e04e b.n 8002a24 + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 8002986: 687b ldr r3, [r7, #4] + 8002988: 2202 movs r2, #2 + 800298a: f883 203d strb.w r2, [r3, #61] @ 0x3d + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + 800298e: 687b ldr r3, [r7, #4] + 8002990: 681b ldr r3, [r3, #0] + 8002992: 68da ldr r2, [r3, #12] + 8002994: 687b ldr r3, [r7, #4] + 8002996: 681b ldr r3, [r3, #0] + 8002998: f042 0201 orr.w r2, r2, #1 + 800299c: 60da str r2, [r3, #12] + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 800299e: 687b ldr r3, [r7, #4] + 80029a0: 681b ldr r3, [r3, #0] + 80029a2: 4a22 ldr r2, [pc, #136] @ (8002a2c ) + 80029a4: 4293 cmp r3, r2 + 80029a6: d022 beq.n 80029ee + 80029a8: 687b ldr r3, [r7, #4] + 80029aa: 681b ldr r3, [r3, #0] + 80029ac: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 80029b0: d01d beq.n 80029ee + 80029b2: 687b ldr r3, [r7, #4] + 80029b4: 681b ldr r3, [r3, #0] + 80029b6: 4a1e ldr r2, [pc, #120] @ (8002a30 ) + 80029b8: 4293 cmp r3, r2 + 80029ba: d018 beq.n 80029ee + 80029bc: 687b ldr r3, [r7, #4] + 80029be: 681b ldr r3, [r3, #0] + 80029c0: 4a1c ldr r2, [pc, #112] @ (8002a34 ) + 80029c2: 4293 cmp r3, r2 + 80029c4: d013 beq.n 80029ee + 80029c6: 687b ldr r3, [r7, #4] + 80029c8: 681b ldr r3, [r3, #0] + 80029ca: 4a1b ldr r2, [pc, #108] @ (8002a38 ) + 80029cc: 4293 cmp r3, r2 + 80029ce: d00e beq.n 80029ee + 80029d0: 687b ldr r3, [r7, #4] + 80029d2: 681b ldr r3, [r3, #0] + 80029d4: 4a1b ldr r2, [pc, #108] @ (8002a44 ) + 80029d6: 4293 cmp r3, r2 + 80029d8: d009 beq.n 80029ee + 80029da: 687b ldr r3, [r7, #4] + 80029dc: 681b ldr r3, [r3, #0] + 80029de: 4a1a ldr r2, [pc, #104] @ (8002a48 ) + 80029e0: 4293 cmp r3, r2 + 80029e2: d004 beq.n 80029ee + 80029e4: 687b ldr r3, [r7, #4] + 80029e6: 681b ldr r3, [r3, #0] + 80029e8: 4a1a ldr r2, [pc, #104] @ (8002a54 ) + 80029ea: 4293 cmp r3, r2 + 80029ec: d111 bne.n 8002a12 + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 80029ee: 687b ldr r3, [r7, #4] + 80029f0: 681b ldr r3, [r3, #0] + 80029f2: 689b ldr r3, [r3, #8] + 80029f4: f003 0307 and.w r3, r3, #7 + 80029f8: 60fb str r3, [r7, #12] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 80029fa: 68fb ldr r3, [r7, #12] + 80029fc: 2b06 cmp r3, #6 + 80029fe: d010 beq.n 8002a22 + { + __HAL_TIM_ENABLE(htim); + 8002a00: 687b ldr r3, [r7, #4] + 8002a02: 681b ldr r3, [r3, #0] + 8002a04: 681a ldr r2, [r3, #0] + 8002a06: 687b ldr r3, [r7, #4] + 8002a08: 681b ldr r3, [r3, #0] + 8002a0a: f042 0201 orr.w r2, r2, #1 + 8002a0e: 601a str r2, [r3, #0] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 8002a10: e007 b.n 8002a22 + } + } + else + { + __HAL_TIM_ENABLE(htim); + 8002a12: 687b ldr r3, [r7, #4] + 8002a14: 681b ldr r3, [r3, #0] + 8002a16: 681a ldr r2, [r3, #0] + 8002a18: 687b ldr r3, [r7, #4] + 8002a1a: 681b ldr r3, [r3, #0] + 8002a1c: f042 0201 orr.w r2, r2, #1 + 8002a20: 601a str r2, [r3, #0] + } + + /* Return function status */ + return HAL_OK; + 8002a22: 2300 movs r3, #0 +} + 8002a24: 4618 mov r0, r3 + 8002a26: 3710 adds r7, #16 + 8002a28: 46bd mov sp, r7 + 8002a2a: bd80 pop {r7, pc} + 8002a2c: 40010000 .word 0x40010000 + 8002a30: 40000400 .word 0x40000400 + 8002a34: 40000800 .word 0x40000800 + 8002a38: 40000c00 .word 0x40000c00 + 8002a3c: 40001000 .word 0x40001000 + 8002a40: 40001400 .word 0x40001400 + 8002a44: 40010400 .word 0x40010400 + 8002a48: 40014000 .word 0x40014000 + 8002a4c: 40014400 .word 0x40014400 + 8002a50: 40014800 .word 0x40014800 + 8002a54: 40001800 .word 0x40001800 + 8002a58: 40001c00 .word 0x40001c00 + 8002a5c: 40002000 .word 0x40002000 + 8002a60: 08005cd0 .word 0x08005cd0 + +08002a64 : + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + 8002a64: b580 push {r7, lr} + 8002a66: b084 sub sp, #16 + 8002a68: af00 add r7, sp, #0 + 8002a6a: 6078 str r0, [r7, #4] + uint32_t itsource = htim->Instance->DIER; + 8002a6c: 687b ldr r3, [r7, #4] + 8002a6e: 681b ldr r3, [r3, #0] + 8002a70: 68db ldr r3, [r3, #12] + 8002a72: 60fb str r3, [r7, #12] + uint32_t itflag = htim->Instance->SR; + 8002a74: 687b ldr r3, [r7, #4] + 8002a76: 681b ldr r3, [r3, #0] + 8002a78: 691b ldr r3, [r3, #16] + 8002a7a: 60bb str r3, [r7, #8] + + /* Capture compare 1 event */ + if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) + 8002a7c: 68bb ldr r3, [r7, #8] + 8002a7e: f003 0302 and.w r3, r3, #2 + 8002a82: 2b00 cmp r3, #0 + 8002a84: d020 beq.n 8002ac8 + { + if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) + 8002a86: 68fb ldr r3, [r7, #12] + 8002a88: f003 0302 and.w r3, r3, #2 + 8002a8c: 2b00 cmp r3, #0 + 8002a8e: d01b beq.n 8002ac8 + { + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); + 8002a90: 687b ldr r3, [r7, #4] + 8002a92: 681b ldr r3, [r3, #0] + 8002a94: f06f 0202 mvn.w r2, #2 + 8002a98: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + 8002a9a: 687b ldr r3, [r7, #4] + 8002a9c: 2201 movs r2, #1 + 8002a9e: 771a strb r2, [r3, #28] + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + 8002aa0: 687b ldr r3, [r7, #4] + 8002aa2: 681b ldr r3, [r3, #0] + 8002aa4: 699b ldr r3, [r3, #24] + 8002aa6: f003 0303 and.w r3, r3, #3 + 8002aaa: 2b00 cmp r3, #0 + 8002aac: d003 beq.n 8002ab6 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 8002aae: 6878 ldr r0, [r7, #4] + 8002ab0: f000 f8d2 bl 8002c58 + 8002ab4: e005 b.n 8002ac2 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 8002ab6: 6878 ldr r0, [r7, #4] + 8002ab8: f000 f8c4 bl 8002c44 + HAL_TIM_PWM_PulseFinishedCallback(htim); + 8002abc: 6878 ldr r0, [r7, #4] + 8002abe: f000 f8d5 bl 8002c6c +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 8002ac2: 687b ldr r3, [r7, #4] + 8002ac4: 2200 movs r2, #0 + 8002ac6: 771a strb r2, [r3, #28] + } + } + } + /* Capture compare 2 event */ + if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) + 8002ac8: 68bb ldr r3, [r7, #8] + 8002aca: f003 0304 and.w r3, r3, #4 + 8002ace: 2b00 cmp r3, #0 + 8002ad0: d020 beq.n 8002b14 + { + if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) + 8002ad2: 68fb ldr r3, [r7, #12] + 8002ad4: f003 0304 and.w r3, r3, #4 + 8002ad8: 2b00 cmp r3, #0 + 8002ada: d01b beq.n 8002b14 + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); + 8002adc: 687b ldr r3, [r7, #4] + 8002ade: 681b ldr r3, [r3, #0] + 8002ae0: f06f 0204 mvn.w r2, #4 + 8002ae4: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + 8002ae6: 687b ldr r3, [r7, #4] + 8002ae8: 2202 movs r2, #2 + 8002aea: 771a strb r2, [r3, #28] + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + 8002aec: 687b ldr r3, [r7, #4] + 8002aee: 681b ldr r3, [r3, #0] + 8002af0: 699b ldr r3, [r3, #24] + 8002af2: f403 7340 and.w r3, r3, #768 @ 0x300 + 8002af6: 2b00 cmp r3, #0 + 8002af8: d003 beq.n 8002b02 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 8002afa: 6878 ldr r0, [r7, #4] + 8002afc: f000 f8ac bl 8002c58 + 8002b00: e005 b.n 8002b0e + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 8002b02: 6878 ldr r0, [r7, #4] + 8002b04: f000 f89e bl 8002c44 + HAL_TIM_PWM_PulseFinishedCallback(htim); + 8002b08: 6878 ldr r0, [r7, #4] + 8002b0a: f000 f8af bl 8002c6c +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 8002b0e: 687b ldr r3, [r7, #4] + 8002b10: 2200 movs r2, #0 + 8002b12: 771a strb r2, [r3, #28] + } + } + /* Capture compare 3 event */ + if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) + 8002b14: 68bb ldr r3, [r7, #8] + 8002b16: f003 0308 and.w r3, r3, #8 + 8002b1a: 2b00 cmp r3, #0 + 8002b1c: d020 beq.n 8002b60 + { + if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) + 8002b1e: 68fb ldr r3, [r7, #12] + 8002b20: f003 0308 and.w r3, r3, #8 + 8002b24: 2b00 cmp r3, #0 + 8002b26: d01b beq.n 8002b60 + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); + 8002b28: 687b ldr r3, [r7, #4] + 8002b2a: 681b ldr r3, [r3, #0] + 8002b2c: f06f 0208 mvn.w r2, #8 + 8002b30: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + 8002b32: 687b ldr r3, [r7, #4] + 8002b34: 2204 movs r2, #4 + 8002b36: 771a strb r2, [r3, #28] + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + 8002b38: 687b ldr r3, [r7, #4] + 8002b3a: 681b ldr r3, [r3, #0] + 8002b3c: 69db ldr r3, [r3, #28] + 8002b3e: f003 0303 and.w r3, r3, #3 + 8002b42: 2b00 cmp r3, #0 + 8002b44: d003 beq.n 8002b4e + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 8002b46: 6878 ldr r0, [r7, #4] + 8002b48: f000 f886 bl 8002c58 + 8002b4c: e005 b.n 8002b5a + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 8002b4e: 6878 ldr r0, [r7, #4] + 8002b50: f000 f878 bl 8002c44 + HAL_TIM_PWM_PulseFinishedCallback(htim); + 8002b54: 6878 ldr r0, [r7, #4] + 8002b56: f000 f889 bl 8002c6c +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 8002b5a: 687b ldr r3, [r7, #4] + 8002b5c: 2200 movs r2, #0 + 8002b5e: 771a strb r2, [r3, #28] + } + } + /* Capture compare 4 event */ + if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) + 8002b60: 68bb ldr r3, [r7, #8] + 8002b62: f003 0310 and.w r3, r3, #16 + 8002b66: 2b00 cmp r3, #0 + 8002b68: d020 beq.n 8002bac + { + if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) + 8002b6a: 68fb ldr r3, [r7, #12] + 8002b6c: f003 0310 and.w r3, r3, #16 + 8002b70: 2b00 cmp r3, #0 + 8002b72: d01b beq.n 8002bac + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); + 8002b74: 687b ldr r3, [r7, #4] + 8002b76: 681b ldr r3, [r3, #0] + 8002b78: f06f 0210 mvn.w r2, #16 + 8002b7c: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + 8002b7e: 687b ldr r3, [r7, #4] + 8002b80: 2208 movs r2, #8 + 8002b82: 771a strb r2, [r3, #28] + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + 8002b84: 687b ldr r3, [r7, #4] + 8002b86: 681b ldr r3, [r3, #0] + 8002b88: 69db ldr r3, [r3, #28] + 8002b8a: f403 7340 and.w r3, r3, #768 @ 0x300 + 8002b8e: 2b00 cmp r3, #0 + 8002b90: d003 beq.n 8002b9a + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 8002b92: 6878 ldr r0, [r7, #4] + 8002b94: f000 f860 bl 8002c58 + 8002b98: e005 b.n 8002ba6 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 8002b9a: 6878 ldr r0, [r7, #4] + 8002b9c: f000 f852 bl 8002c44 + HAL_TIM_PWM_PulseFinishedCallback(htim); + 8002ba0: 6878 ldr r0, [r7, #4] + 8002ba2: f000 f863 bl 8002c6c +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 8002ba6: 687b ldr r3, [r7, #4] + 8002ba8: 2200 movs r2, #0 + 8002baa: 771a strb r2, [r3, #28] + } + } + /* TIM Update event */ + if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) + 8002bac: 68bb ldr r3, [r7, #8] + 8002bae: f003 0301 and.w r3, r3, #1 + 8002bb2: 2b00 cmp r3, #0 + 8002bb4: d00c beq.n 8002bd0 + { + if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) + 8002bb6: 68fb ldr r3, [r7, #12] + 8002bb8: f003 0301 and.w r3, r3, #1 + 8002bbc: 2b00 cmp r3, #0 + 8002bbe: d007 beq.n 8002bd0 + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); + 8002bc0: 687b ldr r3, [r7, #4] + 8002bc2: 681b ldr r3, [r3, #0] + 8002bc4: f06f 0201 mvn.w r2, #1 + 8002bc8: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); + 8002bca: 6878 ldr r0, [r7, #4] + 8002bcc: f7fd fe24 bl 8000818 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break input event */ + if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) + 8002bd0: 68bb ldr r3, [r7, #8] + 8002bd2: f003 0380 and.w r3, r3, #128 @ 0x80 + 8002bd6: 2b00 cmp r3, #0 + 8002bd8: d00c beq.n 8002bf4 + { + if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) + 8002bda: 68fb ldr r3, [r7, #12] + 8002bdc: f003 0380 and.w r3, r3, #128 @ 0x80 + 8002be0: 2b00 cmp r3, #0 + 8002be2: d007 beq.n 8002bf4 + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK); + 8002be4: 687b ldr r3, [r7, #4] + 8002be6: 681b ldr r3, [r3, #0] + 8002be8: f06f 0280 mvn.w r2, #128 @ 0x80 + 8002bec: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->BreakCallback(htim); +#else + HAL_TIMEx_BreakCallback(htim); + 8002bee: 6878 ldr r0, [r7, #4] + 8002bf0: f000 f900 bl 8002df4 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Trigger detection event */ + if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) + 8002bf4: 68bb ldr r3, [r7, #8] + 8002bf6: f003 0340 and.w r3, r3, #64 @ 0x40 + 8002bfa: 2b00 cmp r3, #0 + 8002bfc: d00c beq.n 8002c18 + { + if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) + 8002bfe: 68fb ldr r3, [r7, #12] + 8002c00: f003 0340 and.w r3, r3, #64 @ 0x40 + 8002c04: 2b00 cmp r3, #0 + 8002c06: d007 beq.n 8002c18 + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); + 8002c08: 687b ldr r3, [r7, #4] + 8002c0a: 681b ldr r3, [r3, #0] + 8002c0c: f06f 0240 mvn.w r2, #64 @ 0x40 + 8002c10: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); + 8002c12: 6878 ldr r0, [r7, #4] + 8002c14: f000 f834 bl 8002c80 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM commutation event */ + if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) + 8002c18: 68bb ldr r3, [r7, #8] + 8002c1a: f003 0320 and.w r3, r3, #32 + 8002c1e: 2b00 cmp r3, #0 + 8002c20: d00c beq.n 8002c3c + { + if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) + 8002c22: 68fb ldr r3, [r7, #12] + 8002c24: f003 0320 and.w r3, r3, #32 + 8002c28: 2b00 cmp r3, #0 + 8002c2a: d007 beq.n 8002c3c + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); + 8002c2c: 687b ldr r3, [r7, #4] + 8002c2e: 681b ldr r3, [r3, #0] + 8002c30: f06f 0220 mvn.w r2, #32 + 8002c34: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); + 8002c36: 6878 ldr r0, [r7, #4] + 8002c38: f000 f8d2 bl 8002de0 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + 8002c3c: bf00 nop + 8002c3e: 3710 adds r7, #16 + 8002c40: 46bd mov sp, r7 + 8002c42: bd80 pop {r7, pc} + +08002c44 : + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + 8002c44: b480 push {r7} + 8002c46: b083 sub sp, #12 + 8002c48: af00 add r7, sp, #0 + 8002c4a: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + 8002c4c: bf00 nop + 8002c4e: 370c adds r7, #12 + 8002c50: 46bd mov sp, r7 + 8002c52: f85d 7b04 ldr.w r7, [sp], #4 + 8002c56: 4770 bx lr + +08002c58 : + * @brief Input Capture callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + 8002c58: b480 push {r7} + 8002c5a: b083 sub sp, #12 + 8002c5c: af00 add r7, sp, #0 + 8002c5e: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + 8002c60: bf00 nop + 8002c62: 370c adds r7, #12 + 8002c64: 46bd mov sp, r7 + 8002c66: f85d 7b04 ldr.w r7, [sp], #4 + 8002c6a: 4770 bx lr + +08002c6c : + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + 8002c6c: b480 push {r7} + 8002c6e: b083 sub sp, #12 + 8002c70: af00 add r7, sp, #0 + 8002c72: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + 8002c74: bf00 nop + 8002c76: 370c adds r7, #12 + 8002c78: 46bd mov sp, r7 + 8002c7a: f85d 7b04 ldr.w r7, [sp], #4 + 8002c7e: 4770 bx lr + +08002c80 : + * @brief Hall Trigger detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + 8002c80: b480 push {r7} + 8002c82: b083 sub sp, #12 + 8002c84: af00 add r7, sp, #0 + 8002c86: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + 8002c88: bf00 nop + 8002c8a: 370c adds r7, #12 + 8002c8c: 46bd mov sp, r7 + 8002c8e: f85d 7b04 ldr.w r7, [sp], #4 + 8002c92: 4770 bx lr + +08002c94 : + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) +{ + 8002c94: b480 push {r7} + 8002c96: b085 sub sp, #20 + 8002c98: af00 add r7, sp, #0 + 8002c9a: 6078 str r0, [r7, #4] + 8002c9c: 6039 str r1, [r7, #0] + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + 8002c9e: 687b ldr r3, [r7, #4] + 8002ca0: 681b ldr r3, [r3, #0] + 8002ca2: 60fb str r3, [r7, #12] + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + 8002ca4: 687b ldr r3, [r7, #4] + 8002ca6: 4a43 ldr r2, [pc, #268] @ (8002db4 ) + 8002ca8: 4293 cmp r3, r2 + 8002caa: d013 beq.n 8002cd4 + 8002cac: 687b ldr r3, [r7, #4] + 8002cae: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8002cb2: d00f beq.n 8002cd4 + 8002cb4: 687b ldr r3, [r7, #4] + 8002cb6: 4a40 ldr r2, [pc, #256] @ (8002db8 ) + 8002cb8: 4293 cmp r3, r2 + 8002cba: d00b beq.n 8002cd4 + 8002cbc: 687b ldr r3, [r7, #4] + 8002cbe: 4a3f ldr r2, [pc, #252] @ (8002dbc ) + 8002cc0: 4293 cmp r3, r2 + 8002cc2: d007 beq.n 8002cd4 + 8002cc4: 687b ldr r3, [r7, #4] + 8002cc6: 4a3e ldr r2, [pc, #248] @ (8002dc0 ) + 8002cc8: 4293 cmp r3, r2 + 8002cca: d003 beq.n 8002cd4 + 8002ccc: 687b ldr r3, [r7, #4] + 8002cce: 4a3d ldr r2, [pc, #244] @ (8002dc4 ) + 8002cd0: 4293 cmp r3, r2 + 8002cd2: d108 bne.n 8002ce6 + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + 8002cd4: 68fb ldr r3, [r7, #12] + 8002cd6: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8002cda: 60fb str r3, [r7, #12] + tmpcr1 |= Structure->CounterMode; + 8002cdc: 683b ldr r3, [r7, #0] + 8002cde: 685b ldr r3, [r3, #4] + 8002ce0: 68fa ldr r2, [r7, #12] + 8002ce2: 4313 orrs r3, r2 + 8002ce4: 60fb str r3, [r7, #12] + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + 8002ce6: 687b ldr r3, [r7, #4] + 8002ce8: 4a32 ldr r2, [pc, #200] @ (8002db4 ) + 8002cea: 4293 cmp r3, r2 + 8002cec: d02b beq.n 8002d46 + 8002cee: 687b ldr r3, [r7, #4] + 8002cf0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8002cf4: d027 beq.n 8002d46 + 8002cf6: 687b ldr r3, [r7, #4] + 8002cf8: 4a2f ldr r2, [pc, #188] @ (8002db8 ) + 8002cfa: 4293 cmp r3, r2 + 8002cfc: d023 beq.n 8002d46 + 8002cfe: 687b ldr r3, [r7, #4] + 8002d00: 4a2e ldr r2, [pc, #184] @ (8002dbc ) + 8002d02: 4293 cmp r3, r2 + 8002d04: d01f beq.n 8002d46 + 8002d06: 687b ldr r3, [r7, #4] + 8002d08: 4a2d ldr r2, [pc, #180] @ (8002dc0 ) + 8002d0a: 4293 cmp r3, r2 + 8002d0c: d01b beq.n 8002d46 + 8002d0e: 687b ldr r3, [r7, #4] + 8002d10: 4a2c ldr r2, [pc, #176] @ (8002dc4 ) + 8002d12: 4293 cmp r3, r2 + 8002d14: d017 beq.n 8002d46 + 8002d16: 687b ldr r3, [r7, #4] + 8002d18: 4a2b ldr r2, [pc, #172] @ (8002dc8 ) + 8002d1a: 4293 cmp r3, r2 + 8002d1c: d013 beq.n 8002d46 + 8002d1e: 687b ldr r3, [r7, #4] + 8002d20: 4a2a ldr r2, [pc, #168] @ (8002dcc ) + 8002d22: 4293 cmp r3, r2 + 8002d24: d00f beq.n 8002d46 + 8002d26: 687b ldr r3, [r7, #4] + 8002d28: 4a29 ldr r2, [pc, #164] @ (8002dd0 ) + 8002d2a: 4293 cmp r3, r2 + 8002d2c: d00b beq.n 8002d46 + 8002d2e: 687b ldr r3, [r7, #4] + 8002d30: 4a28 ldr r2, [pc, #160] @ (8002dd4 ) + 8002d32: 4293 cmp r3, r2 + 8002d34: d007 beq.n 8002d46 + 8002d36: 687b ldr r3, [r7, #4] + 8002d38: 4a27 ldr r2, [pc, #156] @ (8002dd8 ) + 8002d3a: 4293 cmp r3, r2 + 8002d3c: d003 beq.n 8002d46 + 8002d3e: 687b ldr r3, [r7, #4] + 8002d40: 4a26 ldr r2, [pc, #152] @ (8002ddc ) + 8002d42: 4293 cmp r3, r2 + 8002d44: d108 bne.n 8002d58 + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + 8002d46: 68fb ldr r3, [r7, #12] + 8002d48: f423 7340 bic.w r3, r3, #768 @ 0x300 + 8002d4c: 60fb str r3, [r7, #12] + tmpcr1 |= (uint32_t)Structure->ClockDivision; + 8002d4e: 683b ldr r3, [r7, #0] + 8002d50: 68db ldr r3, [r3, #12] + 8002d52: 68fa ldr r2, [r7, #12] + 8002d54: 4313 orrs r3, r2 + 8002d56: 60fb str r3, [r7, #12] + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + 8002d58: 68fb ldr r3, [r7, #12] + 8002d5a: f023 0280 bic.w r2, r3, #128 @ 0x80 + 8002d5e: 683b ldr r3, [r7, #0] + 8002d60: 695b ldr r3, [r3, #20] + 8002d62: 4313 orrs r3, r2 + 8002d64: 60fb str r3, [r7, #12] + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + 8002d66: 683b ldr r3, [r7, #0] + 8002d68: 689a ldr r2, [r3, #8] + 8002d6a: 687b ldr r3, [r7, #4] + 8002d6c: 62da str r2, [r3, #44] @ 0x2c + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + 8002d6e: 683b ldr r3, [r7, #0] + 8002d70: 681a ldr r2, [r3, #0] + 8002d72: 687b ldr r3, [r7, #4] + 8002d74: 629a str r2, [r3, #40] @ 0x28 + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + 8002d76: 687b ldr r3, [r7, #4] + 8002d78: 4a0e ldr r2, [pc, #56] @ (8002db4 ) + 8002d7a: 4293 cmp r3, r2 + 8002d7c: d003 beq.n 8002d86 + 8002d7e: 687b ldr r3, [r7, #4] + 8002d80: 4a10 ldr r2, [pc, #64] @ (8002dc4 ) + 8002d82: 4293 cmp r3, r2 + 8002d84: d103 bne.n 8002d8e + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + 8002d86: 683b ldr r3, [r7, #0] + 8002d88: 691a ldr r2, [r3, #16] + 8002d8a: 687b ldr r3, [r7, #4] + 8002d8c: 631a str r2, [r3, #48] @ 0x30 + } + + /* Disable Update Event (UEV) with Update Generation (UG) + by changing Update Request Source (URS) to avoid Update flag (UIF) */ + SET_BIT(TIMx->CR1, TIM_CR1_URS); + 8002d8e: 687b ldr r3, [r7, #4] + 8002d90: 681b ldr r3, [r3, #0] + 8002d92: f043 0204 orr.w r2, r3, #4 + 8002d96: 687b ldr r3, [r7, #4] + 8002d98: 601a str r2, [r3, #0] + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; + 8002d9a: 687b ldr r3, [r7, #4] + 8002d9c: 2201 movs r2, #1 + 8002d9e: 615a str r2, [r3, #20] + + TIMx->CR1 = tmpcr1; + 8002da0: 687b ldr r3, [r7, #4] + 8002da2: 68fa ldr r2, [r7, #12] + 8002da4: 601a str r2, [r3, #0] +} + 8002da6: bf00 nop + 8002da8: 3714 adds r7, #20 + 8002daa: 46bd mov sp, r7 + 8002dac: f85d 7b04 ldr.w r7, [sp], #4 + 8002db0: 4770 bx lr + 8002db2: bf00 nop + 8002db4: 40010000 .word 0x40010000 + 8002db8: 40000400 .word 0x40000400 + 8002dbc: 40000800 .word 0x40000800 + 8002dc0: 40000c00 .word 0x40000c00 + 8002dc4: 40010400 .word 0x40010400 + 8002dc8: 40014000 .word 0x40014000 + 8002dcc: 40014400 .word 0x40014400 + 8002dd0: 40014800 .word 0x40014800 + 8002dd4: 40001800 .word 0x40001800 + 8002dd8: 40001c00 .word 0x40001c00 + 8002ddc: 40002000 .word 0x40002000 + +08002de0 : + * @brief Commutation callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) +{ + 8002de0: b480 push {r7} + 8002de2: b083 sub sp, #12 + 8002de4: af00 add r7, sp, #0 + 8002de6: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutCallback could be implemented in the user file + */ +} + 8002de8: bf00 nop + 8002dea: 370c adds r7, #12 + 8002dec: 46bd mov sp, r7 + 8002dee: f85d 7b04 ldr.w r7, [sp], #4 + 8002df2: 4770 bx lr + +08002df4 : + * @brief Break detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + 8002df4: b480 push {r7} + 8002df6: b083 sub sp, #12 + 8002df8: af00 add r7, sp, #0 + 8002dfa: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_BreakCallback could be implemented in the user file + */ +} + 8002dfc: bf00 nop + 8002dfe: 370c adds r7, #12 + 8002e00: 46bd mov sp, r7 + 8002e02: f85d 7b04 ldr.w r7, [sp], #4 + 8002e06: 4770 bx lr + +08002e08 <__NVIC_SetPriority>: +{ + 8002e08: b480 push {r7} + 8002e0a: b083 sub sp, #12 + 8002e0c: af00 add r7, sp, #0 + 8002e0e: 4603 mov r3, r0 + 8002e10: 6039 str r1, [r7, #0] + 8002e12: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8002e14: f997 3007 ldrsb.w r3, [r7, #7] + 8002e18: 2b00 cmp r3, #0 + 8002e1a: db0a blt.n 8002e32 <__NVIC_SetPriority+0x2a> + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8002e1c: 683b ldr r3, [r7, #0] + 8002e1e: b2da uxtb r2, r3 + 8002e20: 490c ldr r1, [pc, #48] @ (8002e54 <__NVIC_SetPriority+0x4c>) + 8002e22: f997 3007 ldrsb.w r3, [r7, #7] + 8002e26: 0112 lsls r2, r2, #4 + 8002e28: b2d2 uxtb r2, r2 + 8002e2a: 440b add r3, r1 + 8002e2c: f883 2300 strb.w r2, [r3, #768] @ 0x300 +} + 8002e30: e00a b.n 8002e48 <__NVIC_SetPriority+0x40> + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8002e32: 683b ldr r3, [r7, #0] + 8002e34: b2da uxtb r2, r3 + 8002e36: 4908 ldr r1, [pc, #32] @ (8002e58 <__NVIC_SetPriority+0x50>) + 8002e38: 79fb ldrb r3, [r7, #7] + 8002e3a: f003 030f and.w r3, r3, #15 + 8002e3e: 3b04 subs r3, #4 + 8002e40: 0112 lsls r2, r2, #4 + 8002e42: b2d2 uxtb r2, r2 + 8002e44: 440b add r3, r1 + 8002e46: 761a strb r2, [r3, #24] +} + 8002e48: bf00 nop + 8002e4a: 370c adds r7, #12 + 8002e4c: 46bd mov sp, r7 + 8002e4e: f85d 7b04 ldr.w r7, [sp], #4 + 8002e52: 4770 bx lr + 8002e54: e000e100 .word 0xe000e100 + 8002e58: e000ed00 .word 0xe000ed00 + +08002e5c : + +/* + SysTick handler implementation that also clears overflow flag. +*/ +#if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0) +void SysTick_Handler (void) { + 8002e5c: b580 push {r7, lr} + 8002e5e: af00 add r7, sp, #0 + /* Clear overflow flag */ + SysTick->CTRL; + 8002e60: 4b05 ldr r3, [pc, #20] @ (8002e78 ) + 8002e62: 681b ldr r3, [r3, #0] + + if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { + 8002e64: f001 fd46 bl 80048f4 + 8002e68: 4603 mov r3, r0 + 8002e6a: 2b01 cmp r3, #1 + 8002e6c: d001 beq.n 8002e72 + /* Call tick handler */ + xPortSysTickHandler(); + 8002e6e: f002 fb3b bl 80054e8 + } +} + 8002e72: bf00 nop + 8002e74: bd80 pop {r7, pc} + 8002e76: bf00 nop + 8002e78: e000e010 .word 0xe000e010 + +08002e7c : +#endif /* SysTick */ + +/* + Setup SVC to reset value. +*/ +__STATIC_INLINE void SVC_Setup (void) { + 8002e7c: b580 push {r7, lr} + 8002e7e: af00 add r7, sp, #0 +#if (__ARM_ARCH_7A__ == 0U) + /* Service Call interrupt might be configured before kernel start */ + /* and when its priority is lower or equal to BASEPRI, svc intruction */ + /* causes a Hard Fault. */ + NVIC_SetPriority (SVCall_IRQ_NBR, 0U); + 8002e80: 2100 movs r1, #0 + 8002e82: f06f 0004 mvn.w r0, #4 + 8002e86: f7ff ffbf bl 8002e08 <__NVIC_SetPriority> +#endif +} + 8002e8a: bf00 nop + 8002e8c: bd80 pop {r7, pc} + ... + +08002e90 : +static uint32_t OS_Tick_GetOverflow (void); +/* Get OS Tick interval */ +static uint32_t OS_Tick_GetInterval (void); +/*---------------------------------------------------------------------------*/ + +osStatus_t osKernelInitialize (void) { + 8002e90: b480 push {r7} + 8002e92: b083 sub sp, #12 + 8002e94: af00 add r7, sp, #0 + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 8002e96: f3ef 8305 mrs r3, IPSR + 8002e9a: 603b str r3, [r7, #0] + return(result); + 8002e9c: 683b ldr r3, [r7, #0] + osStatus_t stat; + + if (IS_IRQ()) { + 8002e9e: 2b00 cmp r3, #0 + 8002ea0: d003 beq.n 8002eaa + stat = osErrorISR; + 8002ea2: f06f 0305 mvn.w r3, #5 + 8002ea6: 607b str r3, [r7, #4] + 8002ea8: e00c b.n 8002ec4 + } + else { + if (KernelState == osKernelInactive) { + 8002eaa: 4b0a ldr r3, [pc, #40] @ (8002ed4 ) + 8002eac: 681b ldr r3, [r3, #0] + 8002eae: 2b00 cmp r3, #0 + 8002eb0: d105 bne.n 8002ebe + EvrFreeRTOSSetup(0U); + #endif + #if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1) + vPortDefineHeapRegions (configHEAP_5_REGIONS); + #endif + KernelState = osKernelReady; + 8002eb2: 4b08 ldr r3, [pc, #32] @ (8002ed4 ) + 8002eb4: 2201 movs r2, #1 + 8002eb6: 601a str r2, [r3, #0] + stat = osOK; + 8002eb8: 2300 movs r3, #0 + 8002eba: 607b str r3, [r7, #4] + 8002ebc: e002 b.n 8002ec4 + } else { + stat = osError; + 8002ebe: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 8002ec2: 607b str r3, [r7, #4] + } + } + + return (stat); + 8002ec4: 687b ldr r3, [r7, #4] +} + 8002ec6: 4618 mov r0, r3 + 8002ec8: 370c adds r7, #12 + 8002eca: 46bd mov sp, r7 + 8002ecc: f85d 7b04 ldr.w r7, [sp], #4 + 8002ed0: 4770 bx lr + 8002ed2: bf00 nop + 8002ed4: 200001a4 .word 0x200001a4 + +08002ed8 : + } + + return (state); +} + +osStatus_t osKernelStart (void) { + 8002ed8: b580 push {r7, lr} + 8002eda: b082 sub sp, #8 + 8002edc: af00 add r7, sp, #0 + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 8002ede: f3ef 8305 mrs r3, IPSR + 8002ee2: 603b str r3, [r7, #0] + return(result); + 8002ee4: 683b ldr r3, [r7, #0] + osStatus_t stat; + + if (IS_IRQ()) { + 8002ee6: 2b00 cmp r3, #0 + 8002ee8: d003 beq.n 8002ef2 + stat = osErrorISR; + 8002eea: f06f 0305 mvn.w r3, #5 + 8002eee: 607b str r3, [r7, #4] + 8002ef0: e010 b.n 8002f14 + } + else { + if (KernelState == osKernelReady) { + 8002ef2: 4b0b ldr r3, [pc, #44] @ (8002f20 ) + 8002ef4: 681b ldr r3, [r3, #0] + 8002ef6: 2b01 cmp r3, #1 + 8002ef8: d109 bne.n 8002f0e + /* Ensure SVC priority is at the reset value */ + SVC_Setup(); + 8002efa: f7ff ffbf bl 8002e7c + /* Change state to enable IRQ masking check */ + KernelState = osKernelRunning; + 8002efe: 4b08 ldr r3, [pc, #32] @ (8002f20 ) + 8002f00: 2202 movs r2, #2 + 8002f02: 601a str r2, [r3, #0] + /* Start the kernel scheduler */ + vTaskStartScheduler(); + 8002f04: f001 f892 bl 800402c + stat = osOK; + 8002f08: 2300 movs r3, #0 + 8002f0a: 607b str r3, [r7, #4] + 8002f0c: e002 b.n 8002f14 + } else { + stat = osError; + 8002f0e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 8002f12: 607b str r3, [r7, #4] + } + } + + return (stat); + 8002f14: 687b ldr r3, [r7, #4] +} + 8002f16: 4618 mov r0, r3 + 8002f18: 3708 adds r7, #8 + 8002f1a: 46bd mov sp, r7 + 8002f1c: bd80 pop {r7, pc} + 8002f1e: bf00 nop + 8002f20: 200001a4 .word 0x200001a4 + +08002f24 : + return (configCPU_CLOCK_HZ); +} + +/*---------------------------------------------------------------------------*/ + +osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) { + 8002f24: b580 push {r7, lr} + 8002f26: b08e sub sp, #56 @ 0x38 + 8002f28: af04 add r7, sp, #16 + 8002f2a: 60f8 str r0, [r7, #12] + 8002f2c: 60b9 str r1, [r7, #8] + 8002f2e: 607a str r2, [r7, #4] + uint32_t stack; + TaskHandle_t hTask; + UBaseType_t prio; + int32_t mem; + + hTask = NULL; + 8002f30: 2300 movs r3, #0 + 8002f32: 613b str r3, [r7, #16] + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 8002f34: f3ef 8305 mrs r3, IPSR + 8002f38: 617b str r3, [r7, #20] + return(result); + 8002f3a: 697b ldr r3, [r7, #20] + + if (!IS_IRQ() && (func != NULL)) { + 8002f3c: 2b00 cmp r3, #0 + 8002f3e: d17e bne.n 800303e + 8002f40: 68fb ldr r3, [r7, #12] + 8002f42: 2b00 cmp r3, #0 + 8002f44: d07b beq.n 800303e + stack = configMINIMAL_STACK_SIZE; + 8002f46: 2380 movs r3, #128 @ 0x80 + 8002f48: 623b str r3, [r7, #32] + prio = (UBaseType_t)osPriorityNormal; + 8002f4a: 2318 movs r3, #24 + 8002f4c: 61fb str r3, [r7, #28] + + name = NULL; + 8002f4e: 2300 movs r3, #0 + 8002f50: 627b str r3, [r7, #36] @ 0x24 + mem = -1; + 8002f52: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 8002f56: 61bb str r3, [r7, #24] + + if (attr != NULL) { + 8002f58: 687b ldr r3, [r7, #4] + 8002f5a: 2b00 cmp r3, #0 + 8002f5c: d045 beq.n 8002fea + if (attr->name != NULL) { + 8002f5e: 687b ldr r3, [r7, #4] + 8002f60: 681b ldr r3, [r3, #0] + 8002f62: 2b00 cmp r3, #0 + 8002f64: d002 beq.n 8002f6c + name = attr->name; + 8002f66: 687b ldr r3, [r7, #4] + 8002f68: 681b ldr r3, [r3, #0] + 8002f6a: 627b str r3, [r7, #36] @ 0x24 + } + if (attr->priority != osPriorityNone) { + 8002f6c: 687b ldr r3, [r7, #4] + 8002f6e: 699b ldr r3, [r3, #24] + 8002f70: 2b00 cmp r3, #0 + 8002f72: d002 beq.n 8002f7a + prio = (UBaseType_t)attr->priority; + 8002f74: 687b ldr r3, [r7, #4] + 8002f76: 699b ldr r3, [r3, #24] + 8002f78: 61fb str r3, [r7, #28] + } + + if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) { + 8002f7a: 69fb ldr r3, [r7, #28] + 8002f7c: 2b00 cmp r3, #0 + 8002f7e: d008 beq.n 8002f92 + 8002f80: 69fb ldr r3, [r7, #28] + 8002f82: 2b38 cmp r3, #56 @ 0x38 + 8002f84: d805 bhi.n 8002f92 + 8002f86: 687b ldr r3, [r7, #4] + 8002f88: 685b ldr r3, [r3, #4] + 8002f8a: f003 0301 and.w r3, r3, #1 + 8002f8e: 2b00 cmp r3, #0 + 8002f90: d001 beq.n 8002f96 + return (NULL); + 8002f92: 2300 movs r3, #0 + 8002f94: e054 b.n 8003040 + } + + if (attr->stack_size > 0U) { + 8002f96: 687b ldr r3, [r7, #4] + 8002f98: 695b ldr r3, [r3, #20] + 8002f9a: 2b00 cmp r3, #0 + 8002f9c: d003 beq.n 8002fa6 + /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports. */ + /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */ + stack = attr->stack_size / sizeof(StackType_t); + 8002f9e: 687b ldr r3, [r7, #4] + 8002fa0: 695b ldr r3, [r3, #20] + 8002fa2: 089b lsrs r3, r3, #2 + 8002fa4: 623b str r3, [r7, #32] + } + + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && + 8002fa6: 687b ldr r3, [r7, #4] + 8002fa8: 689b ldr r3, [r3, #8] + 8002faa: 2b00 cmp r3, #0 + 8002fac: d00e beq.n 8002fcc + 8002fae: 687b ldr r3, [r7, #4] + 8002fb0: 68db ldr r3, [r3, #12] + 8002fb2: 2ba7 cmp r3, #167 @ 0xa7 + 8002fb4: d90a bls.n 8002fcc + (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { + 8002fb6: 687b ldr r3, [r7, #4] + 8002fb8: 691b ldr r3, [r3, #16] + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && + 8002fba: 2b00 cmp r3, #0 + 8002fbc: d006 beq.n 8002fcc + (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { + 8002fbe: 687b ldr r3, [r7, #4] + 8002fc0: 695b ldr r3, [r3, #20] + 8002fc2: 2b00 cmp r3, #0 + 8002fc4: d002 beq.n 8002fcc + mem = 1; + 8002fc6: 2301 movs r3, #1 + 8002fc8: 61bb str r3, [r7, #24] + 8002fca: e010 b.n 8002fee + } + else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) { + 8002fcc: 687b ldr r3, [r7, #4] + 8002fce: 689b ldr r3, [r3, #8] + 8002fd0: 2b00 cmp r3, #0 + 8002fd2: d10c bne.n 8002fee + 8002fd4: 687b ldr r3, [r7, #4] + 8002fd6: 68db ldr r3, [r3, #12] + 8002fd8: 2b00 cmp r3, #0 + 8002fda: d108 bne.n 8002fee + 8002fdc: 687b ldr r3, [r7, #4] + 8002fde: 691b ldr r3, [r3, #16] + 8002fe0: 2b00 cmp r3, #0 + 8002fe2: d104 bne.n 8002fee + mem = 0; + 8002fe4: 2300 movs r3, #0 + 8002fe6: 61bb str r3, [r7, #24] + 8002fe8: e001 b.n 8002fee + } + } + } + else { + mem = 0; + 8002fea: 2300 movs r3, #0 + 8002fec: 61bb str r3, [r7, #24] + } + + if (mem == 1) { + 8002fee: 69bb ldr r3, [r7, #24] + 8002ff0: 2b01 cmp r3, #1 + 8002ff2: d110 bne.n 8003016 + #if (configSUPPORT_STATIC_ALLOCATION == 1) + hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, + 8002ff4: 687b ldr r3, [r7, #4] + 8002ff6: 691b ldr r3, [r3, #16] + (StaticTask_t *)attr->cb_mem); + 8002ff8: 687a ldr r2, [r7, #4] + 8002ffa: 6892 ldr r2, [r2, #8] + hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, + 8002ffc: 9202 str r2, [sp, #8] + 8002ffe: 9301 str r3, [sp, #4] + 8003000: 69fb ldr r3, [r7, #28] + 8003002: 9300 str r3, [sp, #0] + 8003004: 68bb ldr r3, [r7, #8] + 8003006: 6a3a ldr r2, [r7, #32] + 8003008: 6a79 ldr r1, [r7, #36] @ 0x24 + 800300a: 68f8 ldr r0, [r7, #12] + 800300c: f000 fe1a bl 8003c44 + 8003010: 4603 mov r3, r0 + 8003012: 613b str r3, [r7, #16] + 8003014: e013 b.n 800303e + #endif + } + else { + if (mem == 0) { + 8003016: 69bb ldr r3, [r7, #24] + 8003018: 2b00 cmp r3, #0 + 800301a: d110 bne.n 800303e + #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) { + 800301c: 6a3b ldr r3, [r7, #32] + 800301e: b29a uxth r2, r3 + 8003020: f107 0310 add.w r3, r7, #16 + 8003024: 9301 str r3, [sp, #4] + 8003026: 69fb ldr r3, [r7, #28] + 8003028: 9300 str r3, [sp, #0] + 800302a: 68bb ldr r3, [r7, #8] + 800302c: 6a79 ldr r1, [r7, #36] @ 0x24 + 800302e: 68f8 ldr r0, [r7, #12] + 8003030: f000 fe68 bl 8003d04 + 8003034: 4603 mov r3, r0 + 8003036: 2b01 cmp r3, #1 + 8003038: d001 beq.n 800303e + hTask = NULL; + 800303a: 2300 movs r3, #0 + 800303c: 613b str r3, [r7, #16] + #endif + } + } + } + + return ((osThreadId_t)hTask); + 800303e: 693b ldr r3, [r7, #16] +} + 8003040: 4618 mov r0, r3 + 8003042: 3728 adds r7, #40 @ 0x28 + 8003044: 46bd mov sp, r7 + 8003046: bd80 pop {r7, pc} + +08003048 : + /* Return flags before clearing */ + return (rflags); +} +#endif /* (configUSE_OS2_THREAD_FLAGS == 1) */ + +osStatus_t osDelay (uint32_t ticks) { + 8003048: b580 push {r7, lr} + 800304a: b084 sub sp, #16 + 800304c: af00 add r7, sp, #0 + 800304e: 6078 str r0, [r7, #4] + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 8003050: f3ef 8305 mrs r3, IPSR + 8003054: 60bb str r3, [r7, #8] + return(result); + 8003056: 68bb ldr r3, [r7, #8] + osStatus_t stat; + + if (IS_IRQ()) { + 8003058: 2b00 cmp r3, #0 + 800305a: d003 beq.n 8003064 + stat = osErrorISR; + 800305c: f06f 0305 mvn.w r3, #5 + 8003060: 60fb str r3, [r7, #12] + 8003062: e007 b.n 8003074 + } + else { + stat = osOK; + 8003064: 2300 movs r3, #0 + 8003066: 60fb str r3, [r7, #12] + + if (ticks != 0U) { + 8003068: 687b ldr r3, [r7, #4] + 800306a: 2b00 cmp r3, #0 + 800306c: d002 beq.n 8003074 + vTaskDelay(ticks); + 800306e: 6878 ldr r0, [r7, #4] + 8003070: f000 ffa6 bl 8003fc0 + } + } + + return (stat); + 8003074: 68fb ldr r3, [r7, #12] +} + 8003076: 4618 mov r0, r3 + 8003078: 3710 adds r7, #16 + 800307a: 46bd mov sp, r7 + 800307c: bd80 pop {r7, pc} + ... + +08003080 : + +/* + vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION + equals to 1 and is required for static memory allocation support. +*/ +__WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) { + 8003080: b480 push {r7} + 8003082: b085 sub sp, #20 + 8003084: af00 add r7, sp, #0 + 8003086: 60f8 str r0, [r7, #12] + 8003088: 60b9 str r1, [r7, #8] + 800308a: 607a str r2, [r7, #4] + /* Idle task control block and stack */ + static StaticTask_t Idle_TCB; + static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE]; + + *ppxIdleTaskTCBBuffer = &Idle_TCB; + 800308c: 68fb ldr r3, [r7, #12] + 800308e: 4a07 ldr r2, [pc, #28] @ (80030ac ) + 8003090: 601a str r2, [r3, #0] + *ppxIdleTaskStackBuffer = &Idle_Stack[0]; + 8003092: 68bb ldr r3, [r7, #8] + 8003094: 4a06 ldr r2, [pc, #24] @ (80030b0 ) + 8003096: 601a str r2, [r3, #0] + *pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE; + 8003098: 687b ldr r3, [r7, #4] + 800309a: 2280 movs r2, #128 @ 0x80 + 800309c: 601a str r2, [r3, #0] +} + 800309e: bf00 nop + 80030a0: 3714 adds r7, #20 + 80030a2: 46bd mov sp, r7 + 80030a4: f85d 7b04 ldr.w r7, [sp], #4 + 80030a8: 4770 bx lr + 80030aa: bf00 nop + 80030ac: 200001a8 .word 0x200001a8 + 80030b0: 20000250 .word 0x20000250 + +080030b4 : + +/* + vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION + equals to 1 and is required for static memory allocation support. +*/ +__WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) { + 80030b4: b480 push {r7} + 80030b6: b085 sub sp, #20 + 80030b8: af00 add r7, sp, #0 + 80030ba: 60f8 str r0, [r7, #12] + 80030bc: 60b9 str r1, [r7, #8] + 80030be: 607a str r2, [r7, #4] + /* Timer task control block and stack */ + static StaticTask_t Timer_TCB; + static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH]; + + *ppxTimerTaskTCBBuffer = &Timer_TCB; + 80030c0: 68fb ldr r3, [r7, #12] + 80030c2: 4a07 ldr r2, [pc, #28] @ (80030e0 ) + 80030c4: 601a str r2, [r3, #0] + *ppxTimerTaskStackBuffer = &Timer_Stack[0]; + 80030c6: 68bb ldr r3, [r7, #8] + 80030c8: 4a06 ldr r2, [pc, #24] @ (80030e4 ) + 80030ca: 601a str r2, [r3, #0] + *pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH; + 80030cc: 687b ldr r3, [r7, #4] + 80030ce: f44f 7280 mov.w r2, #256 @ 0x100 + 80030d2: 601a str r2, [r3, #0] +} + 80030d4: bf00 nop + 80030d6: 3714 adds r7, #20 + 80030d8: 46bd mov sp, r7 + 80030da: f85d 7b04 ldr.w r7, [sp], #4 + 80030de: 4770 bx lr + 80030e0: 20000450 .word 0x20000450 + 80030e4: 200004f8 .word 0x200004f8 + +080030e8 : +/*----------------------------------------------------------- + * PUBLIC LIST API documented in list.h + *----------------------------------------------------------*/ + +void vListInitialise( List_t * const pxList ) +{ + 80030e8: b480 push {r7} + 80030ea: b083 sub sp, #12 + 80030ec: af00 add r7, sp, #0 + 80030ee: 6078 str r0, [r7, #4] + /* The list structure contains a list item which is used to mark the + end of the list. To initialise the list the list end is inserted + as the only list entry. */ + pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + 80030f0: 687b ldr r3, [r7, #4] + 80030f2: f103 0208 add.w r2, r3, #8 + 80030f6: 687b ldr r3, [r7, #4] + 80030f8: 605a str r2, [r3, #4] + + /* The list end value is the highest possible value in the list to + ensure it remains at the end of the list. */ + pxList->xListEnd.xItemValue = portMAX_DELAY; + 80030fa: 687b ldr r3, [r7, #4] + 80030fc: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8003100: 609a str r2, [r3, #8] + + /* The list end next and previous pointers point to itself so we know + when the list is empty. */ + pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + 8003102: 687b ldr r3, [r7, #4] + 8003104: f103 0208 add.w r2, r3, #8 + 8003108: 687b ldr r3, [r7, #4] + 800310a: 60da str r2, [r3, #12] + pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + 800310c: 687b ldr r3, [r7, #4] + 800310e: f103 0208 add.w r2, r3, #8 + 8003112: 687b ldr r3, [r7, #4] + 8003114: 611a str r2, [r3, #16] + + pxList->uxNumberOfItems = ( UBaseType_t ) 0U; + 8003116: 687b ldr r3, [r7, #4] + 8003118: 2200 movs r2, #0 + 800311a: 601a str r2, [r3, #0] + + /* Write known values into the list if + configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ); + listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ); +} + 800311c: bf00 nop + 800311e: 370c adds r7, #12 + 8003120: 46bd mov sp, r7 + 8003122: f85d 7b04 ldr.w r7, [sp], #4 + 8003126: 4770 bx lr + +08003128 : +/*-----------------------------------------------------------*/ + +void vListInitialiseItem( ListItem_t * const pxItem ) +{ + 8003128: b480 push {r7} + 800312a: b083 sub sp, #12 + 800312c: af00 add r7, sp, #0 + 800312e: 6078 str r0, [r7, #4] + /* Make sure the list item is not recorded as being on a list. */ + pxItem->pxContainer = NULL; + 8003130: 687b ldr r3, [r7, #4] + 8003132: 2200 movs r2, #0 + 8003134: 611a str r2, [r3, #16] + + /* Write known values into the list item if + configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); + listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); +} + 8003136: bf00 nop + 8003138: 370c adds r7, #12 + 800313a: 46bd mov sp, r7 + 800313c: f85d 7b04 ldr.w r7, [sp], #4 + 8003140: 4770 bx lr + +08003142 : +/*-----------------------------------------------------------*/ + +void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) +{ + 8003142: b480 push {r7} + 8003144: b085 sub sp, #20 + 8003146: af00 add r7, sp, #0 + 8003148: 6078 str r0, [r7, #4] + 800314a: 6039 str r1, [r7, #0] +ListItem_t * const pxIndex = pxList->pxIndex; + 800314c: 687b ldr r3, [r7, #4] + 800314e: 685b ldr r3, [r3, #4] + 8003150: 60fb str r3, [r7, #12] + listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); + + /* Insert a new list item into pxList, but rather than sort the list, + makes the new list item the last item to be removed by a call to + listGET_OWNER_OF_NEXT_ENTRY(). */ + pxNewListItem->pxNext = pxIndex; + 8003152: 683b ldr r3, [r7, #0] + 8003154: 68fa ldr r2, [r7, #12] + 8003156: 605a str r2, [r3, #4] + pxNewListItem->pxPrevious = pxIndex->pxPrevious; + 8003158: 68fb ldr r3, [r7, #12] + 800315a: 689a ldr r2, [r3, #8] + 800315c: 683b ldr r3, [r7, #0] + 800315e: 609a str r2, [r3, #8] + + /* Only used during decision coverage testing. */ + mtCOVERAGE_TEST_DELAY(); + + pxIndex->pxPrevious->pxNext = pxNewListItem; + 8003160: 68fb ldr r3, [r7, #12] + 8003162: 689b ldr r3, [r3, #8] + 8003164: 683a ldr r2, [r7, #0] + 8003166: 605a str r2, [r3, #4] + pxIndex->pxPrevious = pxNewListItem; + 8003168: 68fb ldr r3, [r7, #12] + 800316a: 683a ldr r2, [r7, #0] + 800316c: 609a str r2, [r3, #8] + + /* Remember which list the item is in. */ + pxNewListItem->pxContainer = pxList; + 800316e: 683b ldr r3, [r7, #0] + 8003170: 687a ldr r2, [r7, #4] + 8003172: 611a str r2, [r3, #16] + + ( pxList->uxNumberOfItems )++; + 8003174: 687b ldr r3, [r7, #4] + 8003176: 681b ldr r3, [r3, #0] + 8003178: 1c5a adds r2, r3, #1 + 800317a: 687b ldr r3, [r7, #4] + 800317c: 601a str r2, [r3, #0] +} + 800317e: bf00 nop + 8003180: 3714 adds r7, #20 + 8003182: 46bd mov sp, r7 + 8003184: f85d 7b04 ldr.w r7, [sp], #4 + 8003188: 4770 bx lr + +0800318a : +/*-----------------------------------------------------------*/ + +void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) +{ + 800318a: b480 push {r7} + 800318c: b085 sub sp, #20 + 800318e: af00 add r7, sp, #0 + 8003190: 6078 str r0, [r7, #4] + 8003192: 6039 str r1, [r7, #0] +ListItem_t *pxIterator; +const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; + 8003194: 683b ldr r3, [r7, #0] + 8003196: 681b ldr r3, [r3, #0] + 8003198: 60bb str r3, [r7, #8] + new list item should be placed after it. This ensures that TCBs which are + stored in ready lists (all of which have the same xItemValue value) get a + share of the CPU. However, if the xItemValue is the same as the back marker + the iteration loop below will not end. Therefore the value is checked + first, and the algorithm slightly modified if necessary. */ + if( xValueOfInsertion == portMAX_DELAY ) + 800319a: 68bb ldr r3, [r7, #8] + 800319c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 80031a0: d103 bne.n 80031aa + { + pxIterator = pxList->xListEnd.pxPrevious; + 80031a2: 687b ldr r3, [r7, #4] + 80031a4: 691b ldr r3, [r3, #16] + 80031a6: 60fb str r3, [r7, #12] + 80031a8: e00c b.n 80031c4 + 4) Using a queue or semaphore before it has been initialised or + before the scheduler has been started (are interrupts firing + before vTaskStartScheduler() has been called?). + **********************************************************************/ + + for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */ + 80031aa: 687b ldr r3, [r7, #4] + 80031ac: 3308 adds r3, #8 + 80031ae: 60fb str r3, [r7, #12] + 80031b0: e002 b.n 80031b8 + 80031b2: 68fb ldr r3, [r7, #12] + 80031b4: 685b ldr r3, [r3, #4] + 80031b6: 60fb str r3, [r7, #12] + 80031b8: 68fb ldr r3, [r7, #12] + 80031ba: 685b ldr r3, [r3, #4] + 80031bc: 681b ldr r3, [r3, #0] + 80031be: 68ba ldr r2, [r7, #8] + 80031c0: 429a cmp r2, r3 + 80031c2: d2f6 bcs.n 80031b2 + /* There is nothing to do here, just iterating to the wanted + insertion position. */ + } + } + + pxNewListItem->pxNext = pxIterator->pxNext; + 80031c4: 68fb ldr r3, [r7, #12] + 80031c6: 685a ldr r2, [r3, #4] + 80031c8: 683b ldr r3, [r7, #0] + 80031ca: 605a str r2, [r3, #4] + pxNewListItem->pxNext->pxPrevious = pxNewListItem; + 80031cc: 683b ldr r3, [r7, #0] + 80031ce: 685b ldr r3, [r3, #4] + 80031d0: 683a ldr r2, [r7, #0] + 80031d2: 609a str r2, [r3, #8] + pxNewListItem->pxPrevious = pxIterator; + 80031d4: 683b ldr r3, [r7, #0] + 80031d6: 68fa ldr r2, [r7, #12] + 80031d8: 609a str r2, [r3, #8] + pxIterator->pxNext = pxNewListItem; + 80031da: 68fb ldr r3, [r7, #12] + 80031dc: 683a ldr r2, [r7, #0] + 80031de: 605a str r2, [r3, #4] + + /* Remember which list the item is in. This allows fast removal of the + item later. */ + pxNewListItem->pxContainer = pxList; + 80031e0: 683b ldr r3, [r7, #0] + 80031e2: 687a ldr r2, [r7, #4] + 80031e4: 611a str r2, [r3, #16] + + ( pxList->uxNumberOfItems )++; + 80031e6: 687b ldr r3, [r7, #4] + 80031e8: 681b ldr r3, [r3, #0] + 80031ea: 1c5a adds r2, r3, #1 + 80031ec: 687b ldr r3, [r7, #4] + 80031ee: 601a str r2, [r3, #0] +} + 80031f0: bf00 nop + 80031f2: 3714 adds r7, #20 + 80031f4: 46bd mov sp, r7 + 80031f6: f85d 7b04 ldr.w r7, [sp], #4 + 80031fa: 4770 bx lr + +080031fc : +/*-----------------------------------------------------------*/ + +UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) +{ + 80031fc: b480 push {r7} + 80031fe: b085 sub sp, #20 + 8003200: af00 add r7, sp, #0 + 8003202: 6078 str r0, [r7, #4] +/* The list item knows which list it is in. Obtain the list from the list +item. */ +List_t * const pxList = pxItemToRemove->pxContainer; + 8003204: 687b ldr r3, [r7, #4] + 8003206: 691b ldr r3, [r3, #16] + 8003208: 60fb str r3, [r7, #12] + + pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; + 800320a: 687b ldr r3, [r7, #4] + 800320c: 685b ldr r3, [r3, #4] + 800320e: 687a ldr r2, [r7, #4] + 8003210: 6892 ldr r2, [r2, #8] + 8003212: 609a str r2, [r3, #8] + pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; + 8003214: 687b ldr r3, [r7, #4] + 8003216: 689b ldr r3, [r3, #8] + 8003218: 687a ldr r2, [r7, #4] + 800321a: 6852 ldr r2, [r2, #4] + 800321c: 605a str r2, [r3, #4] + + /* Only used during decision coverage testing. */ + mtCOVERAGE_TEST_DELAY(); + + /* Make sure the index is left pointing to a valid item. */ + if( pxList->pxIndex == pxItemToRemove ) + 800321e: 68fb ldr r3, [r7, #12] + 8003220: 685b ldr r3, [r3, #4] + 8003222: 687a ldr r2, [r7, #4] + 8003224: 429a cmp r2, r3 + 8003226: d103 bne.n 8003230 + { + pxList->pxIndex = pxItemToRemove->pxPrevious; + 8003228: 687b ldr r3, [r7, #4] + 800322a: 689a ldr r2, [r3, #8] + 800322c: 68fb ldr r3, [r7, #12] + 800322e: 605a str r2, [r3, #4] + else + { + mtCOVERAGE_TEST_MARKER(); + } + + pxItemToRemove->pxContainer = NULL; + 8003230: 687b ldr r3, [r7, #4] + 8003232: 2200 movs r2, #0 + 8003234: 611a str r2, [r3, #16] + ( pxList->uxNumberOfItems )--; + 8003236: 68fb ldr r3, [r7, #12] + 8003238: 681b ldr r3, [r3, #0] + 800323a: 1e5a subs r2, r3, #1 + 800323c: 68fb ldr r3, [r7, #12] + 800323e: 601a str r2, [r3, #0] + + return pxList->uxNumberOfItems; + 8003240: 68fb ldr r3, [r7, #12] + 8003242: 681b ldr r3, [r3, #0] +} + 8003244: 4618 mov r0, r3 + 8003246: 3714 adds r7, #20 + 8003248: 46bd mov sp, r7 + 800324a: f85d 7b04 ldr.w r7, [sp], #4 + 800324e: 4770 bx lr + +08003250 : + } \ + taskEXIT_CRITICAL() +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) +{ + 8003250: b580 push {r7, lr} + 8003252: b084 sub sp, #16 + 8003254: af00 add r7, sp, #0 + 8003256: 6078 str r0, [r7, #4] + 8003258: 6039 str r1, [r7, #0] +Queue_t * const pxQueue = xQueue; + 800325a: 687b ldr r3, [r7, #4] + 800325c: 60fb str r3, [r7, #12] + + configASSERT( pxQueue ); + 800325e: 68fb ldr r3, [r7, #12] + 8003260: 2b00 cmp r3, #0 + 8003262: d10b bne.n 800327c + __asm volatile + 8003264: f04f 0350 mov.w r3, #80 @ 0x50 + 8003268: f383 8811 msr BASEPRI, r3 + 800326c: f3bf 8f6f isb sy + 8003270: f3bf 8f4f dsb sy + 8003274: 60bb str r3, [r7, #8] +} + 8003276: bf00 nop + 8003278: bf00 nop + 800327a: e7fd b.n 8003278 + + taskENTER_CRITICAL(); + 800327c: f002 f8a4 bl 80053c8 + { + pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ + 8003280: 68fb ldr r3, [r7, #12] + 8003282: 681a ldr r2, [r3, #0] + 8003284: 68fb ldr r3, [r7, #12] + 8003286: 6bdb ldr r3, [r3, #60] @ 0x3c + 8003288: 68f9 ldr r1, [r7, #12] + 800328a: 6c09 ldr r1, [r1, #64] @ 0x40 + 800328c: fb01 f303 mul.w r3, r1, r3 + 8003290: 441a add r2, r3 + 8003292: 68fb ldr r3, [r7, #12] + 8003294: 609a str r2, [r3, #8] + pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; + 8003296: 68fb ldr r3, [r7, #12] + 8003298: 2200 movs r2, #0 + 800329a: 639a str r2, [r3, #56] @ 0x38 + pxQueue->pcWriteTo = pxQueue->pcHead; + 800329c: 68fb ldr r3, [r7, #12] + 800329e: 681a ldr r2, [r3, #0] + 80032a0: 68fb ldr r3, [r7, #12] + 80032a2: 605a str r2, [r3, #4] + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ + 80032a4: 68fb ldr r3, [r7, #12] + 80032a6: 681a ldr r2, [r3, #0] + 80032a8: 68fb ldr r3, [r7, #12] + 80032aa: 6bdb ldr r3, [r3, #60] @ 0x3c + 80032ac: 3b01 subs r3, #1 + 80032ae: 68f9 ldr r1, [r7, #12] + 80032b0: 6c09 ldr r1, [r1, #64] @ 0x40 + 80032b2: fb01 f303 mul.w r3, r1, r3 + 80032b6: 441a add r2, r3 + 80032b8: 68fb ldr r3, [r7, #12] + 80032ba: 60da str r2, [r3, #12] + pxQueue->cRxLock = queueUNLOCKED; + 80032bc: 68fb ldr r3, [r7, #12] + 80032be: 22ff movs r2, #255 @ 0xff + 80032c0: f883 2044 strb.w r2, [r3, #68] @ 0x44 + pxQueue->cTxLock = queueUNLOCKED; + 80032c4: 68fb ldr r3, [r7, #12] + 80032c6: 22ff movs r2, #255 @ 0xff + 80032c8: f883 2045 strb.w r2, [r3, #69] @ 0x45 + + if( xNewQueue == pdFALSE ) + 80032cc: 683b ldr r3, [r7, #0] + 80032ce: 2b00 cmp r3, #0 + 80032d0: d114 bne.n 80032fc + /* If there are tasks blocked waiting to read from the queue, then + the tasks will remain blocked as after this function exits the queue + will still be empty. If there are tasks blocked waiting to write to + the queue, then one should be unblocked as after this function exits + it will be possible to write to it. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + 80032d2: 68fb ldr r3, [r7, #12] + 80032d4: 691b ldr r3, [r3, #16] + 80032d6: 2b00 cmp r3, #0 + 80032d8: d01a beq.n 8003310 + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + 80032da: 68fb ldr r3, [r7, #12] + 80032dc: 3310 adds r3, #16 + 80032de: 4618 mov r0, r3 + 80032e0: f001 f942 bl 8004568 + 80032e4: 4603 mov r3, r0 + 80032e6: 2b00 cmp r3, #0 + 80032e8: d012 beq.n 8003310 + { + queueYIELD_IF_USING_PREEMPTION(); + 80032ea: 4b0d ldr r3, [pc, #52] @ (8003320 ) + 80032ec: f04f 5280 mov.w r2, #268435456 @ 0x10000000 + 80032f0: 601a str r2, [r3, #0] + 80032f2: f3bf 8f4f dsb sy + 80032f6: f3bf 8f6f isb sy + 80032fa: e009 b.n 8003310 + } + } + else + { + /* Ensure the event queues start in the correct state. */ + vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); + 80032fc: 68fb ldr r3, [r7, #12] + 80032fe: 3310 adds r3, #16 + 8003300: 4618 mov r0, r3 + 8003302: f7ff fef1 bl 80030e8 + vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); + 8003306: 68fb ldr r3, [r7, #12] + 8003308: 3324 adds r3, #36 @ 0x24 + 800330a: 4618 mov r0, r3 + 800330c: f7ff feec bl 80030e8 + } + } + taskEXIT_CRITICAL(); + 8003310: f002 f88c bl 800542c + + /* A value is returned for calling semantic consistency with previous + versions. */ + return pdPASS; + 8003314: 2301 movs r3, #1 +} + 8003316: 4618 mov r0, r3 + 8003318: 3710 adds r7, #16 + 800331a: 46bd mov sp, r7 + 800331c: bd80 pop {r7, pc} + 800331e: bf00 nop + 8003320: e000ed04 .word 0xe000ed04 + +08003324 : +/*-----------------------------------------------------------*/ + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + + QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) + { + 8003324: b580 push {r7, lr} + 8003326: b08e sub sp, #56 @ 0x38 + 8003328: af02 add r7, sp, #8 + 800332a: 60f8 str r0, [r7, #12] + 800332c: 60b9 str r1, [r7, #8] + 800332e: 607a str r2, [r7, #4] + 8003330: 603b str r3, [r7, #0] + Queue_t *pxNewQueue; + + configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); + 8003332: 68fb ldr r3, [r7, #12] + 8003334: 2b00 cmp r3, #0 + 8003336: d10b bne.n 8003350 + __asm volatile + 8003338: f04f 0350 mov.w r3, #80 @ 0x50 + 800333c: f383 8811 msr BASEPRI, r3 + 8003340: f3bf 8f6f isb sy + 8003344: f3bf 8f4f dsb sy + 8003348: 62bb str r3, [r7, #40] @ 0x28 +} + 800334a: bf00 nop + 800334c: bf00 nop + 800334e: e7fd b.n 800334c + + /* The StaticQueue_t structure and the queue storage area must be + supplied. */ + configASSERT( pxStaticQueue != NULL ); + 8003350: 683b ldr r3, [r7, #0] + 8003352: 2b00 cmp r3, #0 + 8003354: d10b bne.n 800336e + __asm volatile + 8003356: f04f 0350 mov.w r3, #80 @ 0x50 + 800335a: f383 8811 msr BASEPRI, r3 + 800335e: f3bf 8f6f isb sy + 8003362: f3bf 8f4f dsb sy + 8003366: 627b str r3, [r7, #36] @ 0x24 +} + 8003368: bf00 nop + 800336a: bf00 nop + 800336c: e7fd b.n 800336a + + /* A queue storage area should be provided if the item size is not 0, and + should not be provided if the item size is 0. */ + configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) ); + 800336e: 687b ldr r3, [r7, #4] + 8003370: 2b00 cmp r3, #0 + 8003372: d002 beq.n 800337a + 8003374: 68bb ldr r3, [r7, #8] + 8003376: 2b00 cmp r3, #0 + 8003378: d001 beq.n 800337e + 800337a: 2301 movs r3, #1 + 800337c: e000 b.n 8003380 + 800337e: 2300 movs r3, #0 + 8003380: 2b00 cmp r3, #0 + 8003382: d10b bne.n 800339c + __asm volatile + 8003384: f04f 0350 mov.w r3, #80 @ 0x50 + 8003388: f383 8811 msr BASEPRI, r3 + 800338c: f3bf 8f6f isb sy + 8003390: f3bf 8f4f dsb sy + 8003394: 623b str r3, [r7, #32] +} + 8003396: bf00 nop + 8003398: bf00 nop + 800339a: e7fd b.n 8003398 + configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ); + 800339c: 687b ldr r3, [r7, #4] + 800339e: 2b00 cmp r3, #0 + 80033a0: d102 bne.n 80033a8 + 80033a2: 68bb ldr r3, [r7, #8] + 80033a4: 2b00 cmp r3, #0 + 80033a6: d101 bne.n 80033ac + 80033a8: 2301 movs r3, #1 + 80033aa: e000 b.n 80033ae + 80033ac: 2300 movs r3, #0 + 80033ae: 2b00 cmp r3, #0 + 80033b0: d10b bne.n 80033ca + __asm volatile + 80033b2: f04f 0350 mov.w r3, #80 @ 0x50 + 80033b6: f383 8811 msr BASEPRI, r3 + 80033ba: f3bf 8f6f isb sy + 80033be: f3bf 8f4f dsb sy + 80033c2: 61fb str r3, [r7, #28] +} + 80033c4: bf00 nop + 80033c6: bf00 nop + 80033c8: e7fd b.n 80033c6 + #if( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + variable of type StaticQueue_t or StaticSemaphore_t equals the size of + the real queue and semaphore structures. */ + volatile size_t xSize = sizeof( StaticQueue_t ); + 80033ca: 2350 movs r3, #80 @ 0x50 + 80033cc: 617b str r3, [r7, #20] + configASSERT( xSize == sizeof( Queue_t ) ); + 80033ce: 697b ldr r3, [r7, #20] + 80033d0: 2b50 cmp r3, #80 @ 0x50 + 80033d2: d00b beq.n 80033ec + __asm volatile + 80033d4: f04f 0350 mov.w r3, #80 @ 0x50 + 80033d8: f383 8811 msr BASEPRI, r3 + 80033dc: f3bf 8f6f isb sy + 80033e0: f3bf 8f4f dsb sy + 80033e4: 61bb str r3, [r7, #24] +} + 80033e6: bf00 nop + 80033e8: bf00 nop + 80033ea: e7fd b.n 80033e8 + ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ + 80033ec: 697b ldr r3, [r7, #20] + #endif /* configASSERT_DEFINED */ + + /* The address of a statically allocated queue was passed in, use it. + The address of a statically allocated storage area was also passed in + but is already set. */ + pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ + 80033ee: 683b ldr r3, [r7, #0] + 80033f0: 62fb str r3, [r7, #44] @ 0x2c + + if( pxNewQueue != NULL ) + 80033f2: 6afb ldr r3, [r7, #44] @ 0x2c + 80033f4: 2b00 cmp r3, #0 + 80033f6: d00d beq.n 8003414 + #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* Queues can be allocated wither statically or dynamically, so + note this queue was allocated statically in case the queue is + later deleted. */ + pxNewQueue->ucStaticallyAllocated = pdTRUE; + 80033f8: 6afb ldr r3, [r7, #44] @ 0x2c + 80033fa: 2201 movs r2, #1 + 80033fc: f883 2046 strb.w r2, [r3, #70] @ 0x46 + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + + prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); + 8003400: f897 2038 ldrb.w r2, [r7, #56] @ 0x38 + 8003404: 6afb ldr r3, [r7, #44] @ 0x2c + 8003406: 9300 str r3, [sp, #0] + 8003408: 4613 mov r3, r2 + 800340a: 687a ldr r2, [r7, #4] + 800340c: 68b9 ldr r1, [r7, #8] + 800340e: 68f8 ldr r0, [r7, #12] + 8003410: f000 f805 bl 800341e + { + traceQUEUE_CREATE_FAILED( ucQueueType ); + mtCOVERAGE_TEST_MARKER(); + } + + return pxNewQueue; + 8003414: 6afb ldr r3, [r7, #44] @ 0x2c + } + 8003416: 4618 mov r0, r3 + 8003418: 3730 adds r7, #48 @ 0x30 + 800341a: 46bd mov sp, r7 + 800341c: bd80 pop {r7, pc} + +0800341e : + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) +{ + 800341e: b580 push {r7, lr} + 8003420: b084 sub sp, #16 + 8003422: af00 add r7, sp, #0 + 8003424: 60f8 str r0, [r7, #12] + 8003426: 60b9 str r1, [r7, #8] + 8003428: 607a str r2, [r7, #4] + 800342a: 70fb strb r3, [r7, #3] + /* Remove compiler warnings about unused parameters should + configUSE_TRACE_FACILITY not be set to 1. */ + ( void ) ucQueueType; + + if( uxItemSize == ( UBaseType_t ) 0 ) + 800342c: 68bb ldr r3, [r7, #8] + 800342e: 2b00 cmp r3, #0 + 8003430: d103 bne.n 800343a + { + /* No RAM was allocated for the queue storage area, but PC head cannot + be set to NULL because NULL is used as a key to say the queue is used as + a mutex. Therefore just set pcHead to point to the queue as a benign + value that is known to be within the memory map. */ + pxNewQueue->pcHead = ( int8_t * ) pxNewQueue; + 8003432: 69bb ldr r3, [r7, #24] + 8003434: 69ba ldr r2, [r7, #24] + 8003436: 601a str r2, [r3, #0] + 8003438: e002 b.n 8003440 + } + else + { + /* Set the head to the start of the queue storage area. */ + pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage; + 800343a: 69bb ldr r3, [r7, #24] + 800343c: 687a ldr r2, [r7, #4] + 800343e: 601a str r2, [r3, #0] + } + + /* Initialise the queue members as described where the queue type is + defined. */ + pxNewQueue->uxLength = uxQueueLength; + 8003440: 69bb ldr r3, [r7, #24] + 8003442: 68fa ldr r2, [r7, #12] + 8003444: 63da str r2, [r3, #60] @ 0x3c + pxNewQueue->uxItemSize = uxItemSize; + 8003446: 69bb ldr r3, [r7, #24] + 8003448: 68ba ldr r2, [r7, #8] + 800344a: 641a str r2, [r3, #64] @ 0x40 + ( void ) xQueueGenericReset( pxNewQueue, pdTRUE ); + 800344c: 2101 movs r1, #1 + 800344e: 69b8 ldr r0, [r7, #24] + 8003450: f7ff fefe bl 8003250 + + #if ( configUSE_TRACE_FACILITY == 1 ) + { + pxNewQueue->ucQueueType = ucQueueType; + 8003454: 69bb ldr r3, [r7, #24] + 8003456: 78fa ldrb r2, [r7, #3] + 8003458: f883 204c strb.w r2, [r3, #76] @ 0x4c + pxNewQueue->pxQueueSetContainer = NULL; + } + #endif /* configUSE_QUEUE_SETS */ + + traceQUEUE_CREATE( pxNewQueue ); +} + 800345c: bf00 nop + 800345e: 3710 adds r7, #16 + 8003460: 46bd mov sp, r7 + 8003462: bd80 pop {r7, pc} + +08003464 : + +#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) +{ + 8003464: b580 push {r7, lr} + 8003466: b08e sub sp, #56 @ 0x38 + 8003468: af00 add r7, sp, #0 + 800346a: 60f8 str r0, [r7, #12] + 800346c: 60b9 str r1, [r7, #8] + 800346e: 607a str r2, [r7, #4] + 8003470: 603b str r3, [r7, #0] +BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired; + 8003472: 2300 movs r3, #0 + 8003474: 637b str r3, [r7, #52] @ 0x34 +TimeOut_t xTimeOut; +Queue_t * const pxQueue = xQueue; + 8003476: 68fb ldr r3, [r7, #12] + 8003478: 633b str r3, [r7, #48] @ 0x30 + + configASSERT( pxQueue ); + 800347a: 6b3b ldr r3, [r7, #48] @ 0x30 + 800347c: 2b00 cmp r3, #0 + 800347e: d10b bne.n 8003498 + __asm volatile + 8003480: f04f 0350 mov.w r3, #80 @ 0x50 + 8003484: f383 8811 msr BASEPRI, r3 + 8003488: f3bf 8f6f isb sy + 800348c: f3bf 8f4f dsb sy + 8003490: 62bb str r3, [r7, #40] @ 0x28 +} + 8003492: bf00 nop + 8003494: bf00 nop + 8003496: e7fd b.n 8003494 + configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + 8003498: 68bb ldr r3, [r7, #8] + 800349a: 2b00 cmp r3, #0 + 800349c: d103 bne.n 80034a6 + 800349e: 6b3b ldr r3, [r7, #48] @ 0x30 + 80034a0: 6c1b ldr r3, [r3, #64] @ 0x40 + 80034a2: 2b00 cmp r3, #0 + 80034a4: d101 bne.n 80034aa + 80034a6: 2301 movs r3, #1 + 80034a8: e000 b.n 80034ac + 80034aa: 2300 movs r3, #0 + 80034ac: 2b00 cmp r3, #0 + 80034ae: d10b bne.n 80034c8 + __asm volatile + 80034b0: f04f 0350 mov.w r3, #80 @ 0x50 + 80034b4: f383 8811 msr BASEPRI, r3 + 80034b8: f3bf 8f6f isb sy + 80034bc: f3bf 8f4f dsb sy + 80034c0: 627b str r3, [r7, #36] @ 0x24 +} + 80034c2: bf00 nop + 80034c4: bf00 nop + 80034c6: e7fd b.n 80034c4 + configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); + 80034c8: 683b ldr r3, [r7, #0] + 80034ca: 2b02 cmp r3, #2 + 80034cc: d103 bne.n 80034d6 + 80034ce: 6b3b ldr r3, [r7, #48] @ 0x30 + 80034d0: 6bdb ldr r3, [r3, #60] @ 0x3c + 80034d2: 2b01 cmp r3, #1 + 80034d4: d101 bne.n 80034da + 80034d6: 2301 movs r3, #1 + 80034d8: e000 b.n 80034dc + 80034da: 2300 movs r3, #0 + 80034dc: 2b00 cmp r3, #0 + 80034de: d10b bne.n 80034f8 + __asm volatile + 80034e0: f04f 0350 mov.w r3, #80 @ 0x50 + 80034e4: f383 8811 msr BASEPRI, r3 + 80034e8: f3bf 8f6f isb sy + 80034ec: f3bf 8f4f dsb sy + 80034f0: 623b str r3, [r7, #32] +} + 80034f2: bf00 nop + 80034f4: bf00 nop + 80034f6: e7fd b.n 80034f4 + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + 80034f8: f001 f9fc bl 80048f4 + 80034fc: 4603 mov r3, r0 + 80034fe: 2b00 cmp r3, #0 + 8003500: d102 bne.n 8003508 + 8003502: 687b ldr r3, [r7, #4] + 8003504: 2b00 cmp r3, #0 + 8003506: d101 bne.n 800350c + 8003508: 2301 movs r3, #1 + 800350a: e000 b.n 800350e + 800350c: 2300 movs r3, #0 + 800350e: 2b00 cmp r3, #0 + 8003510: d10b bne.n 800352a + __asm volatile + 8003512: f04f 0350 mov.w r3, #80 @ 0x50 + 8003516: f383 8811 msr BASEPRI, r3 + 800351a: f3bf 8f6f isb sy + 800351e: f3bf 8f4f dsb sy + 8003522: 61fb str r3, [r7, #28] +} + 8003524: bf00 nop + 8003526: bf00 nop + 8003528: e7fd b.n 8003526 + /*lint -save -e904 This function relaxes the coding standard somewhat to + allow return statements within the function itself. This is done in the + interest of execution time efficiency. */ + for( ;; ) + { + taskENTER_CRITICAL(); + 800352a: f001 ff4d bl 80053c8 + { + /* Is there room on the queue now? The running task must be the + highest priority task wanting to access the queue. If the head item + in the queue is to be overwritten then it does not matter if the + queue is full. */ + if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) + 800352e: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003530: 6b9a ldr r2, [r3, #56] @ 0x38 + 8003532: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003534: 6bdb ldr r3, [r3, #60] @ 0x3c + 8003536: 429a cmp r2, r3 + 8003538: d302 bcc.n 8003540 + 800353a: 683b ldr r3, [r7, #0] + 800353c: 2b02 cmp r3, #2 + 800353e: d129 bne.n 8003594 + } + } + } + #else /* configUSE_QUEUE_SETS */ + { + xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); + 8003540: 683a ldr r2, [r7, #0] + 8003542: 68b9 ldr r1, [r7, #8] + 8003544: 6b38 ldr r0, [r7, #48] @ 0x30 + 8003546: f000 fa0f bl 8003968 + 800354a: 62f8 str r0, [r7, #44] @ 0x2c + + /* If there was a task waiting for data to arrive on the + queue then unblock it now. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + 800354c: 6b3b ldr r3, [r7, #48] @ 0x30 + 800354e: 6a5b ldr r3, [r3, #36] @ 0x24 + 8003550: 2b00 cmp r3, #0 + 8003552: d010 beq.n 8003576 + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + 8003554: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003556: 3324 adds r3, #36 @ 0x24 + 8003558: 4618 mov r0, r3 + 800355a: f001 f805 bl 8004568 + 800355e: 4603 mov r3, r0 + 8003560: 2b00 cmp r3, #0 + 8003562: d013 beq.n 800358c + { + /* The unblocked task has a priority higher than + our own so yield immediately. Yes it is ok to do + this from within the critical section - the kernel + takes care of that. */ + queueYIELD_IF_USING_PREEMPTION(); + 8003564: 4b3f ldr r3, [pc, #252] @ (8003664 ) + 8003566: f04f 5280 mov.w r2, #268435456 @ 0x10000000 + 800356a: 601a str r2, [r3, #0] + 800356c: f3bf 8f4f dsb sy + 8003570: f3bf 8f6f isb sy + 8003574: e00a b.n 800358c + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( xYieldRequired != pdFALSE ) + 8003576: 6afb ldr r3, [r7, #44] @ 0x2c + 8003578: 2b00 cmp r3, #0 + 800357a: d007 beq.n 800358c + { + /* This path is a special case that will only get + executed if the task was holding multiple mutexes and + the mutexes were given back in an order that is + different to that in which they were taken. */ + queueYIELD_IF_USING_PREEMPTION(); + 800357c: 4b39 ldr r3, [pc, #228] @ (8003664 ) + 800357e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 + 8003582: 601a str r2, [r3, #0] + 8003584: f3bf 8f4f dsb sy + 8003588: f3bf 8f6f isb sy + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_QUEUE_SETS */ + + taskEXIT_CRITICAL(); + 800358c: f001 ff4e bl 800542c + return pdPASS; + 8003590: 2301 movs r3, #1 + 8003592: e063 b.n 800365c + } + else + { + if( xTicksToWait == ( TickType_t ) 0 ) + 8003594: 687b ldr r3, [r7, #4] + 8003596: 2b00 cmp r3, #0 + 8003598: d103 bne.n 80035a2 + { + /* The queue was full and no block time is specified (or + the block time has expired) so leave now. */ + taskEXIT_CRITICAL(); + 800359a: f001 ff47 bl 800542c + + /* Return to the original privilege level before exiting + the function. */ + traceQUEUE_SEND_FAILED( pxQueue ); + return errQUEUE_FULL; + 800359e: 2300 movs r3, #0 + 80035a0: e05c b.n 800365c + } + else if( xEntryTimeSet == pdFALSE ) + 80035a2: 6b7b ldr r3, [r7, #52] @ 0x34 + 80035a4: 2b00 cmp r3, #0 + 80035a6: d106 bne.n 80035b6 + { + /* The queue was full and a block time was specified so + configure the timeout structure. */ + vTaskInternalSetTimeOutState( &xTimeOut ); + 80035a8: f107 0314 add.w r3, r7, #20 + 80035ac: 4618 mov r0, r3 + 80035ae: f001 f83f bl 8004630 + xEntryTimeSet = pdTRUE; + 80035b2: 2301 movs r3, #1 + 80035b4: 637b str r3, [r7, #52] @ 0x34 + /* Entry time was already set. */ + mtCOVERAGE_TEST_MARKER(); + } + } + } + taskEXIT_CRITICAL(); + 80035b6: f001 ff39 bl 800542c + + /* Interrupts and other tasks can send to and receive from the queue + now the critical section has been exited. */ + + vTaskSuspendAll(); + 80035ba: f000 fda7 bl 800410c + prvLockQueue( pxQueue ); + 80035be: f001 ff03 bl 80053c8 + 80035c2: 6b3b ldr r3, [r7, #48] @ 0x30 + 80035c4: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 + 80035c8: b25b sxtb r3, r3 + 80035ca: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 80035ce: d103 bne.n 80035d8 + 80035d0: 6b3b ldr r3, [r7, #48] @ 0x30 + 80035d2: 2200 movs r2, #0 + 80035d4: f883 2044 strb.w r2, [r3, #68] @ 0x44 + 80035d8: 6b3b ldr r3, [r7, #48] @ 0x30 + 80035da: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 + 80035de: b25b sxtb r3, r3 + 80035e0: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 80035e4: d103 bne.n 80035ee + 80035e6: 6b3b ldr r3, [r7, #48] @ 0x30 + 80035e8: 2200 movs r2, #0 + 80035ea: f883 2045 strb.w r2, [r3, #69] @ 0x45 + 80035ee: f001 ff1d bl 800542c + + /* Update the timeout state to see if it has expired yet. */ + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + 80035f2: 1d3a adds r2, r7, #4 + 80035f4: f107 0314 add.w r3, r7, #20 + 80035f8: 4611 mov r1, r2 + 80035fa: 4618 mov r0, r3 + 80035fc: f001 f82e bl 800465c + 8003600: 4603 mov r3, r0 + 8003602: 2b00 cmp r3, #0 + 8003604: d124 bne.n 8003650 + { + if( prvIsQueueFull( pxQueue ) != pdFALSE ) + 8003606: 6b38 ldr r0, [r7, #48] @ 0x30 + 8003608: f000 faa6 bl 8003b58 + 800360c: 4603 mov r3, r0 + 800360e: 2b00 cmp r3, #0 + 8003610: d018 beq.n 8003644 + { + traceBLOCKING_ON_QUEUE_SEND( pxQueue ); + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); + 8003612: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003614: 3310 adds r3, #16 + 8003616: 687a ldr r2, [r7, #4] + 8003618: 4611 mov r1, r2 + 800361a: 4618 mov r0, r3 + 800361c: f000 ff52 bl 80044c4 + /* Unlocking the queue means queue events can effect the + event list. It is possible that interrupts occurring now + remove this task from the event list again - but as the + scheduler is suspended the task will go onto the pending + ready last instead of the actual ready list. */ + prvUnlockQueue( pxQueue ); + 8003620: 6b38 ldr r0, [r7, #48] @ 0x30 + 8003622: f000 fa31 bl 8003a88 + /* Resuming the scheduler will move tasks from the pending + ready list into the ready list - so it is feasible that this + task is already in a ready list before it yields - in which + case the yield will not cause a context switch unless there + is also a higher priority task in the pending ready list. */ + if( xTaskResumeAll() == pdFALSE ) + 8003626: f000 fd7f bl 8004128 + 800362a: 4603 mov r3, r0 + 800362c: 2b00 cmp r3, #0 + 800362e: f47f af7c bne.w 800352a + { + portYIELD_WITHIN_API(); + 8003632: 4b0c ldr r3, [pc, #48] @ (8003664 ) + 8003634: f04f 5280 mov.w r2, #268435456 @ 0x10000000 + 8003638: 601a str r2, [r3, #0] + 800363a: f3bf 8f4f dsb sy + 800363e: f3bf 8f6f isb sy + 8003642: e772 b.n 800352a + } + } + else + { + /* Try again. */ + prvUnlockQueue( pxQueue ); + 8003644: 6b38 ldr r0, [r7, #48] @ 0x30 + 8003646: f000 fa1f bl 8003a88 + ( void ) xTaskResumeAll(); + 800364a: f000 fd6d bl 8004128 + 800364e: e76c b.n 800352a + } + } + else + { + /* The timeout has expired. */ + prvUnlockQueue( pxQueue ); + 8003650: 6b38 ldr r0, [r7, #48] @ 0x30 + 8003652: f000 fa19 bl 8003a88 + ( void ) xTaskResumeAll(); + 8003656: f000 fd67 bl 8004128 + + traceQUEUE_SEND_FAILED( pxQueue ); + return errQUEUE_FULL; + 800365a: 2300 movs r3, #0 + } + } /*lint -restore */ +} + 800365c: 4618 mov r0, r3 + 800365e: 3738 adds r7, #56 @ 0x38 + 8003660: 46bd mov sp, r7 + 8003662: bd80 pop {r7, pc} + 8003664: e000ed04 .word 0xe000ed04 + +08003668 : +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) +{ + 8003668: b580 push {r7, lr} + 800366a: b090 sub sp, #64 @ 0x40 + 800366c: af00 add r7, sp, #0 + 800366e: 60f8 str r0, [r7, #12] + 8003670: 60b9 str r1, [r7, #8] + 8003672: 607a str r2, [r7, #4] + 8003674: 603b str r3, [r7, #0] +BaseType_t xReturn; +UBaseType_t uxSavedInterruptStatus; +Queue_t * const pxQueue = xQueue; + 8003676: 68fb ldr r3, [r7, #12] + 8003678: 63bb str r3, [r7, #56] @ 0x38 + + configASSERT( pxQueue ); + 800367a: 6bbb ldr r3, [r7, #56] @ 0x38 + 800367c: 2b00 cmp r3, #0 + 800367e: d10b bne.n 8003698 + __asm volatile + 8003680: f04f 0350 mov.w r3, #80 @ 0x50 + 8003684: f383 8811 msr BASEPRI, r3 + 8003688: f3bf 8f6f isb sy + 800368c: f3bf 8f4f dsb sy + 8003690: 62bb str r3, [r7, #40] @ 0x28 +} + 8003692: bf00 nop + 8003694: bf00 nop + 8003696: e7fd b.n 8003694 + configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + 8003698: 68bb ldr r3, [r7, #8] + 800369a: 2b00 cmp r3, #0 + 800369c: d103 bne.n 80036a6 + 800369e: 6bbb ldr r3, [r7, #56] @ 0x38 + 80036a0: 6c1b ldr r3, [r3, #64] @ 0x40 + 80036a2: 2b00 cmp r3, #0 + 80036a4: d101 bne.n 80036aa + 80036a6: 2301 movs r3, #1 + 80036a8: e000 b.n 80036ac + 80036aa: 2300 movs r3, #0 + 80036ac: 2b00 cmp r3, #0 + 80036ae: d10b bne.n 80036c8 + __asm volatile + 80036b0: f04f 0350 mov.w r3, #80 @ 0x50 + 80036b4: f383 8811 msr BASEPRI, r3 + 80036b8: f3bf 8f6f isb sy + 80036bc: f3bf 8f4f dsb sy + 80036c0: 627b str r3, [r7, #36] @ 0x24 +} + 80036c2: bf00 nop + 80036c4: bf00 nop + 80036c6: e7fd b.n 80036c4 + configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); + 80036c8: 683b ldr r3, [r7, #0] + 80036ca: 2b02 cmp r3, #2 + 80036cc: d103 bne.n 80036d6 + 80036ce: 6bbb ldr r3, [r7, #56] @ 0x38 + 80036d0: 6bdb ldr r3, [r3, #60] @ 0x3c + 80036d2: 2b01 cmp r3, #1 + 80036d4: d101 bne.n 80036da + 80036d6: 2301 movs r3, #1 + 80036d8: e000 b.n 80036dc + 80036da: 2300 movs r3, #0 + 80036dc: 2b00 cmp r3, #0 + 80036de: d10b bne.n 80036f8 + __asm volatile + 80036e0: f04f 0350 mov.w r3, #80 @ 0x50 + 80036e4: f383 8811 msr BASEPRI, r3 + 80036e8: f3bf 8f6f isb sy + 80036ec: f3bf 8f4f dsb sy + 80036f0: 623b str r3, [r7, #32] +} + 80036f2: bf00 nop + 80036f4: bf00 nop + 80036f6: e7fd b.n 80036f4 + that have been assigned a priority at or (logically) below the maximum + system call interrupt priority. FreeRTOS maintains a separate interrupt + safe API to ensure interrupt entry is as fast and as simple as possible. + More information (albeit Cortex-M specific) is provided on the following + link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + 80036f8: f001 ff46 bl 8005588 + __asm volatile + 80036fc: f3ef 8211 mrs r2, BASEPRI + 8003700: f04f 0350 mov.w r3, #80 @ 0x50 + 8003704: f383 8811 msr BASEPRI, r3 + 8003708: f3bf 8f6f isb sy + 800370c: f3bf 8f4f dsb sy + 8003710: 61fa str r2, [r7, #28] + 8003712: 61bb str r3, [r7, #24] + return ulOriginalBASEPRI; + 8003714: 69fb ldr r3, [r7, #28] + /* Similar to xQueueGenericSend, except without blocking if there is no room + in the queue. Also don't directly wake a task that was blocked on a queue + read, instead return a flag to say whether a context switch is required or + not (i.e. has a task with a higher priority than us been woken by this + post). */ + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + 8003716: 637b str r3, [r7, #52] @ 0x34 + { + if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) + 8003718: 6bbb ldr r3, [r7, #56] @ 0x38 + 800371a: 6b9a ldr r2, [r3, #56] @ 0x38 + 800371c: 6bbb ldr r3, [r7, #56] @ 0x38 + 800371e: 6bdb ldr r3, [r3, #60] @ 0x3c + 8003720: 429a cmp r2, r3 + 8003722: d302 bcc.n 800372a + 8003724: 683b ldr r3, [r7, #0] + 8003726: 2b02 cmp r3, #2 + 8003728: d12f bne.n 800378a + { + const int8_t cTxLock = pxQueue->cTxLock; + 800372a: 6bbb ldr r3, [r7, #56] @ 0x38 + 800372c: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 + 8003730: f887 3033 strb.w r3, [r7, #51] @ 0x33 + const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; + 8003734: 6bbb ldr r3, [r7, #56] @ 0x38 + 8003736: 6b9b ldr r3, [r3, #56] @ 0x38 + 8003738: 62fb str r3, [r7, #44] @ 0x2c + /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a + semaphore or mutex. That means prvCopyDataToQueue() cannot result + in a task disinheriting a priority and prvCopyDataToQueue() can be + called here even though the disinherit function does not check if + the scheduler is suspended before accessing the ready lists. */ + ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); + 800373a: 683a ldr r2, [r7, #0] + 800373c: 68b9 ldr r1, [r7, #8] + 800373e: 6bb8 ldr r0, [r7, #56] @ 0x38 + 8003740: f000 f912 bl 8003968 + + /* The event list is not altered if the queue is locked. This will + be done when the queue is unlocked later. */ + if( cTxLock == queueUNLOCKED ) + 8003744: f997 3033 ldrsb.w r3, [r7, #51] @ 0x33 + 8003748: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 800374c: d112 bne.n 8003774 + } + } + } + #else /* configUSE_QUEUE_SETS */ + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + 800374e: 6bbb ldr r3, [r7, #56] @ 0x38 + 8003750: 6a5b ldr r3, [r3, #36] @ 0x24 + 8003752: 2b00 cmp r3, #0 + 8003754: d016 beq.n 8003784 + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + 8003756: 6bbb ldr r3, [r7, #56] @ 0x38 + 8003758: 3324 adds r3, #36 @ 0x24 + 800375a: 4618 mov r0, r3 + 800375c: f000 ff04 bl 8004568 + 8003760: 4603 mov r3, r0 + 8003762: 2b00 cmp r3, #0 + 8003764: d00e beq.n 8003784 + { + /* The task waiting has a higher priority so record that a + context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + 8003766: 687b ldr r3, [r7, #4] + 8003768: 2b00 cmp r3, #0 + 800376a: d00b beq.n 8003784 + { + *pxHigherPriorityTaskWoken = pdTRUE; + 800376c: 687b ldr r3, [r7, #4] + 800376e: 2201 movs r2, #1 + 8003770: 601a str r2, [r3, #0] + 8003772: e007 b.n 8003784 + } + else + { + /* Increment the lock count so the task that unlocks the queue + knows that data was posted while it was locked. */ + pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 ); + 8003774: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 + 8003778: 3301 adds r3, #1 + 800377a: b2db uxtb r3, r3 + 800377c: b25a sxtb r2, r3 + 800377e: 6bbb ldr r3, [r7, #56] @ 0x38 + 8003780: f883 2045 strb.w r2, [r3, #69] @ 0x45 + } + + xReturn = pdPASS; + 8003784: 2301 movs r3, #1 + 8003786: 63fb str r3, [r7, #60] @ 0x3c + { + 8003788: e001 b.n 800378e + } + else + { + traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); + xReturn = errQUEUE_FULL; + 800378a: 2300 movs r3, #0 + 800378c: 63fb str r3, [r7, #60] @ 0x3c + 800378e: 6b7b ldr r3, [r7, #52] @ 0x34 + 8003790: 617b str r3, [r7, #20] + __asm volatile + 8003792: 697b ldr r3, [r7, #20] + 8003794: f383 8811 msr BASEPRI, r3 +} + 8003798: bf00 nop + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; + 800379a: 6bfb ldr r3, [r7, #60] @ 0x3c +} + 800379c: 4618 mov r0, r3 + 800379e: 3740 adds r7, #64 @ 0x40 + 80037a0: 46bd mov sp, r7 + 80037a2: bd80 pop {r7, pc} + +080037a4 : + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) +{ + 80037a4: b580 push {r7, lr} + 80037a6: b08c sub sp, #48 @ 0x30 + 80037a8: af00 add r7, sp, #0 + 80037aa: 60f8 str r0, [r7, #12] + 80037ac: 60b9 str r1, [r7, #8] + 80037ae: 607a str r2, [r7, #4] +BaseType_t xEntryTimeSet = pdFALSE; + 80037b0: 2300 movs r3, #0 + 80037b2: 62fb str r3, [r7, #44] @ 0x2c +TimeOut_t xTimeOut; +Queue_t * const pxQueue = xQueue; + 80037b4: 68fb ldr r3, [r7, #12] + 80037b6: 62bb str r3, [r7, #40] @ 0x28 + + /* Check the pointer is not NULL. */ + configASSERT( ( pxQueue ) ); + 80037b8: 6abb ldr r3, [r7, #40] @ 0x28 + 80037ba: 2b00 cmp r3, #0 + 80037bc: d10b bne.n 80037d6 + __asm volatile + 80037be: f04f 0350 mov.w r3, #80 @ 0x50 + 80037c2: f383 8811 msr BASEPRI, r3 + 80037c6: f3bf 8f6f isb sy + 80037ca: f3bf 8f4f dsb sy + 80037ce: 623b str r3, [r7, #32] +} + 80037d0: bf00 nop + 80037d2: bf00 nop + 80037d4: e7fd b.n 80037d2 + + /* The buffer into which data is received can only be NULL if the data size + is zero (so no data is copied into the buffer. */ + configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); + 80037d6: 68bb ldr r3, [r7, #8] + 80037d8: 2b00 cmp r3, #0 + 80037da: d103 bne.n 80037e4 + 80037dc: 6abb ldr r3, [r7, #40] @ 0x28 + 80037de: 6c1b ldr r3, [r3, #64] @ 0x40 + 80037e0: 2b00 cmp r3, #0 + 80037e2: d101 bne.n 80037e8 + 80037e4: 2301 movs r3, #1 + 80037e6: e000 b.n 80037ea + 80037e8: 2300 movs r3, #0 + 80037ea: 2b00 cmp r3, #0 + 80037ec: d10b bne.n 8003806 + __asm volatile + 80037ee: f04f 0350 mov.w r3, #80 @ 0x50 + 80037f2: f383 8811 msr BASEPRI, r3 + 80037f6: f3bf 8f6f isb sy + 80037fa: f3bf 8f4f dsb sy + 80037fe: 61fb str r3, [r7, #28] +} + 8003800: bf00 nop + 8003802: bf00 nop + 8003804: e7fd b.n 8003802 + + /* Cannot block if the scheduler is suspended. */ + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + 8003806: f001 f875 bl 80048f4 + 800380a: 4603 mov r3, r0 + 800380c: 2b00 cmp r3, #0 + 800380e: d102 bne.n 8003816 + 8003810: 687b ldr r3, [r7, #4] + 8003812: 2b00 cmp r3, #0 + 8003814: d101 bne.n 800381a + 8003816: 2301 movs r3, #1 + 8003818: e000 b.n 800381c + 800381a: 2300 movs r3, #0 + 800381c: 2b00 cmp r3, #0 + 800381e: d10b bne.n 8003838 + __asm volatile + 8003820: f04f 0350 mov.w r3, #80 @ 0x50 + 8003824: f383 8811 msr BASEPRI, r3 + 8003828: f3bf 8f6f isb sy + 800382c: f3bf 8f4f dsb sy + 8003830: 61bb str r3, [r7, #24] +} + 8003832: bf00 nop + 8003834: bf00 nop + 8003836: e7fd b.n 8003834 + /*lint -save -e904 This function relaxes the coding standard somewhat to + allow return statements within the function itself. This is done in the + interest of execution time efficiency. */ + for( ;; ) + { + taskENTER_CRITICAL(); + 8003838: f001 fdc6 bl 80053c8 + { + const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; + 800383c: 6abb ldr r3, [r7, #40] @ 0x28 + 800383e: 6b9b ldr r3, [r3, #56] @ 0x38 + 8003840: 627b str r3, [r7, #36] @ 0x24 + + /* Is there data in the queue now? To be running the calling task + must be the highest priority task wanting to access the queue. */ + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + 8003842: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003844: 2b00 cmp r3, #0 + 8003846: d01f beq.n 8003888 + { + /* Data available, remove one item. */ + prvCopyDataFromQueue( pxQueue, pvBuffer ); + 8003848: 68b9 ldr r1, [r7, #8] + 800384a: 6ab8 ldr r0, [r7, #40] @ 0x28 + 800384c: f000 f8f6 bl 8003a3c + traceQUEUE_RECEIVE( pxQueue ); + pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; + 8003850: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003852: 1e5a subs r2, r3, #1 + 8003854: 6abb ldr r3, [r7, #40] @ 0x28 + 8003856: 639a str r2, [r3, #56] @ 0x38 + + /* There is now space in the queue, were any tasks waiting to + post to the queue? If so, unblock the highest priority waiting + task. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + 8003858: 6abb ldr r3, [r7, #40] @ 0x28 + 800385a: 691b ldr r3, [r3, #16] + 800385c: 2b00 cmp r3, #0 + 800385e: d00f beq.n 8003880 + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + 8003860: 6abb ldr r3, [r7, #40] @ 0x28 + 8003862: 3310 adds r3, #16 + 8003864: 4618 mov r0, r3 + 8003866: f000 fe7f bl 8004568 + 800386a: 4603 mov r3, r0 + 800386c: 2b00 cmp r3, #0 + 800386e: d007 beq.n 8003880 + { + queueYIELD_IF_USING_PREEMPTION(); + 8003870: 4b3c ldr r3, [pc, #240] @ (8003964 ) + 8003872: f04f 5280 mov.w r2, #268435456 @ 0x10000000 + 8003876: 601a str r2, [r3, #0] + 8003878: f3bf 8f4f dsb sy + 800387c: f3bf 8f6f isb sy + else + { + mtCOVERAGE_TEST_MARKER(); + } + + taskEXIT_CRITICAL(); + 8003880: f001 fdd4 bl 800542c + return pdPASS; + 8003884: 2301 movs r3, #1 + 8003886: e069 b.n 800395c + } + else + { + if( xTicksToWait == ( TickType_t ) 0 ) + 8003888: 687b ldr r3, [r7, #4] + 800388a: 2b00 cmp r3, #0 + 800388c: d103 bne.n 8003896 + { + /* The queue was empty and no block time is specified (or + the block time has expired) so leave now. */ + taskEXIT_CRITICAL(); + 800388e: f001 fdcd bl 800542c + traceQUEUE_RECEIVE_FAILED( pxQueue ); + return errQUEUE_EMPTY; + 8003892: 2300 movs r3, #0 + 8003894: e062 b.n 800395c + } + else if( xEntryTimeSet == pdFALSE ) + 8003896: 6afb ldr r3, [r7, #44] @ 0x2c + 8003898: 2b00 cmp r3, #0 + 800389a: d106 bne.n 80038aa + { + /* The queue was empty and a block time was specified so + configure the timeout structure. */ + vTaskInternalSetTimeOutState( &xTimeOut ); + 800389c: f107 0310 add.w r3, r7, #16 + 80038a0: 4618 mov r0, r3 + 80038a2: f000 fec5 bl 8004630 + xEntryTimeSet = pdTRUE; + 80038a6: 2301 movs r3, #1 + 80038a8: 62fb str r3, [r7, #44] @ 0x2c + /* Entry time was already set. */ + mtCOVERAGE_TEST_MARKER(); + } + } + } + taskEXIT_CRITICAL(); + 80038aa: f001 fdbf bl 800542c + + /* Interrupts and other tasks can send to and receive from the queue + now the critical section has been exited. */ + + vTaskSuspendAll(); + 80038ae: f000 fc2d bl 800410c + prvLockQueue( pxQueue ); + 80038b2: f001 fd89 bl 80053c8 + 80038b6: 6abb ldr r3, [r7, #40] @ 0x28 + 80038b8: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 + 80038bc: b25b sxtb r3, r3 + 80038be: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 80038c2: d103 bne.n 80038cc + 80038c4: 6abb ldr r3, [r7, #40] @ 0x28 + 80038c6: 2200 movs r2, #0 + 80038c8: f883 2044 strb.w r2, [r3, #68] @ 0x44 + 80038cc: 6abb ldr r3, [r7, #40] @ 0x28 + 80038ce: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 + 80038d2: b25b sxtb r3, r3 + 80038d4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 80038d8: d103 bne.n 80038e2 + 80038da: 6abb ldr r3, [r7, #40] @ 0x28 + 80038dc: 2200 movs r2, #0 + 80038de: f883 2045 strb.w r2, [r3, #69] @ 0x45 + 80038e2: f001 fda3 bl 800542c + + /* Update the timeout state to see if it has expired yet. */ + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + 80038e6: 1d3a adds r2, r7, #4 + 80038e8: f107 0310 add.w r3, r7, #16 + 80038ec: 4611 mov r1, r2 + 80038ee: 4618 mov r0, r3 + 80038f0: f000 feb4 bl 800465c + 80038f4: 4603 mov r3, r0 + 80038f6: 2b00 cmp r3, #0 + 80038f8: d123 bne.n 8003942 + { + /* The timeout has not expired. If the queue is still empty place + the task on the list of tasks waiting to receive from the queue. */ + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + 80038fa: 6ab8 ldr r0, [r7, #40] @ 0x28 + 80038fc: f000 f916 bl 8003b2c + 8003900: 4603 mov r3, r0 + 8003902: 2b00 cmp r3, #0 + 8003904: d017 beq.n 8003936 + { + traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); + 8003906: 6abb ldr r3, [r7, #40] @ 0x28 + 8003908: 3324 adds r3, #36 @ 0x24 + 800390a: 687a ldr r2, [r7, #4] + 800390c: 4611 mov r1, r2 + 800390e: 4618 mov r0, r3 + 8003910: f000 fdd8 bl 80044c4 + prvUnlockQueue( pxQueue ); + 8003914: 6ab8 ldr r0, [r7, #40] @ 0x28 + 8003916: f000 f8b7 bl 8003a88 + if( xTaskResumeAll() == pdFALSE ) + 800391a: f000 fc05 bl 8004128 + 800391e: 4603 mov r3, r0 + 8003920: 2b00 cmp r3, #0 + 8003922: d189 bne.n 8003838 + { + portYIELD_WITHIN_API(); + 8003924: 4b0f ldr r3, [pc, #60] @ (8003964 ) + 8003926: f04f 5280 mov.w r2, #268435456 @ 0x10000000 + 800392a: 601a str r2, [r3, #0] + 800392c: f3bf 8f4f dsb sy + 8003930: f3bf 8f6f isb sy + 8003934: e780 b.n 8003838 + } + else + { + /* The queue contains data again. Loop back to try and read the + data. */ + prvUnlockQueue( pxQueue ); + 8003936: 6ab8 ldr r0, [r7, #40] @ 0x28 + 8003938: f000 f8a6 bl 8003a88 + ( void ) xTaskResumeAll(); + 800393c: f000 fbf4 bl 8004128 + 8003940: e77a b.n 8003838 + } + else + { + /* Timed out. If there is no data in the queue exit, otherwise loop + back and attempt to read the data. */ + prvUnlockQueue( pxQueue ); + 8003942: 6ab8 ldr r0, [r7, #40] @ 0x28 + 8003944: f000 f8a0 bl 8003a88 + ( void ) xTaskResumeAll(); + 8003948: f000 fbee bl 8004128 + + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + 800394c: 6ab8 ldr r0, [r7, #40] @ 0x28 + 800394e: f000 f8ed bl 8003b2c + 8003952: 4603 mov r3, r0 + 8003954: 2b00 cmp r3, #0 + 8003956: f43f af6f beq.w 8003838 + { + traceQUEUE_RECEIVE_FAILED( pxQueue ); + return errQUEUE_EMPTY; + 800395a: 2300 movs r3, #0 + { + mtCOVERAGE_TEST_MARKER(); + } + } + } /*lint -restore */ +} + 800395c: 4618 mov r0, r3 + 800395e: 3730 adds r7, #48 @ 0x30 + 8003960: 46bd mov sp, r7 + 8003962: bd80 pop {r7, pc} + 8003964: e000ed04 .word 0xe000ed04 + +08003968 : + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) +{ + 8003968: b580 push {r7, lr} + 800396a: b086 sub sp, #24 + 800396c: af00 add r7, sp, #0 + 800396e: 60f8 str r0, [r7, #12] + 8003970: 60b9 str r1, [r7, #8] + 8003972: 607a str r2, [r7, #4] +BaseType_t xReturn = pdFALSE; + 8003974: 2300 movs r3, #0 + 8003976: 617b str r3, [r7, #20] +UBaseType_t uxMessagesWaiting; + + /* This function is called from a critical section. */ + + uxMessagesWaiting = pxQueue->uxMessagesWaiting; + 8003978: 68fb ldr r3, [r7, #12] + 800397a: 6b9b ldr r3, [r3, #56] @ 0x38 + 800397c: 613b str r3, [r7, #16] + + if( pxQueue->uxItemSize == ( UBaseType_t ) 0 ) + 800397e: 68fb ldr r3, [r7, #12] + 8003980: 6c1b ldr r3, [r3, #64] @ 0x40 + 8003982: 2b00 cmp r3, #0 + 8003984: d10d bne.n 80039a2 + { + #if ( configUSE_MUTEXES == 1 ) + { + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + 8003986: 68fb ldr r3, [r7, #12] + 8003988: 681b ldr r3, [r3, #0] + 800398a: 2b00 cmp r3, #0 + 800398c: d14d bne.n 8003a2a + { + /* The mutex is no longer being held. */ + xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder ); + 800398e: 68fb ldr r3, [r7, #12] + 8003990: 689b ldr r3, [r3, #8] + 8003992: 4618 mov r0, r3 + 8003994: f000 ffcc bl 8004930 + 8003998: 6178 str r0, [r7, #20] + pxQueue->u.xSemaphore.xMutexHolder = NULL; + 800399a: 68fb ldr r3, [r7, #12] + 800399c: 2200 movs r2, #0 + 800399e: 609a str r2, [r3, #8] + 80039a0: e043 b.n 8003a2a + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_MUTEXES */ + } + else if( xPosition == queueSEND_TO_BACK ) + 80039a2: 687b ldr r3, [r7, #4] + 80039a4: 2b00 cmp r3, #0 + 80039a6: d119 bne.n 80039dc + { + ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ + 80039a8: 68fb ldr r3, [r7, #12] + 80039aa: 6858 ldr r0, [r3, #4] + 80039ac: 68fb ldr r3, [r7, #12] + 80039ae: 6c1b ldr r3, [r3, #64] @ 0x40 + 80039b0: 461a mov r2, r3 + 80039b2: 68b9 ldr r1, [r7, #8] + 80039b4: f002 f8ae bl 8005b14 + pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ + 80039b8: 68fb ldr r3, [r7, #12] + 80039ba: 685a ldr r2, [r3, #4] + 80039bc: 68fb ldr r3, [r7, #12] + 80039be: 6c1b ldr r3, [r3, #64] @ 0x40 + 80039c0: 441a add r2, r3 + 80039c2: 68fb ldr r3, [r7, #12] + 80039c4: 605a str r2, [r3, #4] + if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ + 80039c6: 68fb ldr r3, [r7, #12] + 80039c8: 685a ldr r2, [r3, #4] + 80039ca: 68fb ldr r3, [r7, #12] + 80039cc: 689b ldr r3, [r3, #8] + 80039ce: 429a cmp r2, r3 + 80039d0: d32b bcc.n 8003a2a + { + pxQueue->pcWriteTo = pxQueue->pcHead; + 80039d2: 68fb ldr r3, [r7, #12] + 80039d4: 681a ldr r2, [r3, #0] + 80039d6: 68fb ldr r3, [r7, #12] + 80039d8: 605a str r2, [r3, #4] + 80039da: e026 b.n 8003a2a + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */ + 80039dc: 68fb ldr r3, [r7, #12] + 80039de: 68d8 ldr r0, [r3, #12] + 80039e0: 68fb ldr r3, [r7, #12] + 80039e2: 6c1b ldr r3, [r3, #64] @ 0x40 + 80039e4: 461a mov r2, r3 + 80039e6: 68b9 ldr r1, [r7, #8] + 80039e8: f002 f894 bl 8005b14 + pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize; + 80039ec: 68fb ldr r3, [r7, #12] + 80039ee: 68da ldr r2, [r3, #12] + 80039f0: 68fb ldr r3, [r7, #12] + 80039f2: 6c1b ldr r3, [r3, #64] @ 0x40 + 80039f4: 425b negs r3, r3 + 80039f6: 441a add r2, r3 + 80039f8: 68fb ldr r3, [r7, #12] + 80039fa: 60da str r2, [r3, #12] + if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ + 80039fc: 68fb ldr r3, [r7, #12] + 80039fe: 68da ldr r2, [r3, #12] + 8003a00: 68fb ldr r3, [r7, #12] + 8003a02: 681b ldr r3, [r3, #0] + 8003a04: 429a cmp r2, r3 + 8003a06: d207 bcs.n 8003a18 + { + pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize ); + 8003a08: 68fb ldr r3, [r7, #12] + 8003a0a: 689a ldr r2, [r3, #8] + 8003a0c: 68fb ldr r3, [r7, #12] + 8003a0e: 6c1b ldr r3, [r3, #64] @ 0x40 + 8003a10: 425b negs r3, r3 + 8003a12: 441a add r2, r3 + 8003a14: 68fb ldr r3, [r7, #12] + 8003a16: 60da str r2, [r3, #12] + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xPosition == queueOVERWRITE ) + 8003a18: 687b ldr r3, [r7, #4] + 8003a1a: 2b02 cmp r3, #2 + 8003a1c: d105 bne.n 8003a2a + { + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + 8003a1e: 693b ldr r3, [r7, #16] + 8003a20: 2b00 cmp r3, #0 + 8003a22: d002 beq.n 8003a2a + { + /* An item is not being added but overwritten, so subtract + one from the recorded number of items in the queue so when + one is added again below the number of recorded items remains + correct. */ + --uxMessagesWaiting; + 8003a24: 693b ldr r3, [r7, #16] + 8003a26: 3b01 subs r3, #1 + 8003a28: 613b str r3, [r7, #16] + { + mtCOVERAGE_TEST_MARKER(); + } + } + + pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; + 8003a2a: 693b ldr r3, [r7, #16] + 8003a2c: 1c5a adds r2, r3, #1 + 8003a2e: 68fb ldr r3, [r7, #12] + 8003a30: 639a str r2, [r3, #56] @ 0x38 + + return xReturn; + 8003a32: 697b ldr r3, [r7, #20] +} + 8003a34: 4618 mov r0, r3 + 8003a36: 3718 adds r7, #24 + 8003a38: 46bd mov sp, r7 + 8003a3a: bd80 pop {r7, pc} + +08003a3c : +/*-----------------------------------------------------------*/ + +static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) +{ + 8003a3c: b580 push {r7, lr} + 8003a3e: b082 sub sp, #8 + 8003a40: af00 add r7, sp, #0 + 8003a42: 6078 str r0, [r7, #4] + 8003a44: 6039 str r1, [r7, #0] + if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) + 8003a46: 687b ldr r3, [r7, #4] + 8003a48: 6c1b ldr r3, [r3, #64] @ 0x40 + 8003a4a: 2b00 cmp r3, #0 + 8003a4c: d018 beq.n 8003a80 + { + pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ + 8003a4e: 687b ldr r3, [r7, #4] + 8003a50: 68da ldr r2, [r3, #12] + 8003a52: 687b ldr r3, [r7, #4] + 8003a54: 6c1b ldr r3, [r3, #64] @ 0x40 + 8003a56: 441a add r2, r3 + 8003a58: 687b ldr r3, [r7, #4] + 8003a5a: 60da str r2, [r3, #12] + if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ + 8003a5c: 687b ldr r3, [r7, #4] + 8003a5e: 68da ldr r2, [r3, #12] + 8003a60: 687b ldr r3, [r7, #4] + 8003a62: 689b ldr r3, [r3, #8] + 8003a64: 429a cmp r2, r3 + 8003a66: d303 bcc.n 8003a70 + { + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; + 8003a68: 687b ldr r3, [r7, #4] + 8003a6a: 681a ldr r2, [r3, #0] + 8003a6c: 687b ldr r3, [r7, #4] + 8003a6e: 60da str r2, [r3, #12] + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ + 8003a70: 687b ldr r3, [r7, #4] + 8003a72: 68d9 ldr r1, [r3, #12] + 8003a74: 687b ldr r3, [r7, #4] + 8003a76: 6c1b ldr r3, [r3, #64] @ 0x40 + 8003a78: 461a mov r2, r3 + 8003a7a: 6838 ldr r0, [r7, #0] + 8003a7c: f002 f84a bl 8005b14 + } +} + 8003a80: bf00 nop + 8003a82: 3708 adds r7, #8 + 8003a84: 46bd mov sp, r7 + 8003a86: bd80 pop {r7, pc} + +08003a88 : +/*-----------------------------------------------------------*/ + +static void prvUnlockQueue( Queue_t * const pxQueue ) +{ + 8003a88: b580 push {r7, lr} + 8003a8a: b084 sub sp, #16 + 8003a8c: af00 add r7, sp, #0 + 8003a8e: 6078 str r0, [r7, #4] + + /* The lock counts contains the number of extra data items placed or + removed from the queue while the queue was locked. When a queue is + locked items can be added or removed, but the event lists cannot be + updated. */ + taskENTER_CRITICAL(); + 8003a90: f001 fc9a bl 80053c8 + { + int8_t cTxLock = pxQueue->cTxLock; + 8003a94: 687b ldr r3, [r7, #4] + 8003a96: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 + 8003a9a: 73fb strb r3, [r7, #15] + + /* See if data was added to the queue while it was locked. */ + while( cTxLock > queueLOCKED_UNMODIFIED ) + 8003a9c: e011 b.n 8003ac2 + } + #else /* configUSE_QUEUE_SETS */ + { + /* Tasks that are removed from the event list will get added to + the pending ready list as the scheduler is still suspended. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + 8003a9e: 687b ldr r3, [r7, #4] + 8003aa0: 6a5b ldr r3, [r3, #36] @ 0x24 + 8003aa2: 2b00 cmp r3, #0 + 8003aa4: d012 beq.n 8003acc + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + 8003aa6: 687b ldr r3, [r7, #4] + 8003aa8: 3324 adds r3, #36 @ 0x24 + 8003aaa: 4618 mov r0, r3 + 8003aac: f000 fd5c bl 8004568 + 8003ab0: 4603 mov r3, r0 + 8003ab2: 2b00 cmp r3, #0 + 8003ab4: d001 beq.n 8003aba + { + /* The task waiting has a higher priority so record that + a context switch is required. */ + vTaskMissedYield(); + 8003ab6: f000 fe35 bl 8004724 + break; + } + } + #endif /* configUSE_QUEUE_SETS */ + + --cTxLock; + 8003aba: 7bfb ldrb r3, [r7, #15] + 8003abc: 3b01 subs r3, #1 + 8003abe: b2db uxtb r3, r3 + 8003ac0: 73fb strb r3, [r7, #15] + while( cTxLock > queueLOCKED_UNMODIFIED ) + 8003ac2: f997 300f ldrsb.w r3, [r7, #15] + 8003ac6: 2b00 cmp r3, #0 + 8003ac8: dce9 bgt.n 8003a9e + 8003aca: e000 b.n 8003ace + break; + 8003acc: bf00 nop + } + + pxQueue->cTxLock = queueUNLOCKED; + 8003ace: 687b ldr r3, [r7, #4] + 8003ad0: 22ff movs r2, #255 @ 0xff + 8003ad2: f883 2045 strb.w r2, [r3, #69] @ 0x45 + } + taskEXIT_CRITICAL(); + 8003ad6: f001 fca9 bl 800542c + + /* Do the same for the Rx lock. */ + taskENTER_CRITICAL(); + 8003ada: f001 fc75 bl 80053c8 + { + int8_t cRxLock = pxQueue->cRxLock; + 8003ade: 687b ldr r3, [r7, #4] + 8003ae0: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 + 8003ae4: 73bb strb r3, [r7, #14] + + while( cRxLock > queueLOCKED_UNMODIFIED ) + 8003ae6: e011 b.n 8003b0c + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + 8003ae8: 687b ldr r3, [r7, #4] + 8003aea: 691b ldr r3, [r3, #16] + 8003aec: 2b00 cmp r3, #0 + 8003aee: d012 beq.n 8003b16 + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + 8003af0: 687b ldr r3, [r7, #4] + 8003af2: 3310 adds r3, #16 + 8003af4: 4618 mov r0, r3 + 8003af6: f000 fd37 bl 8004568 + 8003afa: 4603 mov r3, r0 + 8003afc: 2b00 cmp r3, #0 + 8003afe: d001 beq.n 8003b04 + { + vTaskMissedYield(); + 8003b00: f000 fe10 bl 8004724 + else + { + mtCOVERAGE_TEST_MARKER(); + } + + --cRxLock; + 8003b04: 7bbb ldrb r3, [r7, #14] + 8003b06: 3b01 subs r3, #1 + 8003b08: b2db uxtb r3, r3 + 8003b0a: 73bb strb r3, [r7, #14] + while( cRxLock > queueLOCKED_UNMODIFIED ) + 8003b0c: f997 300e ldrsb.w r3, [r7, #14] + 8003b10: 2b00 cmp r3, #0 + 8003b12: dce9 bgt.n 8003ae8 + 8003b14: e000 b.n 8003b18 + } + else + { + break; + 8003b16: bf00 nop + } + } + + pxQueue->cRxLock = queueUNLOCKED; + 8003b18: 687b ldr r3, [r7, #4] + 8003b1a: 22ff movs r2, #255 @ 0xff + 8003b1c: f883 2044 strb.w r2, [r3, #68] @ 0x44 + } + taskEXIT_CRITICAL(); + 8003b20: f001 fc84 bl 800542c +} + 8003b24: bf00 nop + 8003b26: 3710 adds r7, #16 + 8003b28: 46bd mov sp, r7 + 8003b2a: bd80 pop {r7, pc} + +08003b2c : +/*-----------------------------------------------------------*/ + +static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) +{ + 8003b2c: b580 push {r7, lr} + 8003b2e: b084 sub sp, #16 + 8003b30: af00 add r7, sp, #0 + 8003b32: 6078 str r0, [r7, #4] +BaseType_t xReturn; + + taskENTER_CRITICAL(); + 8003b34: f001 fc48 bl 80053c8 + { + if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) + 8003b38: 687b ldr r3, [r7, #4] + 8003b3a: 6b9b ldr r3, [r3, #56] @ 0x38 + 8003b3c: 2b00 cmp r3, #0 + 8003b3e: d102 bne.n 8003b46 + { + xReturn = pdTRUE; + 8003b40: 2301 movs r3, #1 + 8003b42: 60fb str r3, [r7, #12] + 8003b44: e001 b.n 8003b4a + } + else + { + xReturn = pdFALSE; + 8003b46: 2300 movs r3, #0 + 8003b48: 60fb str r3, [r7, #12] + } + } + taskEXIT_CRITICAL(); + 8003b4a: f001 fc6f bl 800542c + + return xReturn; + 8003b4e: 68fb ldr r3, [r7, #12] +} + 8003b50: 4618 mov r0, r3 + 8003b52: 3710 adds r7, #16 + 8003b54: 46bd mov sp, r7 + 8003b56: bd80 pop {r7, pc} + +08003b58 : + return xReturn; +} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ +/*-----------------------------------------------------------*/ + +static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) +{ + 8003b58: b580 push {r7, lr} + 8003b5a: b084 sub sp, #16 + 8003b5c: af00 add r7, sp, #0 + 8003b5e: 6078 str r0, [r7, #4] +BaseType_t xReturn; + + taskENTER_CRITICAL(); + 8003b60: f001 fc32 bl 80053c8 + { + if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) + 8003b64: 687b ldr r3, [r7, #4] + 8003b66: 6b9a ldr r2, [r3, #56] @ 0x38 + 8003b68: 687b ldr r3, [r7, #4] + 8003b6a: 6bdb ldr r3, [r3, #60] @ 0x3c + 8003b6c: 429a cmp r2, r3 + 8003b6e: d102 bne.n 8003b76 + { + xReturn = pdTRUE; + 8003b70: 2301 movs r3, #1 + 8003b72: 60fb str r3, [r7, #12] + 8003b74: e001 b.n 8003b7a + } + else + { + xReturn = pdFALSE; + 8003b76: 2300 movs r3, #0 + 8003b78: 60fb str r3, [r7, #12] + } + } + taskEXIT_CRITICAL(); + 8003b7a: f001 fc57 bl 800542c + + return xReturn; + 8003b7e: 68fb ldr r3, [r7, #12] +} + 8003b80: 4618 mov r0, r3 + 8003b82: 3710 adds r7, #16 + 8003b84: 46bd mov sp, r7 + 8003b86: bd80 pop {r7, pc} + +08003b88 : +/*-----------------------------------------------------------*/ + +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + { + 8003b88: b480 push {r7} + 8003b8a: b085 sub sp, #20 + 8003b8c: af00 add r7, sp, #0 + 8003b8e: 6078 str r0, [r7, #4] + 8003b90: 6039 str r1, [r7, #0] + UBaseType_t ux; + + /* See if there is an empty space in the registry. A NULL name denotes + a free slot. */ + for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) + 8003b92: 2300 movs r3, #0 + 8003b94: 60fb str r3, [r7, #12] + 8003b96: e014 b.n 8003bc2 + { + if( xQueueRegistry[ ux ].pcQueueName == NULL ) + 8003b98: 4a0f ldr r2, [pc, #60] @ (8003bd8 ) + 8003b9a: 68fb ldr r3, [r7, #12] + 8003b9c: f852 3033 ldr.w r3, [r2, r3, lsl #3] + 8003ba0: 2b00 cmp r3, #0 + 8003ba2: d10b bne.n 8003bbc + { + /* Store the information on this queue. */ + xQueueRegistry[ ux ].pcQueueName = pcQueueName; + 8003ba4: 490c ldr r1, [pc, #48] @ (8003bd8 ) + 8003ba6: 68fb ldr r3, [r7, #12] + 8003ba8: 683a ldr r2, [r7, #0] + 8003baa: f841 2033 str.w r2, [r1, r3, lsl #3] + xQueueRegistry[ ux ].xHandle = xQueue; + 8003bae: 4a0a ldr r2, [pc, #40] @ (8003bd8 ) + 8003bb0: 68fb ldr r3, [r7, #12] + 8003bb2: 00db lsls r3, r3, #3 + 8003bb4: 4413 add r3, r2 + 8003bb6: 687a ldr r2, [r7, #4] + 8003bb8: 605a str r2, [r3, #4] + + traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ); + break; + 8003bba: e006 b.n 8003bca + for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) + 8003bbc: 68fb ldr r3, [r7, #12] + 8003bbe: 3301 adds r3, #1 + 8003bc0: 60fb str r3, [r7, #12] + 8003bc2: 68fb ldr r3, [r7, #12] + 8003bc4: 2b07 cmp r3, #7 + 8003bc6: d9e7 bls.n 8003b98 + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + 8003bc8: bf00 nop + 8003bca: bf00 nop + 8003bcc: 3714 adds r7, #20 + 8003bce: 46bd mov sp, r7 + 8003bd0: f85d 7b04 ldr.w r7, [sp], #4 + 8003bd4: 4770 bx lr + 8003bd6: bf00 nop + 8003bd8: 200008f8 .word 0x200008f8 + +08003bdc : +/*-----------------------------------------------------------*/ + +#if ( configUSE_TIMERS == 1 ) + + void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) + { + 8003bdc: b580 push {r7, lr} + 8003bde: b086 sub sp, #24 + 8003be0: af00 add r7, sp, #0 + 8003be2: 60f8 str r0, [r7, #12] + 8003be4: 60b9 str r1, [r7, #8] + 8003be6: 607a str r2, [r7, #4] + Queue_t * const pxQueue = xQueue; + 8003be8: 68fb ldr r3, [r7, #12] + 8003bea: 617b str r3, [r7, #20] + will not actually cause the task to block, just place it on a blocked + list. It will not block until the scheduler is unlocked - at which + time a yield will be performed. If an item is added to the queue while + the queue is locked, and the calling task blocks on the queue, then the + calling task will be immediately unblocked when the queue is unlocked. */ + prvLockQueue( pxQueue ); + 8003bec: f001 fbec bl 80053c8 + 8003bf0: 697b ldr r3, [r7, #20] + 8003bf2: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 + 8003bf6: b25b sxtb r3, r3 + 8003bf8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8003bfc: d103 bne.n 8003c06 + 8003bfe: 697b ldr r3, [r7, #20] + 8003c00: 2200 movs r2, #0 + 8003c02: f883 2044 strb.w r2, [r3, #68] @ 0x44 + 8003c06: 697b ldr r3, [r7, #20] + 8003c08: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 + 8003c0c: b25b sxtb r3, r3 + 8003c0e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8003c12: d103 bne.n 8003c1c + 8003c14: 697b ldr r3, [r7, #20] + 8003c16: 2200 movs r2, #0 + 8003c18: f883 2045 strb.w r2, [r3, #69] @ 0x45 + 8003c1c: f001 fc06 bl 800542c + if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U ) + 8003c20: 697b ldr r3, [r7, #20] + 8003c22: 6b9b ldr r3, [r3, #56] @ 0x38 + 8003c24: 2b00 cmp r3, #0 + 8003c26: d106 bne.n 8003c36 + { + /* There is nothing in the queue, block for the specified period. */ + vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely ); + 8003c28: 697b ldr r3, [r7, #20] + 8003c2a: 3324 adds r3, #36 @ 0x24 + 8003c2c: 687a ldr r2, [r7, #4] + 8003c2e: 68b9 ldr r1, [r7, #8] + 8003c30: 4618 mov r0, r3 + 8003c32: f000 fc6d bl 8004510 + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + prvUnlockQueue( pxQueue ); + 8003c36: 6978 ldr r0, [r7, #20] + 8003c38: f7ff ff26 bl 8003a88 + } + 8003c3c: bf00 nop + 8003c3e: 3718 adds r7, #24 + 8003c40: 46bd mov sp, r7 + 8003c42: bd80 pop {r7, pc} + +08003c44 : + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer ) + { + 8003c44: b580 push {r7, lr} + 8003c46: b08e sub sp, #56 @ 0x38 + 8003c48: af04 add r7, sp, #16 + 8003c4a: 60f8 str r0, [r7, #12] + 8003c4c: 60b9 str r1, [r7, #8] + 8003c4e: 607a str r2, [r7, #4] + 8003c50: 603b str r3, [r7, #0] + TCB_t *pxNewTCB; + TaskHandle_t xReturn; + + configASSERT( puxStackBuffer != NULL ); + 8003c52: 6b7b ldr r3, [r7, #52] @ 0x34 + 8003c54: 2b00 cmp r3, #0 + 8003c56: d10b bne.n 8003c70 + __asm volatile + 8003c58: f04f 0350 mov.w r3, #80 @ 0x50 + 8003c5c: f383 8811 msr BASEPRI, r3 + 8003c60: f3bf 8f6f isb sy + 8003c64: f3bf 8f4f dsb sy + 8003c68: 623b str r3, [r7, #32] +} + 8003c6a: bf00 nop + 8003c6c: bf00 nop + 8003c6e: e7fd b.n 8003c6c + configASSERT( pxTaskBuffer != NULL ); + 8003c70: 6bbb ldr r3, [r7, #56] @ 0x38 + 8003c72: 2b00 cmp r3, #0 + 8003c74: d10b bne.n 8003c8e + __asm volatile + 8003c76: f04f 0350 mov.w r3, #80 @ 0x50 + 8003c7a: f383 8811 msr BASEPRI, r3 + 8003c7e: f3bf 8f6f isb sy + 8003c82: f3bf 8f4f dsb sy + 8003c86: 61fb str r3, [r7, #28] +} + 8003c88: bf00 nop + 8003c8a: bf00 nop + 8003c8c: e7fd b.n 8003c8a + #if( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + variable of type StaticTask_t equals the size of the real task + structure. */ + volatile size_t xSize = sizeof( StaticTask_t ); + 8003c8e: 23a8 movs r3, #168 @ 0xa8 + 8003c90: 613b str r3, [r7, #16] + configASSERT( xSize == sizeof( TCB_t ) ); + 8003c92: 693b ldr r3, [r7, #16] + 8003c94: 2ba8 cmp r3, #168 @ 0xa8 + 8003c96: d00b beq.n 8003cb0 + __asm volatile + 8003c98: f04f 0350 mov.w r3, #80 @ 0x50 + 8003c9c: f383 8811 msr BASEPRI, r3 + 8003ca0: f3bf 8f6f isb sy + 8003ca4: f3bf 8f4f dsb sy + 8003ca8: 61bb str r3, [r7, #24] +} + 8003caa: bf00 nop + 8003cac: bf00 nop + 8003cae: e7fd b.n 8003cac + ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */ + 8003cb0: 693b ldr r3, [r7, #16] + } + #endif /* configASSERT_DEFINED */ + + + if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) ) + 8003cb2: 6bbb ldr r3, [r7, #56] @ 0x38 + 8003cb4: 2b00 cmp r3, #0 + 8003cb6: d01e beq.n 8003cf6 + 8003cb8: 6b7b ldr r3, [r7, #52] @ 0x34 + 8003cba: 2b00 cmp r3, #0 + 8003cbc: d01b beq.n 8003cf6 + { + /* The memory used for the task's TCB and stack are passed into this + function - use them. */ + pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ + 8003cbe: 6bbb ldr r3, [r7, #56] @ 0x38 + 8003cc0: 627b str r3, [r7, #36] @ 0x24 + pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer; + 8003cc2: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003cc4: 6b7a ldr r2, [r7, #52] @ 0x34 + 8003cc6: 631a str r2, [r3, #48] @ 0x30 + + #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ + { + /* Tasks can be created statically or dynamically, so note this + task was created statically in case the task is later deleted. */ + pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; + 8003cc8: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003cca: 2202 movs r2, #2 + 8003ccc: f883 20a5 strb.w r2, [r3, #165] @ 0xa5 + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); + 8003cd0: 2300 movs r3, #0 + 8003cd2: 9303 str r3, [sp, #12] + 8003cd4: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003cd6: 9302 str r3, [sp, #8] + 8003cd8: f107 0314 add.w r3, r7, #20 + 8003cdc: 9301 str r3, [sp, #4] + 8003cde: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003ce0: 9300 str r3, [sp, #0] + 8003ce2: 683b ldr r3, [r7, #0] + 8003ce4: 687a ldr r2, [r7, #4] + 8003ce6: 68b9 ldr r1, [r7, #8] + 8003ce8: 68f8 ldr r0, [r7, #12] + 8003cea: f000 f851 bl 8003d90 + prvAddNewTaskToReadyList( pxNewTCB ); + 8003cee: 6a78 ldr r0, [r7, #36] @ 0x24 + 8003cf0: f000 f8f6 bl 8003ee0 + 8003cf4: e001 b.n 8003cfa + } + else + { + xReturn = NULL; + 8003cf6: 2300 movs r3, #0 + 8003cf8: 617b str r3, [r7, #20] + } + + return xReturn; + 8003cfa: 697b ldr r3, [r7, #20] + } + 8003cfc: 4618 mov r0, r3 + 8003cfe: 3728 adds r7, #40 @ 0x28 + 8003d00: 46bd mov sp, r7 + 8003d02: bd80 pop {r7, pc} + +08003d04 : + const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const configSTACK_DEPTH_TYPE usStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask ) + { + 8003d04: b580 push {r7, lr} + 8003d06: b08c sub sp, #48 @ 0x30 + 8003d08: af04 add r7, sp, #16 + 8003d0a: 60f8 str r0, [r7, #12] + 8003d0c: 60b9 str r1, [r7, #8] + 8003d0e: 603b str r3, [r7, #0] + 8003d10: 4613 mov r3, r2 + 8003d12: 80fb strh r3, [r7, #6] + #else /* portSTACK_GROWTH */ + { + StackType_t *pxStack; + + /* Allocate space for the stack used by the task being created. */ + pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */ + 8003d14: 88fb ldrh r3, [r7, #6] + 8003d16: 009b lsls r3, r3, #2 + 8003d18: 4618 mov r0, r3 + 8003d1a: f001 fc77 bl 800560c + 8003d1e: 6178 str r0, [r7, #20] + + if( pxStack != NULL ) + 8003d20: 697b ldr r3, [r7, #20] + 8003d22: 2b00 cmp r3, #0 + 8003d24: d00e beq.n 8003d44 + { + /* Allocate space for the TCB. */ + pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */ + 8003d26: 20a8 movs r0, #168 @ 0xa8 + 8003d28: f001 fc70 bl 800560c + 8003d2c: 61f8 str r0, [r7, #28] + + if( pxNewTCB != NULL ) + 8003d2e: 69fb ldr r3, [r7, #28] + 8003d30: 2b00 cmp r3, #0 + 8003d32: d003 beq.n 8003d3c + { + /* Store the stack location in the TCB. */ + pxNewTCB->pxStack = pxStack; + 8003d34: 69fb ldr r3, [r7, #28] + 8003d36: 697a ldr r2, [r7, #20] + 8003d38: 631a str r2, [r3, #48] @ 0x30 + 8003d3a: e005 b.n 8003d48 + } + else + { + /* The stack cannot be used as the TCB was not created. Free + it again. */ + vPortFree( pxStack ); + 8003d3c: 6978 ldr r0, [r7, #20] + 8003d3e: f001 fd33 bl 80057a8 + 8003d42: e001 b.n 8003d48 + } + } + else + { + pxNewTCB = NULL; + 8003d44: 2300 movs r3, #0 + 8003d46: 61fb str r3, [r7, #28] + } + } + #endif /* portSTACK_GROWTH */ + + if( pxNewTCB != NULL ) + 8003d48: 69fb ldr r3, [r7, #28] + 8003d4a: 2b00 cmp r3, #0 + 8003d4c: d017 beq.n 8003d7e + { + #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */ + { + /* Tasks can be created statically or dynamically, so note this + task was created dynamically in case it is later deleted. */ + pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB; + 8003d4e: 69fb ldr r3, [r7, #28] + 8003d50: 2200 movs r2, #0 + 8003d52: f883 20a5 strb.w r2, [r3, #165] @ 0xa5 + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); + 8003d56: 88fa ldrh r2, [r7, #6] + 8003d58: 2300 movs r3, #0 + 8003d5a: 9303 str r3, [sp, #12] + 8003d5c: 69fb ldr r3, [r7, #28] + 8003d5e: 9302 str r3, [sp, #8] + 8003d60: 6afb ldr r3, [r7, #44] @ 0x2c + 8003d62: 9301 str r3, [sp, #4] + 8003d64: 6abb ldr r3, [r7, #40] @ 0x28 + 8003d66: 9300 str r3, [sp, #0] + 8003d68: 683b ldr r3, [r7, #0] + 8003d6a: 68b9 ldr r1, [r7, #8] + 8003d6c: 68f8 ldr r0, [r7, #12] + 8003d6e: f000 f80f bl 8003d90 + prvAddNewTaskToReadyList( pxNewTCB ); + 8003d72: 69f8 ldr r0, [r7, #28] + 8003d74: f000 f8b4 bl 8003ee0 + xReturn = pdPASS; + 8003d78: 2301 movs r3, #1 + 8003d7a: 61bb str r3, [r7, #24] + 8003d7c: e002 b.n 8003d84 + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + 8003d7e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 8003d82: 61bb str r3, [r7, #24] + } + + return xReturn; + 8003d84: 69bb ldr r3, [r7, #24] + } + 8003d86: 4618 mov r0, r3 + 8003d88: 3720 adds r7, #32 + 8003d8a: 46bd mov sp, r7 + 8003d8c: bd80 pop {r7, pc} + ... + +08003d90 : + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask, + TCB_t *pxNewTCB, + const MemoryRegion_t * const xRegions ) +{ + 8003d90: b580 push {r7, lr} + 8003d92: b088 sub sp, #32 + 8003d94: af00 add r7, sp, #0 + 8003d96: 60f8 str r0, [r7, #12] + 8003d98: 60b9 str r1, [r7, #8] + 8003d9a: 607a str r2, [r7, #4] + 8003d9c: 603b str r3, [r7, #0] + + /* Avoid dependency on memset() if it is not required. */ + #if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 ) + { + /* Fill the stack with a known value to assist debugging. */ + ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) ); + 8003d9e: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003da0: 6b18 ldr r0, [r3, #48] @ 0x30 + 8003da2: 687b ldr r3, [r7, #4] + 8003da4: 009b lsls r3, r3, #2 + 8003da6: 461a mov r2, r3 + 8003da8: 21a5 movs r1, #165 @ 0xa5 + 8003daa: f001 fe29 bl 8005a00 + grows from high memory to low (as per the 80x86) or vice versa. + portSTACK_GROWTH is used to make the result positive or negative as required + by the port. */ + #if( portSTACK_GROWTH < 0 ) + { + pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] ); + 8003dae: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003db0: 6b1a ldr r2, [r3, #48] @ 0x30 + 8003db2: 687b ldr r3, [r7, #4] + 8003db4: f103 4380 add.w r3, r3, #1073741824 @ 0x40000000 + 8003db8: 3b01 subs r3, #1 + 8003dba: 009b lsls r3, r3, #2 + 8003dbc: 4413 add r3, r2 + 8003dbe: 61bb str r3, [r7, #24] + pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */ + 8003dc0: 69bb ldr r3, [r7, #24] + 8003dc2: f023 0307 bic.w r3, r3, #7 + 8003dc6: 61bb str r3, [r7, #24] + + /* Check the alignment of the calculated top of stack is correct. */ + configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); + 8003dc8: 69bb ldr r3, [r7, #24] + 8003dca: f003 0307 and.w r3, r3, #7 + 8003dce: 2b00 cmp r3, #0 + 8003dd0: d00b beq.n 8003dea + __asm volatile + 8003dd2: f04f 0350 mov.w r3, #80 @ 0x50 + 8003dd6: f383 8811 msr BASEPRI, r3 + 8003dda: f3bf 8f6f isb sy + 8003dde: f3bf 8f4f dsb sy + 8003de2: 617b str r3, [r7, #20] +} + 8003de4: bf00 nop + 8003de6: bf00 nop + 8003de8: e7fd b.n 8003de6 + pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 ); + } + #endif /* portSTACK_GROWTH */ + + /* Store the task name in the TCB. */ + if( pcName != NULL ) + 8003dea: 68bb ldr r3, [r7, #8] + 8003dec: 2b00 cmp r3, #0 + 8003dee: d01f beq.n 8003e30 + { + for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) + 8003df0: 2300 movs r3, #0 + 8003df2: 61fb str r3, [r7, #28] + 8003df4: e012 b.n 8003e1c + { + pxNewTCB->pcTaskName[ x ] = pcName[ x ]; + 8003df6: 68ba ldr r2, [r7, #8] + 8003df8: 69fb ldr r3, [r7, #28] + 8003dfa: 4413 add r3, r2 + 8003dfc: 7819 ldrb r1, [r3, #0] + 8003dfe: 6b3a ldr r2, [r7, #48] @ 0x30 + 8003e00: 69fb ldr r3, [r7, #28] + 8003e02: 4413 add r3, r2 + 8003e04: 3334 adds r3, #52 @ 0x34 + 8003e06: 460a mov r2, r1 + 8003e08: 701a strb r2, [r3, #0] + + /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than + configMAX_TASK_NAME_LEN characters just in case the memory after the + string is not accessible (extremely unlikely). */ + if( pcName[ x ] == ( char ) 0x00 ) + 8003e0a: 68ba ldr r2, [r7, #8] + 8003e0c: 69fb ldr r3, [r7, #28] + 8003e0e: 4413 add r3, r2 + 8003e10: 781b ldrb r3, [r3, #0] + 8003e12: 2b00 cmp r3, #0 + 8003e14: d006 beq.n 8003e24 + for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) + 8003e16: 69fb ldr r3, [r7, #28] + 8003e18: 3301 adds r3, #1 + 8003e1a: 61fb str r3, [r7, #28] + 8003e1c: 69fb ldr r3, [r7, #28] + 8003e1e: 2b0f cmp r3, #15 + 8003e20: d9e9 bls.n 8003df6 + 8003e22: e000 b.n 8003e26 + { + break; + 8003e24: bf00 nop + } + } + + /* Ensure the name string is terminated in the case that the string length + was greater or equal to configMAX_TASK_NAME_LEN. */ + pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0'; + 8003e26: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003e28: 2200 movs r2, #0 + 8003e2a: f883 2043 strb.w r2, [r3, #67] @ 0x43 + 8003e2e: e003 b.n 8003e38 + } + else + { + /* The task has not been given a name, so just ensure there is a NULL + terminator when it is read out. */ + pxNewTCB->pcTaskName[ 0 ] = 0x00; + 8003e30: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003e32: 2200 movs r2, #0 + 8003e34: f883 2034 strb.w r2, [r3, #52] @ 0x34 + } + + /* This is used as an array index so must ensure it's not too large. First + remove the privilege bit if one is present. */ + if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) + 8003e38: 6abb ldr r3, [r7, #40] @ 0x28 + 8003e3a: 2b37 cmp r3, #55 @ 0x37 + 8003e3c: d901 bls.n 8003e42 + { + uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U; + 8003e3e: 2337 movs r3, #55 @ 0x37 + 8003e40: 62bb str r3, [r7, #40] @ 0x28 + else + { + mtCOVERAGE_TEST_MARKER(); + } + + pxNewTCB->uxPriority = uxPriority; + 8003e42: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003e44: 6aba ldr r2, [r7, #40] @ 0x28 + 8003e46: 62da str r2, [r3, #44] @ 0x2c + #if ( configUSE_MUTEXES == 1 ) + { + pxNewTCB->uxBasePriority = uxPriority; + 8003e48: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003e4a: 6aba ldr r2, [r7, #40] @ 0x28 + 8003e4c: 64da str r2, [r3, #76] @ 0x4c + pxNewTCB->uxMutexesHeld = 0; + 8003e4e: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003e50: 2200 movs r2, #0 + 8003e52: 651a str r2, [r3, #80] @ 0x50 + } + #endif /* configUSE_MUTEXES */ + + vListInitialiseItem( &( pxNewTCB->xStateListItem ) ); + 8003e54: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003e56: 3304 adds r3, #4 + 8003e58: 4618 mov r0, r3 + 8003e5a: f7ff f965 bl 8003128 + vListInitialiseItem( &( pxNewTCB->xEventListItem ) ); + 8003e5e: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003e60: 3318 adds r3, #24 + 8003e62: 4618 mov r0, r3 + 8003e64: f7ff f960 bl 8003128 + + /* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get + back to the containing TCB from a generic item in a list. */ + listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB ); + 8003e68: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003e6a: 6b3a ldr r2, [r7, #48] @ 0x30 + 8003e6c: 611a str r2, [r3, #16] + + /* Event lists are always in priority order. */ + listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 8003e6e: 6abb ldr r3, [r7, #40] @ 0x28 + 8003e70: f1c3 0238 rsb r2, r3, #56 @ 0x38 + 8003e74: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003e76: 619a str r2, [r3, #24] + listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB ); + 8003e78: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003e7a: 6b3a ldr r2, [r7, #48] @ 0x30 + 8003e7c: 625a str r2, [r3, #36] @ 0x24 + } + #endif + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + { + pxNewTCB->ulNotifiedValue = 0; + 8003e7e: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003e80: 2200 movs r2, #0 + 8003e82: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 + pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; + 8003e86: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003e88: 2200 movs r2, #0 + 8003e8a: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 + #if ( configUSE_NEWLIB_REENTRANT == 1 ) + { + /* Initialise this task's Newlib reent structure. + See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html + for additional information. */ + _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) ); + 8003e8e: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003e90: 3354 adds r3, #84 @ 0x54 + 8003e92: 224c movs r2, #76 @ 0x4c + 8003e94: 2100 movs r1, #0 + 8003e96: 4618 mov r0, r3 + 8003e98: f001 fdb2 bl 8005a00 + 8003e9c: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003e9e: 4a0d ldr r2, [pc, #52] @ (8003ed4 ) + 8003ea0: 659a str r2, [r3, #88] @ 0x58 + 8003ea2: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003ea4: 4a0c ldr r2, [pc, #48] @ (8003ed8 ) + 8003ea6: 65da str r2, [r3, #92] @ 0x5c + 8003ea8: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003eaa: 4a0c ldr r2, [pc, #48] @ (8003edc ) + 8003eac: 661a str r2, [r3, #96] @ 0x60 + } + #endif /* portSTACK_GROWTH */ + } + #else /* portHAS_STACK_OVERFLOW_CHECKING */ + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); + 8003eae: 683a ldr r2, [r7, #0] + 8003eb0: 68f9 ldr r1, [r7, #12] + 8003eb2: 69b8 ldr r0, [r7, #24] + 8003eb4: f001 f95a bl 800516c + 8003eb8: 4602 mov r2, r0 + 8003eba: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003ebc: 601a str r2, [r3, #0] + } + #endif /* portHAS_STACK_OVERFLOW_CHECKING */ + } + #endif /* portUSING_MPU_WRAPPERS */ + + if( pxCreatedTask != NULL ) + 8003ebe: 6afb ldr r3, [r7, #44] @ 0x2c + 8003ec0: 2b00 cmp r3, #0 + 8003ec2: d002 beq.n 8003eca + { + /* Pass the handle out in an anonymous way. The handle can be used to + change the created task's priority, delete the created task, etc.*/ + *pxCreatedTask = ( TaskHandle_t ) pxNewTCB; + 8003ec4: 6afb ldr r3, [r7, #44] @ 0x2c + 8003ec6: 6b3a ldr r2, [r7, #48] @ 0x30 + 8003ec8: 601a str r2, [r3, #0] + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} + 8003eca: bf00 nop + 8003ecc: 3720 adds r7, #32 + 8003ece: 46bd mov sp, r7 + 8003ed0: bd80 pop {r7, pc} + 8003ed2: bf00 nop + 8003ed4: 20004b90 .word 0x20004b90 + 8003ed8: 20004bf8 .word 0x20004bf8 + 8003edc: 20004c60 .word 0x20004c60 + +08003ee0 : +/*-----------------------------------------------------------*/ + +static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) +{ + 8003ee0: b580 push {r7, lr} + 8003ee2: b082 sub sp, #8 + 8003ee4: af00 add r7, sp, #0 + 8003ee6: 6078 str r0, [r7, #4] + /* Ensure interrupts don't access the task lists while the lists are being + updated. */ + taskENTER_CRITICAL(); + 8003ee8: f001 fa6e bl 80053c8 + { + uxCurrentNumberOfTasks++; + 8003eec: 4b2d ldr r3, [pc, #180] @ (8003fa4 ) + 8003eee: 681b ldr r3, [r3, #0] + 8003ef0: 3301 adds r3, #1 + 8003ef2: 4a2c ldr r2, [pc, #176] @ (8003fa4 ) + 8003ef4: 6013 str r3, [r2, #0] + if( pxCurrentTCB == NULL ) + 8003ef6: 4b2c ldr r3, [pc, #176] @ (8003fa8 ) + 8003ef8: 681b ldr r3, [r3, #0] + 8003efa: 2b00 cmp r3, #0 + 8003efc: d109 bne.n 8003f12 + { + /* There are no other tasks, or all the other tasks are in + the suspended state - make this the current task. */ + pxCurrentTCB = pxNewTCB; + 8003efe: 4a2a ldr r2, [pc, #168] @ (8003fa8 ) + 8003f00: 687b ldr r3, [r7, #4] + 8003f02: 6013 str r3, [r2, #0] + + if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) + 8003f04: 4b27 ldr r3, [pc, #156] @ (8003fa4 ) + 8003f06: 681b ldr r3, [r3, #0] + 8003f08: 2b01 cmp r3, #1 + 8003f0a: d110 bne.n 8003f2e + { + /* This is the first task to be created so do the preliminary + initialisation required. We will not recover if this call + fails, but we will report the failure. */ + prvInitialiseTaskLists(); + 8003f0c: f000 fc2e bl 800476c + 8003f10: e00d b.n 8003f2e + else + { + /* If the scheduler is not already running, make this task the + current task if it is the highest priority task to be created + so far. */ + if( xSchedulerRunning == pdFALSE ) + 8003f12: 4b26 ldr r3, [pc, #152] @ (8003fac ) + 8003f14: 681b ldr r3, [r3, #0] + 8003f16: 2b00 cmp r3, #0 + 8003f18: d109 bne.n 8003f2e + { + if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) + 8003f1a: 4b23 ldr r3, [pc, #140] @ (8003fa8 ) + 8003f1c: 681b ldr r3, [r3, #0] + 8003f1e: 6ada ldr r2, [r3, #44] @ 0x2c + 8003f20: 687b ldr r3, [r7, #4] + 8003f22: 6adb ldr r3, [r3, #44] @ 0x2c + 8003f24: 429a cmp r2, r3 + 8003f26: d802 bhi.n 8003f2e + { + pxCurrentTCB = pxNewTCB; + 8003f28: 4a1f ldr r2, [pc, #124] @ (8003fa8 ) + 8003f2a: 687b ldr r3, [r7, #4] + 8003f2c: 6013 str r3, [r2, #0] + { + mtCOVERAGE_TEST_MARKER(); + } + } + + uxTaskNumber++; + 8003f2e: 4b20 ldr r3, [pc, #128] @ (8003fb0 ) + 8003f30: 681b ldr r3, [r3, #0] + 8003f32: 3301 adds r3, #1 + 8003f34: 4a1e ldr r2, [pc, #120] @ (8003fb0 ) + 8003f36: 6013 str r3, [r2, #0] + + #if ( configUSE_TRACE_FACILITY == 1 ) + { + /* Add a counter into the TCB for tracing only. */ + pxNewTCB->uxTCBNumber = uxTaskNumber; + 8003f38: 4b1d ldr r3, [pc, #116] @ (8003fb0 ) + 8003f3a: 681a ldr r2, [r3, #0] + 8003f3c: 687b ldr r3, [r7, #4] + 8003f3e: 645a str r2, [r3, #68] @ 0x44 + } + #endif /* configUSE_TRACE_FACILITY */ + traceTASK_CREATE( pxNewTCB ); + + prvAddTaskToReadyList( pxNewTCB ); + 8003f40: 687b ldr r3, [r7, #4] + 8003f42: 6ada ldr r2, [r3, #44] @ 0x2c + 8003f44: 4b1b ldr r3, [pc, #108] @ (8003fb4 ) + 8003f46: 681b ldr r3, [r3, #0] + 8003f48: 429a cmp r2, r3 + 8003f4a: d903 bls.n 8003f54 + 8003f4c: 687b ldr r3, [r7, #4] + 8003f4e: 6adb ldr r3, [r3, #44] @ 0x2c + 8003f50: 4a18 ldr r2, [pc, #96] @ (8003fb4 ) + 8003f52: 6013 str r3, [r2, #0] + 8003f54: 687b ldr r3, [r7, #4] + 8003f56: 6ada ldr r2, [r3, #44] @ 0x2c + 8003f58: 4613 mov r3, r2 + 8003f5a: 009b lsls r3, r3, #2 + 8003f5c: 4413 add r3, r2 + 8003f5e: 009b lsls r3, r3, #2 + 8003f60: 4a15 ldr r2, [pc, #84] @ (8003fb8 ) + 8003f62: 441a add r2, r3 + 8003f64: 687b ldr r3, [r7, #4] + 8003f66: 3304 adds r3, #4 + 8003f68: 4619 mov r1, r3 + 8003f6a: 4610 mov r0, r2 + 8003f6c: f7ff f8e9 bl 8003142 + + portSETUP_TCB( pxNewTCB ); + } + taskEXIT_CRITICAL(); + 8003f70: f001 fa5c bl 800542c + + if( xSchedulerRunning != pdFALSE ) + 8003f74: 4b0d ldr r3, [pc, #52] @ (8003fac ) + 8003f76: 681b ldr r3, [r3, #0] + 8003f78: 2b00 cmp r3, #0 + 8003f7a: d00e beq.n 8003f9a + { + /* If the created task is of a higher priority than the current task + then it should run now. */ + if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority ) + 8003f7c: 4b0a ldr r3, [pc, #40] @ (8003fa8 ) + 8003f7e: 681b ldr r3, [r3, #0] + 8003f80: 6ada ldr r2, [r3, #44] @ 0x2c + 8003f82: 687b ldr r3, [r7, #4] + 8003f84: 6adb ldr r3, [r3, #44] @ 0x2c + 8003f86: 429a cmp r2, r3 + 8003f88: d207 bcs.n 8003f9a + { + taskYIELD_IF_USING_PREEMPTION(); + 8003f8a: 4b0c ldr r3, [pc, #48] @ (8003fbc ) + 8003f8c: f04f 5280 mov.w r2, #268435456 @ 0x10000000 + 8003f90: 601a str r2, [r3, #0] + 8003f92: f3bf 8f4f dsb sy + 8003f96: f3bf 8f6f isb sy + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} + 8003f9a: bf00 nop + 8003f9c: 3708 adds r7, #8 + 8003f9e: 46bd mov sp, r7 + 8003fa0: bd80 pop {r7, pc} + 8003fa2: bf00 nop + 8003fa4: 20000e0c .word 0x20000e0c + 8003fa8: 20000938 .word 0x20000938 + 8003fac: 20000e18 .word 0x20000e18 + 8003fb0: 20000e28 .word 0x20000e28 + 8003fb4: 20000e14 .word 0x20000e14 + 8003fb8: 2000093c .word 0x2000093c + 8003fbc: e000ed04 .word 0xe000ed04 + +08003fc0 : +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskDelay == 1 ) + + void vTaskDelay( const TickType_t xTicksToDelay ) + { + 8003fc0: b580 push {r7, lr} + 8003fc2: b084 sub sp, #16 + 8003fc4: af00 add r7, sp, #0 + 8003fc6: 6078 str r0, [r7, #4] + BaseType_t xAlreadyYielded = pdFALSE; + 8003fc8: 2300 movs r3, #0 + 8003fca: 60fb str r3, [r7, #12] + + /* A delay time of zero just forces a reschedule. */ + if( xTicksToDelay > ( TickType_t ) 0U ) + 8003fcc: 687b ldr r3, [r7, #4] + 8003fce: 2b00 cmp r3, #0 + 8003fd0: d018 beq.n 8004004 + { + configASSERT( uxSchedulerSuspended == 0 ); + 8003fd2: 4b14 ldr r3, [pc, #80] @ (8004024 ) + 8003fd4: 681b ldr r3, [r3, #0] + 8003fd6: 2b00 cmp r3, #0 + 8003fd8: d00b beq.n 8003ff2 + __asm volatile + 8003fda: f04f 0350 mov.w r3, #80 @ 0x50 + 8003fde: f383 8811 msr BASEPRI, r3 + 8003fe2: f3bf 8f6f isb sy + 8003fe6: f3bf 8f4f dsb sy + 8003fea: 60bb str r3, [r7, #8] +} + 8003fec: bf00 nop + 8003fee: bf00 nop + 8003ff0: e7fd b.n 8003fee + vTaskSuspendAll(); + 8003ff2: f000 f88b bl 800410c + list or removed from the blocked list until the scheduler + is resumed. + + This task cannot be in an event list as it is the currently + executing task. */ + prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE ); + 8003ff6: 2100 movs r1, #0 + 8003ff8: 6878 ldr r0, [r7, #4] + 8003ffa: f000 fd09 bl 8004a10 + } + xAlreadyYielded = xTaskResumeAll(); + 8003ffe: f000 f893 bl 8004128 + 8004002: 60f8 str r0, [r7, #12] + mtCOVERAGE_TEST_MARKER(); + } + + /* Force a reschedule if xTaskResumeAll has not already done so, we may + have put ourselves to sleep. */ + if( xAlreadyYielded == pdFALSE ) + 8004004: 68fb ldr r3, [r7, #12] + 8004006: 2b00 cmp r3, #0 + 8004008: d107 bne.n 800401a + { + portYIELD_WITHIN_API(); + 800400a: 4b07 ldr r3, [pc, #28] @ (8004028 ) + 800400c: f04f 5280 mov.w r2, #268435456 @ 0x10000000 + 8004010: 601a str r2, [r3, #0] + 8004012: f3bf 8f4f dsb sy + 8004016: f3bf 8f6f isb sy + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + 800401a: bf00 nop + 800401c: 3710 adds r7, #16 + 800401e: 46bd mov sp, r7 + 8004020: bd80 pop {r7, pc} + 8004022: bf00 nop + 8004024: 20000e34 .word 0x20000e34 + 8004028: e000ed04 .word 0xe000ed04 + +0800402c : + +#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */ +/*-----------------------------------------------------------*/ + +void vTaskStartScheduler( void ) +{ + 800402c: b580 push {r7, lr} + 800402e: b08a sub sp, #40 @ 0x28 + 8004030: af04 add r7, sp, #16 +BaseType_t xReturn; + + /* Add the idle task at the lowest priority. */ + #if( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + StaticTask_t *pxIdleTaskTCBBuffer = NULL; + 8004032: 2300 movs r3, #0 + 8004034: 60bb str r3, [r7, #8] + StackType_t *pxIdleTaskStackBuffer = NULL; + 8004036: 2300 movs r3, #0 + 8004038: 607b str r3, [r7, #4] + uint32_t ulIdleTaskStackSize; + + /* The Idle task is created using user provided RAM - obtain the + address of the RAM then create the idle task. */ + vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize ); + 800403a: 463a mov r2, r7 + 800403c: 1d39 adds r1, r7, #4 + 800403e: f107 0308 add.w r3, r7, #8 + 8004042: 4618 mov r0, r3 + 8004044: f7ff f81c bl 8003080 + xIdleTaskHandle = xTaskCreateStatic( prvIdleTask, + 8004048: 6839 ldr r1, [r7, #0] + 800404a: 687b ldr r3, [r7, #4] + 800404c: 68ba ldr r2, [r7, #8] + 800404e: 9202 str r2, [sp, #8] + 8004050: 9301 str r3, [sp, #4] + 8004052: 2300 movs r3, #0 + 8004054: 9300 str r3, [sp, #0] + 8004056: 2300 movs r3, #0 + 8004058: 460a mov r2, r1 + 800405a: 4924 ldr r1, [pc, #144] @ (80040ec ) + 800405c: 4824 ldr r0, [pc, #144] @ (80040f0 ) + 800405e: f7ff fdf1 bl 8003c44 + 8004062: 4603 mov r3, r0 + 8004064: 4a23 ldr r2, [pc, #140] @ (80040f4 ) + 8004066: 6013 str r3, [r2, #0] + ( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */ + portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ + pxIdleTaskStackBuffer, + pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ + + if( xIdleTaskHandle != NULL ) + 8004068: 4b22 ldr r3, [pc, #136] @ (80040f4 ) + 800406a: 681b ldr r3, [r3, #0] + 800406c: 2b00 cmp r3, #0 + 800406e: d002 beq.n 8004076 + { + xReturn = pdPASS; + 8004070: 2301 movs r3, #1 + 8004072: 617b str r3, [r7, #20] + 8004074: e001 b.n 800407a + } + else + { + xReturn = pdFAIL; + 8004076: 2300 movs r3, #0 + 8004078: 617b str r3, [r7, #20] + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + #if ( configUSE_TIMERS == 1 ) + { + if( xReturn == pdPASS ) + 800407a: 697b ldr r3, [r7, #20] + 800407c: 2b01 cmp r3, #1 + 800407e: d102 bne.n 8004086 + { + xReturn = xTimerCreateTimerTask(); + 8004080: f000 fd1a bl 8004ab8 + 8004084: 6178 str r0, [r7, #20] + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_TIMERS */ + + if( xReturn == pdPASS ) + 8004086: 697b ldr r3, [r7, #20] + 8004088: 2b01 cmp r3, #1 + 800408a: d11b bne.n 80040c4 + __asm volatile + 800408c: f04f 0350 mov.w r3, #80 @ 0x50 + 8004090: f383 8811 msr BASEPRI, r3 + 8004094: f3bf 8f6f isb sy + 8004098: f3bf 8f4f dsb sy + 800409c: 613b str r3, [r7, #16] +} + 800409e: bf00 nop + { + /* Switch Newlib's _impure_ptr variable to point to the _reent + structure specific to the task that will run first. + See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html + for additional information. */ + _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); + 80040a0: 4b15 ldr r3, [pc, #84] @ (80040f8 ) + 80040a2: 681b ldr r3, [r3, #0] + 80040a4: 3354 adds r3, #84 @ 0x54 + 80040a6: 4a15 ldr r2, [pc, #84] @ (80040fc ) + 80040a8: 6013 str r3, [r2, #0] + } + #endif /* configUSE_NEWLIB_REENTRANT */ + + xNextTaskUnblockTime = portMAX_DELAY; + 80040aa: 4b15 ldr r3, [pc, #84] @ (8004100 ) + 80040ac: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 80040b0: 601a str r2, [r3, #0] + xSchedulerRunning = pdTRUE; + 80040b2: 4b14 ldr r3, [pc, #80] @ (8004104 ) + 80040b4: 2201 movs r2, #1 + 80040b6: 601a str r2, [r3, #0] + xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; + 80040b8: 4b13 ldr r3, [pc, #76] @ (8004108 ) + 80040ba: 2200 movs r2, #0 + 80040bc: 601a str r2, [r3, #0] + + traceTASK_SWITCHED_IN(); + + /* Setting up the timer tick is hardware specific and thus in the + portable interface. */ + if( xPortStartScheduler() != pdFALSE ) + 80040be: f001 f8df bl 8005280 + } + + /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0, + meaning xIdleTaskHandle is not used anywhere else. */ + ( void ) xIdleTaskHandle; +} + 80040c2: e00f b.n 80040e4 + configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ); + 80040c4: 697b ldr r3, [r7, #20] + 80040c6: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 80040ca: d10b bne.n 80040e4 + __asm volatile + 80040cc: f04f 0350 mov.w r3, #80 @ 0x50 + 80040d0: f383 8811 msr BASEPRI, r3 + 80040d4: f3bf 8f6f isb sy + 80040d8: f3bf 8f4f dsb sy + 80040dc: 60fb str r3, [r7, #12] +} + 80040de: bf00 nop + 80040e0: bf00 nop + 80040e2: e7fd b.n 80040e0 +} + 80040e4: bf00 nop + 80040e6: 3718 adds r7, #24 + 80040e8: 46bd mov sp, r7 + 80040ea: bd80 pop {r7, pc} + 80040ec: 08005d08 .word 0x08005d08 + 80040f0: 0800473d .word 0x0800473d + 80040f4: 20000e30 .word 0x20000e30 + 80040f8: 20000938 .word 0x20000938 + 80040fc: 20000010 .word 0x20000010 + 8004100: 20000e2c .word 0x20000e2c + 8004104: 20000e18 .word 0x20000e18 + 8004108: 20000e10 .word 0x20000e10 + +0800410c : + vPortEndScheduler(); +} +/*----------------------------------------------------------*/ + +void vTaskSuspendAll( void ) +{ + 800410c: b480 push {r7} + 800410e: af00 add r7, sp, #0 + do not otherwise exhibit real time behaviour. */ + portSOFTWARE_BARRIER(); + + /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment + is used to allow calls to vTaskSuspendAll() to nest. */ + ++uxSchedulerSuspended; + 8004110: 4b04 ldr r3, [pc, #16] @ (8004124 ) + 8004112: 681b ldr r3, [r3, #0] + 8004114: 3301 adds r3, #1 + 8004116: 4a03 ldr r2, [pc, #12] @ (8004124 ) + 8004118: 6013 str r3, [r2, #0] + + /* Enforces ordering for ports and optimised compilers that may otherwise place + the above increment elsewhere. */ + portMEMORY_BARRIER(); +} + 800411a: bf00 nop + 800411c: 46bd mov sp, r7 + 800411e: f85d 7b04 ldr.w r7, [sp], #4 + 8004122: 4770 bx lr + 8004124: 20000e34 .word 0x20000e34 + +08004128 : + +#endif /* configUSE_TICKLESS_IDLE */ +/*----------------------------------------------------------*/ + +BaseType_t xTaskResumeAll( void ) +{ + 8004128: b580 push {r7, lr} + 800412a: b084 sub sp, #16 + 800412c: af00 add r7, sp, #0 +TCB_t *pxTCB = NULL; + 800412e: 2300 movs r3, #0 + 8004130: 60fb str r3, [r7, #12] +BaseType_t xAlreadyYielded = pdFALSE; + 8004132: 2300 movs r3, #0 + 8004134: 60bb str r3, [r7, #8] + + /* If uxSchedulerSuspended is zero then this function does not match a + previous call to vTaskSuspendAll(). */ + configASSERT( uxSchedulerSuspended ); + 8004136: 4b42 ldr r3, [pc, #264] @ (8004240 ) + 8004138: 681b ldr r3, [r3, #0] + 800413a: 2b00 cmp r3, #0 + 800413c: d10b bne.n 8004156 + __asm volatile + 800413e: f04f 0350 mov.w r3, #80 @ 0x50 + 8004142: f383 8811 msr BASEPRI, r3 + 8004146: f3bf 8f6f isb sy + 800414a: f3bf 8f4f dsb sy + 800414e: 603b str r3, [r7, #0] +} + 8004150: bf00 nop + 8004152: bf00 nop + 8004154: e7fd b.n 8004152 + /* It is possible that an ISR caused a task to be removed from an event + list while the scheduler was suspended. If this was the case then the + removed task will have been added to the xPendingReadyList. Once the + scheduler has been resumed it is safe to move all the pending ready + tasks from this list into their appropriate ready list. */ + taskENTER_CRITICAL(); + 8004156: f001 f937 bl 80053c8 + { + --uxSchedulerSuspended; + 800415a: 4b39 ldr r3, [pc, #228] @ (8004240 ) + 800415c: 681b ldr r3, [r3, #0] + 800415e: 3b01 subs r3, #1 + 8004160: 4a37 ldr r2, [pc, #220] @ (8004240 ) + 8004162: 6013 str r3, [r2, #0] + + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + 8004164: 4b36 ldr r3, [pc, #216] @ (8004240 ) + 8004166: 681b ldr r3, [r3, #0] + 8004168: 2b00 cmp r3, #0 + 800416a: d162 bne.n 8004232 + { + if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) + 800416c: 4b35 ldr r3, [pc, #212] @ (8004244 ) + 800416e: 681b ldr r3, [r3, #0] + 8004170: 2b00 cmp r3, #0 + 8004172: d05e beq.n 8004232 + { + /* Move any readied tasks from the pending list into the + appropriate ready list. */ + while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) + 8004174: e02f b.n 80041d6 + { + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + 8004176: 4b34 ldr r3, [pc, #208] @ (8004248 ) + 8004178: 68db ldr r3, [r3, #12] + 800417a: 68db ldr r3, [r3, #12] + 800417c: 60fb str r3, [r7, #12] + ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); + 800417e: 68fb ldr r3, [r7, #12] + 8004180: 3318 adds r3, #24 + 8004182: 4618 mov r0, r3 + 8004184: f7ff f83a bl 80031fc + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + 8004188: 68fb ldr r3, [r7, #12] + 800418a: 3304 adds r3, #4 + 800418c: 4618 mov r0, r3 + 800418e: f7ff f835 bl 80031fc + prvAddTaskToReadyList( pxTCB ); + 8004192: 68fb ldr r3, [r7, #12] + 8004194: 6ada ldr r2, [r3, #44] @ 0x2c + 8004196: 4b2d ldr r3, [pc, #180] @ (800424c ) + 8004198: 681b ldr r3, [r3, #0] + 800419a: 429a cmp r2, r3 + 800419c: d903 bls.n 80041a6 + 800419e: 68fb ldr r3, [r7, #12] + 80041a0: 6adb ldr r3, [r3, #44] @ 0x2c + 80041a2: 4a2a ldr r2, [pc, #168] @ (800424c ) + 80041a4: 6013 str r3, [r2, #0] + 80041a6: 68fb ldr r3, [r7, #12] + 80041a8: 6ada ldr r2, [r3, #44] @ 0x2c + 80041aa: 4613 mov r3, r2 + 80041ac: 009b lsls r3, r3, #2 + 80041ae: 4413 add r3, r2 + 80041b0: 009b lsls r3, r3, #2 + 80041b2: 4a27 ldr r2, [pc, #156] @ (8004250 ) + 80041b4: 441a add r2, r3 + 80041b6: 68fb ldr r3, [r7, #12] + 80041b8: 3304 adds r3, #4 + 80041ba: 4619 mov r1, r3 + 80041bc: 4610 mov r0, r2 + 80041be: f7fe ffc0 bl 8003142 + + /* If the moved task has a priority higher than the current + task then a yield must be performed. */ + if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) + 80041c2: 68fb ldr r3, [r7, #12] + 80041c4: 6ada ldr r2, [r3, #44] @ 0x2c + 80041c6: 4b23 ldr r3, [pc, #140] @ (8004254 ) + 80041c8: 681b ldr r3, [r3, #0] + 80041ca: 6adb ldr r3, [r3, #44] @ 0x2c + 80041cc: 429a cmp r2, r3 + 80041ce: d302 bcc.n 80041d6 + { + xYieldPending = pdTRUE; + 80041d0: 4b21 ldr r3, [pc, #132] @ (8004258 ) + 80041d2: 2201 movs r2, #1 + 80041d4: 601a str r2, [r3, #0] + while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) + 80041d6: 4b1c ldr r3, [pc, #112] @ (8004248 ) + 80041d8: 681b ldr r3, [r3, #0] + 80041da: 2b00 cmp r3, #0 + 80041dc: d1cb bne.n 8004176 + { + mtCOVERAGE_TEST_MARKER(); + } + } + + if( pxTCB != NULL ) + 80041de: 68fb ldr r3, [r7, #12] + 80041e0: 2b00 cmp r3, #0 + 80041e2: d001 beq.n 80041e8 + which may have prevented the next unblock time from being + re-calculated, in which case re-calculate it now. Mainly + important for low power tickless implementations, where + this can prevent an unnecessary exit from low power + state. */ + prvResetNextTaskUnblockTime(); + 80041e4: f000 fb66 bl 80048b4 + /* If any ticks occurred while the scheduler was suspended then + they should be processed now. This ensures the tick count does + not slip, and that any delayed tasks are resumed at the correct + time. */ + { + TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */ + 80041e8: 4b1c ldr r3, [pc, #112] @ (800425c ) + 80041ea: 681b ldr r3, [r3, #0] + 80041ec: 607b str r3, [r7, #4] + + if( xPendedCounts > ( TickType_t ) 0U ) + 80041ee: 687b ldr r3, [r7, #4] + 80041f0: 2b00 cmp r3, #0 + 80041f2: d010 beq.n 8004216 + { + do + { + if( xTaskIncrementTick() != pdFALSE ) + 80041f4: f000 f846 bl 8004284 + 80041f8: 4603 mov r3, r0 + 80041fa: 2b00 cmp r3, #0 + 80041fc: d002 beq.n 8004204 + { + xYieldPending = pdTRUE; + 80041fe: 4b16 ldr r3, [pc, #88] @ (8004258 ) + 8004200: 2201 movs r2, #1 + 8004202: 601a str r2, [r3, #0] + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + --xPendedCounts; + 8004204: 687b ldr r3, [r7, #4] + 8004206: 3b01 subs r3, #1 + 8004208: 607b str r3, [r7, #4] + } while( xPendedCounts > ( TickType_t ) 0U ); + 800420a: 687b ldr r3, [r7, #4] + 800420c: 2b00 cmp r3, #0 + 800420e: d1f1 bne.n 80041f4 + + xPendedTicks = 0; + 8004210: 4b12 ldr r3, [pc, #72] @ (800425c ) + 8004212: 2200 movs r2, #0 + 8004214: 601a str r2, [r3, #0] + { + mtCOVERAGE_TEST_MARKER(); + } + } + + if( xYieldPending != pdFALSE ) + 8004216: 4b10 ldr r3, [pc, #64] @ (8004258 ) + 8004218: 681b ldr r3, [r3, #0] + 800421a: 2b00 cmp r3, #0 + 800421c: d009 beq.n 8004232 + { + #if( configUSE_PREEMPTION != 0 ) + { + xAlreadyYielded = pdTRUE; + 800421e: 2301 movs r3, #1 + 8004220: 60bb str r3, [r7, #8] + } + #endif + taskYIELD_IF_USING_PREEMPTION(); + 8004222: 4b0f ldr r3, [pc, #60] @ (8004260 ) + 8004224: f04f 5280 mov.w r2, #268435456 @ 0x10000000 + 8004228: 601a str r2, [r3, #0] + 800422a: f3bf 8f4f dsb sy + 800422e: f3bf 8f6f isb sy + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + 8004232: f001 f8fb bl 800542c + + return xAlreadyYielded; + 8004236: 68bb ldr r3, [r7, #8] +} + 8004238: 4618 mov r0, r3 + 800423a: 3710 adds r7, #16 + 800423c: 46bd mov sp, r7 + 800423e: bd80 pop {r7, pc} + 8004240: 20000e34 .word 0x20000e34 + 8004244: 20000e0c .word 0x20000e0c + 8004248: 20000dcc .word 0x20000dcc + 800424c: 20000e14 .word 0x20000e14 + 8004250: 2000093c .word 0x2000093c + 8004254: 20000938 .word 0x20000938 + 8004258: 20000e20 .word 0x20000e20 + 800425c: 20000e1c .word 0x20000e1c + 8004260: e000ed04 .word 0xe000ed04 + +08004264 : +/*-----------------------------------------------------------*/ + +TickType_t xTaskGetTickCount( void ) +{ + 8004264: b480 push {r7} + 8004266: b083 sub sp, #12 + 8004268: af00 add r7, sp, #0 +TickType_t xTicks; + + /* Critical section required if running on a 16 bit processor. */ + portTICK_TYPE_ENTER_CRITICAL(); + { + xTicks = xTickCount; + 800426a: 4b05 ldr r3, [pc, #20] @ (8004280 ) + 800426c: 681b ldr r3, [r3, #0] + 800426e: 607b str r3, [r7, #4] + } + portTICK_TYPE_EXIT_CRITICAL(); + + return xTicks; + 8004270: 687b ldr r3, [r7, #4] +} + 8004272: 4618 mov r0, r3 + 8004274: 370c adds r7, #12 + 8004276: 46bd mov sp, r7 + 8004278: f85d 7b04 ldr.w r7, [sp], #4 + 800427c: 4770 bx lr + 800427e: bf00 nop + 8004280: 20000e10 .word 0x20000e10 + +08004284 : + +#endif /* INCLUDE_xTaskAbortDelay */ +/*----------------------------------------------------------*/ + +BaseType_t xTaskIncrementTick( void ) +{ + 8004284: b580 push {r7, lr} + 8004286: b086 sub sp, #24 + 8004288: af00 add r7, sp, #0 +TCB_t * pxTCB; +TickType_t xItemValue; +BaseType_t xSwitchRequired = pdFALSE; + 800428a: 2300 movs r3, #0 + 800428c: 617b str r3, [r7, #20] + + /* Called by the portable layer each time a tick interrupt occurs. + Increments the tick then checks to see if the new tick value will cause any + tasks to be unblocked. */ + traceTASK_INCREMENT_TICK( xTickCount ); + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + 800428e: 4b4f ldr r3, [pc, #316] @ (80043cc ) + 8004290: 681b ldr r3, [r3, #0] + 8004292: 2b00 cmp r3, #0 + 8004294: f040 8090 bne.w 80043b8 + { + /* Minor optimisation. The tick count cannot change in this + block. */ + const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; + 8004298: 4b4d ldr r3, [pc, #308] @ (80043d0 ) + 800429a: 681b ldr r3, [r3, #0] + 800429c: 3301 adds r3, #1 + 800429e: 613b str r3, [r7, #16] + + /* Increment the RTOS tick, switching the delayed and overflowed + delayed lists if it wraps to 0. */ + xTickCount = xConstTickCount; + 80042a0: 4a4b ldr r2, [pc, #300] @ (80043d0 ) + 80042a2: 693b ldr r3, [r7, #16] + 80042a4: 6013 str r3, [r2, #0] + + if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */ + 80042a6: 693b ldr r3, [r7, #16] + 80042a8: 2b00 cmp r3, #0 + 80042aa: d121 bne.n 80042f0 + { + taskSWITCH_DELAYED_LISTS(); + 80042ac: 4b49 ldr r3, [pc, #292] @ (80043d4 ) + 80042ae: 681b ldr r3, [r3, #0] + 80042b0: 681b ldr r3, [r3, #0] + 80042b2: 2b00 cmp r3, #0 + 80042b4: d00b beq.n 80042ce + __asm volatile + 80042b6: f04f 0350 mov.w r3, #80 @ 0x50 + 80042ba: f383 8811 msr BASEPRI, r3 + 80042be: f3bf 8f6f isb sy + 80042c2: f3bf 8f4f dsb sy + 80042c6: 603b str r3, [r7, #0] +} + 80042c8: bf00 nop + 80042ca: bf00 nop + 80042cc: e7fd b.n 80042ca + 80042ce: 4b41 ldr r3, [pc, #260] @ (80043d4 ) + 80042d0: 681b ldr r3, [r3, #0] + 80042d2: 60fb str r3, [r7, #12] + 80042d4: 4b40 ldr r3, [pc, #256] @ (80043d8 ) + 80042d6: 681b ldr r3, [r3, #0] + 80042d8: 4a3e ldr r2, [pc, #248] @ (80043d4 ) + 80042da: 6013 str r3, [r2, #0] + 80042dc: 4a3e ldr r2, [pc, #248] @ (80043d8 ) + 80042de: 68fb ldr r3, [r7, #12] + 80042e0: 6013 str r3, [r2, #0] + 80042e2: 4b3e ldr r3, [pc, #248] @ (80043dc ) + 80042e4: 681b ldr r3, [r3, #0] + 80042e6: 3301 adds r3, #1 + 80042e8: 4a3c ldr r2, [pc, #240] @ (80043dc ) + 80042ea: 6013 str r3, [r2, #0] + 80042ec: f000 fae2 bl 80048b4 + + /* See if this tick has made a timeout expire. Tasks are stored in + the queue in the order of their wake time - meaning once one task + has been found whose block time has not expired there is no need to + look any further down the list. */ + if( xConstTickCount >= xNextTaskUnblockTime ) + 80042f0: 4b3b ldr r3, [pc, #236] @ (80043e0 ) + 80042f2: 681b ldr r3, [r3, #0] + 80042f4: 693a ldr r2, [r7, #16] + 80042f6: 429a cmp r2, r3 + 80042f8: d349 bcc.n 800438e + { + for( ;; ) + { + if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) + 80042fa: 4b36 ldr r3, [pc, #216] @ (80043d4 ) + 80042fc: 681b ldr r3, [r3, #0] + 80042fe: 681b ldr r3, [r3, #0] + 8004300: 2b00 cmp r3, #0 + 8004302: d104 bne.n 800430e + /* The delayed list is empty. Set xNextTaskUnblockTime + to the maximum possible value so it is extremely + unlikely that the + if( xTickCount >= xNextTaskUnblockTime ) test will pass + next time through. */ + xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 8004304: 4b36 ldr r3, [pc, #216] @ (80043e0 ) + 8004306: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 800430a: 601a str r2, [r3, #0] + break; + 800430c: e03f b.n 800438e + { + /* The delayed list is not empty, get the value of the + item at the head of the delayed list. This is the time + at which the task at the head of the delayed list must + be removed from the Blocked state. */ + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + 800430e: 4b31 ldr r3, [pc, #196] @ (80043d4 ) + 8004310: 681b ldr r3, [r3, #0] + 8004312: 68db ldr r3, [r3, #12] + 8004314: 68db ldr r3, [r3, #12] + 8004316: 60bb str r3, [r7, #8] + xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); + 8004318: 68bb ldr r3, [r7, #8] + 800431a: 685b ldr r3, [r3, #4] + 800431c: 607b str r3, [r7, #4] + + if( xConstTickCount < xItemValue ) + 800431e: 693a ldr r2, [r7, #16] + 8004320: 687b ldr r3, [r7, #4] + 8004322: 429a cmp r2, r3 + 8004324: d203 bcs.n 800432e + /* It is not time to unblock this item yet, but the + item value is the time at which the task at the head + of the blocked list must be removed from the Blocked + state - so record the item value in + xNextTaskUnblockTime. */ + xNextTaskUnblockTime = xItemValue; + 8004326: 4a2e ldr r2, [pc, #184] @ (80043e0 ) + 8004328: 687b ldr r3, [r7, #4] + 800432a: 6013 str r3, [r2, #0] + break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */ + 800432c: e02f b.n 800438e + { + mtCOVERAGE_TEST_MARKER(); + } + + /* It is time to remove the item from the Blocked state. */ + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + 800432e: 68bb ldr r3, [r7, #8] + 8004330: 3304 adds r3, #4 + 8004332: 4618 mov r0, r3 + 8004334: f7fe ff62 bl 80031fc + + /* Is the task waiting on an event also? If so remove + it from the event list. */ + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) + 8004338: 68bb ldr r3, [r7, #8] + 800433a: 6a9b ldr r3, [r3, #40] @ 0x28 + 800433c: 2b00 cmp r3, #0 + 800433e: d004 beq.n 800434a + { + ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); + 8004340: 68bb ldr r3, [r7, #8] + 8004342: 3318 adds r3, #24 + 8004344: 4618 mov r0, r3 + 8004346: f7fe ff59 bl 80031fc + mtCOVERAGE_TEST_MARKER(); + } + + /* Place the unblocked task into the appropriate ready + list. */ + prvAddTaskToReadyList( pxTCB ); + 800434a: 68bb ldr r3, [r7, #8] + 800434c: 6ada ldr r2, [r3, #44] @ 0x2c + 800434e: 4b25 ldr r3, [pc, #148] @ (80043e4 ) + 8004350: 681b ldr r3, [r3, #0] + 8004352: 429a cmp r2, r3 + 8004354: d903 bls.n 800435e + 8004356: 68bb ldr r3, [r7, #8] + 8004358: 6adb ldr r3, [r3, #44] @ 0x2c + 800435a: 4a22 ldr r2, [pc, #136] @ (80043e4 ) + 800435c: 6013 str r3, [r2, #0] + 800435e: 68bb ldr r3, [r7, #8] + 8004360: 6ada ldr r2, [r3, #44] @ 0x2c + 8004362: 4613 mov r3, r2 + 8004364: 009b lsls r3, r3, #2 + 8004366: 4413 add r3, r2 + 8004368: 009b lsls r3, r3, #2 + 800436a: 4a1f ldr r2, [pc, #124] @ (80043e8 ) + 800436c: 441a add r2, r3 + 800436e: 68bb ldr r3, [r7, #8] + 8004370: 3304 adds r3, #4 + 8004372: 4619 mov r1, r3 + 8004374: 4610 mov r0, r2 + 8004376: f7fe fee4 bl 8003142 + { + /* Preemption is on, but a context switch should + only be performed if the unblocked task has a + priority that is equal to or higher than the + currently executing task. */ + if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) + 800437a: 68bb ldr r3, [r7, #8] + 800437c: 6ada ldr r2, [r3, #44] @ 0x2c + 800437e: 4b1b ldr r3, [pc, #108] @ (80043ec ) + 8004380: 681b ldr r3, [r3, #0] + 8004382: 6adb ldr r3, [r3, #44] @ 0x2c + 8004384: 429a cmp r2, r3 + 8004386: d3b8 bcc.n 80042fa + { + xSwitchRequired = pdTRUE; + 8004388: 2301 movs r3, #1 + 800438a: 617b str r3, [r7, #20] + if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) + 800438c: e7b5 b.n 80042fa + /* Tasks of equal priority to the currently running task will share + processing time (time slice) if preemption is on, and the application + writer has not explicitly turned time slicing off. */ + #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) + { + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) + 800438e: 4b17 ldr r3, [pc, #92] @ (80043ec ) + 8004390: 681b ldr r3, [r3, #0] + 8004392: 6ada ldr r2, [r3, #44] @ 0x2c + 8004394: 4914 ldr r1, [pc, #80] @ (80043e8 ) + 8004396: 4613 mov r3, r2 + 8004398: 009b lsls r3, r3, #2 + 800439a: 4413 add r3, r2 + 800439c: 009b lsls r3, r3, #2 + 800439e: 440b add r3, r1 + 80043a0: 681b ldr r3, [r3, #0] + 80043a2: 2b01 cmp r3, #1 + 80043a4: d901 bls.n 80043aa + { + xSwitchRequired = pdTRUE; + 80043a6: 2301 movs r3, #1 + 80043a8: 617b str r3, [r7, #20] + } + #endif /* configUSE_TICK_HOOK */ + + #if ( configUSE_PREEMPTION == 1 ) + { + if( xYieldPending != pdFALSE ) + 80043aa: 4b11 ldr r3, [pc, #68] @ (80043f0 ) + 80043ac: 681b ldr r3, [r3, #0] + 80043ae: 2b00 cmp r3, #0 + 80043b0: d007 beq.n 80043c2 + { + xSwitchRequired = pdTRUE; + 80043b2: 2301 movs r3, #1 + 80043b4: 617b str r3, [r7, #20] + 80043b6: e004 b.n 80043c2 + } + #endif /* configUSE_PREEMPTION */ + } + else + { + ++xPendedTicks; + 80043b8: 4b0e ldr r3, [pc, #56] @ (80043f4 ) + 80043ba: 681b ldr r3, [r3, #0] + 80043bc: 3301 adds r3, #1 + 80043be: 4a0d ldr r2, [pc, #52] @ (80043f4 ) + 80043c0: 6013 str r3, [r2, #0] + vApplicationTickHook(); + } + #endif + } + + return xSwitchRequired; + 80043c2: 697b ldr r3, [r7, #20] +} + 80043c4: 4618 mov r0, r3 + 80043c6: 3718 adds r7, #24 + 80043c8: 46bd mov sp, r7 + 80043ca: bd80 pop {r7, pc} + 80043cc: 20000e34 .word 0x20000e34 + 80043d0: 20000e10 .word 0x20000e10 + 80043d4: 20000dc4 .word 0x20000dc4 + 80043d8: 20000dc8 .word 0x20000dc8 + 80043dc: 20000e24 .word 0x20000e24 + 80043e0: 20000e2c .word 0x20000e2c + 80043e4: 20000e14 .word 0x20000e14 + 80043e8: 2000093c .word 0x2000093c + 80043ec: 20000938 .word 0x20000938 + 80043f0: 20000e20 .word 0x20000e20 + 80043f4: 20000e1c .word 0x20000e1c + +080043f8 : + +#endif /* configUSE_APPLICATION_TASK_TAG */ +/*-----------------------------------------------------------*/ + +void vTaskSwitchContext( void ) +{ + 80043f8: b480 push {r7} + 80043fa: b085 sub sp, #20 + 80043fc: af00 add r7, sp, #0 + if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE ) + 80043fe: 4b2b ldr r3, [pc, #172] @ (80044ac ) + 8004400: 681b ldr r3, [r3, #0] + 8004402: 2b00 cmp r3, #0 + 8004404: d003 beq.n 800440e + { + /* The scheduler is currently suspended - do not allow a context + switch. */ + xYieldPending = pdTRUE; + 8004406: 4b2a ldr r3, [pc, #168] @ (80044b0 ) + 8004408: 2201 movs r2, #1 + 800440a: 601a str r2, [r3, #0] + for additional information. */ + _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); + } + #endif /* configUSE_NEWLIB_REENTRANT */ + } +} + 800440c: e047 b.n 800449e + xYieldPending = pdFALSE; + 800440e: 4b28 ldr r3, [pc, #160] @ (80044b0 ) + 8004410: 2200 movs r2, #0 + 8004412: 601a str r2, [r3, #0] + taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + 8004414: 4b27 ldr r3, [pc, #156] @ (80044b4 ) + 8004416: 681b ldr r3, [r3, #0] + 8004418: 60fb str r3, [r7, #12] + 800441a: e011 b.n 8004440 + 800441c: 68fb ldr r3, [r7, #12] + 800441e: 2b00 cmp r3, #0 + 8004420: d10b bne.n 800443a + __asm volatile + 8004422: f04f 0350 mov.w r3, #80 @ 0x50 + 8004426: f383 8811 msr BASEPRI, r3 + 800442a: f3bf 8f6f isb sy + 800442e: f3bf 8f4f dsb sy + 8004432: 607b str r3, [r7, #4] +} + 8004434: bf00 nop + 8004436: bf00 nop + 8004438: e7fd b.n 8004436 + 800443a: 68fb ldr r3, [r7, #12] + 800443c: 3b01 subs r3, #1 + 800443e: 60fb str r3, [r7, #12] + 8004440: 491d ldr r1, [pc, #116] @ (80044b8 ) + 8004442: 68fa ldr r2, [r7, #12] + 8004444: 4613 mov r3, r2 + 8004446: 009b lsls r3, r3, #2 + 8004448: 4413 add r3, r2 + 800444a: 009b lsls r3, r3, #2 + 800444c: 440b add r3, r1 + 800444e: 681b ldr r3, [r3, #0] + 8004450: 2b00 cmp r3, #0 + 8004452: d0e3 beq.n 800441c + 8004454: 68fa ldr r2, [r7, #12] + 8004456: 4613 mov r3, r2 + 8004458: 009b lsls r3, r3, #2 + 800445a: 4413 add r3, r2 + 800445c: 009b lsls r3, r3, #2 + 800445e: 4a16 ldr r2, [pc, #88] @ (80044b8 ) + 8004460: 4413 add r3, r2 + 8004462: 60bb str r3, [r7, #8] + 8004464: 68bb ldr r3, [r7, #8] + 8004466: 685b ldr r3, [r3, #4] + 8004468: 685a ldr r2, [r3, #4] + 800446a: 68bb ldr r3, [r7, #8] + 800446c: 605a str r2, [r3, #4] + 800446e: 68bb ldr r3, [r7, #8] + 8004470: 685a ldr r2, [r3, #4] + 8004472: 68bb ldr r3, [r7, #8] + 8004474: 3308 adds r3, #8 + 8004476: 429a cmp r2, r3 + 8004478: d104 bne.n 8004484 + 800447a: 68bb ldr r3, [r7, #8] + 800447c: 685b ldr r3, [r3, #4] + 800447e: 685a ldr r2, [r3, #4] + 8004480: 68bb ldr r3, [r7, #8] + 8004482: 605a str r2, [r3, #4] + 8004484: 68bb ldr r3, [r7, #8] + 8004486: 685b ldr r3, [r3, #4] + 8004488: 68db ldr r3, [r3, #12] + 800448a: 4a0c ldr r2, [pc, #48] @ (80044bc ) + 800448c: 6013 str r3, [r2, #0] + 800448e: 4a09 ldr r2, [pc, #36] @ (80044b4 ) + 8004490: 68fb ldr r3, [r7, #12] + 8004492: 6013 str r3, [r2, #0] + _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); + 8004494: 4b09 ldr r3, [pc, #36] @ (80044bc ) + 8004496: 681b ldr r3, [r3, #0] + 8004498: 3354 adds r3, #84 @ 0x54 + 800449a: 4a09 ldr r2, [pc, #36] @ (80044c0 ) + 800449c: 6013 str r3, [r2, #0] +} + 800449e: bf00 nop + 80044a0: 3714 adds r7, #20 + 80044a2: 46bd mov sp, r7 + 80044a4: f85d 7b04 ldr.w r7, [sp], #4 + 80044a8: 4770 bx lr + 80044aa: bf00 nop + 80044ac: 20000e34 .word 0x20000e34 + 80044b0: 20000e20 .word 0x20000e20 + 80044b4: 20000e14 .word 0x20000e14 + 80044b8: 2000093c .word 0x2000093c + 80044bc: 20000938 .word 0x20000938 + 80044c0: 20000010 .word 0x20000010 + +080044c4 : +/*-----------------------------------------------------------*/ + +void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) +{ + 80044c4: b580 push {r7, lr} + 80044c6: b084 sub sp, #16 + 80044c8: af00 add r7, sp, #0 + 80044ca: 6078 str r0, [r7, #4] + 80044cc: 6039 str r1, [r7, #0] + configASSERT( pxEventList ); + 80044ce: 687b ldr r3, [r7, #4] + 80044d0: 2b00 cmp r3, #0 + 80044d2: d10b bne.n 80044ec + __asm volatile + 80044d4: f04f 0350 mov.w r3, #80 @ 0x50 + 80044d8: f383 8811 msr BASEPRI, r3 + 80044dc: f3bf 8f6f isb sy + 80044e0: f3bf 8f4f dsb sy + 80044e4: 60fb str r3, [r7, #12] +} + 80044e6: bf00 nop + 80044e8: bf00 nop + 80044ea: e7fd b.n 80044e8 + + /* Place the event list item of the TCB in the appropriate event list. + This is placed in the list in priority order so the highest priority task + is the first to be woken by the event. The queue that contains the event + list is locked, preventing simultaneous access from interrupts. */ + vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) ); + 80044ec: 4b07 ldr r3, [pc, #28] @ (800450c ) + 80044ee: 681b ldr r3, [r3, #0] + 80044f0: 3318 adds r3, #24 + 80044f2: 4619 mov r1, r3 + 80044f4: 6878 ldr r0, [r7, #4] + 80044f6: f7fe fe48 bl 800318a + + prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); + 80044fa: 2101 movs r1, #1 + 80044fc: 6838 ldr r0, [r7, #0] + 80044fe: f000 fa87 bl 8004a10 +} + 8004502: bf00 nop + 8004504: 3710 adds r7, #16 + 8004506: 46bd mov sp, r7 + 8004508: bd80 pop {r7, pc} + 800450a: bf00 nop + 800450c: 20000938 .word 0x20000938 + +08004510 : +/*-----------------------------------------------------------*/ + +#if( configUSE_TIMERS == 1 ) + + void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) + { + 8004510: b580 push {r7, lr} + 8004512: b086 sub sp, #24 + 8004514: af00 add r7, sp, #0 + 8004516: 60f8 str r0, [r7, #12] + 8004518: 60b9 str r1, [r7, #8] + 800451a: 607a str r2, [r7, #4] + configASSERT( pxEventList ); + 800451c: 68fb ldr r3, [r7, #12] + 800451e: 2b00 cmp r3, #0 + 8004520: d10b bne.n 800453a + __asm volatile + 8004522: f04f 0350 mov.w r3, #80 @ 0x50 + 8004526: f383 8811 msr BASEPRI, r3 + 800452a: f3bf 8f6f isb sy + 800452e: f3bf 8f4f dsb sy + 8004532: 617b str r3, [r7, #20] +} + 8004534: bf00 nop + 8004536: bf00 nop + 8004538: e7fd b.n 8004536 + + /* Place the event list item of the TCB in the appropriate event list. + In this case it is assume that this is the only task that is going to + be waiting on this event list, so the faster vListInsertEnd() function + can be used in place of vListInsert. */ + vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) ); + 800453a: 4b0a ldr r3, [pc, #40] @ (8004564 ) + 800453c: 681b ldr r3, [r3, #0] + 800453e: 3318 adds r3, #24 + 8004540: 4619 mov r1, r3 + 8004542: 68f8 ldr r0, [r7, #12] + 8004544: f7fe fdfd bl 8003142 + + /* If the task should block indefinitely then set the block time to a + value that will be recognised as an indefinite delay inside the + prvAddCurrentTaskToDelayedList() function. */ + if( xWaitIndefinitely != pdFALSE ) + 8004548: 687b ldr r3, [r7, #4] + 800454a: 2b00 cmp r3, #0 + 800454c: d002 beq.n 8004554 + { + xTicksToWait = portMAX_DELAY; + 800454e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 8004552: 60bb str r3, [r7, #8] + } + + traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) ); + prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely ); + 8004554: 6879 ldr r1, [r7, #4] + 8004556: 68b8 ldr r0, [r7, #8] + 8004558: f000 fa5a bl 8004a10 + } + 800455c: bf00 nop + 800455e: 3718 adds r7, #24 + 8004560: 46bd mov sp, r7 + 8004562: bd80 pop {r7, pc} + 8004564: 20000938 .word 0x20000938 + +08004568 : + +#endif /* configUSE_TIMERS */ +/*-----------------------------------------------------------*/ + +BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) +{ + 8004568: b580 push {r7, lr} + 800456a: b086 sub sp, #24 + 800456c: af00 add r7, sp, #0 + 800456e: 6078 str r0, [r7, #4] + get called - the lock count on the queue will get modified instead. This + means exclusive access to the event list is guaranteed here. + + This function assumes that a check has already been made to ensure that + pxEventList is not empty. */ + pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + 8004570: 687b ldr r3, [r7, #4] + 8004572: 68db ldr r3, [r3, #12] + 8004574: 68db ldr r3, [r3, #12] + 8004576: 613b str r3, [r7, #16] + configASSERT( pxUnblockedTCB ); + 8004578: 693b ldr r3, [r7, #16] + 800457a: 2b00 cmp r3, #0 + 800457c: d10b bne.n 8004596 + __asm volatile + 800457e: f04f 0350 mov.w r3, #80 @ 0x50 + 8004582: f383 8811 msr BASEPRI, r3 + 8004586: f3bf 8f6f isb sy + 800458a: f3bf 8f4f dsb sy + 800458e: 60fb str r3, [r7, #12] +} + 8004590: bf00 nop + 8004592: bf00 nop + 8004594: e7fd b.n 8004592 + ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) ); + 8004596: 693b ldr r3, [r7, #16] + 8004598: 3318 adds r3, #24 + 800459a: 4618 mov r0, r3 + 800459c: f7fe fe2e bl 80031fc + + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + 80045a0: 4b1d ldr r3, [pc, #116] @ (8004618 ) + 80045a2: 681b ldr r3, [r3, #0] + 80045a4: 2b00 cmp r3, #0 + 80045a6: d11d bne.n 80045e4 + { + ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) ); + 80045a8: 693b ldr r3, [r7, #16] + 80045aa: 3304 adds r3, #4 + 80045ac: 4618 mov r0, r3 + 80045ae: f7fe fe25 bl 80031fc + prvAddTaskToReadyList( pxUnblockedTCB ); + 80045b2: 693b ldr r3, [r7, #16] + 80045b4: 6ada ldr r2, [r3, #44] @ 0x2c + 80045b6: 4b19 ldr r3, [pc, #100] @ (800461c ) + 80045b8: 681b ldr r3, [r3, #0] + 80045ba: 429a cmp r2, r3 + 80045bc: d903 bls.n 80045c6 + 80045be: 693b ldr r3, [r7, #16] + 80045c0: 6adb ldr r3, [r3, #44] @ 0x2c + 80045c2: 4a16 ldr r2, [pc, #88] @ (800461c ) + 80045c4: 6013 str r3, [r2, #0] + 80045c6: 693b ldr r3, [r7, #16] + 80045c8: 6ada ldr r2, [r3, #44] @ 0x2c + 80045ca: 4613 mov r3, r2 + 80045cc: 009b lsls r3, r3, #2 + 80045ce: 4413 add r3, r2 + 80045d0: 009b lsls r3, r3, #2 + 80045d2: 4a13 ldr r2, [pc, #76] @ (8004620 ) + 80045d4: 441a add r2, r3 + 80045d6: 693b ldr r3, [r7, #16] + 80045d8: 3304 adds r3, #4 + 80045da: 4619 mov r1, r3 + 80045dc: 4610 mov r0, r2 + 80045de: f7fe fdb0 bl 8003142 + 80045e2: e005 b.n 80045f0 + } + else + { + /* The delayed and ready lists cannot be accessed, so hold this task + pending until the scheduler is resumed. */ + vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); + 80045e4: 693b ldr r3, [r7, #16] + 80045e6: 3318 adds r3, #24 + 80045e8: 4619 mov r1, r3 + 80045ea: 480e ldr r0, [pc, #56] @ (8004624 ) + 80045ec: f7fe fda9 bl 8003142 + } + + if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) + 80045f0: 693b ldr r3, [r7, #16] + 80045f2: 6ada ldr r2, [r3, #44] @ 0x2c + 80045f4: 4b0c ldr r3, [pc, #48] @ (8004628 ) + 80045f6: 681b ldr r3, [r3, #0] + 80045f8: 6adb ldr r3, [r3, #44] @ 0x2c + 80045fa: 429a cmp r2, r3 + 80045fc: d905 bls.n 800460a + { + /* Return true if the task removed from the event list has a higher + priority than the calling task. This allows the calling task to know if + it should force a context switch now. */ + xReturn = pdTRUE; + 80045fe: 2301 movs r3, #1 + 8004600: 617b str r3, [r7, #20] + + /* Mark that a yield is pending in case the user is not using the + "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ + xYieldPending = pdTRUE; + 8004602: 4b0a ldr r3, [pc, #40] @ (800462c ) + 8004604: 2201 movs r2, #1 + 8004606: 601a str r2, [r3, #0] + 8004608: e001 b.n 800460e + } + else + { + xReturn = pdFALSE; + 800460a: 2300 movs r3, #0 + 800460c: 617b str r3, [r7, #20] + } + + return xReturn; + 800460e: 697b ldr r3, [r7, #20] +} + 8004610: 4618 mov r0, r3 + 8004612: 3718 adds r7, #24 + 8004614: 46bd mov sp, r7 + 8004616: bd80 pop {r7, pc} + 8004618: 20000e34 .word 0x20000e34 + 800461c: 20000e14 .word 0x20000e14 + 8004620: 2000093c .word 0x2000093c + 8004624: 20000dcc .word 0x20000dcc + 8004628: 20000938 .word 0x20000938 + 800462c: 20000e20 .word 0x20000e20 + +08004630 : + taskEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) +{ + 8004630: b480 push {r7} + 8004632: b083 sub sp, #12 + 8004634: af00 add r7, sp, #0 + 8004636: 6078 str r0, [r7, #4] + /* For internal use only as it does not use a critical section. */ + pxTimeOut->xOverflowCount = xNumOfOverflows; + 8004638: 4b06 ldr r3, [pc, #24] @ (8004654 ) + 800463a: 681a ldr r2, [r3, #0] + 800463c: 687b ldr r3, [r7, #4] + 800463e: 601a str r2, [r3, #0] + pxTimeOut->xTimeOnEntering = xTickCount; + 8004640: 4b05 ldr r3, [pc, #20] @ (8004658 ) + 8004642: 681a ldr r2, [r3, #0] + 8004644: 687b ldr r3, [r7, #4] + 8004646: 605a str r2, [r3, #4] +} + 8004648: bf00 nop + 800464a: 370c adds r7, #12 + 800464c: 46bd mov sp, r7 + 800464e: f85d 7b04 ldr.w r7, [sp], #4 + 8004652: 4770 bx lr + 8004654: 20000e24 .word 0x20000e24 + 8004658: 20000e10 .word 0x20000e10 + +0800465c : +/*-----------------------------------------------------------*/ + +BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) +{ + 800465c: b580 push {r7, lr} + 800465e: b088 sub sp, #32 + 8004660: af00 add r7, sp, #0 + 8004662: 6078 str r0, [r7, #4] + 8004664: 6039 str r1, [r7, #0] +BaseType_t xReturn; + + configASSERT( pxTimeOut ); + 8004666: 687b ldr r3, [r7, #4] + 8004668: 2b00 cmp r3, #0 + 800466a: d10b bne.n 8004684 + __asm volatile + 800466c: f04f 0350 mov.w r3, #80 @ 0x50 + 8004670: f383 8811 msr BASEPRI, r3 + 8004674: f3bf 8f6f isb sy + 8004678: f3bf 8f4f dsb sy + 800467c: 613b str r3, [r7, #16] +} + 800467e: bf00 nop + 8004680: bf00 nop + 8004682: e7fd b.n 8004680 + configASSERT( pxTicksToWait ); + 8004684: 683b ldr r3, [r7, #0] + 8004686: 2b00 cmp r3, #0 + 8004688: d10b bne.n 80046a2 + __asm volatile + 800468a: f04f 0350 mov.w r3, #80 @ 0x50 + 800468e: f383 8811 msr BASEPRI, r3 + 8004692: f3bf 8f6f isb sy + 8004696: f3bf 8f4f dsb sy + 800469a: 60fb str r3, [r7, #12] +} + 800469c: bf00 nop + 800469e: bf00 nop + 80046a0: e7fd b.n 800469e + + taskENTER_CRITICAL(); + 80046a2: f000 fe91 bl 80053c8 + { + /* Minor optimisation. The tick count cannot change in this block. */ + const TickType_t xConstTickCount = xTickCount; + 80046a6: 4b1d ldr r3, [pc, #116] @ (800471c ) + 80046a8: 681b ldr r3, [r3, #0] + 80046aa: 61bb str r3, [r7, #24] + const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering; + 80046ac: 687b ldr r3, [r7, #4] + 80046ae: 685b ldr r3, [r3, #4] + 80046b0: 69ba ldr r2, [r7, #24] + 80046b2: 1ad3 subs r3, r2, r3 + 80046b4: 617b str r3, [r7, #20] + } + else + #endif + + #if ( INCLUDE_vTaskSuspend == 1 ) + if( *pxTicksToWait == portMAX_DELAY ) + 80046b6: 683b ldr r3, [r7, #0] + 80046b8: 681b ldr r3, [r3, #0] + 80046ba: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 80046be: d102 bne.n 80046c6 + { + /* If INCLUDE_vTaskSuspend is set to 1 and the block time + specified is the maximum block time then the task should block + indefinitely, and therefore never time out. */ + xReturn = pdFALSE; + 80046c0: 2300 movs r3, #0 + 80046c2: 61fb str r3, [r7, #28] + 80046c4: e023 b.n 800470e + } + else + #endif + + if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */ + 80046c6: 687b ldr r3, [r7, #4] + 80046c8: 681a ldr r2, [r3, #0] + 80046ca: 4b15 ldr r3, [pc, #84] @ (8004720 ) + 80046cc: 681b ldr r3, [r3, #0] + 80046ce: 429a cmp r2, r3 + 80046d0: d007 beq.n 80046e2 + 80046d2: 687b ldr r3, [r7, #4] + 80046d4: 685b ldr r3, [r3, #4] + 80046d6: 69ba ldr r2, [r7, #24] + 80046d8: 429a cmp r2, r3 + 80046da: d302 bcc.n 80046e2 + /* The tick count is greater than the time at which + vTaskSetTimeout() was called, but has also overflowed since + vTaskSetTimeOut() was called. It must have wrapped all the way + around and gone past again. This passed since vTaskSetTimeout() + was called. */ + xReturn = pdTRUE; + 80046dc: 2301 movs r3, #1 + 80046de: 61fb str r3, [r7, #28] + 80046e0: e015 b.n 800470e + } + else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */ + 80046e2: 683b ldr r3, [r7, #0] + 80046e4: 681b ldr r3, [r3, #0] + 80046e6: 697a ldr r2, [r7, #20] + 80046e8: 429a cmp r2, r3 + 80046ea: d20b bcs.n 8004704 + { + /* Not a genuine timeout. Adjust parameters for time remaining. */ + *pxTicksToWait -= xElapsedTime; + 80046ec: 683b ldr r3, [r7, #0] + 80046ee: 681a ldr r2, [r3, #0] + 80046f0: 697b ldr r3, [r7, #20] + 80046f2: 1ad2 subs r2, r2, r3 + 80046f4: 683b ldr r3, [r7, #0] + 80046f6: 601a str r2, [r3, #0] + vTaskInternalSetTimeOutState( pxTimeOut ); + 80046f8: 6878 ldr r0, [r7, #4] + 80046fa: f7ff ff99 bl 8004630 + xReturn = pdFALSE; + 80046fe: 2300 movs r3, #0 + 8004700: 61fb str r3, [r7, #28] + 8004702: e004 b.n 800470e + } + else + { + *pxTicksToWait = 0; + 8004704: 683b ldr r3, [r7, #0] + 8004706: 2200 movs r2, #0 + 8004708: 601a str r2, [r3, #0] + xReturn = pdTRUE; + 800470a: 2301 movs r3, #1 + 800470c: 61fb str r3, [r7, #28] + } + } + taskEXIT_CRITICAL(); + 800470e: f000 fe8d bl 800542c + + return xReturn; + 8004712: 69fb ldr r3, [r7, #28] +} + 8004714: 4618 mov r0, r3 + 8004716: 3720 adds r7, #32 + 8004718: 46bd mov sp, r7 + 800471a: bd80 pop {r7, pc} + 800471c: 20000e10 .word 0x20000e10 + 8004720: 20000e24 .word 0x20000e24 + +08004724 : +/*-----------------------------------------------------------*/ + +void vTaskMissedYield( void ) +{ + 8004724: b480 push {r7} + 8004726: af00 add r7, sp, #0 + xYieldPending = pdTRUE; + 8004728: 4b03 ldr r3, [pc, #12] @ (8004738 ) + 800472a: 2201 movs r2, #1 + 800472c: 601a str r2, [r3, #0] +} + 800472e: bf00 nop + 8004730: 46bd mov sp, r7 + 8004732: f85d 7b04 ldr.w r7, [sp], #4 + 8004736: 4770 bx lr + 8004738: 20000e20 .word 0x20000e20 + +0800473c : + * + * void prvIdleTask( void *pvParameters ); + * + */ +static portTASK_FUNCTION( prvIdleTask, pvParameters ) +{ + 800473c: b580 push {r7, lr} + 800473e: b082 sub sp, #8 + 8004740: af00 add r7, sp, #0 + 8004742: 6078 str r0, [r7, #4] + + for( ;; ) + { + /* See if any tasks have deleted themselves - if so then the idle task + is responsible for freeing the deleted task's TCB and stack. */ + prvCheckTasksWaitingTermination(); + 8004744: f000 f852 bl 80047ec + + A critical region is not required here as we are just reading from + the list, and an occasional incorrect value will not matter. If + the ready list at the idle priority contains more than one task + then a task other than the idle task is ready to execute. */ + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 ) + 8004748: 4b06 ldr r3, [pc, #24] @ (8004764 ) + 800474a: 681b ldr r3, [r3, #0] + 800474c: 2b01 cmp r3, #1 + 800474e: d9f9 bls.n 8004744 + { + taskYIELD(); + 8004750: 4b05 ldr r3, [pc, #20] @ (8004768 ) + 8004752: f04f 5280 mov.w r2, #268435456 @ 0x10000000 + 8004756: 601a str r2, [r3, #0] + 8004758: f3bf 8f4f dsb sy + 800475c: f3bf 8f6f isb sy + prvCheckTasksWaitingTermination(); + 8004760: e7f0 b.n 8004744 + 8004762: bf00 nop + 8004764: 2000093c .word 0x2000093c + 8004768: e000ed04 .word 0xe000ed04 + +0800476c : + +#endif /* portUSING_MPU_WRAPPERS */ +/*-----------------------------------------------------------*/ + +static void prvInitialiseTaskLists( void ) +{ + 800476c: b580 push {r7, lr} + 800476e: b082 sub sp, #8 + 8004770: af00 add r7, sp, #0 +UBaseType_t uxPriority; + + for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) + 8004772: 2300 movs r3, #0 + 8004774: 607b str r3, [r7, #4] + 8004776: e00c b.n 8004792 + { + vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) ); + 8004778: 687a ldr r2, [r7, #4] + 800477a: 4613 mov r3, r2 + 800477c: 009b lsls r3, r3, #2 + 800477e: 4413 add r3, r2 + 8004780: 009b lsls r3, r3, #2 + 8004782: 4a12 ldr r2, [pc, #72] @ (80047cc ) + 8004784: 4413 add r3, r2 + 8004786: 4618 mov r0, r3 + 8004788: f7fe fcae bl 80030e8 + for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) + 800478c: 687b ldr r3, [r7, #4] + 800478e: 3301 adds r3, #1 + 8004790: 607b str r3, [r7, #4] + 8004792: 687b ldr r3, [r7, #4] + 8004794: 2b37 cmp r3, #55 @ 0x37 + 8004796: d9ef bls.n 8004778 + } + + vListInitialise( &xDelayedTaskList1 ); + 8004798: 480d ldr r0, [pc, #52] @ (80047d0 ) + 800479a: f7fe fca5 bl 80030e8 + vListInitialise( &xDelayedTaskList2 ); + 800479e: 480d ldr r0, [pc, #52] @ (80047d4 ) + 80047a0: f7fe fca2 bl 80030e8 + vListInitialise( &xPendingReadyList ); + 80047a4: 480c ldr r0, [pc, #48] @ (80047d8 ) + 80047a6: f7fe fc9f bl 80030e8 + + #if ( INCLUDE_vTaskDelete == 1 ) + { + vListInitialise( &xTasksWaitingTermination ); + 80047aa: 480c ldr r0, [pc, #48] @ (80047dc ) + 80047ac: f7fe fc9c bl 80030e8 + } + #endif /* INCLUDE_vTaskDelete */ + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + vListInitialise( &xSuspendedTaskList ); + 80047b0: 480b ldr r0, [pc, #44] @ (80047e0 ) + 80047b2: f7fe fc99 bl 80030e8 + } + #endif /* INCLUDE_vTaskSuspend */ + + /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList + using list2. */ + pxDelayedTaskList = &xDelayedTaskList1; + 80047b6: 4b0b ldr r3, [pc, #44] @ (80047e4 ) + 80047b8: 4a05 ldr r2, [pc, #20] @ (80047d0 ) + 80047ba: 601a str r2, [r3, #0] + pxOverflowDelayedTaskList = &xDelayedTaskList2; + 80047bc: 4b0a ldr r3, [pc, #40] @ (80047e8 ) + 80047be: 4a05 ldr r2, [pc, #20] @ (80047d4 ) + 80047c0: 601a str r2, [r3, #0] +} + 80047c2: bf00 nop + 80047c4: 3708 adds r7, #8 + 80047c6: 46bd mov sp, r7 + 80047c8: bd80 pop {r7, pc} + 80047ca: bf00 nop + 80047cc: 2000093c .word 0x2000093c + 80047d0: 20000d9c .word 0x20000d9c + 80047d4: 20000db0 .word 0x20000db0 + 80047d8: 20000dcc .word 0x20000dcc + 80047dc: 20000de0 .word 0x20000de0 + 80047e0: 20000df8 .word 0x20000df8 + 80047e4: 20000dc4 .word 0x20000dc4 + 80047e8: 20000dc8 .word 0x20000dc8 + +080047ec : +/*-----------------------------------------------------------*/ + +static void prvCheckTasksWaitingTermination( void ) +{ + 80047ec: b580 push {r7, lr} + 80047ee: b082 sub sp, #8 + 80047f0: af00 add r7, sp, #0 + { + TCB_t *pxTCB; + + /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL() + being called too often in the idle task. */ + while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) + 80047f2: e019 b.n 8004828 + { + taskENTER_CRITICAL(); + 80047f4: f000 fde8 bl 80053c8 + { + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + 80047f8: 4b10 ldr r3, [pc, #64] @ (800483c ) + 80047fa: 68db ldr r3, [r3, #12] + 80047fc: 68db ldr r3, [r3, #12] + 80047fe: 607b str r3, [r7, #4] + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + 8004800: 687b ldr r3, [r7, #4] + 8004802: 3304 adds r3, #4 + 8004804: 4618 mov r0, r3 + 8004806: f7fe fcf9 bl 80031fc + --uxCurrentNumberOfTasks; + 800480a: 4b0d ldr r3, [pc, #52] @ (8004840 ) + 800480c: 681b ldr r3, [r3, #0] + 800480e: 3b01 subs r3, #1 + 8004810: 4a0b ldr r2, [pc, #44] @ (8004840 ) + 8004812: 6013 str r3, [r2, #0] + --uxDeletedTasksWaitingCleanUp; + 8004814: 4b0b ldr r3, [pc, #44] @ (8004844 ) + 8004816: 681b ldr r3, [r3, #0] + 8004818: 3b01 subs r3, #1 + 800481a: 4a0a ldr r2, [pc, #40] @ (8004844 ) + 800481c: 6013 str r3, [r2, #0] + } + taskEXIT_CRITICAL(); + 800481e: f000 fe05 bl 800542c + + prvDeleteTCB( pxTCB ); + 8004822: 6878 ldr r0, [r7, #4] + 8004824: f000 f810 bl 8004848 + while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) + 8004828: 4b06 ldr r3, [pc, #24] @ (8004844 ) + 800482a: 681b ldr r3, [r3, #0] + 800482c: 2b00 cmp r3, #0 + 800482e: d1e1 bne.n 80047f4 + } + } + #endif /* INCLUDE_vTaskDelete */ +} + 8004830: bf00 nop + 8004832: bf00 nop + 8004834: 3708 adds r7, #8 + 8004836: 46bd mov sp, r7 + 8004838: bd80 pop {r7, pc} + 800483a: bf00 nop + 800483c: 20000de0 .word 0x20000de0 + 8004840: 20000e0c .word 0x20000e0c + 8004844: 20000df4 .word 0x20000df4 + +08004848 : +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskDelete == 1 ) + + static void prvDeleteTCB( TCB_t *pxTCB ) + { + 8004848: b580 push {r7, lr} + 800484a: b084 sub sp, #16 + 800484c: af00 add r7, sp, #0 + 800484e: 6078 str r0, [r7, #4] + to the task to free any memory allocated at the application level. + See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html + for additional information. */ + #if ( configUSE_NEWLIB_REENTRANT == 1 ) + { + _reclaim_reent( &( pxTCB->xNewLib_reent ) ); + 8004850: 687b ldr r3, [r7, #4] + 8004852: 3354 adds r3, #84 @ 0x54 + 8004854: 4618 mov r0, r3 + 8004856: f001 f8ff bl 8005a58 <_reclaim_reent> + #elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ + { + /* The task could have been allocated statically or dynamically, so + check what was statically allocated before trying to free the + memory. */ + if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ) + 800485a: 687b ldr r3, [r7, #4] + 800485c: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 + 8004860: 2b00 cmp r3, #0 + 8004862: d108 bne.n 8004876 + { + /* Both the stack and TCB were allocated dynamically, so both + must be freed. */ + vPortFree( pxTCB->pxStack ); + 8004864: 687b ldr r3, [r7, #4] + 8004866: 6b1b ldr r3, [r3, #48] @ 0x30 + 8004868: 4618 mov r0, r3 + 800486a: f000 ff9d bl 80057a8 + vPortFree( pxTCB ); + 800486e: 6878 ldr r0, [r7, #4] + 8004870: f000 ff9a bl 80057a8 + configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + } + 8004874: e019 b.n 80048aa + else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY ) + 8004876: 687b ldr r3, [r7, #4] + 8004878: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 + 800487c: 2b01 cmp r3, #1 + 800487e: d103 bne.n 8004888 + vPortFree( pxTCB ); + 8004880: 6878 ldr r0, [r7, #4] + 8004882: f000 ff91 bl 80057a8 + } + 8004886: e010 b.n 80048aa + configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); + 8004888: 687b ldr r3, [r7, #4] + 800488a: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 + 800488e: 2b02 cmp r3, #2 + 8004890: d00b beq.n 80048aa + __asm volatile + 8004892: f04f 0350 mov.w r3, #80 @ 0x50 + 8004896: f383 8811 msr BASEPRI, r3 + 800489a: f3bf 8f6f isb sy + 800489e: f3bf 8f4f dsb sy + 80048a2: 60fb str r3, [r7, #12] +} + 80048a4: bf00 nop + 80048a6: bf00 nop + 80048a8: e7fd b.n 80048a6 + } + 80048aa: bf00 nop + 80048ac: 3710 adds r7, #16 + 80048ae: 46bd mov sp, r7 + 80048b0: bd80 pop {r7, pc} + ... + +080048b4 : + +#endif /* INCLUDE_vTaskDelete */ +/*-----------------------------------------------------------*/ + +static void prvResetNextTaskUnblockTime( void ) +{ + 80048b4: b480 push {r7} + 80048b6: b083 sub sp, #12 + 80048b8: af00 add r7, sp, #0 +TCB_t *pxTCB; + + if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) + 80048ba: 4b0c ldr r3, [pc, #48] @ (80048ec ) + 80048bc: 681b ldr r3, [r3, #0] + 80048be: 681b ldr r3, [r3, #0] + 80048c0: 2b00 cmp r3, #0 + 80048c2: d104 bne.n 80048ce + { + /* The new current delayed list is empty. Set xNextTaskUnblockTime to + the maximum possible value so it is extremely unlikely that the + if( xTickCount >= xNextTaskUnblockTime ) test will pass until + there is an item in the delayed list. */ + xNextTaskUnblockTime = portMAX_DELAY; + 80048c4: 4b0a ldr r3, [pc, #40] @ (80048f0 ) + 80048c6: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 80048ca: 601a str r2, [r3, #0] + which the task at the head of the delayed list should be removed + from the Blocked state. */ + ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); + } +} + 80048cc: e008 b.n 80048e0 + ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + 80048ce: 4b07 ldr r3, [pc, #28] @ (80048ec ) + 80048d0: 681b ldr r3, [r3, #0] + 80048d2: 68db ldr r3, [r3, #12] + 80048d4: 68db ldr r3, [r3, #12] + 80048d6: 607b str r3, [r7, #4] + xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); + 80048d8: 687b ldr r3, [r7, #4] + 80048da: 685b ldr r3, [r3, #4] + 80048dc: 4a04 ldr r2, [pc, #16] @ (80048f0 ) + 80048de: 6013 str r3, [r2, #0] +} + 80048e0: bf00 nop + 80048e2: 370c adds r7, #12 + 80048e4: 46bd mov sp, r7 + 80048e6: f85d 7b04 ldr.w r7, [sp], #4 + 80048ea: 4770 bx lr + 80048ec: 20000dc4 .word 0x20000dc4 + 80048f0: 20000e2c .word 0x20000e2c + +080048f4 : +/*-----------------------------------------------------------*/ + +#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + + BaseType_t xTaskGetSchedulerState( void ) + { + 80048f4: b480 push {r7} + 80048f6: b083 sub sp, #12 + 80048f8: af00 add r7, sp, #0 + BaseType_t xReturn; + + if( xSchedulerRunning == pdFALSE ) + 80048fa: 4b0b ldr r3, [pc, #44] @ (8004928 ) + 80048fc: 681b ldr r3, [r3, #0] + 80048fe: 2b00 cmp r3, #0 + 8004900: d102 bne.n 8004908 + { + xReturn = taskSCHEDULER_NOT_STARTED; + 8004902: 2301 movs r3, #1 + 8004904: 607b str r3, [r7, #4] + 8004906: e008 b.n 800491a + } + else + { + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + 8004908: 4b08 ldr r3, [pc, #32] @ (800492c ) + 800490a: 681b ldr r3, [r3, #0] + 800490c: 2b00 cmp r3, #0 + 800490e: d102 bne.n 8004916 + { + xReturn = taskSCHEDULER_RUNNING; + 8004910: 2302 movs r3, #2 + 8004912: 607b str r3, [r7, #4] + 8004914: e001 b.n 800491a + } + else + { + xReturn = taskSCHEDULER_SUSPENDED; + 8004916: 2300 movs r3, #0 + 8004918: 607b str r3, [r7, #4] + } + } + + return xReturn; + 800491a: 687b ldr r3, [r7, #4] + } + 800491c: 4618 mov r0, r3 + 800491e: 370c adds r7, #12 + 8004920: 46bd mov sp, r7 + 8004922: f85d 7b04 ldr.w r7, [sp], #4 + 8004926: 4770 bx lr + 8004928: 20000e18 .word 0x20000e18 + 800492c: 20000e34 .word 0x20000e34 + +08004930 : +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) + { + 8004930: b580 push {r7, lr} + 8004932: b086 sub sp, #24 + 8004934: af00 add r7, sp, #0 + 8004936: 6078 str r0, [r7, #4] + TCB_t * const pxTCB = pxMutexHolder; + 8004938: 687b ldr r3, [r7, #4] + 800493a: 613b str r3, [r7, #16] + BaseType_t xReturn = pdFALSE; + 800493c: 2300 movs r3, #0 + 800493e: 617b str r3, [r7, #20] + + if( pxMutexHolder != NULL ) + 8004940: 687b ldr r3, [r7, #4] + 8004942: 2b00 cmp r3, #0 + 8004944: d058 beq.n 80049f8 + { + /* A task can only have an inherited priority if it holds the mutex. + If the mutex is held by a task then it cannot be given from an + interrupt, and if a mutex is given by the holding task then it must + be the running state task. */ + configASSERT( pxTCB == pxCurrentTCB ); + 8004946: 4b2f ldr r3, [pc, #188] @ (8004a04 ) + 8004948: 681b ldr r3, [r3, #0] + 800494a: 693a ldr r2, [r7, #16] + 800494c: 429a cmp r2, r3 + 800494e: d00b beq.n 8004968 + __asm volatile + 8004950: f04f 0350 mov.w r3, #80 @ 0x50 + 8004954: f383 8811 msr BASEPRI, r3 + 8004958: f3bf 8f6f isb sy + 800495c: f3bf 8f4f dsb sy + 8004960: 60fb str r3, [r7, #12] +} + 8004962: bf00 nop + 8004964: bf00 nop + 8004966: e7fd b.n 8004964 + configASSERT( pxTCB->uxMutexesHeld ); + 8004968: 693b ldr r3, [r7, #16] + 800496a: 6d1b ldr r3, [r3, #80] @ 0x50 + 800496c: 2b00 cmp r3, #0 + 800496e: d10b bne.n 8004988 + __asm volatile + 8004970: f04f 0350 mov.w r3, #80 @ 0x50 + 8004974: f383 8811 msr BASEPRI, r3 + 8004978: f3bf 8f6f isb sy + 800497c: f3bf 8f4f dsb sy + 8004980: 60bb str r3, [r7, #8] +} + 8004982: bf00 nop + 8004984: bf00 nop + 8004986: e7fd b.n 8004984 + ( pxTCB->uxMutexesHeld )--; + 8004988: 693b ldr r3, [r7, #16] + 800498a: 6d1b ldr r3, [r3, #80] @ 0x50 + 800498c: 1e5a subs r2, r3, #1 + 800498e: 693b ldr r3, [r7, #16] + 8004990: 651a str r2, [r3, #80] @ 0x50 + + /* Has the holder of the mutex inherited the priority of another + task? */ + if( pxTCB->uxPriority != pxTCB->uxBasePriority ) + 8004992: 693b ldr r3, [r7, #16] + 8004994: 6ada ldr r2, [r3, #44] @ 0x2c + 8004996: 693b ldr r3, [r7, #16] + 8004998: 6cdb ldr r3, [r3, #76] @ 0x4c + 800499a: 429a cmp r2, r3 + 800499c: d02c beq.n 80049f8 + { + /* Only disinherit if no other mutexes are held. */ + if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 ) + 800499e: 693b ldr r3, [r7, #16] + 80049a0: 6d1b ldr r3, [r3, #80] @ 0x50 + 80049a2: 2b00 cmp r3, #0 + 80049a4: d128 bne.n 80049f8 + /* A task can only have an inherited priority if it holds + the mutex. If the mutex is held by a task then it cannot be + given from an interrupt, and if a mutex is given by the + holding task then it must be the running state task. Remove + the holding task from the ready/delayed list. */ + if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + 80049a6: 693b ldr r3, [r7, #16] + 80049a8: 3304 adds r3, #4 + 80049aa: 4618 mov r0, r3 + 80049ac: f7fe fc26 bl 80031fc + } + + /* Disinherit the priority before adding the task into the + new ready list. */ + traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); + pxTCB->uxPriority = pxTCB->uxBasePriority; + 80049b0: 693b ldr r3, [r7, #16] + 80049b2: 6cda ldr r2, [r3, #76] @ 0x4c + 80049b4: 693b ldr r3, [r7, #16] + 80049b6: 62da str r2, [r3, #44] @ 0x2c + + /* Reset the event list item value. It cannot be in use for + any other purpose if this task is running, and it must be + running to give back the mutex. */ + listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 80049b8: 693b ldr r3, [r7, #16] + 80049ba: 6adb ldr r3, [r3, #44] @ 0x2c + 80049bc: f1c3 0238 rsb r2, r3, #56 @ 0x38 + 80049c0: 693b ldr r3, [r7, #16] + 80049c2: 619a str r2, [r3, #24] + prvAddTaskToReadyList( pxTCB ); + 80049c4: 693b ldr r3, [r7, #16] + 80049c6: 6ada ldr r2, [r3, #44] @ 0x2c + 80049c8: 4b0f ldr r3, [pc, #60] @ (8004a08 ) + 80049ca: 681b ldr r3, [r3, #0] + 80049cc: 429a cmp r2, r3 + 80049ce: d903 bls.n 80049d8 + 80049d0: 693b ldr r3, [r7, #16] + 80049d2: 6adb ldr r3, [r3, #44] @ 0x2c + 80049d4: 4a0c ldr r2, [pc, #48] @ (8004a08 ) + 80049d6: 6013 str r3, [r2, #0] + 80049d8: 693b ldr r3, [r7, #16] + 80049da: 6ada ldr r2, [r3, #44] @ 0x2c + 80049dc: 4613 mov r3, r2 + 80049de: 009b lsls r3, r3, #2 + 80049e0: 4413 add r3, r2 + 80049e2: 009b lsls r3, r3, #2 + 80049e4: 4a09 ldr r2, [pc, #36] @ (8004a0c ) + 80049e6: 441a add r2, r3 + 80049e8: 693b ldr r3, [r7, #16] + 80049ea: 3304 adds r3, #4 + 80049ec: 4619 mov r1, r3 + 80049ee: 4610 mov r0, r2 + 80049f0: f7fe fba7 bl 8003142 + in an order different to that in which they were taken. + If a context switch did not occur when the first mutex was + returned, even if a task was waiting on it, then a context + switch should occur when the last mutex is returned whether + a task is waiting on it or not. */ + xReturn = pdTRUE; + 80049f4: 2301 movs r3, #1 + 80049f6: 617b str r3, [r7, #20] + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; + 80049f8: 697b ldr r3, [r7, #20] + } + 80049fa: 4618 mov r0, r3 + 80049fc: 3718 adds r7, #24 + 80049fe: 46bd mov sp, r7 + 8004a00: bd80 pop {r7, pc} + 8004a02: bf00 nop + 8004a04: 20000938 .word 0x20000938 + 8004a08: 20000e14 .word 0x20000e14 + 8004a0c: 2000093c .word 0x2000093c + +08004a10 : + +#endif +/*-----------------------------------------------------------*/ + +static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) +{ + 8004a10: b580 push {r7, lr} + 8004a12: b084 sub sp, #16 + 8004a14: af00 add r7, sp, #0 + 8004a16: 6078 str r0, [r7, #4] + 8004a18: 6039 str r1, [r7, #0] +TickType_t xTimeToWake; +const TickType_t xConstTickCount = xTickCount; + 8004a1a: 4b21 ldr r3, [pc, #132] @ (8004aa0 ) + 8004a1c: 681b ldr r3, [r3, #0] + 8004a1e: 60fb str r3, [r7, #12] + } + #endif + + /* Remove the task from the ready list before adding it to the blocked list + as the same list item is used for both lists. */ + if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + 8004a20: 4b20 ldr r3, [pc, #128] @ (8004aa4 ) + 8004a22: 681b ldr r3, [r3, #0] + 8004a24: 3304 adds r3, #4 + 8004a26: 4618 mov r0, r3 + 8004a28: f7fe fbe8 bl 80031fc + mtCOVERAGE_TEST_MARKER(); + } + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) + 8004a2c: 687b ldr r3, [r7, #4] + 8004a2e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8004a32: d10a bne.n 8004a4a + 8004a34: 683b ldr r3, [r7, #0] + 8004a36: 2b00 cmp r3, #0 + 8004a38: d007 beq.n 8004a4a + { + /* Add the task to the suspended task list instead of a delayed task + list to ensure it is not woken by a timing event. It will block + indefinitely. */ + vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); + 8004a3a: 4b1a ldr r3, [pc, #104] @ (8004aa4 ) + 8004a3c: 681b ldr r3, [r3, #0] + 8004a3e: 3304 adds r3, #4 + 8004a40: 4619 mov r1, r3 + 8004a42: 4819 ldr r0, [pc, #100] @ (8004aa8 ) + 8004a44: f7fe fb7d bl 8003142 + + /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ + ( void ) xCanBlockIndefinitely; + } + #endif /* INCLUDE_vTaskSuspend */ +} + 8004a48: e026 b.n 8004a98 + xTimeToWake = xConstTickCount + xTicksToWait; + 8004a4a: 68fa ldr r2, [r7, #12] + 8004a4c: 687b ldr r3, [r7, #4] + 8004a4e: 4413 add r3, r2 + 8004a50: 60bb str r3, [r7, #8] + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); + 8004a52: 4b14 ldr r3, [pc, #80] @ (8004aa4 ) + 8004a54: 681b ldr r3, [r3, #0] + 8004a56: 68ba ldr r2, [r7, #8] + 8004a58: 605a str r2, [r3, #4] + if( xTimeToWake < xConstTickCount ) + 8004a5a: 68ba ldr r2, [r7, #8] + 8004a5c: 68fb ldr r3, [r7, #12] + 8004a5e: 429a cmp r2, r3 + 8004a60: d209 bcs.n 8004a76 + vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + 8004a62: 4b12 ldr r3, [pc, #72] @ (8004aac ) + 8004a64: 681a ldr r2, [r3, #0] + 8004a66: 4b0f ldr r3, [pc, #60] @ (8004aa4 ) + 8004a68: 681b ldr r3, [r3, #0] + 8004a6a: 3304 adds r3, #4 + 8004a6c: 4619 mov r1, r3 + 8004a6e: 4610 mov r0, r2 + 8004a70: f7fe fb8b bl 800318a +} + 8004a74: e010 b.n 8004a98 + vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + 8004a76: 4b0e ldr r3, [pc, #56] @ (8004ab0 ) + 8004a78: 681a ldr r2, [r3, #0] + 8004a7a: 4b0a ldr r3, [pc, #40] @ (8004aa4 ) + 8004a7c: 681b ldr r3, [r3, #0] + 8004a7e: 3304 adds r3, #4 + 8004a80: 4619 mov r1, r3 + 8004a82: 4610 mov r0, r2 + 8004a84: f7fe fb81 bl 800318a + if( xTimeToWake < xNextTaskUnblockTime ) + 8004a88: 4b0a ldr r3, [pc, #40] @ (8004ab4 ) + 8004a8a: 681b ldr r3, [r3, #0] + 8004a8c: 68ba ldr r2, [r7, #8] + 8004a8e: 429a cmp r2, r3 + 8004a90: d202 bcs.n 8004a98 + xNextTaskUnblockTime = xTimeToWake; + 8004a92: 4a08 ldr r2, [pc, #32] @ (8004ab4 ) + 8004a94: 68bb ldr r3, [r7, #8] + 8004a96: 6013 str r3, [r2, #0] +} + 8004a98: bf00 nop + 8004a9a: 3710 adds r7, #16 + 8004a9c: 46bd mov sp, r7 + 8004a9e: bd80 pop {r7, pc} + 8004aa0: 20000e10 .word 0x20000e10 + 8004aa4: 20000938 .word 0x20000938 + 8004aa8: 20000df8 .word 0x20000df8 + 8004aac: 20000dc8 .word 0x20000dc8 + 8004ab0: 20000dc4 .word 0x20000dc4 + 8004ab4: 20000e2c .word 0x20000e2c + +08004ab8 : + TimerCallbackFunction_t pxCallbackFunction, + Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + +BaseType_t xTimerCreateTimerTask( void ) +{ + 8004ab8: b580 push {r7, lr} + 8004aba: b08a sub sp, #40 @ 0x28 + 8004abc: af04 add r7, sp, #16 +BaseType_t xReturn = pdFAIL; + 8004abe: 2300 movs r3, #0 + 8004ac0: 617b str r3, [r7, #20] + + /* This function is called when the scheduler is started if + configUSE_TIMERS is set to 1. Check that the infrastructure used by the + timer service task has been created/initialised. If timers have already + been created then the initialisation will already have been performed. */ + prvCheckForValidListAndQueue(); + 8004ac2: f000 fb13 bl 80050ec + + if( xTimerQueue != NULL ) + 8004ac6: 4b1d ldr r3, [pc, #116] @ (8004b3c ) + 8004ac8: 681b ldr r3, [r3, #0] + 8004aca: 2b00 cmp r3, #0 + 8004acc: d021 beq.n 8004b12 + { + #if( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + StaticTask_t *pxTimerTaskTCBBuffer = NULL; + 8004ace: 2300 movs r3, #0 + 8004ad0: 60fb str r3, [r7, #12] + StackType_t *pxTimerTaskStackBuffer = NULL; + 8004ad2: 2300 movs r3, #0 + 8004ad4: 60bb str r3, [r7, #8] + uint32_t ulTimerTaskStackSize; + + vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize ); + 8004ad6: 1d3a adds r2, r7, #4 + 8004ad8: f107 0108 add.w r1, r7, #8 + 8004adc: f107 030c add.w r3, r7, #12 + 8004ae0: 4618 mov r0, r3 + 8004ae2: f7fe fae7 bl 80030b4 + xTimerTaskHandle = xTaskCreateStatic( prvTimerTask, + 8004ae6: 6879 ldr r1, [r7, #4] + 8004ae8: 68bb ldr r3, [r7, #8] + 8004aea: 68fa ldr r2, [r7, #12] + 8004aec: 9202 str r2, [sp, #8] + 8004aee: 9301 str r3, [sp, #4] + 8004af0: 2302 movs r3, #2 + 8004af2: 9300 str r3, [sp, #0] + 8004af4: 2300 movs r3, #0 + 8004af6: 460a mov r2, r1 + 8004af8: 4911 ldr r1, [pc, #68] @ (8004b40 ) + 8004afa: 4812 ldr r0, [pc, #72] @ (8004b44 ) + 8004afc: f7ff f8a2 bl 8003c44 + 8004b00: 4603 mov r3, r0 + 8004b02: 4a11 ldr r2, [pc, #68] @ (8004b48 ) + 8004b04: 6013 str r3, [r2, #0] + NULL, + ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, + pxTimerTaskStackBuffer, + pxTimerTaskTCBBuffer ); + + if( xTimerTaskHandle != NULL ) + 8004b06: 4b10 ldr r3, [pc, #64] @ (8004b48 ) + 8004b08: 681b ldr r3, [r3, #0] + 8004b0a: 2b00 cmp r3, #0 + 8004b0c: d001 beq.n 8004b12 + { + xReturn = pdPASS; + 8004b0e: 2301 movs r3, #1 + 8004b10: 617b str r3, [r7, #20] + else + { + mtCOVERAGE_TEST_MARKER(); + } + + configASSERT( xReturn ); + 8004b12: 697b ldr r3, [r7, #20] + 8004b14: 2b00 cmp r3, #0 + 8004b16: d10b bne.n 8004b30 + __asm volatile + 8004b18: f04f 0350 mov.w r3, #80 @ 0x50 + 8004b1c: f383 8811 msr BASEPRI, r3 + 8004b20: f3bf 8f6f isb sy + 8004b24: f3bf 8f4f dsb sy + 8004b28: 613b str r3, [r7, #16] +} + 8004b2a: bf00 nop + 8004b2c: bf00 nop + 8004b2e: e7fd b.n 8004b2c + return xReturn; + 8004b30: 697b ldr r3, [r7, #20] +} + 8004b32: 4618 mov r0, r3 + 8004b34: 3718 adds r7, #24 + 8004b36: 46bd mov sp, r7 + 8004b38: bd80 pop {r7, pc} + 8004b3a: bf00 nop + 8004b3c: 20000e68 .word 0x20000e68 + 8004b40: 08005d10 .word 0x08005d10 + 8004b44: 08004c85 .word 0x08004c85 + 8004b48: 20000e6c .word 0x20000e6c + +08004b4c : + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) +{ + 8004b4c: b580 push {r7, lr} + 8004b4e: b08a sub sp, #40 @ 0x28 + 8004b50: af00 add r7, sp, #0 + 8004b52: 60f8 str r0, [r7, #12] + 8004b54: 60b9 str r1, [r7, #8] + 8004b56: 607a str r2, [r7, #4] + 8004b58: 603b str r3, [r7, #0] +BaseType_t xReturn = pdFAIL; + 8004b5a: 2300 movs r3, #0 + 8004b5c: 627b str r3, [r7, #36] @ 0x24 +DaemonTaskMessage_t xMessage; + + configASSERT( xTimer ); + 8004b5e: 68fb ldr r3, [r7, #12] + 8004b60: 2b00 cmp r3, #0 + 8004b62: d10b bne.n 8004b7c + __asm volatile + 8004b64: f04f 0350 mov.w r3, #80 @ 0x50 + 8004b68: f383 8811 msr BASEPRI, r3 + 8004b6c: f3bf 8f6f isb sy + 8004b70: f3bf 8f4f dsb sy + 8004b74: 623b str r3, [r7, #32] +} + 8004b76: bf00 nop + 8004b78: bf00 nop + 8004b7a: e7fd b.n 8004b78 + + /* Send a message to the timer service task to perform a particular action + on a particular timer definition. */ + if( xTimerQueue != NULL ) + 8004b7c: 4b19 ldr r3, [pc, #100] @ (8004be4 ) + 8004b7e: 681b ldr r3, [r3, #0] + 8004b80: 2b00 cmp r3, #0 + 8004b82: d02a beq.n 8004bda + { + /* Send a command to the timer service task to start the xTimer timer. */ + xMessage.xMessageID = xCommandID; + 8004b84: 68bb ldr r3, [r7, #8] + 8004b86: 613b str r3, [r7, #16] + xMessage.u.xTimerParameters.xMessageValue = xOptionalValue; + 8004b88: 687b ldr r3, [r7, #4] + 8004b8a: 617b str r3, [r7, #20] + xMessage.u.xTimerParameters.pxTimer = xTimer; + 8004b8c: 68fb ldr r3, [r7, #12] + 8004b8e: 61bb str r3, [r7, #24] + + if( xCommandID < tmrFIRST_FROM_ISR_COMMAND ) + 8004b90: 68bb ldr r3, [r7, #8] + 8004b92: 2b05 cmp r3, #5 + 8004b94: dc18 bgt.n 8004bc8 + { + if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING ) + 8004b96: f7ff fead bl 80048f4 + 8004b9a: 4603 mov r3, r0 + 8004b9c: 2b02 cmp r3, #2 + 8004b9e: d109 bne.n 8004bb4 + { + xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); + 8004ba0: 4b10 ldr r3, [pc, #64] @ (8004be4 ) + 8004ba2: 6818 ldr r0, [r3, #0] + 8004ba4: f107 0110 add.w r1, r7, #16 + 8004ba8: 2300 movs r3, #0 + 8004baa: 6b3a ldr r2, [r7, #48] @ 0x30 + 8004bac: f7fe fc5a bl 8003464 + 8004bb0: 6278 str r0, [r7, #36] @ 0x24 + 8004bb2: e012 b.n 8004bda + } + else + { + xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY ); + 8004bb4: 4b0b ldr r3, [pc, #44] @ (8004be4 ) + 8004bb6: 6818 ldr r0, [r3, #0] + 8004bb8: f107 0110 add.w r1, r7, #16 + 8004bbc: 2300 movs r3, #0 + 8004bbe: 2200 movs r2, #0 + 8004bc0: f7fe fc50 bl 8003464 + 8004bc4: 6278 str r0, [r7, #36] @ 0x24 + 8004bc6: e008 b.n 8004bda + } + } + else + { + xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken ); + 8004bc8: 4b06 ldr r3, [pc, #24] @ (8004be4 ) + 8004bca: 6818 ldr r0, [r3, #0] + 8004bcc: f107 0110 add.w r1, r7, #16 + 8004bd0: 2300 movs r3, #0 + 8004bd2: 683a ldr r2, [r7, #0] + 8004bd4: f7fe fd48 bl 8003668 + 8004bd8: 6278 str r0, [r7, #36] @ 0x24 + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; + 8004bda: 6a7b ldr r3, [r7, #36] @ 0x24 +} + 8004bdc: 4618 mov r0, r3 + 8004bde: 3728 adds r7, #40 @ 0x28 + 8004be0: 46bd mov sp, r7 + 8004be2: bd80 pop {r7, pc} + 8004be4: 20000e68 .word 0x20000e68 + +08004be8 : + return pxTimer->pcTimerName; +} +/*-----------------------------------------------------------*/ + +static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) +{ + 8004be8: b580 push {r7, lr} + 8004bea: b088 sub sp, #32 + 8004bec: af02 add r7, sp, #8 + 8004bee: 6078 str r0, [r7, #4] + 8004bf0: 6039 str r1, [r7, #0] +BaseType_t xResult; +Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + 8004bf2: 4b23 ldr r3, [pc, #140] @ (8004c80 ) + 8004bf4: 681b ldr r3, [r3, #0] + 8004bf6: 68db ldr r3, [r3, #12] + 8004bf8: 68db ldr r3, [r3, #12] + 8004bfa: 617b str r3, [r7, #20] + + /* Remove the timer from the list of active timers. A check has already + been performed to ensure the list is not empty. */ + ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); + 8004bfc: 697b ldr r3, [r7, #20] + 8004bfe: 3304 adds r3, #4 + 8004c00: 4618 mov r0, r3 + 8004c02: f7fe fafb bl 80031fc + traceTIMER_EXPIRED( pxTimer ); + + /* If the timer is an auto-reload timer then calculate the next + expiry time and re-insert the timer in the list of active timers. */ + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) + 8004c06: 697b ldr r3, [r7, #20] + 8004c08: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 + 8004c0c: f003 0304 and.w r3, r3, #4 + 8004c10: 2b00 cmp r3, #0 + 8004c12: d023 beq.n 8004c5c + { + /* The timer is inserted into a list using a time relative to anything + other than the current time. It will therefore be inserted into the + correct list relative to the time this task thinks it is now. */ + if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE ) + 8004c14: 697b ldr r3, [r7, #20] + 8004c16: 699a ldr r2, [r3, #24] + 8004c18: 687b ldr r3, [r7, #4] + 8004c1a: 18d1 adds r1, r2, r3 + 8004c1c: 687b ldr r3, [r7, #4] + 8004c1e: 683a ldr r2, [r7, #0] + 8004c20: 6978 ldr r0, [r7, #20] + 8004c22: f000 f8d5 bl 8004dd0 + 8004c26: 4603 mov r3, r0 + 8004c28: 2b00 cmp r3, #0 + 8004c2a: d020 beq.n 8004c6e + { + /* The timer expired before it was added to the active timer + list. Reload it now. */ + xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); + 8004c2c: 2300 movs r3, #0 + 8004c2e: 9300 str r3, [sp, #0] + 8004c30: 2300 movs r3, #0 + 8004c32: 687a ldr r2, [r7, #4] + 8004c34: 2100 movs r1, #0 + 8004c36: 6978 ldr r0, [r7, #20] + 8004c38: f7ff ff88 bl 8004b4c + 8004c3c: 6138 str r0, [r7, #16] + configASSERT( xResult ); + 8004c3e: 693b ldr r3, [r7, #16] + 8004c40: 2b00 cmp r3, #0 + 8004c42: d114 bne.n 8004c6e + __asm volatile + 8004c44: f04f 0350 mov.w r3, #80 @ 0x50 + 8004c48: f383 8811 msr BASEPRI, r3 + 8004c4c: f3bf 8f6f isb sy + 8004c50: f3bf 8f4f dsb sy + 8004c54: 60fb str r3, [r7, #12] +} + 8004c56: bf00 nop + 8004c58: bf00 nop + 8004c5a: e7fd b.n 8004c58 + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; + 8004c5c: 697b ldr r3, [r7, #20] + 8004c5e: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 + 8004c62: f023 0301 bic.w r3, r3, #1 + 8004c66: b2da uxtb r2, r3 + 8004c68: 697b ldr r3, [r7, #20] + 8004c6a: f883 2028 strb.w r2, [r3, #40] @ 0x28 + mtCOVERAGE_TEST_MARKER(); + } + + /* Call the timer callback. */ + pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); + 8004c6e: 697b ldr r3, [r7, #20] + 8004c70: 6a1b ldr r3, [r3, #32] + 8004c72: 6978 ldr r0, [r7, #20] + 8004c74: 4798 blx r3 +} + 8004c76: bf00 nop + 8004c78: 3718 adds r7, #24 + 8004c7a: 46bd mov sp, r7 + 8004c7c: bd80 pop {r7, pc} + 8004c7e: bf00 nop + 8004c80: 20000e60 .word 0x20000e60 + +08004c84 : +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( prvTimerTask, pvParameters ) +{ + 8004c84: b580 push {r7, lr} + 8004c86: b084 sub sp, #16 + 8004c88: af00 add r7, sp, #0 + 8004c8a: 6078 str r0, [r7, #4] + + for( ;; ) + { + /* Query the timers list to see if it contains any timers, and if so, + obtain the time at which the next timer will expire. */ + xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); + 8004c8c: f107 0308 add.w r3, r7, #8 + 8004c90: 4618 mov r0, r3 + 8004c92: f000 f859 bl 8004d48 + 8004c96: 60f8 str r0, [r7, #12] + + /* If a timer has expired, process it. Otherwise, block this task + until either a timer does expire, or a command is received. */ + prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty ); + 8004c98: 68bb ldr r3, [r7, #8] + 8004c9a: 4619 mov r1, r3 + 8004c9c: 68f8 ldr r0, [r7, #12] + 8004c9e: f000 f805 bl 8004cac + + /* Empty the command queue. */ + prvProcessReceivedCommands(); + 8004ca2: f000 f8d7 bl 8004e54 + xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); + 8004ca6: bf00 nop + 8004ca8: e7f0 b.n 8004c8c + ... + +08004cac : + } +} +/*-----------------------------------------------------------*/ + +static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) +{ + 8004cac: b580 push {r7, lr} + 8004cae: b084 sub sp, #16 + 8004cb0: af00 add r7, sp, #0 + 8004cb2: 6078 str r0, [r7, #4] + 8004cb4: 6039 str r1, [r7, #0] +TickType_t xTimeNow; +BaseType_t xTimerListsWereSwitched; + + vTaskSuspendAll(); + 8004cb6: f7ff fa29 bl 800410c + /* Obtain the time now to make an assessment as to whether the timer + has expired or not. If obtaining the time causes the lists to switch + then don't process this timer as any timers that remained in the list + when the lists were switched will have been processed within the + prvSampleTimeNow() function. */ + xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); + 8004cba: f107 0308 add.w r3, r7, #8 + 8004cbe: 4618 mov r0, r3 + 8004cc0: f000 f866 bl 8004d90 + 8004cc4: 60f8 str r0, [r7, #12] + if( xTimerListsWereSwitched == pdFALSE ) + 8004cc6: 68bb ldr r3, [r7, #8] + 8004cc8: 2b00 cmp r3, #0 + 8004cca: d130 bne.n 8004d2e + { + /* The tick count has not overflowed, has the timer expired? */ + if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) ) + 8004ccc: 683b ldr r3, [r7, #0] + 8004cce: 2b00 cmp r3, #0 + 8004cd0: d10a bne.n 8004ce8 + 8004cd2: 687a ldr r2, [r7, #4] + 8004cd4: 68fb ldr r3, [r7, #12] + 8004cd6: 429a cmp r2, r3 + 8004cd8: d806 bhi.n 8004ce8 + { + ( void ) xTaskResumeAll(); + 8004cda: f7ff fa25 bl 8004128 + prvProcessExpiredTimer( xNextExpireTime, xTimeNow ); + 8004cde: 68f9 ldr r1, [r7, #12] + 8004ce0: 6878 ldr r0, [r7, #4] + 8004ce2: f7ff ff81 bl 8004be8 + else + { + ( void ) xTaskResumeAll(); + } + } +} + 8004ce6: e024 b.n 8004d32 + if( xListWasEmpty != pdFALSE ) + 8004ce8: 683b ldr r3, [r7, #0] + 8004cea: 2b00 cmp r3, #0 + 8004cec: d008 beq.n 8004d00 + xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList ); + 8004cee: 4b13 ldr r3, [pc, #76] @ (8004d3c ) + 8004cf0: 681b ldr r3, [r3, #0] + 8004cf2: 681b ldr r3, [r3, #0] + 8004cf4: 2b00 cmp r3, #0 + 8004cf6: d101 bne.n 8004cfc + 8004cf8: 2301 movs r3, #1 + 8004cfa: e000 b.n 8004cfe + 8004cfc: 2300 movs r3, #0 + 8004cfe: 603b str r3, [r7, #0] + vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty ); + 8004d00: 4b0f ldr r3, [pc, #60] @ (8004d40 ) + 8004d02: 6818 ldr r0, [r3, #0] + 8004d04: 687a ldr r2, [r7, #4] + 8004d06: 68fb ldr r3, [r7, #12] + 8004d08: 1ad3 subs r3, r2, r3 + 8004d0a: 683a ldr r2, [r7, #0] + 8004d0c: 4619 mov r1, r3 + 8004d0e: f7fe ff65 bl 8003bdc + if( xTaskResumeAll() == pdFALSE ) + 8004d12: f7ff fa09 bl 8004128 + 8004d16: 4603 mov r3, r0 + 8004d18: 2b00 cmp r3, #0 + 8004d1a: d10a bne.n 8004d32 + portYIELD_WITHIN_API(); + 8004d1c: 4b09 ldr r3, [pc, #36] @ (8004d44 ) + 8004d1e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 + 8004d22: 601a str r2, [r3, #0] + 8004d24: f3bf 8f4f dsb sy + 8004d28: f3bf 8f6f isb sy +} + 8004d2c: e001 b.n 8004d32 + ( void ) xTaskResumeAll(); + 8004d2e: f7ff f9fb bl 8004128 +} + 8004d32: bf00 nop + 8004d34: 3710 adds r7, #16 + 8004d36: 46bd mov sp, r7 + 8004d38: bd80 pop {r7, pc} + 8004d3a: bf00 nop + 8004d3c: 20000e64 .word 0x20000e64 + 8004d40: 20000e68 .word 0x20000e68 + 8004d44: e000ed04 .word 0xe000ed04 + +08004d48 : +/*-----------------------------------------------------------*/ + +static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) +{ + 8004d48: b480 push {r7} + 8004d4a: b085 sub sp, #20 + 8004d4c: af00 add r7, sp, #0 + 8004d4e: 6078 str r0, [r7, #4] + the timer with the nearest expiry time will expire. If there are no + active timers then just set the next expire time to 0. That will cause + this task to unblock when the tick count overflows, at which point the + timer lists will be switched and the next expiry time can be + re-assessed. */ + *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList ); + 8004d50: 4b0e ldr r3, [pc, #56] @ (8004d8c ) + 8004d52: 681b ldr r3, [r3, #0] + 8004d54: 681b ldr r3, [r3, #0] + 8004d56: 2b00 cmp r3, #0 + 8004d58: d101 bne.n 8004d5e + 8004d5a: 2201 movs r2, #1 + 8004d5c: e000 b.n 8004d60 + 8004d5e: 2200 movs r2, #0 + 8004d60: 687b ldr r3, [r7, #4] + 8004d62: 601a str r2, [r3, #0] + if( *pxListWasEmpty == pdFALSE ) + 8004d64: 687b ldr r3, [r7, #4] + 8004d66: 681b ldr r3, [r3, #0] + 8004d68: 2b00 cmp r3, #0 + 8004d6a: d105 bne.n 8004d78 + { + xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); + 8004d6c: 4b07 ldr r3, [pc, #28] @ (8004d8c ) + 8004d6e: 681b ldr r3, [r3, #0] + 8004d70: 68db ldr r3, [r3, #12] + 8004d72: 681b ldr r3, [r3, #0] + 8004d74: 60fb str r3, [r7, #12] + 8004d76: e001 b.n 8004d7c + } + else + { + /* Ensure the task unblocks when the tick count rolls over. */ + xNextExpireTime = ( TickType_t ) 0U; + 8004d78: 2300 movs r3, #0 + 8004d7a: 60fb str r3, [r7, #12] + } + + return xNextExpireTime; + 8004d7c: 68fb ldr r3, [r7, #12] +} + 8004d7e: 4618 mov r0, r3 + 8004d80: 3714 adds r7, #20 + 8004d82: 46bd mov sp, r7 + 8004d84: f85d 7b04 ldr.w r7, [sp], #4 + 8004d88: 4770 bx lr + 8004d8a: bf00 nop + 8004d8c: 20000e60 .word 0x20000e60 + +08004d90 : +/*-----------------------------------------------------------*/ + +static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) +{ + 8004d90: b580 push {r7, lr} + 8004d92: b084 sub sp, #16 + 8004d94: af00 add r7, sp, #0 + 8004d96: 6078 str r0, [r7, #4] +TickType_t xTimeNow; +PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */ + + xTimeNow = xTaskGetTickCount(); + 8004d98: f7ff fa64 bl 8004264 + 8004d9c: 60f8 str r0, [r7, #12] + + if( xTimeNow < xLastTime ) + 8004d9e: 4b0b ldr r3, [pc, #44] @ (8004dcc ) + 8004da0: 681b ldr r3, [r3, #0] + 8004da2: 68fa ldr r2, [r7, #12] + 8004da4: 429a cmp r2, r3 + 8004da6: d205 bcs.n 8004db4 + { + prvSwitchTimerLists(); + 8004da8: f000 f93a bl 8005020 + *pxTimerListsWereSwitched = pdTRUE; + 8004dac: 687b ldr r3, [r7, #4] + 8004dae: 2201 movs r2, #1 + 8004db0: 601a str r2, [r3, #0] + 8004db2: e002 b.n 8004dba + } + else + { + *pxTimerListsWereSwitched = pdFALSE; + 8004db4: 687b ldr r3, [r7, #4] + 8004db6: 2200 movs r2, #0 + 8004db8: 601a str r2, [r3, #0] + } + + xLastTime = xTimeNow; + 8004dba: 4a04 ldr r2, [pc, #16] @ (8004dcc ) + 8004dbc: 68fb ldr r3, [r7, #12] + 8004dbe: 6013 str r3, [r2, #0] + + return xTimeNow; + 8004dc0: 68fb ldr r3, [r7, #12] +} + 8004dc2: 4618 mov r0, r3 + 8004dc4: 3710 adds r7, #16 + 8004dc6: 46bd mov sp, r7 + 8004dc8: bd80 pop {r7, pc} + 8004dca: bf00 nop + 8004dcc: 20000e70 .word 0x20000e70 + +08004dd0 : +/*-----------------------------------------------------------*/ + +static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) +{ + 8004dd0: b580 push {r7, lr} + 8004dd2: b086 sub sp, #24 + 8004dd4: af00 add r7, sp, #0 + 8004dd6: 60f8 str r0, [r7, #12] + 8004dd8: 60b9 str r1, [r7, #8] + 8004dda: 607a str r2, [r7, #4] + 8004ddc: 603b str r3, [r7, #0] +BaseType_t xProcessTimerNow = pdFALSE; + 8004dde: 2300 movs r3, #0 + 8004de0: 617b str r3, [r7, #20] + + listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime ); + 8004de2: 68fb ldr r3, [r7, #12] + 8004de4: 68ba ldr r2, [r7, #8] + 8004de6: 605a str r2, [r3, #4] + listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); + 8004de8: 68fb ldr r3, [r7, #12] + 8004dea: 68fa ldr r2, [r7, #12] + 8004dec: 611a str r2, [r3, #16] + + if( xNextExpiryTime <= xTimeNow ) + 8004dee: 68ba ldr r2, [r7, #8] + 8004df0: 687b ldr r3, [r7, #4] + 8004df2: 429a cmp r2, r3 + 8004df4: d812 bhi.n 8004e1c + { + /* Has the expiry time elapsed between the command to start/reset a + timer was issued, and the time the command was processed? */ + if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 8004df6: 687a ldr r2, [r7, #4] + 8004df8: 683b ldr r3, [r7, #0] + 8004dfa: 1ad2 subs r2, r2, r3 + 8004dfc: 68fb ldr r3, [r7, #12] + 8004dfe: 699b ldr r3, [r3, #24] + 8004e00: 429a cmp r2, r3 + 8004e02: d302 bcc.n 8004e0a + { + /* The time between a command being issued and the command being + processed actually exceeds the timers period. */ + xProcessTimerNow = pdTRUE; + 8004e04: 2301 movs r3, #1 + 8004e06: 617b str r3, [r7, #20] + 8004e08: e01b b.n 8004e42 + } + else + { + vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) ); + 8004e0a: 4b10 ldr r3, [pc, #64] @ (8004e4c ) + 8004e0c: 681a ldr r2, [r3, #0] + 8004e0e: 68fb ldr r3, [r7, #12] + 8004e10: 3304 adds r3, #4 + 8004e12: 4619 mov r1, r3 + 8004e14: 4610 mov r0, r2 + 8004e16: f7fe f9b8 bl 800318a + 8004e1a: e012 b.n 8004e42 + } + } + else + { + if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) ) + 8004e1c: 687a ldr r2, [r7, #4] + 8004e1e: 683b ldr r3, [r7, #0] + 8004e20: 429a cmp r2, r3 + 8004e22: d206 bcs.n 8004e32 + 8004e24: 68ba ldr r2, [r7, #8] + 8004e26: 683b ldr r3, [r7, #0] + 8004e28: 429a cmp r2, r3 + 8004e2a: d302 bcc.n 8004e32 + { + /* If, since the command was issued, the tick count has overflowed + but the expiry time has not, then the timer must have already passed + its expiry time and should be processed immediately. */ + xProcessTimerNow = pdTRUE; + 8004e2c: 2301 movs r3, #1 + 8004e2e: 617b str r3, [r7, #20] + 8004e30: e007 b.n 8004e42 + } + else + { + vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); + 8004e32: 4b07 ldr r3, [pc, #28] @ (8004e50 ) + 8004e34: 681a ldr r2, [r3, #0] + 8004e36: 68fb ldr r3, [r7, #12] + 8004e38: 3304 adds r3, #4 + 8004e3a: 4619 mov r1, r3 + 8004e3c: 4610 mov r0, r2 + 8004e3e: f7fe f9a4 bl 800318a + } + } + + return xProcessTimerNow; + 8004e42: 697b ldr r3, [r7, #20] +} + 8004e44: 4618 mov r0, r3 + 8004e46: 3718 adds r7, #24 + 8004e48: 46bd mov sp, r7 + 8004e4a: bd80 pop {r7, pc} + 8004e4c: 20000e64 .word 0x20000e64 + 8004e50: 20000e60 .word 0x20000e60 + +08004e54 : +/*-----------------------------------------------------------*/ + +static void prvProcessReceivedCommands( void ) +{ + 8004e54: b580 push {r7, lr} + 8004e56: b08e sub sp, #56 @ 0x38 + 8004e58: af02 add r7, sp, #8 +DaemonTaskMessage_t xMessage; +Timer_t *pxTimer; +BaseType_t xTimerListsWereSwitched, xResult; +TickType_t xTimeNow; + + while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ + 8004e5a: e0ce b.n 8004ffa + { + #if ( INCLUDE_xTimerPendFunctionCall == 1 ) + { + /* Negative commands are pended function calls rather than timer + commands. */ + if( xMessage.xMessageID < ( BaseType_t ) 0 ) + 8004e5c: 687b ldr r3, [r7, #4] + 8004e5e: 2b00 cmp r3, #0 + 8004e60: da19 bge.n 8004e96 + { + const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters ); + 8004e62: 1d3b adds r3, r7, #4 + 8004e64: 3304 adds r3, #4 + 8004e66: 62fb str r3, [r7, #44] @ 0x2c + + /* The timer uses the xCallbackParameters member to request a + callback be executed. Check the callback is not NULL. */ + configASSERT( pxCallback ); + 8004e68: 6afb ldr r3, [r7, #44] @ 0x2c + 8004e6a: 2b00 cmp r3, #0 + 8004e6c: d10b bne.n 8004e86 + __asm volatile + 8004e6e: f04f 0350 mov.w r3, #80 @ 0x50 + 8004e72: f383 8811 msr BASEPRI, r3 + 8004e76: f3bf 8f6f isb sy + 8004e7a: f3bf 8f4f dsb sy + 8004e7e: 61fb str r3, [r7, #28] +} + 8004e80: bf00 nop + 8004e82: bf00 nop + 8004e84: e7fd b.n 8004e82 + + /* Call the function. */ + pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 ); + 8004e86: 6afb ldr r3, [r7, #44] @ 0x2c + 8004e88: 681b ldr r3, [r3, #0] + 8004e8a: 6afa ldr r2, [r7, #44] @ 0x2c + 8004e8c: 6850 ldr r0, [r2, #4] + 8004e8e: 6afa ldr r2, [r7, #44] @ 0x2c + 8004e90: 6892 ldr r2, [r2, #8] + 8004e92: 4611 mov r1, r2 + 8004e94: 4798 blx r3 + } + #endif /* INCLUDE_xTimerPendFunctionCall */ + + /* Commands that are positive are timer commands rather than pended + function calls. */ + if( xMessage.xMessageID >= ( BaseType_t ) 0 ) + 8004e96: 687b ldr r3, [r7, #4] + 8004e98: 2b00 cmp r3, #0 + 8004e9a: f2c0 80ae blt.w 8004ffa + { + /* The messages uses the xTimerParameters member to work on a + software timer. */ + pxTimer = xMessage.u.xTimerParameters.pxTimer; + 8004e9e: 68fb ldr r3, [r7, #12] + 8004ea0: 62bb str r3, [r7, #40] @ 0x28 + + if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */ + 8004ea2: 6abb ldr r3, [r7, #40] @ 0x28 + 8004ea4: 695b ldr r3, [r3, #20] + 8004ea6: 2b00 cmp r3, #0 + 8004ea8: d004 beq.n 8004eb4 + { + /* The timer is in a list, remove it. */ + ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); + 8004eaa: 6abb ldr r3, [r7, #40] @ 0x28 + 8004eac: 3304 adds r3, #4 + 8004eae: 4618 mov r0, r3 + 8004eb0: f7fe f9a4 bl 80031fc + it must be present in the function call. prvSampleTimeNow() must be + called after the message is received from xTimerQueue so there is no + possibility of a higher priority task adding a message to the message + queue with a time that is ahead of the timer daemon task (because it + pre-empted the timer daemon task after the xTimeNow value was set). */ + xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); + 8004eb4: 463b mov r3, r7 + 8004eb6: 4618 mov r0, r3 + 8004eb8: f7ff ff6a bl 8004d90 + 8004ebc: 6278 str r0, [r7, #36] @ 0x24 + + switch( xMessage.xMessageID ) + 8004ebe: 687b ldr r3, [r7, #4] + 8004ec0: 2b09 cmp r3, #9 + 8004ec2: f200 8097 bhi.w 8004ff4 + 8004ec6: a201 add r2, pc, #4 @ (adr r2, 8004ecc ) + 8004ec8: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8004ecc: 08004ef5 .word 0x08004ef5 + 8004ed0: 08004ef5 .word 0x08004ef5 + 8004ed4: 08004ef5 .word 0x08004ef5 + 8004ed8: 08004f6b .word 0x08004f6b + 8004edc: 08004f7f .word 0x08004f7f + 8004ee0: 08004fcb .word 0x08004fcb + 8004ee4: 08004ef5 .word 0x08004ef5 + 8004ee8: 08004ef5 .word 0x08004ef5 + 8004eec: 08004f6b .word 0x08004f6b + 8004ef0: 08004f7f .word 0x08004f7f + case tmrCOMMAND_START_FROM_ISR : + case tmrCOMMAND_RESET : + case tmrCOMMAND_RESET_FROM_ISR : + case tmrCOMMAND_START_DONT_TRACE : + /* Start or restart a timer. */ + pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; + 8004ef4: 6abb ldr r3, [r7, #40] @ 0x28 + 8004ef6: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 + 8004efa: f043 0301 orr.w r3, r3, #1 + 8004efe: b2da uxtb r2, r3 + 8004f00: 6abb ldr r3, [r7, #40] @ 0x28 + 8004f02: f883 2028 strb.w r2, [r3, #40] @ 0x28 + if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE ) + 8004f06: 68ba ldr r2, [r7, #8] + 8004f08: 6abb ldr r3, [r7, #40] @ 0x28 + 8004f0a: 699b ldr r3, [r3, #24] + 8004f0c: 18d1 adds r1, r2, r3 + 8004f0e: 68bb ldr r3, [r7, #8] + 8004f10: 6a7a ldr r2, [r7, #36] @ 0x24 + 8004f12: 6ab8 ldr r0, [r7, #40] @ 0x28 + 8004f14: f7ff ff5c bl 8004dd0 + 8004f18: 4603 mov r3, r0 + 8004f1a: 2b00 cmp r3, #0 + 8004f1c: d06c beq.n 8004ff8 + { + /* The timer expired before it was added to the active + timer list. Process it now. */ + pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); + 8004f1e: 6abb ldr r3, [r7, #40] @ 0x28 + 8004f20: 6a1b ldr r3, [r3, #32] + 8004f22: 6ab8 ldr r0, [r7, #40] @ 0x28 + 8004f24: 4798 blx r3 + traceTIMER_EXPIRED( pxTimer ); + + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) + 8004f26: 6abb ldr r3, [r7, #40] @ 0x28 + 8004f28: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 + 8004f2c: f003 0304 and.w r3, r3, #4 + 8004f30: 2b00 cmp r3, #0 + 8004f32: d061 beq.n 8004ff8 + { + xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY ); + 8004f34: 68ba ldr r2, [r7, #8] + 8004f36: 6abb ldr r3, [r7, #40] @ 0x28 + 8004f38: 699b ldr r3, [r3, #24] + 8004f3a: 441a add r2, r3 + 8004f3c: 2300 movs r3, #0 + 8004f3e: 9300 str r3, [sp, #0] + 8004f40: 2300 movs r3, #0 + 8004f42: 2100 movs r1, #0 + 8004f44: 6ab8 ldr r0, [r7, #40] @ 0x28 + 8004f46: f7ff fe01 bl 8004b4c + 8004f4a: 6238 str r0, [r7, #32] + configASSERT( xResult ); + 8004f4c: 6a3b ldr r3, [r7, #32] + 8004f4e: 2b00 cmp r3, #0 + 8004f50: d152 bne.n 8004ff8 + __asm volatile + 8004f52: f04f 0350 mov.w r3, #80 @ 0x50 + 8004f56: f383 8811 msr BASEPRI, r3 + 8004f5a: f3bf 8f6f isb sy + 8004f5e: f3bf 8f4f dsb sy + 8004f62: 61bb str r3, [r7, #24] +} + 8004f64: bf00 nop + 8004f66: bf00 nop + 8004f68: e7fd b.n 8004f66 + break; + + case tmrCOMMAND_STOP : + case tmrCOMMAND_STOP_FROM_ISR : + /* The timer has already been removed from the active list. */ + pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; + 8004f6a: 6abb ldr r3, [r7, #40] @ 0x28 + 8004f6c: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 + 8004f70: f023 0301 bic.w r3, r3, #1 + 8004f74: b2da uxtb r2, r3 + 8004f76: 6abb ldr r3, [r7, #40] @ 0x28 + 8004f78: f883 2028 strb.w r2, [r3, #40] @ 0x28 + break; + 8004f7c: e03d b.n 8004ffa + + case tmrCOMMAND_CHANGE_PERIOD : + case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR : + pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; + 8004f7e: 6abb ldr r3, [r7, #40] @ 0x28 + 8004f80: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 + 8004f84: f043 0301 orr.w r3, r3, #1 + 8004f88: b2da uxtb r2, r3 + 8004f8a: 6abb ldr r3, [r7, #40] @ 0x28 + 8004f8c: f883 2028 strb.w r2, [r3, #40] @ 0x28 + pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue; + 8004f90: 68ba ldr r2, [r7, #8] + 8004f92: 6abb ldr r3, [r7, #40] @ 0x28 + 8004f94: 619a str r2, [r3, #24] + configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) ); + 8004f96: 6abb ldr r3, [r7, #40] @ 0x28 + 8004f98: 699b ldr r3, [r3, #24] + 8004f9a: 2b00 cmp r3, #0 + 8004f9c: d10b bne.n 8004fb6 + __asm volatile + 8004f9e: f04f 0350 mov.w r3, #80 @ 0x50 + 8004fa2: f383 8811 msr BASEPRI, r3 + 8004fa6: f3bf 8f6f isb sy + 8004faa: f3bf 8f4f dsb sy + 8004fae: 617b str r3, [r7, #20] +} + 8004fb0: bf00 nop + 8004fb2: bf00 nop + 8004fb4: e7fd b.n 8004fb2 + be longer or shorter than the old one. The command time is + therefore set to the current time, and as the period cannot + be zero the next expiry time can only be in the future, + meaning (unlike for the xTimerStart() case above) there is + no fail case that needs to be handled here. */ + ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow ); + 8004fb6: 6abb ldr r3, [r7, #40] @ 0x28 + 8004fb8: 699a ldr r2, [r3, #24] + 8004fba: 6a7b ldr r3, [r7, #36] @ 0x24 + 8004fbc: 18d1 adds r1, r2, r3 + 8004fbe: 6a7b ldr r3, [r7, #36] @ 0x24 + 8004fc0: 6a7a ldr r2, [r7, #36] @ 0x24 + 8004fc2: 6ab8 ldr r0, [r7, #40] @ 0x28 + 8004fc4: f7ff ff04 bl 8004dd0 + break; + 8004fc8: e017 b.n 8004ffa + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* The timer has already been removed from the active list, + just free up the memory if the memory was dynamically + allocated. */ + if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 ) + 8004fca: 6abb ldr r3, [r7, #40] @ 0x28 + 8004fcc: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 + 8004fd0: f003 0302 and.w r3, r3, #2 + 8004fd4: 2b00 cmp r3, #0 + 8004fd6: d103 bne.n 8004fe0 + { + vPortFree( pxTimer ); + 8004fd8: 6ab8 ldr r0, [r7, #40] @ 0x28 + 8004fda: f000 fbe5 bl 80057a8 + no need to free the memory - just mark the timer as + "not active". */ + pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + break; + 8004fde: e00c b.n 8004ffa + pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; + 8004fe0: 6abb ldr r3, [r7, #40] @ 0x28 + 8004fe2: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 + 8004fe6: f023 0301 bic.w r3, r3, #1 + 8004fea: b2da uxtb r2, r3 + 8004fec: 6abb ldr r3, [r7, #40] @ 0x28 + 8004fee: f883 2028 strb.w r2, [r3, #40] @ 0x28 + break; + 8004ff2: e002 b.n 8004ffa + + default : + /* Don't expect to get here. */ + break; + 8004ff4: bf00 nop + 8004ff6: e000 b.n 8004ffa + break; + 8004ff8: bf00 nop + while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ + 8004ffa: 4b08 ldr r3, [pc, #32] @ (800501c ) + 8004ffc: 681b ldr r3, [r3, #0] + 8004ffe: 1d39 adds r1, r7, #4 + 8005000: 2200 movs r2, #0 + 8005002: 4618 mov r0, r3 + 8005004: f7fe fbce bl 80037a4 + 8005008: 4603 mov r3, r0 + 800500a: 2b00 cmp r3, #0 + 800500c: f47f af26 bne.w 8004e5c + } + } + } +} + 8005010: bf00 nop + 8005012: bf00 nop + 8005014: 3730 adds r7, #48 @ 0x30 + 8005016: 46bd mov sp, r7 + 8005018: bd80 pop {r7, pc} + 800501a: bf00 nop + 800501c: 20000e68 .word 0x20000e68 + +08005020 : +/*-----------------------------------------------------------*/ + +static void prvSwitchTimerLists( void ) +{ + 8005020: b580 push {r7, lr} + 8005022: b088 sub sp, #32 + 8005024: af02 add r7, sp, #8 + + /* The tick count has overflowed. The timer lists must be switched. + If there are any timers still referenced from the current timer list + then they must have expired and should be processed before the lists + are switched. */ + while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) + 8005026: e049 b.n 80050bc + { + xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); + 8005028: 4b2e ldr r3, [pc, #184] @ (80050e4 ) + 800502a: 681b ldr r3, [r3, #0] + 800502c: 68db ldr r3, [r3, #12] + 800502e: 681b ldr r3, [r3, #0] + 8005030: 613b str r3, [r7, #16] + + /* Remove the timer from the list. */ + pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + 8005032: 4b2c ldr r3, [pc, #176] @ (80050e4 ) + 8005034: 681b ldr r3, [r3, #0] + 8005036: 68db ldr r3, [r3, #12] + 8005038: 68db ldr r3, [r3, #12] + 800503a: 60fb str r3, [r7, #12] + ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); + 800503c: 68fb ldr r3, [r7, #12] + 800503e: 3304 adds r3, #4 + 8005040: 4618 mov r0, r3 + 8005042: f7fe f8db bl 80031fc + traceTIMER_EXPIRED( pxTimer ); + + /* Execute its callback, then send a command to restart the timer if + it is an auto-reload timer. It cannot be restarted here as the lists + have not yet been switched. */ + pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); + 8005046: 68fb ldr r3, [r7, #12] + 8005048: 6a1b ldr r3, [r3, #32] + 800504a: 68f8 ldr r0, [r7, #12] + 800504c: 4798 blx r3 + + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) + 800504e: 68fb ldr r3, [r7, #12] + 8005050: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 + 8005054: f003 0304 and.w r3, r3, #4 + 8005058: 2b00 cmp r3, #0 + 800505a: d02f beq.n 80050bc + the timer going into the same timer list then it has already expired + and the timer should be re-inserted into the current list so it is + processed again within this loop. Otherwise a command should be sent + to restart the timer to ensure it is only inserted into a list after + the lists have been swapped. */ + xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ); + 800505c: 68fb ldr r3, [r7, #12] + 800505e: 699b ldr r3, [r3, #24] + 8005060: 693a ldr r2, [r7, #16] + 8005062: 4413 add r3, r2 + 8005064: 60bb str r3, [r7, #8] + if( xReloadTime > xNextExpireTime ) + 8005066: 68ba ldr r2, [r7, #8] + 8005068: 693b ldr r3, [r7, #16] + 800506a: 429a cmp r2, r3 + 800506c: d90e bls.n 800508c + { + listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime ); + 800506e: 68fb ldr r3, [r7, #12] + 8005070: 68ba ldr r2, [r7, #8] + 8005072: 605a str r2, [r3, #4] + listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); + 8005074: 68fb ldr r3, [r7, #12] + 8005076: 68fa ldr r2, [r7, #12] + 8005078: 611a str r2, [r3, #16] + vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); + 800507a: 4b1a ldr r3, [pc, #104] @ (80050e4 ) + 800507c: 681a ldr r2, [r3, #0] + 800507e: 68fb ldr r3, [r7, #12] + 8005080: 3304 adds r3, #4 + 8005082: 4619 mov r1, r3 + 8005084: 4610 mov r0, r2 + 8005086: f7fe f880 bl 800318a + 800508a: e017 b.n 80050bc + } + else + { + xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); + 800508c: 2300 movs r3, #0 + 800508e: 9300 str r3, [sp, #0] + 8005090: 2300 movs r3, #0 + 8005092: 693a ldr r2, [r7, #16] + 8005094: 2100 movs r1, #0 + 8005096: 68f8 ldr r0, [r7, #12] + 8005098: f7ff fd58 bl 8004b4c + 800509c: 6078 str r0, [r7, #4] + configASSERT( xResult ); + 800509e: 687b ldr r3, [r7, #4] + 80050a0: 2b00 cmp r3, #0 + 80050a2: d10b bne.n 80050bc + __asm volatile + 80050a4: f04f 0350 mov.w r3, #80 @ 0x50 + 80050a8: f383 8811 msr BASEPRI, r3 + 80050ac: f3bf 8f6f isb sy + 80050b0: f3bf 8f4f dsb sy + 80050b4: 603b str r3, [r7, #0] +} + 80050b6: bf00 nop + 80050b8: bf00 nop + 80050ba: e7fd b.n 80050b8 + while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) + 80050bc: 4b09 ldr r3, [pc, #36] @ (80050e4 ) + 80050be: 681b ldr r3, [r3, #0] + 80050c0: 681b ldr r3, [r3, #0] + 80050c2: 2b00 cmp r3, #0 + 80050c4: d1b0 bne.n 8005028 + { + mtCOVERAGE_TEST_MARKER(); + } + } + + pxTemp = pxCurrentTimerList; + 80050c6: 4b07 ldr r3, [pc, #28] @ (80050e4 ) + 80050c8: 681b ldr r3, [r3, #0] + 80050ca: 617b str r3, [r7, #20] + pxCurrentTimerList = pxOverflowTimerList; + 80050cc: 4b06 ldr r3, [pc, #24] @ (80050e8 ) + 80050ce: 681b ldr r3, [r3, #0] + 80050d0: 4a04 ldr r2, [pc, #16] @ (80050e4 ) + 80050d2: 6013 str r3, [r2, #0] + pxOverflowTimerList = pxTemp; + 80050d4: 4a04 ldr r2, [pc, #16] @ (80050e8 ) + 80050d6: 697b ldr r3, [r7, #20] + 80050d8: 6013 str r3, [r2, #0] +} + 80050da: bf00 nop + 80050dc: 3718 adds r7, #24 + 80050de: 46bd mov sp, r7 + 80050e0: bd80 pop {r7, pc} + 80050e2: bf00 nop + 80050e4: 20000e60 .word 0x20000e60 + 80050e8: 20000e64 .word 0x20000e64 + +080050ec : +/*-----------------------------------------------------------*/ + +static void prvCheckForValidListAndQueue( void ) +{ + 80050ec: b580 push {r7, lr} + 80050ee: b082 sub sp, #8 + 80050f0: af02 add r7, sp, #8 + /* Check that the list from which active timers are referenced, and the + queue used to communicate with the timer service, have been + initialised. */ + taskENTER_CRITICAL(); + 80050f2: f000 f969 bl 80053c8 + { + if( xTimerQueue == NULL ) + 80050f6: 4b15 ldr r3, [pc, #84] @ (800514c ) + 80050f8: 681b ldr r3, [r3, #0] + 80050fa: 2b00 cmp r3, #0 + 80050fc: d120 bne.n 8005140 + { + vListInitialise( &xActiveTimerList1 ); + 80050fe: 4814 ldr r0, [pc, #80] @ (8005150 ) + 8005100: f7fd fff2 bl 80030e8 + vListInitialise( &xActiveTimerList2 ); + 8005104: 4813 ldr r0, [pc, #76] @ (8005154 ) + 8005106: f7fd ffef bl 80030e8 + pxCurrentTimerList = &xActiveTimerList1; + 800510a: 4b13 ldr r3, [pc, #76] @ (8005158 ) + 800510c: 4a10 ldr r2, [pc, #64] @ (8005150 ) + 800510e: 601a str r2, [r3, #0] + pxOverflowTimerList = &xActiveTimerList2; + 8005110: 4b12 ldr r3, [pc, #72] @ (800515c ) + 8005112: 4a10 ldr r2, [pc, #64] @ (8005154 ) + 8005114: 601a str r2, [r3, #0] + /* The timer queue is allocated statically in case + configSUPPORT_DYNAMIC_ALLOCATION is 0. */ + static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ + static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ + + xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); + 8005116: 2300 movs r3, #0 + 8005118: 9300 str r3, [sp, #0] + 800511a: 4b11 ldr r3, [pc, #68] @ (8005160 ) + 800511c: 4a11 ldr r2, [pc, #68] @ (8005164 ) + 800511e: 2110 movs r1, #16 + 8005120: 200a movs r0, #10 + 8005122: f7fe f8ff bl 8003324 + 8005126: 4603 mov r3, r0 + 8005128: 4a08 ldr r2, [pc, #32] @ (800514c ) + 800512a: 6013 str r3, [r2, #0] + } + #endif + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + { + if( xTimerQueue != NULL ) + 800512c: 4b07 ldr r3, [pc, #28] @ (800514c ) + 800512e: 681b ldr r3, [r3, #0] + 8005130: 2b00 cmp r3, #0 + 8005132: d005 beq.n 8005140 + { + vQueueAddToRegistry( xTimerQueue, "TmrQ" ); + 8005134: 4b05 ldr r3, [pc, #20] @ (800514c ) + 8005136: 681b ldr r3, [r3, #0] + 8005138: 490b ldr r1, [pc, #44] @ (8005168 ) + 800513a: 4618 mov r0, r3 + 800513c: f7fe fd24 bl 8003b88 + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + 8005140: f000 f974 bl 800542c +} + 8005144: bf00 nop + 8005146: 46bd mov sp, r7 + 8005148: bd80 pop {r7, pc} + 800514a: bf00 nop + 800514c: 20000e68 .word 0x20000e68 + 8005150: 20000e38 .word 0x20000e38 + 8005154: 20000e4c .word 0x20000e4c + 8005158: 20000e60 .word 0x20000e60 + 800515c: 20000e64 .word 0x20000e64 + 8005160: 20000f14 .word 0x20000f14 + 8005164: 20000e74 .word 0x20000e74 + 8005168: 08005d18 .word 0x08005d18 + +0800516c : + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + 800516c: b480 push {r7} + 800516e: b085 sub sp, #20 + 8005170: af00 add r7, sp, #0 + 8005172: 60f8 str r0, [r7, #12] + 8005174: 60b9 str r1, [r7, #8] + 8005176: 607a str r2, [r7, #4] + /* Simulate the stack frame as it would be created by a context switch + interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + of interrupts, and to ensure alignment. */ + pxTopOfStack--; + 8005178: 68fb ldr r3, [r7, #12] + 800517a: 3b04 subs r3, #4 + 800517c: 60fb str r3, [r7, #12] + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + 800517e: 68fb ldr r3, [r7, #12] + 8005180: f04f 7280 mov.w r2, #16777216 @ 0x1000000 + 8005184: 601a str r2, [r3, #0] + pxTopOfStack--; + 8005186: 68fb ldr r3, [r7, #12] + 8005188: 3b04 subs r3, #4 + 800518a: 60fb str r3, [r7, #12] + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + 800518c: 68bb ldr r3, [r7, #8] + 800518e: f023 0201 bic.w r2, r3, #1 + 8005192: 68fb ldr r3, [r7, #12] + 8005194: 601a str r2, [r3, #0] + pxTopOfStack--; + 8005196: 68fb ldr r3, [r7, #12] + 8005198: 3b04 subs r3, #4 + 800519a: 60fb str r3, [r7, #12] + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + 800519c: 4a0c ldr r2, [pc, #48] @ (80051d0 ) + 800519e: 68fb ldr r3, [r7, #12] + 80051a0: 601a str r2, [r3, #0] + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + 80051a2: 68fb ldr r3, [r7, #12] + 80051a4: 3b14 subs r3, #20 + 80051a6: 60fb str r3, [r7, #12] + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + 80051a8: 687a ldr r2, [r7, #4] + 80051aa: 68fb ldr r3, [r7, #12] + 80051ac: 601a str r2, [r3, #0] + + /* A save method is being used that requires each task to maintain its + own exec return value. */ + pxTopOfStack--; + 80051ae: 68fb ldr r3, [r7, #12] + 80051b0: 3b04 subs r3, #4 + 80051b2: 60fb str r3, [r7, #12] + *pxTopOfStack = portINITIAL_EXC_RETURN; + 80051b4: 68fb ldr r3, [r7, #12] + 80051b6: f06f 0202 mvn.w r2, #2 + 80051ba: 601a str r2, [r3, #0] + + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + 80051bc: 68fb ldr r3, [r7, #12] + 80051be: 3b20 subs r3, #32 + 80051c0: 60fb str r3, [r7, #12] + + return pxTopOfStack; + 80051c2: 68fb ldr r3, [r7, #12] +} + 80051c4: 4618 mov r0, r3 + 80051c6: 3714 adds r7, #20 + 80051c8: 46bd mov sp, r7 + 80051ca: f85d 7b04 ldr.w r7, [sp], #4 + 80051ce: 4770 bx lr + 80051d0: 080051d5 .word 0x080051d5 + +080051d4 : +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + 80051d4: b480 push {r7} + 80051d6: b085 sub sp, #20 + 80051d8: af00 add r7, sp, #0 +volatile uint32_t ulDummy = 0; + 80051da: 2300 movs r3, #0 + 80051dc: 607b str r3, [r7, #4] + its caller as there is nothing to return to. If a task wants to exit it + should instead call vTaskDelete( NULL ). + + Artificially force an assert() to be triggered if configASSERT() is + defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + 80051de: 4b13 ldr r3, [pc, #76] @ (800522c ) + 80051e0: 681b ldr r3, [r3, #0] + 80051e2: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 80051e6: d00b beq.n 8005200 + __asm volatile + 80051e8: f04f 0350 mov.w r3, #80 @ 0x50 + 80051ec: f383 8811 msr BASEPRI, r3 + 80051f0: f3bf 8f6f isb sy + 80051f4: f3bf 8f4f dsb sy + 80051f8: 60fb str r3, [r7, #12] +} + 80051fa: bf00 nop + 80051fc: bf00 nop + 80051fe: e7fd b.n 80051fc + __asm volatile + 8005200: f04f 0350 mov.w r3, #80 @ 0x50 + 8005204: f383 8811 msr BASEPRI, r3 + 8005208: f3bf 8f6f isb sy + 800520c: f3bf 8f4f dsb sy + 8005210: 60bb str r3, [r7, #8] +} + 8005212: bf00 nop + portDISABLE_INTERRUPTS(); + while( ulDummy == 0 ) + 8005214: bf00 nop + 8005216: 687b ldr r3, [r7, #4] + 8005218: 2b00 cmp r3, #0 + 800521a: d0fc beq.n 8005216 + about code appearing after this function is called - making ulDummy + volatile makes the compiler think the function could return and + therefore not output an 'unreachable code' warning for code that appears + after it. */ + } +} + 800521c: bf00 nop + 800521e: bf00 nop + 8005220: 3714 adds r7, #20 + 8005222: 46bd mov sp, r7 + 8005224: f85d 7b04 ldr.w r7, [sp], #4 + 8005228: 4770 bx lr + 800522a: bf00 nop + 800522c: 2000000c .word 0x2000000c + +08005230 : +/*-----------------------------------------------------------*/ + +void vPortSVCHandler( void ) +{ + __asm volatile ( + 8005230: 4b07 ldr r3, [pc, #28] @ (8005250 ) + 8005232: 6819 ldr r1, [r3, #0] + 8005234: 6808 ldr r0, [r1, #0] + 8005236: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800523a: f380 8809 msr PSP, r0 + 800523e: f3bf 8f6f isb sy + 8005242: f04f 0000 mov.w r0, #0 + 8005246: f380 8811 msr BASEPRI, r0 + 800524a: 4770 bx lr + 800524c: f3af 8000 nop.w + +08005250 : + 8005250: 20000938 .word 0x20000938 + " bx r14 \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB \n" + ); +} + 8005254: bf00 nop + 8005256: bf00 nop + +08005258 : +{ + /* Start the first task. This also clears the bit that indicates the FPU is + in use in case the FPU was used before the scheduler was started - which + would otherwise result in the unnecessary leaving of space in the SVC stack + for lazy saving of FPU registers. */ + __asm volatile( + 8005258: 4808 ldr r0, [pc, #32] @ (800527c ) + 800525a: 6800 ldr r0, [r0, #0] + 800525c: 6800 ldr r0, [r0, #0] + 800525e: f380 8808 msr MSP, r0 + 8005262: f04f 0000 mov.w r0, #0 + 8005266: f380 8814 msr CONTROL, r0 + 800526a: b662 cpsie i + 800526c: b661 cpsie f + 800526e: f3bf 8f4f dsb sy + 8005272: f3bf 8f6f isb sy + 8005276: df00 svc 0 + 8005278: bf00 nop + " dsb \n" + " isb \n" + " svc 0 \n" /* System call to start first task. */ + " nop \n" + ); +} + 800527a: bf00 nop + 800527c: e000ed08 .word 0xe000ed08 + +08005280 : + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + 8005280: b580 push {r7, lr} + 8005282: b086 sub sp, #24 + 8005284: af00 add r7, sp, #0 + configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + + /* This port can be used on all revisions of the Cortex-M7 core other than + the r0p1 parts. r0p1 parts should use the port from the + /source/portable/GCC/ARM_CM7/r0p1 directory. */ + configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); + 8005286: 4b47 ldr r3, [pc, #284] @ (80053a4 ) + 8005288: 681b ldr r3, [r3, #0] + 800528a: 4a47 ldr r2, [pc, #284] @ (80053a8 ) + 800528c: 4293 cmp r3, r2 + 800528e: d10b bne.n 80052a8 + __asm volatile + 8005290: f04f 0350 mov.w r3, #80 @ 0x50 + 8005294: f383 8811 msr BASEPRI, r3 + 8005298: f3bf 8f6f isb sy + 800529c: f3bf 8f4f dsb sy + 80052a0: 60fb str r3, [r7, #12] +} + 80052a2: bf00 nop + 80052a4: bf00 nop + 80052a6: e7fd b.n 80052a4 + configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); + 80052a8: 4b3e ldr r3, [pc, #248] @ (80053a4 ) + 80052aa: 681b ldr r3, [r3, #0] + 80052ac: 4a3f ldr r2, [pc, #252] @ (80053ac ) + 80052ae: 4293 cmp r3, r2 + 80052b0: d10b bne.n 80052ca + __asm volatile + 80052b2: f04f 0350 mov.w r3, #80 @ 0x50 + 80052b6: f383 8811 msr BASEPRI, r3 + 80052ba: f3bf 8f6f isb sy + 80052be: f3bf 8f4f dsb sy + 80052c2: 613b str r3, [r7, #16] +} + 80052c4: bf00 nop + 80052c6: bf00 nop + 80052c8: e7fd b.n 80052c6 + + #if( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + 80052ca: 4b39 ldr r3, [pc, #228] @ (80053b0 ) + 80052cc: 617b str r3, [r7, #20] + functions can be called. ISR safe functions are those that end in + "FromISR". FreeRTOS maintains separate thread and ISR API functions to + ensure interrupt entry is as fast and simple as possible. + + Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + 80052ce: 697b ldr r3, [r7, #20] + 80052d0: 781b ldrb r3, [r3, #0] + 80052d2: b2db uxtb r3, r3 + 80052d4: 607b str r3, [r7, #4] + + /* Determine the number of priority bits available. First write to all + possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + 80052d6: 697b ldr r3, [r7, #20] + 80052d8: 22ff movs r2, #255 @ 0xff + 80052da: 701a strb r2, [r3, #0] + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + 80052dc: 697b ldr r3, [r7, #20] + 80052de: 781b ldrb r3, [r3, #0] + 80052e0: b2db uxtb r3, r3 + 80052e2: 70fb strb r3, [r7, #3] + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + 80052e4: 78fb ldrb r3, [r7, #3] + 80052e6: b2db uxtb r3, r3 + 80052e8: f003 0350 and.w r3, r3, #80 @ 0x50 + 80052ec: b2da uxtb r2, r3 + 80052ee: 4b31 ldr r3, [pc, #196] @ (80053b4 ) + 80052f0: 701a strb r2, [r3, #0] + + /* Calculate the maximum acceptable priority group value for the number + of bits read back. */ + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; + 80052f2: 4b31 ldr r3, [pc, #196] @ (80053b8 ) + 80052f4: 2207 movs r2, #7 + 80052f6: 601a str r2, [r3, #0] + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + 80052f8: e009 b.n 800530e + { + ulMaxPRIGROUPValue--; + 80052fa: 4b2f ldr r3, [pc, #188] @ (80053b8 ) + 80052fc: 681b ldr r3, [r3, #0] + 80052fe: 3b01 subs r3, #1 + 8005300: 4a2d ldr r2, [pc, #180] @ (80053b8 ) + 8005302: 6013 str r3, [r2, #0] + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + 8005304: 78fb ldrb r3, [r7, #3] + 8005306: b2db uxtb r3, r3 + 8005308: 005b lsls r3, r3, #1 + 800530a: b2db uxtb r3, r3 + 800530c: 70fb strb r3, [r7, #3] + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + 800530e: 78fb ldrb r3, [r7, #3] + 8005310: b2db uxtb r3, r3 + 8005312: f003 0380 and.w r3, r3, #128 @ 0x80 + 8005316: 2b80 cmp r3, #128 @ 0x80 + 8005318: d0ef beq.n 80052fa + #ifdef configPRIO_BITS + { + /* Check the FreeRTOS configuration that defines the number of + priority bits matches the number of priority bits actually queried + from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); + 800531a: 4b27 ldr r3, [pc, #156] @ (80053b8 ) + 800531c: 681b ldr r3, [r3, #0] + 800531e: f1c3 0307 rsb r3, r3, #7 + 8005322: 2b04 cmp r3, #4 + 8005324: d00b beq.n 800533e + __asm volatile + 8005326: f04f 0350 mov.w r3, #80 @ 0x50 + 800532a: f383 8811 msr BASEPRI, r3 + 800532e: f3bf 8f6f isb sy + 8005332: f3bf 8f4f dsb sy + 8005336: 60bb str r3, [r7, #8] +} + 8005338: bf00 nop + 800533a: bf00 nop + 800533c: e7fd b.n 800533a + } + #endif + + /* Shift the priority group value back to its position within the AIRCR + register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + 800533e: 4b1e ldr r3, [pc, #120] @ (80053b8 ) + 8005340: 681b ldr r3, [r3, #0] + 8005342: 021b lsls r3, r3, #8 + 8005344: 4a1c ldr r2, [pc, #112] @ (80053b8 ) + 8005346: 6013 str r3, [r2, #0] + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + 8005348: 4b1b ldr r3, [pc, #108] @ (80053b8 ) + 800534a: 681b ldr r3, [r3, #0] + 800534c: f403 63e0 and.w r3, r3, #1792 @ 0x700 + 8005350: 4a19 ldr r2, [pc, #100] @ (80053b8 ) + 8005352: 6013 str r3, [r2, #0] + + /* Restore the clobbered interrupt priority register to its original + value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + 8005354: 687b ldr r3, [r7, #4] + 8005356: b2da uxtb r2, r3 + 8005358: 697b ldr r3, [r7, #20] + 800535a: 701a strb r2, [r3, #0] + } + #endif /* conifgASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI; + 800535c: 4b17 ldr r3, [pc, #92] @ (80053bc ) + 800535e: 681b ldr r3, [r3, #0] + 8005360: 4a16 ldr r2, [pc, #88] @ (80053bc ) + 8005362: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 + 8005366: 6013 str r3, [r2, #0] + portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI; + 8005368: 4b14 ldr r3, [pc, #80] @ (80053bc ) + 800536a: 681b ldr r3, [r3, #0] + 800536c: 4a13 ldr r2, [pc, #76] @ (80053bc ) + 800536e: f043 4370 orr.w r3, r3, #4026531840 @ 0xf0000000 + 8005372: 6013 str r3, [r2, #0] + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + vPortSetupTimerInterrupt(); + 8005374: f000 f8da bl 800552c + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + 8005378: 4b11 ldr r3, [pc, #68] @ (80053c0 ) + 800537a: 2200 movs r2, #0 + 800537c: 601a str r2, [r3, #0] + + /* Ensure the VFP is enabled - it should be anyway. */ + vPortEnableVFP(); + 800537e: f000 f8f9 bl 8005574 + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + 8005382: 4b10 ldr r3, [pc, #64] @ (80053c4 ) + 8005384: 681b ldr r3, [r3, #0] + 8005386: 4a0f ldr r2, [pc, #60] @ (80053c4 ) + 8005388: f043 4340 orr.w r3, r3, #3221225472 @ 0xc0000000 + 800538c: 6013 str r3, [r2, #0] + + /* Start the first task. */ + prvPortStartFirstTask(); + 800538e: f7ff ff63 bl 8005258 + exit error function to prevent compiler warnings about a static function + not being called in the case that the application writer overrides this + functionality by defining configTASK_RETURN_ADDRESS. Call + vTaskSwitchContext() so link time optimisation does not remove the + symbol. */ + vTaskSwitchContext(); + 8005392: f7ff f831 bl 80043f8 + prvTaskExitError(); + 8005396: f7ff ff1d bl 80051d4 + + /* Should not get here! */ + return 0; + 800539a: 2300 movs r3, #0 +} + 800539c: 4618 mov r0, r3 + 800539e: 3718 adds r7, #24 + 80053a0: 46bd mov sp, r7 + 80053a2: bd80 pop {r7, pc} + 80053a4: e000ed00 .word 0xe000ed00 + 80053a8: 410fc271 .word 0x410fc271 + 80053ac: 410fc270 .word 0x410fc270 + 80053b0: e000e400 .word 0xe000e400 + 80053b4: 20000f64 .word 0x20000f64 + 80053b8: 20000f68 .word 0x20000f68 + 80053bc: e000ed20 .word 0xe000ed20 + 80053c0: 2000000c .word 0x2000000c + 80053c4: e000ef34 .word 0xe000ef34 + +080053c8 : + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + 80053c8: b480 push {r7} + 80053ca: b083 sub sp, #12 + 80053cc: af00 add r7, sp, #0 + __asm volatile + 80053ce: f04f 0350 mov.w r3, #80 @ 0x50 + 80053d2: f383 8811 msr BASEPRI, r3 + 80053d6: f3bf 8f6f isb sy + 80053da: f3bf 8f4f dsb sy + 80053de: 607b str r3, [r7, #4] +} + 80053e0: bf00 nop + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + 80053e2: 4b10 ldr r3, [pc, #64] @ (8005424 ) + 80053e4: 681b ldr r3, [r3, #0] + 80053e6: 3301 adds r3, #1 + 80053e8: 4a0e ldr r2, [pc, #56] @ (8005424 ) + 80053ea: 6013 str r3, [r2, #0] + /* This is not the interrupt safe version of the enter critical function so + assert() if it is being called from an interrupt context. Only API + functions that end in "FromISR" can be used in an interrupt. Only assert if + the critical nesting count is 1 to protect against recursive calls if the + assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + 80053ec: 4b0d ldr r3, [pc, #52] @ (8005424 ) + 80053ee: 681b ldr r3, [r3, #0] + 80053f0: 2b01 cmp r3, #1 + 80053f2: d110 bne.n 8005416 + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + 80053f4: 4b0c ldr r3, [pc, #48] @ (8005428 ) + 80053f6: 681b ldr r3, [r3, #0] + 80053f8: b2db uxtb r3, r3 + 80053fa: 2b00 cmp r3, #0 + 80053fc: d00b beq.n 8005416 + __asm volatile + 80053fe: f04f 0350 mov.w r3, #80 @ 0x50 + 8005402: f383 8811 msr BASEPRI, r3 + 8005406: f3bf 8f6f isb sy + 800540a: f3bf 8f4f dsb sy + 800540e: 603b str r3, [r7, #0] +} + 8005410: bf00 nop + 8005412: bf00 nop + 8005414: e7fd b.n 8005412 + } +} + 8005416: bf00 nop + 8005418: 370c adds r7, #12 + 800541a: 46bd mov sp, r7 + 800541c: f85d 7b04 ldr.w r7, [sp], #4 + 8005420: 4770 bx lr + 8005422: bf00 nop + 8005424: 2000000c .word 0x2000000c + 8005428: e000ed04 .word 0xe000ed04 + +0800542c : +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + 800542c: b480 push {r7} + 800542e: b083 sub sp, #12 + 8005430: af00 add r7, sp, #0 + configASSERT( uxCriticalNesting ); + 8005432: 4b12 ldr r3, [pc, #72] @ (800547c ) + 8005434: 681b ldr r3, [r3, #0] + 8005436: 2b00 cmp r3, #0 + 8005438: d10b bne.n 8005452 + __asm volatile + 800543a: f04f 0350 mov.w r3, #80 @ 0x50 + 800543e: f383 8811 msr BASEPRI, r3 + 8005442: f3bf 8f6f isb sy + 8005446: f3bf 8f4f dsb sy + 800544a: 607b str r3, [r7, #4] +} + 800544c: bf00 nop + 800544e: bf00 nop + 8005450: e7fd b.n 800544e + uxCriticalNesting--; + 8005452: 4b0a ldr r3, [pc, #40] @ (800547c ) + 8005454: 681b ldr r3, [r3, #0] + 8005456: 3b01 subs r3, #1 + 8005458: 4a08 ldr r2, [pc, #32] @ (800547c ) + 800545a: 6013 str r3, [r2, #0] + if( uxCriticalNesting == 0 ) + 800545c: 4b07 ldr r3, [pc, #28] @ (800547c ) + 800545e: 681b ldr r3, [r3, #0] + 8005460: 2b00 cmp r3, #0 + 8005462: d105 bne.n 8005470 + 8005464: 2300 movs r3, #0 + 8005466: 603b str r3, [r7, #0] + __asm volatile + 8005468: 683b ldr r3, [r7, #0] + 800546a: f383 8811 msr BASEPRI, r3 +} + 800546e: bf00 nop + { + portENABLE_INTERRUPTS(); + } +} + 8005470: bf00 nop + 8005472: 370c adds r7, #12 + 8005474: 46bd mov sp, r7 + 8005476: f85d 7b04 ldr.w r7, [sp], #4 + 800547a: 4770 bx lr + 800547c: 2000000c .word 0x2000000c + +08005480 : + +void xPortPendSVHandler( void ) +{ + /* This is a naked function. */ + + __asm volatile + 8005480: f3ef 8009 mrs r0, PSP + 8005484: f3bf 8f6f isb sy + 8005488: 4b15 ldr r3, [pc, #84] @ (80054e0 ) + 800548a: 681a ldr r2, [r3, #0] + 800548c: f01e 0f10 tst.w lr, #16 + 8005490: bf08 it eq + 8005492: ed20 8a10 vstmdbeq r0!, {s16-s31} + 8005496: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800549a: 6010 str r0, [r2, #0] + 800549c: b409 push {r0, r3} + 800549e: f04f 0050 mov.w r0, #80 @ 0x50 + 80054a2: f380 8811 msr BASEPRI, r0 + 80054a6: f3bf 8f4f dsb sy + 80054aa: f3bf 8f6f isb sy + 80054ae: f7fe ffa3 bl 80043f8 + 80054b2: f04f 0000 mov.w r0, #0 + 80054b6: f380 8811 msr BASEPRI, r0 + 80054ba: bc09 pop {r0, r3} + 80054bc: 6819 ldr r1, [r3, #0] + 80054be: 6808 ldr r0, [r1, #0] + 80054c0: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 80054c4: f01e 0f10 tst.w lr, #16 + 80054c8: bf08 it eq + 80054ca: ecb0 8a10 vldmiaeq r0!, {s16-s31} + 80054ce: f380 8809 msr PSP, r0 + 80054d2: f3bf 8f6f isb sy + 80054d6: 4770 bx lr + 80054d8: f3af 8000 nop.w + 80054dc: f3af 8000 nop.w + +080054e0 : + 80054e0: 20000938 .word 0x20000938 + " \n" + " .align 4 \n" + "pxCurrentTCBConst: .word pxCurrentTCB \n" + ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) + ); +} + 80054e4: bf00 nop + 80054e6: bf00 nop + +080054e8 : +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + 80054e8: b580 push {r7, lr} + 80054ea: b082 sub sp, #8 + 80054ec: af00 add r7, sp, #0 + __asm volatile + 80054ee: f04f 0350 mov.w r3, #80 @ 0x50 + 80054f2: f383 8811 msr BASEPRI, r3 + 80054f6: f3bf 8f6f isb sy + 80054fa: f3bf 8f4f dsb sy + 80054fe: 607b str r3, [r7, #4] +} + 8005500: bf00 nop + save and then restore the interrupt mask value as its value is already + known. */ + portDISABLE_INTERRUPTS(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + 8005502: f7fe febf bl 8004284 + 8005506: 4603 mov r3, r0 + 8005508: 2b00 cmp r3, #0 + 800550a: d003 beq.n 8005514 + { + /* A context switch is required. Context switching is performed in + the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + 800550c: 4b06 ldr r3, [pc, #24] @ (8005528 ) + 800550e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 + 8005512: 601a str r2, [r3, #0] + 8005514: 2300 movs r3, #0 + 8005516: 603b str r3, [r7, #0] + __asm volatile + 8005518: 683b ldr r3, [r7, #0] + 800551a: f383 8811 msr BASEPRI, r3 +} + 800551e: bf00 nop + } + } + portENABLE_INTERRUPTS(); +} + 8005520: bf00 nop + 8005522: 3708 adds r7, #8 + 8005524: 46bd mov sp, r7 + 8005526: bd80 pop {r7, pc} + 8005528: e000ed04 .word 0xe000ed04 + +0800552c : +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__attribute__(( weak )) void vPortSetupTimerInterrupt( void ) +{ + 800552c: b480 push {r7} + 800552e: af00 add r7, sp, #0 + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + 8005530: 4b0b ldr r3, [pc, #44] @ (8005560 ) + 8005532: 2200 movs r2, #0 + 8005534: 601a str r2, [r3, #0] + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + 8005536: 4b0b ldr r3, [pc, #44] @ (8005564 ) + 8005538: 2200 movs r2, #0 + 800553a: 601a str r2, [r3, #0] + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + 800553c: 4b0a ldr r3, [pc, #40] @ (8005568 ) + 800553e: 681b ldr r3, [r3, #0] + 8005540: 4a0a ldr r2, [pc, #40] @ (800556c ) + 8005542: fba2 2303 umull r2, r3, r2, r3 + 8005546: 099b lsrs r3, r3, #6 + 8005548: 4a09 ldr r2, [pc, #36] @ (8005570 ) + 800554a: 3b01 subs r3, #1 + 800554c: 6013 str r3, [r2, #0] + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); + 800554e: 4b04 ldr r3, [pc, #16] @ (8005560 ) + 8005550: 2207 movs r2, #7 + 8005552: 601a str r2, [r3, #0] +} + 8005554: bf00 nop + 8005556: 46bd mov sp, r7 + 8005558: f85d 7b04 ldr.w r7, [sp], #4 + 800555c: 4770 bx lr + 800555e: bf00 nop + 8005560: e000e010 .word 0xe000e010 + 8005564: e000e018 .word 0xe000e018 + 8005568: 20000000 .word 0x20000000 + 800556c: 10624dd3 .word 0x10624dd3 + 8005570: e000e014 .word 0xe000e014 + +08005574 : +/*-----------------------------------------------------------*/ + +/* This is a naked function. */ +static void vPortEnableVFP( void ) +{ + __asm volatile + 8005574: f8df 000c ldr.w r0, [pc, #12] @ 8005584 + 8005578: 6801 ldr r1, [r0, #0] + 800557a: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 + 800557e: 6001 str r1, [r0, #0] + 8005580: 4770 bx lr + " \n" + " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */ + " str r1, [r0] \n" + " bx r14 " + ); +} + 8005582: bf00 nop + 8005584: e000ed88 .word 0xe000ed88 + +08005588 : +/*-----------------------------------------------------------*/ + +#if( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + 8005588: b480 push {r7} + 800558a: b085 sub sp, #20 + 800558c: af00 add r7, sp, #0 + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); + 800558e: f3ef 8305 mrs r3, IPSR + 8005592: 60fb str r3, [r7, #12] + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + 8005594: 68fb ldr r3, [r7, #12] + 8005596: 2b0f cmp r3, #15 + 8005598: d915 bls.n 80055c6 + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + 800559a: 4a18 ldr r2, [pc, #96] @ (80055fc ) + 800559c: 68fb ldr r3, [r7, #12] + 800559e: 4413 add r3, r2 + 80055a0: 781b ldrb r3, [r3, #0] + 80055a2: 72fb strb r3, [r7, #11] + interrupt entry is as fast and simple as possible. + + The following links provide detailed information: + http://www.freertos.org/RTOS-Cortex-M3-M4.html + http://www.freertos.org/FAQHelp.html */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + 80055a4: 4b16 ldr r3, [pc, #88] @ (8005600 ) + 80055a6: 781b ldrb r3, [r3, #0] + 80055a8: 7afa ldrb r2, [r7, #11] + 80055aa: 429a cmp r2, r3 + 80055ac: d20b bcs.n 80055c6 + __asm volatile + 80055ae: f04f 0350 mov.w r3, #80 @ 0x50 + 80055b2: f383 8811 msr BASEPRI, r3 + 80055b6: f3bf 8f6f isb sy + 80055ba: f3bf 8f4f dsb sy + 80055be: 607b str r3, [r7, #4] +} + 80055c0: bf00 nop + 80055c2: bf00 nop + 80055c4: e7fd b.n 80055c2 + configuration then the correct setting can be achieved on all Cortex-M + devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + scheduler. Note however that some vendor specific peripheral libraries + assume a non-zero priority group setting, in which cases using a value + of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + 80055c6: 4b0f ldr r3, [pc, #60] @ (8005604 ) + 80055c8: 681b ldr r3, [r3, #0] + 80055ca: f403 62e0 and.w r2, r3, #1792 @ 0x700 + 80055ce: 4b0e ldr r3, [pc, #56] @ (8005608 ) + 80055d0: 681b ldr r3, [r3, #0] + 80055d2: 429a cmp r2, r3 + 80055d4: d90b bls.n 80055ee + __asm volatile + 80055d6: f04f 0350 mov.w r3, #80 @ 0x50 + 80055da: f383 8811 msr BASEPRI, r3 + 80055de: f3bf 8f6f isb sy + 80055e2: f3bf 8f4f dsb sy + 80055e6: 603b str r3, [r7, #0] +} + 80055e8: bf00 nop + 80055ea: bf00 nop + 80055ec: e7fd b.n 80055ea + } + 80055ee: bf00 nop + 80055f0: 3714 adds r7, #20 + 80055f2: 46bd mov sp, r7 + 80055f4: f85d 7b04 ldr.w r7, [sp], #4 + 80055f8: 4770 bx lr + 80055fa: bf00 nop + 80055fc: e000e3f0 .word 0xe000e3f0 + 8005600: 20000f64 .word 0x20000f64 + 8005604: e000ed0c .word 0xe000ed0c + 8005608: 20000f68 .word 0x20000f68 + +0800560c : +static size_t xBlockAllocatedBit = 0; + +/*-----------------------------------------------------------*/ + +void *pvPortMalloc( size_t xWantedSize ) +{ + 800560c: b580 push {r7, lr} + 800560e: b08a sub sp, #40 @ 0x28 + 8005610: af00 add r7, sp, #0 + 8005612: 6078 str r0, [r7, #4] +BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink; +void *pvReturn = NULL; + 8005614: 2300 movs r3, #0 + 8005616: 61fb str r3, [r7, #28] + + vTaskSuspendAll(); + 8005618: f7fe fd78 bl 800410c + { + /* If this is the first call to malloc then the heap will require + initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + 800561c: 4b5c ldr r3, [pc, #368] @ (8005790 ) + 800561e: 681b ldr r3, [r3, #0] + 8005620: 2b00 cmp r3, #0 + 8005622: d101 bne.n 8005628 + { + prvHeapInit(); + 8005624: f000 f924 bl 8005870 + + /* Check the requested block size is not so large that the top bit is + set. The top bit of the block size member of the BlockLink_t structure + is used to determine who owns the block - the application or the + kernel, so it must be free. */ + if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + 8005628: 4b5a ldr r3, [pc, #360] @ (8005794 ) + 800562a: 681a ldr r2, [r3, #0] + 800562c: 687b ldr r3, [r7, #4] + 800562e: 4013 ands r3, r2 + 8005630: 2b00 cmp r3, #0 + 8005632: f040 8095 bne.w 8005760 + { + /* The wanted size is increased so it can contain a BlockLink_t + structure in addition to the requested amount of bytes. */ + if( xWantedSize > 0 ) + 8005636: 687b ldr r3, [r7, #4] + 8005638: 2b00 cmp r3, #0 + 800563a: d01e beq.n 800567a + { + xWantedSize += xHeapStructSize; + 800563c: 2208 movs r2, #8 + 800563e: 687b ldr r3, [r7, #4] + 8005640: 4413 add r3, r2 + 8005642: 607b str r3, [r7, #4] + + /* Ensure that blocks are always aligned to the required number + of bytes. */ + if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) + 8005644: 687b ldr r3, [r7, #4] + 8005646: f003 0307 and.w r3, r3, #7 + 800564a: 2b00 cmp r3, #0 + 800564c: d015 beq.n 800567a + { + /* Byte alignment required. */ + xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); + 800564e: 687b ldr r3, [r7, #4] + 8005650: f023 0307 bic.w r3, r3, #7 + 8005654: 3308 adds r3, #8 + 8005656: 607b str r3, [r7, #4] + configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 ); + 8005658: 687b ldr r3, [r7, #4] + 800565a: f003 0307 and.w r3, r3, #7 + 800565e: 2b00 cmp r3, #0 + 8005660: d00b beq.n 800567a + __asm volatile + 8005662: f04f 0350 mov.w r3, #80 @ 0x50 + 8005666: f383 8811 msr BASEPRI, r3 + 800566a: f3bf 8f6f isb sy + 800566e: f3bf 8f4f dsb sy + 8005672: 617b str r3, [r7, #20] +} + 8005674: bf00 nop + 8005676: bf00 nop + 8005678: e7fd b.n 8005676 + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + 800567a: 687b ldr r3, [r7, #4] + 800567c: 2b00 cmp r3, #0 + 800567e: d06f beq.n 8005760 + 8005680: 4b45 ldr r3, [pc, #276] @ (8005798 ) + 8005682: 681b ldr r3, [r3, #0] + 8005684: 687a ldr r2, [r7, #4] + 8005686: 429a cmp r2, r3 + 8005688: d86a bhi.n 8005760 + { + /* Traverse the list from the start (lowest address) block until + one of adequate size is found. */ + pxPreviousBlock = &xStart; + 800568a: 4b44 ldr r3, [pc, #272] @ (800579c ) + 800568c: 623b str r3, [r7, #32] + pxBlock = xStart.pxNextFreeBlock; + 800568e: 4b43 ldr r3, [pc, #268] @ (800579c ) + 8005690: 681b ldr r3, [r3, #0] + 8005692: 627b str r3, [r7, #36] @ 0x24 + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + 8005694: e004 b.n 80056a0 + { + pxPreviousBlock = pxBlock; + 8005696: 6a7b ldr r3, [r7, #36] @ 0x24 + 8005698: 623b str r3, [r7, #32] + pxBlock = pxBlock->pxNextFreeBlock; + 800569a: 6a7b ldr r3, [r7, #36] @ 0x24 + 800569c: 681b ldr r3, [r3, #0] + 800569e: 627b str r3, [r7, #36] @ 0x24 + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + 80056a0: 6a7b ldr r3, [r7, #36] @ 0x24 + 80056a2: 685b ldr r3, [r3, #4] + 80056a4: 687a ldr r2, [r7, #4] + 80056a6: 429a cmp r2, r3 + 80056a8: d903 bls.n 80056b2 + 80056aa: 6a7b ldr r3, [r7, #36] @ 0x24 + 80056ac: 681b ldr r3, [r3, #0] + 80056ae: 2b00 cmp r3, #0 + 80056b0: d1f1 bne.n 8005696 + } + + /* If the end marker was reached then a block of adequate size + was not found. */ + if( pxBlock != pxEnd ) + 80056b2: 4b37 ldr r3, [pc, #220] @ (8005790 ) + 80056b4: 681b ldr r3, [r3, #0] + 80056b6: 6a7a ldr r2, [r7, #36] @ 0x24 + 80056b8: 429a cmp r2, r3 + 80056ba: d051 beq.n 8005760 + { + /* Return the memory space pointed to - jumping over the + BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + 80056bc: 6a3b ldr r3, [r7, #32] + 80056be: 681b ldr r3, [r3, #0] + 80056c0: 2208 movs r2, #8 + 80056c2: 4413 add r3, r2 + 80056c4: 61fb str r3, [r7, #28] + + /* This block is being returned for use so must be taken out + of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + 80056c6: 6a7b ldr r3, [r7, #36] @ 0x24 + 80056c8: 681a ldr r2, [r3, #0] + 80056ca: 6a3b ldr r3, [r7, #32] + 80056cc: 601a str r2, [r3, #0] + + /* If the block is larger than required it can be split into + two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) + 80056ce: 6a7b ldr r3, [r7, #36] @ 0x24 + 80056d0: 685a ldr r2, [r3, #4] + 80056d2: 687b ldr r3, [r7, #4] + 80056d4: 1ad2 subs r2, r2, r3 + 80056d6: 2308 movs r3, #8 + 80056d8: 005b lsls r3, r3, #1 + 80056da: 429a cmp r2, r3 + 80056dc: d920 bls.n 8005720 + { + /* This block is to be split into two. Create a new + block following the number of bytes requested. The void + cast is used to prevent byte alignment warnings from the + compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + 80056de: 6a7a ldr r2, [r7, #36] @ 0x24 + 80056e0: 687b ldr r3, [r7, #4] + 80056e2: 4413 add r3, r2 + 80056e4: 61bb str r3, [r7, #24] + configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 ); + 80056e6: 69bb ldr r3, [r7, #24] + 80056e8: f003 0307 and.w r3, r3, #7 + 80056ec: 2b00 cmp r3, #0 + 80056ee: d00b beq.n 8005708 + __asm volatile + 80056f0: f04f 0350 mov.w r3, #80 @ 0x50 + 80056f4: f383 8811 msr BASEPRI, r3 + 80056f8: f3bf 8f6f isb sy + 80056fc: f3bf 8f4f dsb sy + 8005700: 613b str r3, [r7, #16] +} + 8005702: bf00 nop + 8005704: bf00 nop + 8005706: e7fd b.n 8005704 + + /* Calculate the sizes of two blocks split from the + single block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + 8005708: 6a7b ldr r3, [r7, #36] @ 0x24 + 800570a: 685a ldr r2, [r3, #4] + 800570c: 687b ldr r3, [r7, #4] + 800570e: 1ad2 subs r2, r2, r3 + 8005710: 69bb ldr r3, [r7, #24] + 8005712: 605a str r2, [r3, #4] + pxBlock->xBlockSize = xWantedSize; + 8005714: 6a7b ldr r3, [r7, #36] @ 0x24 + 8005716: 687a ldr r2, [r7, #4] + 8005718: 605a str r2, [r3, #4] + + /* Insert the new block into the list of free blocks. */ + prvInsertBlockIntoFreeList( pxNewBlockLink ); + 800571a: 69b8 ldr r0, [r7, #24] + 800571c: f000 f90a bl 8005934 + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + 8005720: 4b1d ldr r3, [pc, #116] @ (8005798 ) + 8005722: 681a ldr r2, [r3, #0] + 8005724: 6a7b ldr r3, [r7, #36] @ 0x24 + 8005726: 685b ldr r3, [r3, #4] + 8005728: 1ad3 subs r3, r2, r3 + 800572a: 4a1b ldr r2, [pc, #108] @ (8005798 ) + 800572c: 6013 str r3, [r2, #0] + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + 800572e: 4b1a ldr r3, [pc, #104] @ (8005798 ) + 8005730: 681a ldr r2, [r3, #0] + 8005732: 4b1b ldr r3, [pc, #108] @ (80057a0 ) + 8005734: 681b ldr r3, [r3, #0] + 8005736: 429a cmp r2, r3 + 8005738: d203 bcs.n 8005742 + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + 800573a: 4b17 ldr r3, [pc, #92] @ (8005798 ) + 800573c: 681b ldr r3, [r3, #0] + 800573e: 4a18 ldr r2, [pc, #96] @ (80057a0 ) + 8005740: 6013 str r3, [r2, #0] + mtCOVERAGE_TEST_MARKER(); + } + + /* The block is being returned - it is allocated and owned + by the application and has no "next" block. */ + pxBlock->xBlockSize |= xBlockAllocatedBit; + 8005742: 6a7b ldr r3, [r7, #36] @ 0x24 + 8005744: 685a ldr r2, [r3, #4] + 8005746: 4b13 ldr r3, [pc, #76] @ (8005794 ) + 8005748: 681b ldr r3, [r3, #0] + 800574a: 431a orrs r2, r3 + 800574c: 6a7b ldr r3, [r7, #36] @ 0x24 + 800574e: 605a str r2, [r3, #4] + pxBlock->pxNextFreeBlock = NULL; + 8005750: 6a7b ldr r3, [r7, #36] @ 0x24 + 8005752: 2200 movs r2, #0 + 8005754: 601a str r2, [r3, #0] + xNumberOfSuccessfulAllocations++; + 8005756: 4b13 ldr r3, [pc, #76] @ (80057a4 ) + 8005758: 681b ldr r3, [r3, #0] + 800575a: 3301 adds r3, #1 + 800575c: 4a11 ldr r2, [pc, #68] @ (80057a4 ) + 800575e: 6013 str r3, [r2, #0] + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xWantedSize ); + } + ( void ) xTaskResumeAll(); + 8005760: f7fe fce2 bl 8004128 + mtCOVERAGE_TEST_MARKER(); + } + } + #endif + + configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); + 8005764: 69fb ldr r3, [r7, #28] + 8005766: f003 0307 and.w r3, r3, #7 + 800576a: 2b00 cmp r3, #0 + 800576c: d00b beq.n 8005786 + __asm volatile + 800576e: f04f 0350 mov.w r3, #80 @ 0x50 + 8005772: f383 8811 msr BASEPRI, r3 + 8005776: f3bf 8f6f isb sy + 800577a: f3bf 8f4f dsb sy + 800577e: 60fb str r3, [r7, #12] +} + 8005780: bf00 nop + 8005782: bf00 nop + 8005784: e7fd b.n 8005782 + return pvReturn; + 8005786: 69fb ldr r3, [r7, #28] +} + 8005788: 4618 mov r0, r3 + 800578a: 3728 adds r7, #40 @ 0x28 + 800578c: 46bd mov sp, r7 + 800578e: bd80 pop {r7, pc} + 8005790: 20004b74 .word 0x20004b74 + 8005794: 20004b88 .word 0x20004b88 + 8005798: 20004b78 .word 0x20004b78 + 800579c: 20004b6c .word 0x20004b6c + 80057a0: 20004b7c .word 0x20004b7c + 80057a4: 20004b80 .word 0x20004b80 + +080057a8 : +/*-----------------------------------------------------------*/ + +void vPortFree( void *pv ) +{ + 80057a8: b580 push {r7, lr} + 80057aa: b086 sub sp, #24 + 80057ac: af00 add r7, sp, #0 + 80057ae: 6078 str r0, [r7, #4] +uint8_t *puc = ( uint8_t * ) pv; + 80057b0: 687b ldr r3, [r7, #4] + 80057b2: 617b str r3, [r7, #20] +BlockLink_t *pxLink; + + if( pv != NULL ) + 80057b4: 687b ldr r3, [r7, #4] + 80057b6: 2b00 cmp r3, #0 + 80057b8: d04f beq.n 800585a + { + /* The memory being freed will have an BlockLink_t structure immediately + before it. */ + puc -= xHeapStructSize; + 80057ba: 2308 movs r3, #8 + 80057bc: 425b negs r3, r3 + 80057be: 697a ldr r2, [r7, #20] + 80057c0: 4413 add r3, r2 + 80057c2: 617b str r3, [r7, #20] + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + 80057c4: 697b ldr r3, [r7, #20] + 80057c6: 613b str r3, [r7, #16] + + /* Check the block is actually allocated. */ + configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + 80057c8: 693b ldr r3, [r7, #16] + 80057ca: 685a ldr r2, [r3, #4] + 80057cc: 4b25 ldr r3, [pc, #148] @ (8005864 ) + 80057ce: 681b ldr r3, [r3, #0] + 80057d0: 4013 ands r3, r2 + 80057d2: 2b00 cmp r3, #0 + 80057d4: d10b bne.n 80057ee + __asm volatile + 80057d6: f04f 0350 mov.w r3, #80 @ 0x50 + 80057da: f383 8811 msr BASEPRI, r3 + 80057de: f3bf 8f6f isb sy + 80057e2: f3bf 8f4f dsb sy + 80057e6: 60fb str r3, [r7, #12] +} + 80057e8: bf00 nop + 80057ea: bf00 nop + 80057ec: e7fd b.n 80057ea + configASSERT( pxLink->pxNextFreeBlock == NULL ); + 80057ee: 693b ldr r3, [r7, #16] + 80057f0: 681b ldr r3, [r3, #0] + 80057f2: 2b00 cmp r3, #0 + 80057f4: d00b beq.n 800580e + __asm volatile + 80057f6: f04f 0350 mov.w r3, #80 @ 0x50 + 80057fa: f383 8811 msr BASEPRI, r3 + 80057fe: f3bf 8f6f isb sy + 8005802: f3bf 8f4f dsb sy + 8005806: 60bb str r3, [r7, #8] +} + 8005808: bf00 nop + 800580a: bf00 nop + 800580c: e7fd b.n 800580a + + if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + 800580e: 693b ldr r3, [r7, #16] + 8005810: 685a ldr r2, [r3, #4] + 8005812: 4b14 ldr r3, [pc, #80] @ (8005864 ) + 8005814: 681b ldr r3, [r3, #0] + 8005816: 4013 ands r3, r2 + 8005818: 2b00 cmp r3, #0 + 800581a: d01e beq.n 800585a + { + if( pxLink->pxNextFreeBlock == NULL ) + 800581c: 693b ldr r3, [r7, #16] + 800581e: 681b ldr r3, [r3, #0] + 8005820: 2b00 cmp r3, #0 + 8005822: d11a bne.n 800585a + { + /* The block is being returned to the heap - it is no longer + allocated. */ + pxLink->xBlockSize &= ~xBlockAllocatedBit; + 8005824: 693b ldr r3, [r7, #16] + 8005826: 685a ldr r2, [r3, #4] + 8005828: 4b0e ldr r3, [pc, #56] @ (8005864 ) + 800582a: 681b ldr r3, [r3, #0] + 800582c: 43db mvns r3, r3 + 800582e: 401a ands r2, r3 + 8005830: 693b ldr r3, [r7, #16] + 8005832: 605a str r2, [r3, #4] + + vTaskSuspendAll(); + 8005834: f7fe fc6a bl 800410c + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + 8005838: 693b ldr r3, [r7, #16] + 800583a: 685a ldr r2, [r3, #4] + 800583c: 4b0a ldr r3, [pc, #40] @ (8005868 ) + 800583e: 681b ldr r3, [r3, #0] + 8005840: 4413 add r3, r2 + 8005842: 4a09 ldr r2, [pc, #36] @ (8005868 ) + 8005844: 6013 str r3, [r2, #0] + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + 8005846: 6938 ldr r0, [r7, #16] + 8005848: f000 f874 bl 8005934 + xNumberOfSuccessfulFrees++; + 800584c: 4b07 ldr r3, [pc, #28] @ (800586c ) + 800584e: 681b ldr r3, [r3, #0] + 8005850: 3301 adds r3, #1 + 8005852: 4a06 ldr r2, [pc, #24] @ (800586c ) + 8005854: 6013 str r3, [r2, #0] + } + ( void ) xTaskResumeAll(); + 8005856: f7fe fc67 bl 8004128 + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} + 800585a: bf00 nop + 800585c: 3718 adds r7, #24 + 800585e: 46bd mov sp, r7 + 8005860: bd80 pop {r7, pc} + 8005862: bf00 nop + 8005864: 20004b88 .word 0x20004b88 + 8005868: 20004b78 .word 0x20004b78 + 800586c: 20004b84 .word 0x20004b84 + +08005870 : + /* This just exists to keep the linker quiet. */ +} +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + 8005870: b480 push {r7} + 8005872: b085 sub sp, #20 + 8005874: af00 add r7, sp, #0 +BlockLink_t *pxFirstFreeBlock; +uint8_t *pucAlignedHeap; +size_t uxAddress; +size_t xTotalHeapSize = configTOTAL_HEAP_SIZE; + 8005876: f44f 5370 mov.w r3, #15360 @ 0x3c00 + 800587a: 60bb str r3, [r7, #8] + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + 800587c: 4b27 ldr r3, [pc, #156] @ (800591c ) + 800587e: 60fb str r3, [r7, #12] + + if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) + 8005880: 68fb ldr r3, [r7, #12] + 8005882: f003 0307 and.w r3, r3, #7 + 8005886: 2b00 cmp r3, #0 + 8005888: d00c beq.n 80058a4 + { + uxAddress += ( portBYTE_ALIGNMENT - 1 ); + 800588a: 68fb ldr r3, [r7, #12] + 800588c: 3307 adds r3, #7 + 800588e: 60fb str r3, [r7, #12] + uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); + 8005890: 68fb ldr r3, [r7, #12] + 8005892: f023 0307 bic.w r3, r3, #7 + 8005896: 60fb str r3, [r7, #12] + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + 8005898: 68ba ldr r2, [r7, #8] + 800589a: 68fb ldr r3, [r7, #12] + 800589c: 1ad3 subs r3, r2, r3 + 800589e: 4a1f ldr r2, [pc, #124] @ (800591c ) + 80058a0: 4413 add r3, r2 + 80058a2: 60bb str r3, [r7, #8] + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + 80058a4: 68fb ldr r3, [r7, #12] + 80058a6: 607b str r3, [r7, #4] + + /* xStart is used to hold a pointer to the first item in the list of free + blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + 80058a8: 4a1d ldr r2, [pc, #116] @ (8005920 ) + 80058aa: 687b ldr r3, [r7, #4] + 80058ac: 6013 str r3, [r2, #0] + xStart.xBlockSize = ( size_t ) 0; + 80058ae: 4b1c ldr r3, [pc, #112] @ (8005920 ) + 80058b0: 2200 movs r2, #0 + 80058b2: 605a str r2, [r3, #4] + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + 80058b4: 687b ldr r3, [r7, #4] + 80058b6: 68ba ldr r2, [r7, #8] + 80058b8: 4413 add r3, r2 + 80058ba: 60fb str r3, [r7, #12] + uxAddress -= xHeapStructSize; + 80058bc: 2208 movs r2, #8 + 80058be: 68fb ldr r3, [r7, #12] + 80058c0: 1a9b subs r3, r3, r2 + 80058c2: 60fb str r3, [r7, #12] + uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); + 80058c4: 68fb ldr r3, [r7, #12] + 80058c6: f023 0307 bic.w r3, r3, #7 + 80058ca: 60fb str r3, [r7, #12] + pxEnd = ( void * ) uxAddress; + 80058cc: 68fb ldr r3, [r7, #12] + 80058ce: 4a15 ldr r2, [pc, #84] @ (8005924 ) + 80058d0: 6013 str r3, [r2, #0] + pxEnd->xBlockSize = 0; + 80058d2: 4b14 ldr r3, [pc, #80] @ (8005924 ) + 80058d4: 681b ldr r3, [r3, #0] + 80058d6: 2200 movs r2, #0 + 80058d8: 605a str r2, [r3, #4] + pxEnd->pxNextFreeBlock = NULL; + 80058da: 4b12 ldr r3, [pc, #72] @ (8005924 ) + 80058dc: 681b ldr r3, [r3, #0] + 80058de: 2200 movs r2, #0 + 80058e0: 601a str r2, [r3, #0] + + /* To start with there is a single free block that is sized to take up the + entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + 80058e2: 687b ldr r3, [r7, #4] + 80058e4: 603b str r3, [r7, #0] + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + 80058e6: 683b ldr r3, [r7, #0] + 80058e8: 68fa ldr r2, [r7, #12] + 80058ea: 1ad2 subs r2, r2, r3 + 80058ec: 683b ldr r3, [r7, #0] + 80058ee: 605a str r2, [r3, #4] + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + 80058f0: 4b0c ldr r3, [pc, #48] @ (8005924 ) + 80058f2: 681a ldr r2, [r3, #0] + 80058f4: 683b ldr r3, [r7, #0] + 80058f6: 601a str r2, [r3, #0] + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + 80058f8: 683b ldr r3, [r7, #0] + 80058fa: 685b ldr r3, [r3, #4] + 80058fc: 4a0a ldr r2, [pc, #40] @ (8005928 ) + 80058fe: 6013 str r3, [r2, #0] + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + 8005900: 683b ldr r3, [r7, #0] + 8005902: 685b ldr r3, [r3, #4] + 8005904: 4a09 ldr r2, [pc, #36] @ (800592c ) + 8005906: 6013 str r3, [r2, #0] + + /* Work out the position of the top bit in a size_t variable. */ + xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ); + 8005908: 4b09 ldr r3, [pc, #36] @ (8005930 ) + 800590a: f04f 4200 mov.w r2, #2147483648 @ 0x80000000 + 800590e: 601a str r2, [r3, #0] +} + 8005910: bf00 nop + 8005912: 3714 adds r7, #20 + 8005914: 46bd mov sp, r7 + 8005916: f85d 7b04 ldr.w r7, [sp], #4 + 800591a: 4770 bx lr + 800591c: 20000f6c .word 0x20000f6c + 8005920: 20004b6c .word 0x20004b6c + 8005924: 20004b74 .word 0x20004b74 + 8005928: 20004b7c .word 0x20004b7c + 800592c: 20004b78 .word 0x20004b78 + 8005930: 20004b88 .word 0x20004b88 + +08005934 : +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert ) +{ + 8005934: b480 push {r7} + 8005936: b085 sub sp, #20 + 8005938: af00 add r7, sp, #0 + 800593a: 6078 str r0, [r7, #4] +BlockLink_t *pxIterator; +uint8_t *puc; + + /* Iterate through the list until a block is found that has a higher address + than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + 800593c: 4b28 ldr r3, [pc, #160] @ (80059e0 ) + 800593e: 60fb str r3, [r7, #12] + 8005940: e002 b.n 8005948 + 8005942: 68fb ldr r3, [r7, #12] + 8005944: 681b ldr r3, [r3, #0] + 8005946: 60fb str r3, [r7, #12] + 8005948: 68fb ldr r3, [r7, #12] + 800594a: 681b ldr r3, [r3, #0] + 800594c: 687a ldr r2, [r7, #4] + 800594e: 429a cmp r2, r3 + 8005950: d8f7 bhi.n 8005942 + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + 8005952: 68fb ldr r3, [r7, #12] + 8005954: 60bb str r3, [r7, #8] + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + 8005956: 68fb ldr r3, [r7, #12] + 8005958: 685b ldr r3, [r3, #4] + 800595a: 68ba ldr r2, [r7, #8] + 800595c: 4413 add r3, r2 + 800595e: 687a ldr r2, [r7, #4] + 8005960: 429a cmp r2, r3 + 8005962: d108 bne.n 8005976 + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + 8005964: 68fb ldr r3, [r7, #12] + 8005966: 685a ldr r2, [r3, #4] + 8005968: 687b ldr r3, [r7, #4] + 800596a: 685b ldr r3, [r3, #4] + 800596c: 441a add r2, r3 + 800596e: 68fb ldr r3, [r7, #12] + 8005970: 605a str r2, [r3, #4] + pxBlockToInsert = pxIterator; + 8005972: 68fb ldr r3, [r7, #12] + 8005974: 607b str r3, [r7, #4] + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + 8005976: 687b ldr r3, [r7, #4] + 8005978: 60bb str r3, [r7, #8] + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + 800597a: 687b ldr r3, [r7, #4] + 800597c: 685b ldr r3, [r3, #4] + 800597e: 68ba ldr r2, [r7, #8] + 8005980: 441a add r2, r3 + 8005982: 68fb ldr r3, [r7, #12] + 8005984: 681b ldr r3, [r3, #0] + 8005986: 429a cmp r2, r3 + 8005988: d118 bne.n 80059bc + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + 800598a: 68fb ldr r3, [r7, #12] + 800598c: 681a ldr r2, [r3, #0] + 800598e: 4b15 ldr r3, [pc, #84] @ (80059e4 ) + 8005990: 681b ldr r3, [r3, #0] + 8005992: 429a cmp r2, r3 + 8005994: d00d beq.n 80059b2 + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + 8005996: 687b ldr r3, [r7, #4] + 8005998: 685a ldr r2, [r3, #4] + 800599a: 68fb ldr r3, [r7, #12] + 800599c: 681b ldr r3, [r3, #0] + 800599e: 685b ldr r3, [r3, #4] + 80059a0: 441a add r2, r3 + 80059a2: 687b ldr r3, [r7, #4] + 80059a4: 605a str r2, [r3, #4] + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + 80059a6: 68fb ldr r3, [r7, #12] + 80059a8: 681b ldr r3, [r3, #0] + 80059aa: 681a ldr r2, [r3, #0] + 80059ac: 687b ldr r3, [r7, #4] + 80059ae: 601a str r2, [r3, #0] + 80059b0: e008 b.n 80059c4 + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + 80059b2: 4b0c ldr r3, [pc, #48] @ (80059e4 ) + 80059b4: 681a ldr r2, [r3, #0] + 80059b6: 687b ldr r3, [r7, #4] + 80059b8: 601a str r2, [r3, #0] + 80059ba: e003 b.n 80059c4 + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + 80059bc: 68fb ldr r3, [r7, #12] + 80059be: 681a ldr r2, [r3, #0] + 80059c0: 687b ldr r3, [r7, #4] + 80059c2: 601a str r2, [r3, #0] + + /* If the block being inserted plugged a gab, so was merged with the block + before and the block after, then it's pxNextFreeBlock pointer will have + already been set, and should not be set here as that would make it point + to itself. */ + if( pxIterator != pxBlockToInsert ) + 80059c4: 68fa ldr r2, [r7, #12] + 80059c6: 687b ldr r3, [r7, #4] + 80059c8: 429a cmp r2, r3 + 80059ca: d002 beq.n 80059d2 + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + 80059cc: 68fb ldr r3, [r7, #12] + 80059ce: 687a ldr r2, [r7, #4] + 80059d0: 601a str r2, [r3, #0] + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} + 80059d2: bf00 nop + 80059d4: 3714 adds r7, #20 + 80059d6: 46bd mov sp, r7 + 80059d8: f85d 7b04 ldr.w r7, [sp], #4 + 80059dc: 4770 bx lr + 80059de: bf00 nop + 80059e0: 20004b6c .word 0x20004b6c + 80059e4: 20004b74 .word 0x20004b74 + +080059e8 <__malloc_lock>: + 80059e8: 4801 ldr r0, [pc, #4] @ (80059f0 <__malloc_lock+0x8>) + 80059ea: f7fb b940 b.w 8000c6e <__retarget_lock_acquire_recursive> + 80059ee: bf00 nop + 80059f0: 20000194 .word 0x20000194 + +080059f4 <__malloc_unlock>: + 80059f4: 4801 ldr r0, [pc, #4] @ (80059fc <__malloc_unlock+0x8>) + 80059f6: f7fb b94f b.w 8000c98 <__retarget_lock_release_recursive> + 80059fa: bf00 nop + 80059fc: 20000194 .word 0x20000194 + +08005a00 : + 8005a00: 4402 add r2, r0 + 8005a02: 4603 mov r3, r0 + 8005a04: 4293 cmp r3, r2 + 8005a06: d100 bne.n 8005a0a + 8005a08: 4770 bx lr + 8005a0a: f803 1b01 strb.w r1, [r3], #1 + 8005a0e: e7f9 b.n 8005a04 + +08005a10 <__libc_init_array>: + 8005a10: b570 push {r4, r5, r6, lr} + 8005a12: 4b0d ldr r3, [pc, #52] @ (8005a48 <__libc_init_array+0x38>) + 8005a14: 4d0d ldr r5, [pc, #52] @ (8005a4c <__libc_init_array+0x3c>) + 8005a16: 1b5b subs r3, r3, r5 + 8005a18: 109c asrs r4, r3, #2 + 8005a1a: 2600 movs r6, #0 + 8005a1c: 42a6 cmp r6, r4 + 8005a1e: d109 bne.n 8005a34 <__libc_init_array+0x24> + 8005a20: f000 f8d0 bl 8005bc4 <_init> + 8005a24: 4d0a ldr r5, [pc, #40] @ (8005a50 <__libc_init_array+0x40>) + 8005a26: 4b0b ldr r3, [pc, #44] @ (8005a54 <__libc_init_array+0x44>) + 8005a28: 1b5b subs r3, r3, r5 + 8005a2a: 109c asrs r4, r3, #2 + 8005a2c: 2600 movs r6, #0 + 8005a2e: 42a6 cmp r6, r4 + 8005a30: d105 bne.n 8005a3e <__libc_init_array+0x2e> + 8005a32: bd70 pop {r4, r5, r6, pc} + 8005a34: f855 3b04 ldr.w r3, [r5], #4 + 8005a38: 4798 blx r3 + 8005a3a: 3601 adds r6, #1 + 8005a3c: e7ee b.n 8005a1c <__libc_init_array+0xc> + 8005a3e: f855 3b04 ldr.w r3, [r5], #4 + 8005a42: 4798 blx r3 + 8005a44: 3601 adds r6, #1 + 8005a46: e7f2 b.n 8005a2e <__libc_init_array+0x1e> + 8005a48: 08005d64 .word 0x08005d64 + 8005a4c: 08005d64 .word 0x08005d64 + 8005a50: 08005d64 .word 0x08005d64 + 8005a54: 08005d68 .word 0x08005d68 + +08005a58 <_reclaim_reent>: + 8005a58: 4b2d ldr r3, [pc, #180] @ (8005b10 <_reclaim_reent+0xb8>) + 8005a5a: 681b ldr r3, [r3, #0] + 8005a5c: 4283 cmp r3, r0 + 8005a5e: b570 push {r4, r5, r6, lr} + 8005a60: 4604 mov r4, r0 + 8005a62: d053 beq.n 8005b0c <_reclaim_reent+0xb4> + 8005a64: 69c3 ldr r3, [r0, #28] + 8005a66: b31b cbz r3, 8005ab0 <_reclaim_reent+0x58> + 8005a68: 68db ldr r3, [r3, #12] + 8005a6a: b163 cbz r3, 8005a86 <_reclaim_reent+0x2e> + 8005a6c: 2500 movs r5, #0 + 8005a6e: 69e3 ldr r3, [r4, #28] + 8005a70: 68db ldr r3, [r3, #12] + 8005a72: 5959 ldr r1, [r3, r5] + 8005a74: b9b1 cbnz r1, 8005aa4 <_reclaim_reent+0x4c> + 8005a76: 3504 adds r5, #4 + 8005a78: 2d80 cmp r5, #128 @ 0x80 + 8005a7a: d1f8 bne.n 8005a6e <_reclaim_reent+0x16> + 8005a7c: 69e3 ldr r3, [r4, #28] + 8005a7e: 4620 mov r0, r4 + 8005a80: 68d9 ldr r1, [r3, #12] + 8005a82: f000 f855 bl 8005b30 <_free_r> + 8005a86: 69e3 ldr r3, [r4, #28] + 8005a88: 6819 ldr r1, [r3, #0] + 8005a8a: b111 cbz r1, 8005a92 <_reclaim_reent+0x3a> + 8005a8c: 4620 mov r0, r4 + 8005a8e: f000 f84f bl 8005b30 <_free_r> + 8005a92: 69e3 ldr r3, [r4, #28] + 8005a94: 689d ldr r5, [r3, #8] + 8005a96: b15d cbz r5, 8005ab0 <_reclaim_reent+0x58> + 8005a98: 4629 mov r1, r5 + 8005a9a: 4620 mov r0, r4 + 8005a9c: 682d ldr r5, [r5, #0] + 8005a9e: f000 f847 bl 8005b30 <_free_r> + 8005aa2: e7f8 b.n 8005a96 <_reclaim_reent+0x3e> + 8005aa4: 680e ldr r6, [r1, #0] + 8005aa6: 4620 mov r0, r4 + 8005aa8: f000 f842 bl 8005b30 <_free_r> + 8005aac: 4631 mov r1, r6 + 8005aae: e7e1 b.n 8005a74 <_reclaim_reent+0x1c> + 8005ab0: 6961 ldr r1, [r4, #20] + 8005ab2: b111 cbz r1, 8005aba <_reclaim_reent+0x62> + 8005ab4: 4620 mov r0, r4 + 8005ab6: f000 f83b bl 8005b30 <_free_r> + 8005aba: 69e1 ldr r1, [r4, #28] + 8005abc: b111 cbz r1, 8005ac4 <_reclaim_reent+0x6c> + 8005abe: 4620 mov r0, r4 + 8005ac0: f000 f836 bl 8005b30 <_free_r> + 8005ac4: 6b21 ldr r1, [r4, #48] @ 0x30 + 8005ac6: b111 cbz r1, 8005ace <_reclaim_reent+0x76> + 8005ac8: 4620 mov r0, r4 + 8005aca: f000 f831 bl 8005b30 <_free_r> + 8005ace: 6b61 ldr r1, [r4, #52] @ 0x34 + 8005ad0: b111 cbz r1, 8005ad8 <_reclaim_reent+0x80> + 8005ad2: 4620 mov r0, r4 + 8005ad4: f000 f82c bl 8005b30 <_free_r> + 8005ad8: 6ba1 ldr r1, [r4, #56] @ 0x38 + 8005ada: b111 cbz r1, 8005ae2 <_reclaim_reent+0x8a> + 8005adc: 4620 mov r0, r4 + 8005ade: f000 f827 bl 8005b30 <_free_r> + 8005ae2: 6ca1 ldr r1, [r4, #72] @ 0x48 + 8005ae4: b111 cbz r1, 8005aec <_reclaim_reent+0x94> + 8005ae6: 4620 mov r0, r4 + 8005ae8: f000 f822 bl 8005b30 <_free_r> + 8005aec: 6c61 ldr r1, [r4, #68] @ 0x44 + 8005aee: b111 cbz r1, 8005af6 <_reclaim_reent+0x9e> + 8005af0: 4620 mov r0, r4 + 8005af2: f000 f81d bl 8005b30 <_free_r> + 8005af6: 6ae1 ldr r1, [r4, #44] @ 0x2c + 8005af8: b111 cbz r1, 8005b00 <_reclaim_reent+0xa8> + 8005afa: 4620 mov r0, r4 + 8005afc: f000 f818 bl 8005b30 <_free_r> + 8005b00: 6a23 ldr r3, [r4, #32] + 8005b02: b11b cbz r3, 8005b0c <_reclaim_reent+0xb4> + 8005b04: 4620 mov r0, r4 + 8005b06: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + 8005b0a: 4718 bx r3 + 8005b0c: bd70 pop {r4, r5, r6, pc} + 8005b0e: bf00 nop + 8005b10: 20000010 .word 0x20000010 + +08005b14 : + 8005b14: 440a add r2, r1 + 8005b16: 4291 cmp r1, r2 + 8005b18: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff + 8005b1c: d100 bne.n 8005b20 + 8005b1e: 4770 bx lr + 8005b20: b510 push {r4, lr} + 8005b22: f811 4b01 ldrb.w r4, [r1], #1 + 8005b26: f803 4f01 strb.w r4, [r3, #1]! + 8005b2a: 4291 cmp r1, r2 + 8005b2c: d1f9 bne.n 8005b22 + 8005b2e: bd10 pop {r4, pc} + +08005b30 <_free_r>: + 8005b30: b538 push {r3, r4, r5, lr} + 8005b32: 4605 mov r5, r0 + 8005b34: 2900 cmp r1, #0 + 8005b36: d041 beq.n 8005bbc <_free_r+0x8c> + 8005b38: f851 3c04 ldr.w r3, [r1, #-4] + 8005b3c: 1f0c subs r4, r1, #4 + 8005b3e: 2b00 cmp r3, #0 + 8005b40: bfb8 it lt + 8005b42: 18e4 addlt r4, r4, r3 + 8005b44: f7ff ff50 bl 80059e8 <__malloc_lock> + 8005b48: 4a1d ldr r2, [pc, #116] @ (8005bc0 <_free_r+0x90>) + 8005b4a: 6813 ldr r3, [r2, #0] + 8005b4c: b933 cbnz r3, 8005b5c <_free_r+0x2c> + 8005b4e: 6063 str r3, [r4, #4] + 8005b50: 6014 str r4, [r2, #0] + 8005b52: 4628 mov r0, r5 + 8005b54: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 8005b58: f7ff bf4c b.w 80059f4 <__malloc_unlock> + 8005b5c: 42a3 cmp r3, r4 + 8005b5e: d908 bls.n 8005b72 <_free_r+0x42> + 8005b60: 6820 ldr r0, [r4, #0] + 8005b62: 1821 adds r1, r4, r0 + 8005b64: 428b cmp r3, r1 + 8005b66: bf01 itttt eq + 8005b68: 6819 ldreq r1, [r3, #0] + 8005b6a: 685b ldreq r3, [r3, #4] + 8005b6c: 1809 addeq r1, r1, r0 + 8005b6e: 6021 streq r1, [r4, #0] + 8005b70: e7ed b.n 8005b4e <_free_r+0x1e> + 8005b72: 461a mov r2, r3 + 8005b74: 685b ldr r3, [r3, #4] + 8005b76: b10b cbz r3, 8005b7c <_free_r+0x4c> + 8005b78: 42a3 cmp r3, r4 + 8005b7a: d9fa bls.n 8005b72 <_free_r+0x42> + 8005b7c: 6811 ldr r1, [r2, #0] + 8005b7e: 1850 adds r0, r2, r1 + 8005b80: 42a0 cmp r0, r4 + 8005b82: d10b bne.n 8005b9c <_free_r+0x6c> + 8005b84: 6820 ldr r0, [r4, #0] + 8005b86: 4401 add r1, r0 + 8005b88: 1850 adds r0, r2, r1 + 8005b8a: 4283 cmp r3, r0 + 8005b8c: 6011 str r1, [r2, #0] + 8005b8e: d1e0 bne.n 8005b52 <_free_r+0x22> + 8005b90: 6818 ldr r0, [r3, #0] + 8005b92: 685b ldr r3, [r3, #4] + 8005b94: 6053 str r3, [r2, #4] + 8005b96: 4408 add r0, r1 + 8005b98: 6010 str r0, [r2, #0] + 8005b9a: e7da b.n 8005b52 <_free_r+0x22> + 8005b9c: d902 bls.n 8005ba4 <_free_r+0x74> + 8005b9e: 230c movs r3, #12 + 8005ba0: 602b str r3, [r5, #0] + 8005ba2: e7d6 b.n 8005b52 <_free_r+0x22> + 8005ba4: 6820 ldr r0, [r4, #0] + 8005ba6: 1821 adds r1, r4, r0 + 8005ba8: 428b cmp r3, r1 + 8005baa: bf04 itt eq + 8005bac: 6819 ldreq r1, [r3, #0] + 8005bae: 685b ldreq r3, [r3, #4] + 8005bb0: 6063 str r3, [r4, #4] + 8005bb2: bf04 itt eq + 8005bb4: 1809 addeq r1, r1, r0 + 8005bb6: 6021 streq r1, [r4, #0] + 8005bb8: 6054 str r4, [r2, #4] + 8005bba: e7ca b.n 8005b52 <_free_r+0x22> + 8005bbc: bd38 pop {r3, r4, r5, pc} + 8005bbe: bf00 nop + 8005bc0: 20004b8c .word 0x20004b8c + +08005bc4 <_init>: + 8005bc4: b5f8 push {r3, r4, r5, r6, r7, lr} + 8005bc6: bf00 nop + 8005bc8: bcf8 pop {r3, r4, r5, r6, r7} + 8005bca: bc08 pop {r3} + 8005bcc: 469e mov lr, r3 + 8005bce: 4770 bx lr + +08005bd0 <_fini>: + 8005bd0: b5f8 push {r3, r4, r5, r6, r7, lr} + 8005bd2: bf00 nop + 8005bd4: bcf8 pop {r3, r4, r5, r6, r7} + 8005bd6: bc08 pop {r3} + 8005bd8: 469e mov lr, r3 + 8005bda: 4770 bx lr diff --git a/Debug/can_logger.map b/Debug/can_logger.map new file mode 100644 index 0000000..32c12c6 --- /dev/null +++ b/Debug/can_logger.map @@ -0,0 +1,5706 @@ +Archive member included to satisfy reference by file (symbol) + +/Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-exit.o) + /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o (exit) +/Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-malloc.o) + ./Core/ThreadSafe/newlib_lock_glue.o (malloc) +/Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-mallocr.o) + /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-malloc.o) (_malloc_r) +/Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-mlock.o) + /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-mallocr.o) (__malloc_lock) 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/Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/crtn.o + .bss 0x00000000 0x0 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/crtn.o + +Memory Configuration + +Name Origin Length Attributes +CCMRAM 0x10000000 0x00010000 xrw +RAM 0x20000000 0x00020000 xrw +FLASH 0x08000000 0x00100000 xr +*default* 0x00000000 0xffffffff + +Linker script and memory map + +LOAD /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/crti.o +LOAD /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/crtbegin.o +LOAD /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o +LOAD ./Core/Src/freertos.o +LOAD ./Core/Src/main.o +LOAD ./Core/Src/stm32f4xx_hal_msp.o +LOAD ./Core/Src/stm32f4xx_hal_timebase_tim.o +LOAD ./Core/Src/stm32f4xx_it.o +LOAD ./Core/Src/syscalls.o +LOAD ./Core/Src/sysmem.o +LOAD ./Core/Src/system_stm32f4xx.o +LOAD ./Core/Startup/startup_stm32f405rgtx.o +LOAD ./Core/ThreadSafe/newlib_lock_glue.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/list.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/queue.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/timers.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o +START GROUP +LOAD /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a +LOAD /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a +END GROUP +START GROUP +LOAD /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/libgcc.a +LOAD /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a +END GROUP +START GROUP +LOAD /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/libgcc.a +LOAD /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a +LOAD /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libnosys.a +END GROUP +START GROUP +LOAD /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/libgcc.a +LOAD /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a +LOAD /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libnosys.a +END GROUP +LOAD /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/crtend.o +LOAD /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/crtn.o + 0x20020000 _estack = (ORIGIN (RAM) + LENGTH (RAM)) + 0x00000200 _Min_Heap_Size = 0x200 + 0x00000400 _Min_Stack_Size = 0x400 + +.isr_vector 0x08000000 0x188 + 0x08000000 . = ALIGN (0x4) + *(.isr_vector) + .isr_vector 0x08000000 0x188 ./Core/Startup/startup_stm32f405rgtx.o + 0x08000000 g_pfnVectors + 0x08000188 . = ALIGN (0x4) + +.text 0x08000190 0x5a4c + 0x08000190 . = ALIGN (0x4) + *(.text) + .text 0x08000190 0x40 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/crtbegin.o + .text 0x080001d0 0x30 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/libgcc.a(_aeabi_uldivmod.o) + 0x080001d0 __aeabi_uldivmod + .text 0x08000200 0x2f8 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/libgcc.a(_udivmoddi4.o) + 0x08000200 __udivmoddi4 + .text 0x080004f8 0x4 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/libgcc.a(_dvmd_tls.o) + 0x080004f8 __aeabi_ldiv0 + 0x080004f8 __aeabi_idiv0 + *(.text*) + .text.main 0x080004fc 0x40 ./Core/Src/main.o + 0x080004fc main + .text.SystemClock_Config + 0x0800053c 0xbc ./Core/Src/main.o + 0x0800053c SystemClock_Config + .text.MX_CAN1_Init + 0x080005f8 0x68 ./Core/Src/main.o + .text.MX_CAN2_Init + 0x08000660 0x68 ./Core/Src/main.o + .text.MX_GPIO_Init + 0x080006c8 0x140 ./Core/Src/main.o + .text.StartDefaultTask + 0x08000808 0x10 ./Core/Src/main.o + 0x08000808 StartDefaultTask + .text.HAL_TIM_PeriodElapsedCallback + 0x08000818 0x24 ./Core/Src/main.o + 0x08000818 HAL_TIM_PeriodElapsedCallback + .text.Error_Handler + 0x0800083c 0xc ./Core/Src/main.o + 0x0800083c Error_Handler + .text.assert_failed + 0x08000848 0x16 ./Core/Src/main.o + 0x08000848 assert_failed + *fill* 0x0800085e 0x2 + .text.HAL_MspInit + 0x08000860 0x58 ./Core/Src/stm32f4xx_hal_msp.o + 0x08000860 HAL_MspInit + .text.HAL_CAN_MspInit + 0x080008b8 0x140 ./Core/Src/stm32f4xx_hal_msp.o + 0x080008b8 HAL_CAN_MspInit + .text.HAL_InitTick + 0x080009f8 0xf8 ./Core/Src/stm32f4xx_hal_timebase_tim.o + 0x080009f8 HAL_InitTick + .text.NMI_Handler + 0x08000af0 0x8 ./Core/Src/stm32f4xx_it.o + 0x08000af0 NMI_Handler + .text.HardFault_Handler + 0x08000af8 0x8 ./Core/Src/stm32f4xx_it.o + 0x08000af8 HardFault_Handler + .text.MemManage_Handler + 0x08000b00 0x8 ./Core/Src/stm32f4xx_it.o + 0x08000b00 MemManage_Handler + .text.BusFault_Handler + 0x08000b08 0x8 ./Core/Src/stm32f4xx_it.o + 0x08000b08 BusFault_Handler + .text.UsageFault_Handler + 0x08000b10 0x8 ./Core/Src/stm32f4xx_it.o + 0x08000b10 UsageFault_Handler + .text.DebugMon_Handler + 0x08000b18 0xe ./Core/Src/stm32f4xx_it.o + 0x08000b18 DebugMon_Handler + *fill* 0x08000b26 0x2 + .text.TIM6_DAC_IRQHandler + 0x08000b28 0x14 ./Core/Src/stm32f4xx_it.o + 0x08000b28 TIM6_DAC_IRQHandler + .text.SystemInit + 0x08000b3c 0x24 ./Core/Src/system_stm32f4xx.o + 0x08000b3c SystemInit + .text.Reset_Handler + 0x08000b60 0x50 ./Core/Startup/startup_stm32f405rgtx.o + 0x08000b60 Reset_Handler + .text.Default_Handler + 0x08000bb0 0x2 ./Core/Startup/startup_stm32f405rgtx.o + 0x08000bb0 DMA1_Stream3_IRQHandler + 0x08000bb0 HASH_RNG_IRQHandler + 0x08000bb0 EXTI2_IRQHandler + 0x08000bb0 TIM8_CC_IRQHandler + 0x08000bb0 TIM1_CC_IRQHandler + 0x08000bb0 DMA2_Stream5_IRQHandler + 0x08000bb0 DMA1_Stream5_IRQHandler + 0x08000bb0 PVD_IRQHandler + 0x08000bb0 SDIO_IRQHandler + 0x08000bb0 TAMP_STAMP_IRQHandler + 0x08000bb0 CAN2_RX1_IRQHandler + 0x08000bb0 EXTI3_IRQHandler + 0x08000bb0 TIM8_TRG_COM_TIM14_IRQHandler + 0x08000bb0 TIM1_UP_TIM10_IRQHandler + 0x08000bb0 TIM8_UP_TIM13_IRQHandler + 0x08000bb0 I2C3_ER_IRQHandler + 0x08000bb0 EXTI0_IRQHandler + 0x08000bb0 I2C2_EV_IRQHandler + 0x08000bb0 DMA1_Stream2_IRQHandler + 0x08000bb0 CAN1_RX0_IRQHandler + 0x08000bb0 FPU_IRQHandler + 0x08000bb0 OTG_HS_WKUP_IRQHandler + 0x08000bb0 CAN2_SCE_IRQHandler + 0x08000bb0 DMA2_Stream2_IRQHandler + 0x08000bb0 SPI1_IRQHandler + 0x08000bb0 TIM1_BRK_TIM9_IRQHandler + 0x08000bb0 CAN2_RX0_IRQHandler + 0x08000bb0 DMA2_Stream3_IRQHandler + 0x08000bb0 USART6_IRQHandler + 0x08000bb0 USART3_IRQHandler + 0x08000bb0 CAN1_RX1_IRQHandler + 0x08000bb0 UART5_IRQHandler + 0x08000bb0 DMA2_Stream0_IRQHandler + 0x08000bb0 TIM4_IRQHandler + 0x08000bb0 I2C1_EV_IRQHandler + 0x08000bb0 DMA1_Stream6_IRQHandler + 0x08000bb0 DMA1_Stream1_IRQHandler + 0x08000bb0 UART4_IRQHandler + 0x08000bb0 TIM3_IRQHandler + 0x08000bb0 RCC_IRQHandler + 0x08000bb0 TIM8_BRK_TIM12_IRQHandler + 0x08000bb0 Default_Handler + 0x08000bb0 EXTI15_10_IRQHandler + 0x08000bb0 ADC_IRQHandler + 0x08000bb0 DMA1_Stream7_IRQHandler + 0x08000bb0 TIM7_IRQHandler + 0x08000bb0 CAN2_TX_IRQHandler + 0x08000bb0 TIM5_IRQHandler + 0x08000bb0 DMA2_Stream7_IRQHandler + 0x08000bb0 I2C3_EV_IRQHandler + 0x08000bb0 EXTI9_5_IRQHandler + 0x08000bb0 RTC_WKUP_IRQHandler + 0x08000bb0 SPI2_IRQHandler + 0x08000bb0 OTG_HS_EP1_IN_IRQHandler + 0x08000bb0 DMA1_Stream0_IRQHandler + 0x08000bb0 CAN1_TX_IRQHandler + 0x08000bb0 EXTI4_IRQHandler + 0x08000bb0 FSMC_IRQHandler + 0x08000bb0 OTG_HS_EP1_OUT_IRQHandler + 0x08000bb0 WWDG_IRQHandler + 0x08000bb0 TIM2_IRQHandler + 0x08000bb0 OTG_FS_WKUP_IRQHandler + 0x08000bb0 TIM1_TRG_COM_TIM11_IRQHandler + 0x08000bb0 OTG_HS_IRQHandler + 0x08000bb0 EXTI1_IRQHandler + 0x08000bb0 USART2_IRQHandler + 0x08000bb0 I2C2_ER_IRQHandler + 0x08000bb0 DMA2_Stream1_IRQHandler + 0x08000bb0 CAN1_SCE_IRQHandler + 0x08000bb0 FLASH_IRQHandler + 0x08000bb0 DMA2_Stream4_IRQHandler + 0x08000bb0 USART1_IRQHandler + 0x08000bb0 OTG_FS_IRQHandler + 0x08000bb0 SPI3_IRQHandler + 0x08000bb0 DMA1_Stream4_IRQHandler + 0x08000bb0 I2C1_ER_IRQHandler + 0x08000bb0 DMA2_Stream6_IRQHandler + 0x08000bb0 RTC_Alarm_IRQHandler + .text.stm32_lock_acquire + 0x08000bb2 0x64 ./Core/ThreadSafe/newlib_lock_glue.o + .text.stm32_lock_release + 0x08000c16 0x58 ./Core/ThreadSafe/newlib_lock_glue.o + .text.__retarget_lock_acquire_recursive + 0x08000c6e 0x2a ./Core/ThreadSafe/newlib_lock_glue.o + 0x08000c6e __retarget_lock_acquire_recursive + .text.__retarget_lock_release_recursive + 0x08000c98 0x2a ./Core/ThreadSafe/newlib_lock_glue.o + 0x08000c98 __retarget_lock_release_recursive + *fill* 0x08000cc2 0x2 + .text.HAL_Init + 0x08000cc4 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x08000cc4 HAL_Init + .text.HAL_IncTick + 0x08000d08 0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x08000d08 HAL_IncTick + .text.HAL_GetTick + 0x08000d30 0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x08000d30 HAL_GetTick + .text.HAL_CAN_Init + 0x08000d48 0x4d4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o + 0x08000d48 HAL_CAN_Init + .text.HAL_CAN_TxMailbox0CompleteCallback + 0x0800121c 0x14 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*(.rodata*) + *fill* 0x08005d1d 0x3 + .rodata.defaultTask_attributes + 0x08005d20 0x24 ./Core/Src/main.o + 0x08005d20 defaultTask_attributes + .rodata.AHBPrescTable + 0x08005d44 0x10 ./Core/Src/system_stm32f4xx.o + 0x08005d44 AHBPrescTable + .rodata.APBPrescTable + 0x08005d54 0x8 ./Core/Src/system_stm32f4xx.o + 0x08005d54 APBPrescTable + 0x08005d5c . = ALIGN (0x4) + +.ARM.extab 0x08005d5c 0x0 + 0x08005d5c . = ALIGN (0x4) + *(.ARM.extab* .gnu.linkonce.armextab.*) + 0x08005d5c . = ALIGN (0x4) + +.ARM 0x08005d5c 0x8 + 0x08005d5c . = ALIGN (0x4) + 0x08005d5c __exidx_start = . + *(.ARM.exidx*) + .ARM.exidx 0x08005d5c 0x8 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/libgcc.a(_udivmoddi4.o) + 0x08005d64 __exidx_end = . + 0x08005d64 . = ALIGN (0x4) + +.preinit_array 0x08005d64 0x0 + 0x08005d64 . = ALIGN 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/Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-findfp.o) + 0x20004b90 __sf + *(COMMON) + 0x20004cc8 . = ALIGN (0x4) + 0x20004cc8 _ebss = . + 0x20004cc8 __bss_end__ = _ebss + +._user_heap_stack + 0x20004cc8 0x600 + 0x20004cc8 . = ALIGN (0x8) + [!provide] PROVIDE (end = .) + 0x20004cc8 PROVIDE (_end = .) + 0x20004ec8 . = (. + _Min_Heap_Size) + *fill* 0x20004cc8 0x200 + 0x200052c8 . = (. + _Min_Stack_Size) + *fill* 0x20004ec8 0x400 + 0x200052c8 . = ALIGN (0x8) + +/DISCARD/ + libc.a(*) + libm.a(*) + libgcc.a(*) + +.ARM.attributes + 0x00000000 0x30 + *(.ARM.attributes) + .ARM.attributes + 0x00000000 0x22 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/Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/libgcc.a(_aeabi_uldivmod.o) + .debug_frame 0x00005168 0x34 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/libgcc.a(_udivmoddi4.o) + +.debug_line_str + 0x00000000 0xba + .debug_line_str + 0x00000000 0xba ./Core/Startup/startup_stm32f405rgtx.o diff --git a/Debug/makefile b/Debug/makefile new file mode 100644 index 0000000..23986b9 --- /dev/null +++ b/Debug/makefile @@ -0,0 +1,99 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (14.3.rel1) +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk +-include Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/subdir.mk +-include Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/subdir.mk +-include Middlewares/Third_Party/FreeRTOS/Source/subdir.mk +-include Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk +-include Core/ThreadSafe/subdir.mk +-include Core/Startup/subdir.mk +-include Core/Src/subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +-include ../makefile.defs + +OPTIONAL_TOOL_DEPS := \ +$(wildcard ../makefile.defs) \ +$(wildcard ../makefile.init) \ +$(wildcard ../makefile.targets) \ + + +BUILD_ARTIFACT_NAME := can_logger +BUILD_ARTIFACT_EXTENSION := elf +BUILD_ARTIFACT_PREFIX := +BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),) + +# Add inputs and outputs from these tool invocations to the build variables +EXECUTABLES += \ +can_logger.elf \ + +MAP_FILES += \ +can_logger.map \ + +SIZE_OUTPUT += \ +default.size.stdout \ + +OBJDUMP_LIST += \ +can_logger.list \ + + +# All Target +all: main-build + +# Main-build Target +main-build: can_logger.elf secondary-outputs + +# Tool invocations +can_logger.elf can_logger.map: $(OBJS) $(USER_OBJS) /Users/erickahmed/Library/Mobile\ Documents/com~apple~CloudDocs/Engineering/Ingegneria\ del\ Veicolo\ LT/3T\ -\ Prova\ Finale/Tesi/code/can_logger/STM32F405RGTX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-gcc -o "can_logger.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m4 -T"/Users/erickahmed/Library/Mobile Documents/com~apple~CloudDocs/Engineering/Ingegneria del Veicolo LT/3T - Prova Finale/Tesi/code/can_logger/STM32F405RGTX_FLASH.ld" --specs=nosys.specs -Wl,-Map="can_logger.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -Wl,--end-group + @echo 'Finished building target: $@' + @echo ' ' + +default.size.stdout: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-size $(EXECUTABLES) + @echo 'Finished building: $@' + @echo ' ' + +can_logger.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-objdump -h -S $(EXECUTABLES) > "can_logger.list" + @echo 'Finished building: $@' + @echo ' ' + +# Other Targets +clean: + -$(RM) can_logger.elf can_logger.list can_logger.map default.size.stdout + -@echo ' ' + +secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) + +fail-specified-linker-script-missing: + @echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.' + @exit 2 + +warn-no-linker-script-specified: + @echo 'Warning: No linker script specified. Check the linker settings in the build configuration.' + +.PHONY: all clean dependents main-build fail-specified-linker-script-missing warn-no-linker-script-specified + +-include ../makefile.targets diff --git a/Debug/objects.list b/Debug/objects.list new file mode 100644 index 0000000..9f0b5c8 --- /dev/null +++ b/Debug/objects.list @@ -0,0 +1,36 @@ +"./Core/Src/freertos.o" +"./Core/Src/main.o" +"./Core/Src/stm32f4xx_hal_msp.o" +"./Core/Src/stm32f4xx_hal_timebase_tim.o" +"./Core/Src/stm32f4xx_it.o" +"./Core/Src/syscalls.o" +"./Core/Src/sysmem.o" +"./Core/Src/system_stm32f4xx.o" +"./Core/Startup/startup_stm32f405rgtx.o" +"./Core/ThreadSafe/newlib_lock_glue.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o" +"./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o" +"./Middlewares/Third_Party/FreeRTOS/Source/croutine.o" +"./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o" +"./Middlewares/Third_Party/FreeRTOS/Source/list.o" +"./Middlewares/Third_Party/FreeRTOS/Source/queue.o" +"./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o" +"./Middlewares/Third_Party/FreeRTOS/Source/tasks.o" +"./Middlewares/Third_Party/FreeRTOS/Source/timers.o" +"./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o" +"./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o" diff --git a/Debug/objects.mk b/Debug/objects.mk new file mode 100644 index 0000000..281954c --- /dev/null +++ b/Debug/objects.mk @@ -0,0 +1,9 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (14.3.rel1) +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/Debug/sources.mk b/Debug/sources.mk new file mode 100644 index 0000000..5cad60c --- /dev/null +++ b/Debug/sources.mk @@ -0,0 +1,33 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (14.3.rel1) +################################################################################ + +ELF_SRCS := +OBJ_SRCS := +S_SRCS := +C_SRCS := +S_UPPER_SRCS := +O_SRCS := +CYCLO_FILES := +SIZE_OUTPUT := +OBJDUMP_LIST := +SU_FILES := +EXECUTABLES := +OBJS := +MAP_FILES := +S_DEPS := +S_UPPER_DEPS := +C_DEPS := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +Core/Src \ +Core/Startup \ +Core/ThreadSafe \ +Drivers/STM32F4xx_HAL_Driver/Src \ +Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 \ +Middlewares/Third_Party/FreeRTOS/Source \ +Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F \ +Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang \ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_mmc.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_mmc.h new file mode 100644 index 0000000..30921aa --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_mmc.h @@ -0,0 +1,747 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_mmc.h + * @author MCD Application Team + * @brief Header file of MMC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F4xx_HAL_MMC_H +#define STM32F4xx_HAL_MMC_H + +#if defined(SDIO) + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_ll_sdmmc.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup MMC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup MMC_Exported_Types MMC Exported Types + * @{ + */ + +/** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure + * @{ + */ +typedef enum +{ + HAL_MMC_STATE_RESET = 0x00000000U, /*!< MMC not yet initialized or disabled */ + HAL_MMC_STATE_READY = 0x00000001U, /*!< MMC initialized and ready for use */ + HAL_MMC_STATE_TIMEOUT = 0x00000002U, /*!< MMC Timeout state */ + HAL_MMC_STATE_BUSY = 0x00000003U, /*!< MMC process ongoing */ + HAL_MMC_STATE_PROGRAMMING = 0x00000004U, /*!< MMC Programming State */ + HAL_MMC_STATE_RECEIVING = 0x00000005U, /*!< MMC Receinving State */ + HAL_MMC_STATE_TRANSFER = 0x00000006U, /*!< MMC Transfer State */ + HAL_MMC_STATE_ERROR = 0x0000000FU /*!< MMC is in error state */ +}HAL_MMC_StateTypeDef; +/** + * @} + */ + +/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure + * @{ + */ +typedef uint32_t HAL_MMC_CardStateTypeDef; + +#define HAL_MMC_CARD_READY 0x00000001U /*!< Card state is ready */ +#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */ +#define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */ +#define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */ +#define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */ +#define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */ +#define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */ +#define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */ +#define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error */ +/** + * @} + */ + +/** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition + * @{ + */ +#define MMC_InitTypeDef SDIO_InitTypeDef +#define MMC_TypeDef SDIO_TypeDef + +/** + * @brief MMC Card Information Structure definition + */ +typedef struct +{ + uint32_t CardType; /*!< Specifies the card Type */ + + uint32_t Class; /*!< Specifies the class of the card class */ + + uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */ + + uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */ + + uint32_t BlockSize; /*!< Specifies one block size in bytes */ + + uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */ + + uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */ + +}HAL_MMC_CardInfoTypeDef; + +/** + * @brief MMC handle Structure definition + */ +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) +typedef struct __MMC_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ +{ + MMC_TypeDef *Instance; /*!< MMC registers base address */ + + MMC_InitTypeDef Init; /*!< MMC required parameters */ + + HAL_LockTypeDef Lock; /*!< MMC locking object */ + + uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */ + + uint32_t TxXferSize; /*!< MMC Tx Transfer size */ + + uint8_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */ + + uint32_t RxXferSize; /*!< MMC Rx Transfer size */ + + __IO uint32_t Context; /*!< MMC transfer context */ + + __IO HAL_MMC_StateTypeDef State; /*!< MMC card State */ + + __IO uint32_t ErrorCode; /*!< MMC Card Error codes */ + + DMA_HandleTypeDef *hdmarx; /*!< MMC Rx DMA handle parameters */ + + DMA_HandleTypeDef *hdmatx; /*!< MMC Tx DMA handle parameters */ + + HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */ + + uint32_t CSD[4U]; /*!< MMC card specific data table */ + + uint32_t CID[4U]; /*!< MMC card identification number table */ + + uint32_t Ext_CSD[128]; + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + void (* TxCpltCallback) (struct __MMC_HandleTypeDef *hmmc); + void (* RxCpltCallback) (struct __MMC_HandleTypeDef *hmmc); + void (* ErrorCallback) (struct __MMC_HandleTypeDef *hmmc); + void (* AbortCpltCallback) (struct __MMC_HandleTypeDef *hmmc); + + void (* MspInitCallback) (struct __MMC_HandleTypeDef *hmmc); + void (* MspDeInitCallback) (struct __MMC_HandleTypeDef *hmmc); +#endif +}MMC_HandleTypeDef; + +/** + * @} + */ + +/** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register + * @{ + */ +typedef struct +{ + __IO uint8_t CSDStruct; /*!< CSD structure */ + __IO uint8_t SysSpecVersion; /*!< System specification version */ + __IO uint8_t Reserved1; /*!< Reserved */ + __IO uint8_t TAAC; /*!< Data read access time 1 */ + __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */ + __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */ + __IO uint16_t CardComdClasses; /*!< Card command classes */ + __IO uint8_t RdBlockLen; /*!< Max. read data block length */ + __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */ + __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */ + __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */ + __IO uint8_t DSRImpl; /*!< DSR implemented */ + __IO uint8_t Reserved2; /*!< Reserved */ + __IO uint32_t DeviceSize; /*!< Device Size */ + __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */ + __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */ + __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */ + __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */ + __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */ + __IO uint8_t EraseGrSize; /*!< Erase group size */ + __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */ + __IO uint8_t WrProtectGrSize; /*!< Write protect group size */ + __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */ + __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */ + __IO uint8_t WrSpeedFact; /*!< Write speed factor */ + __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */ + __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ + __IO uint8_t Reserved3; /*!< Reserved */ + __IO uint8_t ContentProtectAppli; /*!< Content protection application */ + __IO uint8_t FileFormatGroup; /*!< File format group */ + __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */ + __IO uint8_t PermWrProtect; /*!< Permanent write protection */ + __IO uint8_t TempWrProtect; /*!< Temporary write protection */ + __IO uint8_t FileFormat; /*!< File format */ + __IO uint8_t ECC; /*!< ECC code */ + __IO uint8_t CSD_CRC; /*!< CSD CRC */ + __IO uint8_t Reserved4; /*!< Always 1 */ + +}HAL_MMC_CardCSDTypeDef; +/** + * @} + */ + +/** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register + * @{ + */ +typedef struct +{ + __IO uint8_t ManufacturerID; /*!< Manufacturer ID */ + __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */ + __IO uint32_t ProdName1; /*!< Product Name part1 */ + __IO uint8_t ProdName2; /*!< Product Name part2 */ + __IO uint8_t ProdRev; /*!< Product Revision */ + __IO uint32_t ProdSN; /*!< Product Serial Number */ + __IO uint8_t Reserved1; /*!< Reserved1 */ + __IO uint16_t ManufactDate; /*!< Manufacturing Date */ + __IO uint8_t CID_CRC; /*!< CID CRC */ + __IO uint8_t Reserved2; /*!< Always 1 */ + +}HAL_MMC_CardCIDTypeDef; +/** + * @} + */ + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) +/** @defgroup MMC_Exported_Types_Group6 MMC Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_MMC_TX_CPLT_CB_ID = 0x00U, /*!< MMC Tx Complete Callback ID */ + HAL_MMC_RX_CPLT_CB_ID = 0x01U, /*!< MMC Rx Complete Callback ID */ + HAL_MMC_ERROR_CB_ID = 0x02U, /*!< MMC Error Callback ID */ + HAL_MMC_ABORT_CB_ID = 0x03U, /*!< MMC Abort Callback ID */ + + HAL_MMC_MSP_INIT_CB_ID = 0x10U, /*!< MMC MspInit Callback ID */ + HAL_MMC_MSP_DEINIT_CB_ID = 0x11U /*!< MMC MspDeInit Callback ID */ +}HAL_MMC_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition + * @{ + */ +typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); +/** + * @} + */ +#endif +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup MMC_Exported_Constants Exported Constants + * @{ + */ + +#define MMC_BLOCKSIZE 512U /*!< Block size is 512 bytes */ + +/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition + * @{ + */ +#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ +#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ +#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ +#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ +#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ +#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ +#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ +#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ +#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the + number of transferred bytes does not match the block length */ +#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ +#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ +#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ +#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock + command or if there was an attempt to access a locked card */ +#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ +#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ +#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ +#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ +#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ +#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ +#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ +#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ +#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ +#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ +#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out + of erase sequence command was received */ +#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ +#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ +#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ +#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ +#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ +#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ +#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ +#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ +#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) +#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ +#endif +/** + * @} + */ + +/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration + * @{ + */ +#define MMC_CONTEXT_NONE 0x00000000U /*!< None */ +#define MMC_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */ +#define MMC_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */ +#define MMC_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */ +#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */ +#define MMC_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */ +#define MMC_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */ + +/** + * @} + */ + +/** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode + * @{ + */ +/** + * @brief + */ +#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< High voltage in byte mode */ +#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< Dual voltage in byte mode */ +#define MMC_LOW_VOLTAGE_RANGE 0x80000080U /*!< Low voltage in byte mode */ +#define EMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< High voltage in sector mode */ +#define EMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< Dual voltage in sector mode */ +#define EMMC_LOW_VOLTAGE_RANGE 0xC0000080U /*!< Low voltage in sector mode */ +#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U +/** + * @} + */ + +/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards + * @{ + */ +#define MMC_LOW_CAPACITY_CARD 0x00000000U /*!< MMC Card Capacity <=2Gbytes */ +#define MMC_HIGH_CAPACITY_CARD 0x00000001U /*!< MMC Card Capacity >2Gbytes and <2Tbytes */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup MMC_Exported_macros MMC Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +/** @brief Reset MMC handle state. + * @param __HANDLE__ : MMC handle. + * @retval None + */ +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) +#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_MMC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MMC_STATE_RESET) +#endif + +/** + * @brief Enable the MMC device. + * @retval None + */ +#define __HAL_MMC_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance) + +/** + * @brief Disable the MMC device. + * @retval None + */ +#define __HAL_MMC_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance) + +/** + * @brief Enable the SDMMC DMA transfer. + * @retval None + */ +#define __HAL_MMC_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance) + +/** + * @brief Disable the SDMMC DMA transfer. + * @retval None + */ +#define __HAL_MMC_DMA_DISABLE(__HANDLE__) __SDIO_DMA_DISABLE((__HANDLE__)->Instance) + +/** + * @brief Enable the MMC device interrupt. + * @param __HANDLE__: MMC Handle + * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @retval None + */ +#define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Disable the MMC device interrupt. + * @param __HANDLE__: MMC Handle + * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @retval None + */ +#define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Check whether the specified MMC flag is set or not. + * @param __HANDLE__: MMC Handle + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_CMDACT: Command transfer in progress + * @arg SDIO_FLAG_TXACT: Data transmit in progress + * @arg SDIO_FLAG_RXACT: Data receive in progress + * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty + * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full + * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full + * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full + * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty + * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty + * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO + * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @retval The new state of MMC FLAG (SET or RESET). + */ +#define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) + +/** + * @brief Clear the MMC's pending flags. + * @param __HANDLE__: MMC Handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @retval None + */ +#define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) + +/** + * @brief Check whether the specified MMC interrupt has occurred or not. + * @param __HANDLE__: MMC Handle + * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. + * This parameter can be one of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @retval The new state of MMC IT (SET or RESET). + */ +#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Clear the MMC's interrupt pending bits. + * @param __HANDLE__: MMC Handle + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @retval None + */ +#define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup MMC_Exported_Functions MMC Exported Functions + * @{ + */ + +/** @defgroup MMC_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc); +void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc); +void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc); + +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd); +/* Non-Blocking mode: IT */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); + +void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc); + +/* Callback in non blocking modes (DMA) */ +void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc); +void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc); +void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc); +void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc); + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) +/* MMC callback registering/unregistering */ +HAL_StatusTypeDef HAL_MMC_RegisterCallback (MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId); +#endif +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode); +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group4 MMC card related functions + * @{ + */ +HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD); +HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); +HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout); +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions + * @{ + */ +HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc); +uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc); +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group6 Peripheral Abort management + * @{ + */ +HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc); +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup MMC_Private_Types MMC Private Types + * @{ + */ + +/** + * @} + */ + +/* Private defines -----------------------------------------------------------*/ +/** @defgroup MMC_Private_Defines MMC Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup MMC_Private_Variables MMC Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup MMC_Private_Constants MMC Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup MMC_Private_Macros MMC Private Macros + * @{ + */ + +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup MMC_Private_Functions MMC Private Functions + * @{ + */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* SDIO */ + +#endif /* STM32F4xx_HAL_MMC_H */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h new file mode 100644 index 0000000..73fc7de --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h @@ -0,0 +1,758 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_sd.h + * @author MCD Application Team + * @brief Header file of SD HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F4xx_HAL_SD_H +#define STM32F4xx_HAL_SD_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(SDIO) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_ll_sdmmc.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup SD SD + * @brief SD HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SD_Exported_Types SD Exported Types + * @{ + */ + +/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure + * @{ + */ +typedef enum +{ + HAL_SD_STATE_RESET = 0x00000000U, /*!< SD not yet initialized or disabled */ + HAL_SD_STATE_READY = 0x00000001U, /*!< SD initialized and ready for use */ + HAL_SD_STATE_TIMEOUT = 0x00000002U, /*!< SD Timeout state */ + HAL_SD_STATE_BUSY = 0x00000003U, /*!< SD process ongoing */ + HAL_SD_STATE_PROGRAMMING = 0x00000004U, /*!< SD Programming State */ + HAL_SD_STATE_RECEIVING = 0x00000005U, /*!< SD Receiving State */ + HAL_SD_STATE_TRANSFER = 0x00000006U, /*!< SD Transfer State */ + HAL_SD_STATE_ERROR = 0x0000000FU /*!< SD is in error state */ +}HAL_SD_StateTypeDef; +/** + * @} + */ + +/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure + * @{ + */ +typedef uint32_t HAL_SD_CardStateTypeDef; + +#define HAL_SD_CARD_READY 0x00000001U /*!< Card state is ready */ +#define HAL_SD_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */ +#define HAL_SD_CARD_STANDBY 0x00000003U /*!< Card is in standby state */ +#define HAL_SD_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */ +#define HAL_SD_CARD_SENDING 0x00000005U /*!< Card is sending an operation */ +#define HAL_SD_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */ +#define HAL_SD_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */ +#define HAL_SD_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */ +#define HAL_SD_CARD_ERROR 0x000000FFU /*!< Card response Error */ +/** + * @} + */ + +/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition + * @{ + */ +#define SD_InitTypeDef SDIO_InitTypeDef +#define SD_TypeDef SDIO_TypeDef + +/** + * @brief SD Card Information Structure definition + */ +typedef struct +{ + uint32_t CardType; /*!< Specifies the card Type */ + + uint32_t CardVersion; /*!< Specifies the card version */ + + uint32_t Class; /*!< Specifies the class of the card class */ + + uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */ + + uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */ + + uint32_t BlockSize; /*!< Specifies one block size in bytes */ + + uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */ + + uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */ + +}HAL_SD_CardInfoTypeDef; + +/** + * @brief SD handle Structure definition + */ +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +typedef struct __SD_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ +{ + SD_TypeDef *Instance; /*!< SD registers base address */ + + SD_InitTypeDef Init; /*!< SD required parameters */ + + HAL_LockTypeDef Lock; /*!< SD locking object */ + + uint8_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */ + + uint32_t TxXferSize; /*!< SD Tx Transfer size */ + + uint8_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */ + + uint32_t RxXferSize; /*!< SD Rx Transfer size */ + + __IO uint32_t Context; /*!< SD transfer context */ + + __IO HAL_SD_StateTypeDef State; /*!< SD card State */ + + __IO uint32_t ErrorCode; /*!< SD Card Error codes */ + + DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */ + + HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */ + + uint32_t CSD[4]; /*!< SD card specific data table */ + + uint32_t CID[4]; /*!< SD card identification number table */ + +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + void (* TxCpltCallback) (struct __SD_HandleTypeDef *hsd); + void (* RxCpltCallback) (struct __SD_HandleTypeDef *hsd); + void (* ErrorCallback) (struct __SD_HandleTypeDef *hsd); + void (* AbortCpltCallback) (struct __SD_HandleTypeDef *hsd); + + void (* MspInitCallback) (struct __SD_HandleTypeDef *hsd); + void (* MspDeInitCallback) (struct __SD_HandleTypeDef *hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ +}SD_HandleTypeDef; + +/** + * @} + */ + +/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register + * @{ + */ +typedef struct +{ + __IO uint8_t CSDStruct; /*!< CSD structure */ + __IO uint8_t SysSpecVersion; /*!< System specification version */ + __IO uint8_t Reserved1; /*!< Reserved */ + __IO uint8_t TAAC; /*!< Data read access time 1 */ + __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */ + __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */ + __IO uint16_t CardComdClasses; /*!< Card command classes */ + __IO uint8_t RdBlockLen; /*!< Max. read data block length */ + __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */ + __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */ + __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */ + __IO uint8_t DSRImpl; /*!< DSR implemented */ + __IO uint8_t Reserved2; /*!< Reserved */ + __IO uint32_t DeviceSize; /*!< Device Size */ + __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */ + __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */ + __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */ + __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */ + __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */ + __IO uint8_t EraseGrSize; /*!< Erase group size */ + __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */ + __IO uint8_t WrProtectGrSize; /*!< Write protect group size */ + __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */ + __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */ + __IO uint8_t WrSpeedFact; /*!< Write speed factor */ + __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */ + __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ + __IO uint8_t Reserved3; /*!< Reserved */ + __IO uint8_t ContentProtectAppli; /*!< Content protection application */ + __IO uint8_t FileFormatGroup; /*!< File format group */ + __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */ + __IO uint8_t PermWrProtect; /*!< Permanent write protection */ + __IO uint8_t TempWrProtect; /*!< Temporary write protection */ + __IO uint8_t FileFormat; /*!< File format */ + __IO uint8_t ECC; /*!< ECC code */ + __IO uint8_t CSD_CRC; /*!< CSD CRC */ + __IO uint8_t Reserved4; /*!< Always 1 */ +}HAL_SD_CardCSDTypeDef; +/** + * @} + */ + +/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register + * @{ + */ +typedef struct +{ + __IO uint8_t ManufacturerID; /*!< Manufacturer ID */ + __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */ + __IO uint32_t ProdName1; /*!< Product Name part1 */ + __IO uint8_t ProdName2; /*!< Product Name part2 */ + __IO uint8_t ProdRev; /*!< Product Revision */ + __IO uint32_t ProdSN; /*!< Product Serial Number */ + __IO uint8_t Reserved1; /*!< Reserved1 */ + __IO uint16_t ManufactDate; /*!< Manufacturing Date */ + __IO uint8_t CID_CRC; /*!< CID CRC */ + __IO uint8_t Reserved2; /*!< Always 1 */ + +}HAL_SD_CardCIDTypeDef; +/** + * @} + */ + +/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13 + * @{ + */ +typedef struct +{ + __IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */ + __IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */ + __IO uint16_t CardType; /*!< Carries information about card type */ + __IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */ + __IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */ + __IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */ + __IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */ + __IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */ + __IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */ + __IO uint8_t EraseOffset; /*!< Carries information about the erase offset */ + +}HAL_SD_CardStatusTypeDef; +/** + * @} + */ + +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_SD_TX_CPLT_CB_ID = 0x00U, /*!< SD Tx Complete Callback ID */ + HAL_SD_RX_CPLT_CB_ID = 0x01U, /*!< SD Rx Complete Callback ID */ + HAL_SD_ERROR_CB_ID = 0x02U, /*!< SD Error Callback ID */ + HAL_SD_ABORT_CB_ID = 0x03U, /*!< SD Abort Callback ID */ + + HAL_SD_MSP_INIT_CB_ID = 0x10U, /*!< SD MspInit Callback ID */ + HAL_SD_MSP_DEINIT_CB_ID = 0x11U /*!< SD MspDeInit Callback ID */ +}HAL_SD_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition + * @{ + */ +typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd); +/** + * @} + */ +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SD_Exported_Constants Exported Constants + * @{ + */ + +#define BLOCKSIZE 512U /*!< Block size is 512 bytes */ + +/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition + * @{ + */ +#define HAL_SD_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ +#define HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ +#define HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ +#define HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ +#define HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ +#define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ +#define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ +#define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ +#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the + number of transferred bytes does not match the block length */ +#define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ +#define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ +#define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ +#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock + command or if there was an attempt to access a locked card */ +#define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ +#define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ +#define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ +#define HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ +#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ +#define HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ +#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ +#define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ +#define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ +#define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ +#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out + of erase sequence command was received */ +#define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ +#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ +#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ +#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ +#define HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ +#define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ +#define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ +#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ +#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ + +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +#define HAL_SD_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration + * @{ + */ +#define SD_CONTEXT_NONE 0x00000000U /*!< None */ +#define SD_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */ +#define SD_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */ +#define SD_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */ +#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */ +#define SD_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */ +#define SD_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */ + +/** + * @} + */ + +/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards + * @{ + */ +#define CARD_SDSC 0x00000000U /*!< SD Standard Capacity <2Go */ +#define CARD_SDHC_SDXC 0x00000001U /*!< SD High Capacity <32Go, SD Extended Capacity <2To */ +#define CARD_SECURED 0x00000003U + +/** + * @} + */ + +/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version + * @{ + */ +#define CARD_V1_X 0x00000000U +#define CARD_V2_X 0x00000001U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SD_Exported_macros SD Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +/** @brief Reset SD handle state. + * @param __HANDLE__ : SD handle. + * @retval None + */ +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_SD_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SD_STATE_RESET) +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + +/** + * @brief Enable the SD device. + * @retval None + */ +#define __HAL_SD_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance) + +/** + * @brief Disable the SD device. + * @retval None + */ +#define __HAL_SD_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance) + +/** + * @brief Enable the SDMMC DMA transfer. + * @retval None + */ +#define __HAL_SD_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance) + +/** + * @brief Disable the SDMMC DMA transfer. + * @retval None + */ +#define __HAL_SD_DMA_DISABLE(__HANDLE__) __SDIO_DMA_DISABLE((__HANDLE__)->Instance) + +/** + * @brief Enable the SD device interrupt. + * @param __HANDLE__: SD Handle + * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt + * @retval None + */ +#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Disable the SD device interrupt. + * @param __HANDLE__: SD Handle + * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt + * @retval None + */ +#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Check whether the specified SD flag is set or not. + * @param __HANDLE__: SD Handle + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_CMDACT: Command transfer in progress + * @arg SDIO_FLAG_TXACT: Data transmit in progress + * @arg SDIO_FLAG_RXACT: Data receive in progress + * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty + * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full + * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full + * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full + * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty + * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty + * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO + * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO + * @arg SDIO_FLAG_SDIOIT: SDIO interrupt received + * @retval The new state of SD FLAG (SET or RESET). + */ +#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) + +/** + * @brief Clear the SD's pending flags. + * @param __HANDLE__: SD Handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_SDIOIT: SDIO interrupt received + * @retval None + */ +#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) + +/** + * @brief Check whether the specified SD interrupt has occurred or not. + * @param __HANDLE__: SD Handle + * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. + * This parameter can be one of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt + * @retval The new state of SD IT (SET or RESET). + */ +#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Clear the SD's interrupt pending bits. + * @param __HANDLE__: SD Handle + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt + * @retval None + */ +#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SD_Exported_Functions SD Exported Functions + * @{ + */ + +/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd); +void HAL_SD_MspInit(SD_HandleTypeDef *hsd); +void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd); +/** + * @} + */ + +/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); +HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); +HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd); +/* Non-Blocking mode: IT */ +HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); + +void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd); + +/* Callback in non blocking modes (DMA) */ +void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd); +void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd); +void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd); +void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd); + +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +/* SD callback registering/unregistering */ +HAL_StatusTypeDef HAL_SD_RegisterCallback (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId, pSD_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode); +/** + * @} + */ + +/** @defgroup SD_Exported_Functions_Group4 SD card related functions + * @{ + */ +HAL_StatusTypeDef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus); +HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD); +HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus); +HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); +/** + * @} + */ + +/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions + * @{ + */ +HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd); +uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd); +/** + * @} + */ + +/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management + * @{ + */ +HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd); +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup SD_Private_Types SD Private Types + * @{ + */ + +/** + * @} + */ + +/* Private defines -----------------------------------------------------------*/ +/** @defgroup SD_Private_Defines SD Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup SD_Private_Variables SD Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SD_Private_Constants SD Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SD_Private_Macros SD Private Macros + * @{ + */ + +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup SD_Private_Functions SD Private Functions + * @{ + */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* SDIO */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32F4xx_HAL_SD_H */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h new file mode 100644 index 0000000..1d3c652 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h @@ -0,0 +1,1145 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_sdmmc.h + * @author MCD Application Team + * @brief Header file of SDMMC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F4xx_LL_SDMMC_H +#define STM32F4xx_LL_SDMMC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(SDIO) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_Driver + * @{ + */ + +/** @addtogroup SDMMC_LL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types + * @{ + */ + +/** + * @brief SDMMC Configuration Structure definition + */ +typedef struct +{ + uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ + + uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is + enabled or disabled. + This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */ + + uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or + disabled when the bus is idle. + This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ + + uint32_t BusWide; /*!< Specifies the SDMMC bus width. + This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ + + uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled. + This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ + + uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. + This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ + +}SDIO_InitTypeDef; + + +/** + * @brief SDMMC Command Control structure + */ +typedef struct +{ + uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent + to a card as part of a command message. If a command + contains an argument, it must be loaded into this register + before writing the command to the command register. */ + + uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and + Max_Data = 64 */ + + uint32_t Response; /*!< Specifies the SDMMC response type. + This parameter can be a value of @ref SDMMC_LL_Response_Type */ + + uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is + enabled or disabled. + This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ + + uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM) + is enabled or disabled. + This parameter can be a value of @ref SDMMC_LL_CPSM_State */ +}SDIO_CmdInitTypeDef; + + +/** + * @brief SDMMC Data Control structure + */ +typedef struct +{ + uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ + + uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ + + uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. + This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */ + + uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer + is a read or write. + This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ + + uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. + This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ + + uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM) + is enabled or disabled. + This parameter can be a value of @ref SDMMC_LL_DPSM_State */ +}SDIO_DataInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants + * @{ + */ +#define SDMMC_ERROR_NONE 0x00000000U /*!< No error */ +#define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /*!< Command response received (but CRC check failed) */ +#define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /*!< Data block sent/received (CRC check failed) */ +#define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /*!< Command response timeout */ +#define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /*!< Data timeout */ +#define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /*!< Transmit FIFO underrun */ +#define SDMMC_ERROR_RX_OVERRUN 0x00000020U /*!< Receive FIFO overrun */ +#define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /*!< Misaligned address */ +#define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the + number of transferred bytes does not match the block length */ +#define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /*!< An error in the sequence of erase command occurs */ +#define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /*!< An invalid selection for erase groups */ +#define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /*!< Attempt to program a write protect block */ +#define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock + command or if there was an attempt to access a locked card */ +#define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /*!< CRC check of the previous command failed */ +#define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /*!< Command is not legal for the card state */ +#define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /*!< Card internal ECC was applied but failed to correct the data */ +#define SDMMC_ERROR_CC_ERR 0x00008000U /*!< Internal card controller error */ +#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /*!< General or unknown error */ +#define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /*!< The card could not sustain data reading in stream rmode */ +#define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /*!< The card could not sustain data programming in stream mode */ +#define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /*!< CID/CSD overwrite error */ +#define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /*!< Only partial address space was erased */ +#define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /*!< Command has been executed without using internal ECC */ +#define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out + of erase sequence command was received */ +#define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /*!< Error in sequence of authentication */ +#define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /*!< Error in case of invalid voltage range */ +#define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /*!< Error when addressed block is out of range */ +#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /*!< Error when command request is not applicable */ +#define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /*!< the used parameter is not valid */ +#define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /*!< Error when feature is not insupported */ +#define SDMMC_ERROR_BUSY 0x20000000U /*!< Error when transfer process is busy */ +#define SDMMC_ERROR_DMA 0x40000000U /*!< Error while DMA transfer */ +#define SDMMC_ERROR_TIMEOUT 0x80000000U /*!< Timeout error */ + +/** + * @brief SDMMC Commands Index + */ +#define SDMMC_CMD_GO_IDLE_STATE 0U /*!< Resets the SD memory card. */ +#define SDMMC_CMD_SEND_OP_COND 1U /*!< Sends host capacity support information and activates the card's initialization process. */ +#define SDMMC_CMD_ALL_SEND_CID 2U /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ +#define SDMMC_CMD_SET_REL_ADDR 3U /*!< Asks the card to publish a new relative address (RCA). */ +#define SDMMC_CMD_SET_DSR 4U /*!< Programs the DSR of all cards. */ +#define SDMMC_CMD_SDMMC_SEN_OP_COND 5U /*!< Sends host capacity support information (HCS) and asks the accessed card to send its + operating condition register (OCR) content in the response on the CMD line. */ +#define SDMMC_CMD_HS_SWITCH 6U /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ +#define SDMMC_CMD_SEL_DESEL_CARD 7U /*!< Selects the card by its own relative address and gets deselected by any other address */ +#define SDMMC_CMD_HS_SEND_EXT_CSD 8U /*!< Sends SD Memory Card interface condition, which includes host supply voltage information + and asks the card whether card supports voltage. */ +#define SDMMC_CMD_SEND_CSD 9U /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ +#define SDMMC_CMD_SEND_CID 10U /*!< Addressed card sends its card identification (CID) on the CMD line. */ +#define SDMMC_CMD_READ_DAT_UNTIL_STOP 11U /*!< SD card doesn't support it. */ +#define SDMMC_CMD_STOP_TRANSMISSION 12U /*!< Forces the card to stop transmission. */ +#define SDMMC_CMD_SEND_STATUS 13U /*!< Addressed card sends its status register. */ +#define SDMMC_CMD_HS_BUSTEST_READ 14U /*!< Reserved */ +#define SDMMC_CMD_GO_INACTIVE_STATE 15U /*!< Sends an addressed card into the inactive state. */ +#define SDMMC_CMD_SET_BLOCKLEN 16U /*!< Sets the block length (in bytes for SDSC) for all following block commands + (read, write, lock). Default block length is fixed to 512 Bytes. Not effective + for SDHS and SDXC. */ +#define SDMMC_CMD_READ_SINGLE_BLOCK 17U /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of + fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_READ_MULT_BLOCK 18U /*!< Continuously transfers data blocks from card to host until interrupted by + STOP_TRANSMISSION command. */ +#define SDMMC_CMD_HS_BUSTEST_WRITE 19U /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ +#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP 20U /*!< Speed class control command. */ +#define SDMMC_CMD_SET_BLOCK_COUNT 23U /*!< Specify block count for CMD18 and CMD25. */ +#define SDMMC_CMD_WRITE_SINGLE_BLOCK 24U /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of + fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_WRITE_MULT_BLOCK 25U /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ +#define SDMMC_CMD_PROG_CID 26U /*!< Reserved for manufacturers. */ +#define SDMMC_CMD_PROG_CSD 27U /*!< Programming of the programmable bits of the CSD. */ +#define SDMMC_CMD_SET_WRITE_PROT 28U /*!< Sets the write protection bit of the addressed group. */ +#define SDMMC_CMD_CLR_WRITE_PROT 29U /*!< Clears the write protection bit of the addressed group. */ +#define SDMMC_CMD_SEND_WRITE_PROT 30U /*!< Asks the card to send the status of the write protection bits. */ +#define SDMMC_CMD_SD_ERASE_GRP_START 32U /*!< Sets the address of the first write block to be erased. (For SD card only). */ +#define SDMMC_CMD_SD_ERASE_GRP_END 33U /*!< Sets the address of the last write block of the continuous range to be erased. */ +#define SDMMC_CMD_ERASE_GRP_START 35U /*!< Sets the address of the first write block to be erased. Reserved for each command + system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE_GRP_END 36U /*!< Sets the address of the last write block of the continuous range to be erased. + Reserved for each command system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE 38U /*!< Reserved for SD security applications. */ +#define SDMMC_CMD_FAST_IO 39U /*!< SD card doesn't support it (Reserved). */ +#define SDMMC_CMD_GO_IRQ_STATE 40U /*!< SD card doesn't support it (Reserved). */ +#define SDMMC_CMD_LOCK_UNLOCK 42U /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by + the SET_BLOCK_LEN command. */ +#define SDMMC_CMD_APP_CMD 55U /*!< Indicates to the card that the next command is an application specific command rather + than a standard command. */ +#define SDMMC_CMD_GEN_CMD 56U /*!< Used either to transfer a data block to the card or to get a data block from the card + for general purpose/application specific commands. */ +#define SDMMC_CMD_NO_CMD 64U /*!< No command */ + +/** + * @brief Following commands are SD Card Specific commands. + * SDMMC_APP_CMD should be sent before sending these commands. + */ +#define SDMMC_CMD_APP_SD_SET_BUSWIDTH 6U /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus + widths are given in SCR register. */ +#define SDMMC_CMD_SD_APP_STATUS 13U /*!< (ACMD13) Sends the SD status. */ +#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS 22U /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with + 32bit+CRC data block. */ +#define SDMMC_CMD_SD_APP_OP_COND 41U /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to + send its operating condition register (OCR) content in the response on the CMD line. */ +#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT 42U /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ +#define SDMMC_CMD_SD_APP_SEND_SCR 51U /*!< Reads the SD Configuration Register (SCR). */ +#define SDMMC_CMD_SDMMC_RW_DIRECT 52U /*!< For SD I/O card only, reserved for security specification. */ +#define SDMMC_CMD_SDMMC_RW_EXTENDED 53U /*!< For SD I/O card only, reserved for security specification. */ + +/** + * @brief Following commands are SD Card Specific security commands. + * SDMMC_CMD_APP_CMD should be sent before sending these commands. + */ +#define SDMMC_CMD_SD_APP_GET_MKB 43U +#define SDMMC_CMD_SD_APP_GET_MID 44U +#define SDMMC_CMD_SD_APP_SET_CER_RN1 45U +#define SDMMC_CMD_SD_APP_GET_CER_RN2 46U +#define SDMMC_CMD_SD_APP_SET_CER_RES2 47U +#define SDMMC_CMD_SD_APP_GET_CER_RES1 48U +#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK 18U +#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK 25U +#define SDMMC_CMD_SD_APP_SECURE_ERASE 38U +#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA 49U +#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB 48U + +/** + * @brief Masks for errors Card Status R1 (OCR Register) + */ +#define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U +#define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U +#define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U +#define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U +#define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U +#define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U +#define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U +#define SDMMC_OCR_COM_CRC_FAILED 0x00800000U +#define SDMMC_OCR_ILLEGAL_CMD 0x00400000U +#define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U +#define SDMMC_OCR_CC_ERROR 0x00100000U +#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U +#define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U +#define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U +#define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U +#define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U +#define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U +#define SDMMC_OCR_ERASE_RESET 0x00002000U +#define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U +#define SDMMC_OCR_ERRORBITS 0xFDFFE008U + +/** + * @brief Masks for R6 Response + */ +#define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U +#define SDMMC_R6_ILLEGAL_CMD 0x00004000U +#define SDMMC_R6_COM_CRC_FAILED 0x00008000U + +#define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U +#define SDMMC_HIGH_CAPACITY 0x40000000U +#define SDMMC_STD_CAPACITY 0x00000000U +#define SDMMC_CHECK_PATTERN 0x000001AAU +#define SD_SWITCH_1_8V_CAPACITY 0x01000000U + +#define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU + +#define SDMMC_MAX_TRIAL 0x0000FFFFU + +#define SDMMC_ALLZERO 0x00000000U + +#define SDMMC_WIDE_BUS_SUPPORT 0x00040000U +#define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U +#define SDMMC_CARD_LOCKED 0x02000000U + +#ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (ms) */ +#define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) +#endif /* SDMMC_DATATIMEOUT */ + +#ifndef SDMMC_SWDATATIMEOUT /*Software Data Timeout (ms) */ +#define SDMMC_SWDATATIMEOUT SDMMC_DATATIMEOUT +#endif /* SDMMC_SWDATATIMEOUT */ + +#define SDMMC_0TO7BITS 0x000000FFU +#define SDMMC_8TO15BITS 0x0000FF00U +#define SDMMC_16TO23BITS 0x00FF0000U +#define SDMMC_24TO31BITS 0xFF000000U +#define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU + +#define SDMMC_HALFFIFO 0x00000008U +#define SDMMC_HALFFIFOBYTES 0x00000020U + +/** + * @brief Command Class supported + */ +#define SDIO_CCCC_ERASE 0x00000020U + +#define SDIO_CMDTIMEOUT 5000U /* Command send and response timeout */ +#define SDIO_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */ +#define SDIO_STOPTRANSFERTIMEOUT 100000000U /* Timeout for STOP TRANSMISSION command */ + +/** @defgroup SDIO_LL_Clock_Edge Clock Edge + * @{ + */ +#define SDIO_CLOCK_EDGE_RISING 0x00000000U +#define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE + +#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \ + ((EDGE) == SDIO_CLOCK_EDGE_FALLING)) +/** + * @} + */ + +/** @defgroup SDIO_LL_Clock_Bypass Clock Bypass + * @{ + */ +#define SDIO_CLOCK_BYPASS_DISABLE 0x00000000U +#define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS + +#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \ + ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE)) +/** + * @} + */ + +/** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving + * @{ + */ +#define SDIO_CLOCK_POWER_SAVE_DISABLE 0x00000000U +#define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV + +#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \ + ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE)) +/** + * @} + */ + +/** @defgroup SDIO_LL_Bus_Wide Bus Width + * @{ + */ +#define SDIO_BUS_WIDE_1B 0x00000000U +#define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0 +#define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1 + +#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \ + ((WIDE) == SDIO_BUS_WIDE_4B) || \ + ((WIDE) == SDIO_BUS_WIDE_8B)) +/** + * @} + */ + +/** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control + * @{ + */ +#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE 0x00000000U +#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN + +#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \ + ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE)) +/** + * @} + */ + +/** @defgroup SDIO_LL_Clock_Division Clock Division + * @{ + */ +#define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFFU) +/** + * @} + */ + +/** @defgroup SDIO_LL_Command_Index Command Index + * @{ + */ +#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40U) +/** + * @} + */ + +/** @defgroup SDIO_LL_Response_Type Response Type + * @{ + */ +#define SDIO_RESPONSE_NO 0x00000000U +#define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0 +#define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP + +#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \ + ((RESPONSE) == SDIO_RESPONSE_SHORT) || \ + ((RESPONSE) == SDIO_RESPONSE_LONG)) +/** + * @} + */ + +/** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt + * @{ + */ +#define SDIO_WAIT_NO 0x00000000U +#define SDIO_WAIT_IT SDIO_CMD_WAITINT +#define SDIO_WAIT_PEND SDIO_CMD_WAITPEND + +#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \ + ((WAIT) == SDIO_WAIT_IT) || \ + ((WAIT) == SDIO_WAIT_PEND)) +/** + * @} + */ + +/** @defgroup SDIO_LL_CPSM_State CPSM State + * @{ + */ +#define SDIO_CPSM_DISABLE 0x00000000U +#define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN + +#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \ + ((CPSM) == SDIO_CPSM_ENABLE)) +/** + * @} + */ + +/** @defgroup SDIO_LL_Response_Registers Response Register + * @{ + */ +#define SDIO_RESP1 0x00000000U +#define SDIO_RESP2 0x00000004U +#define SDIO_RESP3 0x00000008U +#define SDIO_RESP4 0x0000000CU + +#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \ + ((RESP) == SDIO_RESP2) || \ + ((RESP) == SDIO_RESP3) || \ + ((RESP) == SDIO_RESP4)) +/** + * @} + */ + +/** @defgroup SDIO_LL_Data_Length Data Length + * @{ + */ +#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU) +/** + * @} + */ + +/** @defgroup SDIO_LL_Data_Block_Size Data Block Size + * @{ + */ +#define SDIO_DATABLOCK_SIZE_1B 0x00000000U +#define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0 +#define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1 +#define SDIO_DATABLOCK_SIZE_8B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1) +#define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2 +#define SDIO_DATABLOCK_SIZE_32B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2) +#define SDIO_DATABLOCK_SIZE_64B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2) +#define SDIO_DATABLOCK_SIZE_128B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2) +#define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3 +#define SDIO_DATABLOCK_SIZE_512B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_3) +#define SDIO_DATABLOCK_SIZE_1024B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3) +#define SDIO_DATABLOCK_SIZE_2048B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3) +#define SDIO_DATABLOCK_SIZE_4096B (SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) +#define SDIO_DATABLOCK_SIZE_8192B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) +#define SDIO_DATABLOCK_SIZE_16384B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) + +#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_16384B)) +/** + * @} + */ + +/** @defgroup SDIO_LL_Transfer_Direction Transfer Direction + * @{ + */ +#define SDIO_TRANSFER_DIR_TO_CARD 0x00000000U +#define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR + +#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \ + ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO)) +/** + * @} + */ + +/** @defgroup SDIO_LL_Transfer_Type Transfer Type + * @{ + */ +#define SDIO_TRANSFER_MODE_BLOCK 0x00000000U +#define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE + +#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \ + ((MODE) == SDIO_TRANSFER_MODE_STREAM)) +/** + * @} + */ + +/** @defgroup SDIO_LL_DPSM_State DPSM State + * @{ + */ +#define SDIO_DPSM_DISABLE 0x00000000U +#define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN + +#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\ + ((DPSM) == SDIO_DPSM_ENABLE)) +/** + * @} + */ + +/** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode + * @{ + */ +#define SDIO_READ_WAIT_MODE_DATA2 0x00000000U +#define SDIO_READ_WAIT_MODE_CLK (SDIO_DCTRL_RWMOD) + +#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \ + ((MODE) == SDIO_READ_WAIT_MODE_DATA2)) +/** + * @} + */ + +/** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources + * @{ + */ +#define SDIO_IT_CCRCFAIL SDIO_MASK_CCRCFAILIE +#define SDIO_IT_DCRCFAIL SDIO_MASK_DCRCFAILIE +#define SDIO_IT_CTIMEOUT SDIO_MASK_CTIMEOUTIE +#define SDIO_IT_DTIMEOUT SDIO_MASK_DTIMEOUTIE +#define SDIO_IT_TXUNDERR SDIO_MASK_TXUNDERRIE +#define SDIO_IT_RXOVERR SDIO_MASK_RXOVERRIE +#define SDIO_IT_CMDREND SDIO_MASK_CMDRENDIE +#define SDIO_IT_CMDSENT SDIO_MASK_CMDSENTIE +#define SDIO_IT_DATAEND SDIO_MASK_DATAENDIE +#if defined(SDIO_STA_STBITERR) +#define SDIO_IT_STBITERR SDIO_MASK_STBITERRIE +#endif +#define SDIO_IT_DBCKEND SDIO_MASK_DBCKENDIE +#define SDIO_IT_CMDACT SDIO_MASK_CMDACTIE +#define SDIO_IT_TXACT SDIO_MASK_TXACTIE +#define SDIO_IT_RXACT SDIO_MASK_RXACTIE +#define SDIO_IT_TXFIFOHE SDIO_MASK_TXFIFOHEIE +#define SDIO_IT_RXFIFOHF SDIO_MASK_RXFIFOHFIE +#define SDIO_IT_TXFIFOF SDIO_MASK_TXFIFOFIE +#define SDIO_IT_RXFIFOF SDIO_MASK_RXFIFOFIE +#define SDIO_IT_TXFIFOE SDIO_MASK_TXFIFOEIE +#define SDIO_IT_RXFIFOE SDIO_MASK_RXFIFOEIE +#define SDIO_IT_TXDAVL SDIO_MASK_TXDAVLIE +#define SDIO_IT_RXDAVL SDIO_MASK_RXDAVLIE +#define SDIO_IT_SDIOIT SDIO_MASK_SDIOITIE +#if defined(SDIO_CMD_CEATACMD) +#define SDIO_IT_CEATAEND SDIO_MASK_CEATAENDIE +#endif +/** + * @} + */ + +/** @defgroup SDIO_LL_Flags Flags + * @{ + */ +#define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL +#define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL +#define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT +#define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT +#define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR +#define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR +#define SDIO_FLAG_CMDREND SDIO_STA_CMDREND +#define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT +#define SDIO_FLAG_DATAEND SDIO_STA_DATAEND +#if defined(SDIO_STA_STBITERR) +#define SDIO_FLAG_STBITERR SDIO_STA_STBITERR +#endif +#define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND +#define SDIO_FLAG_CMDACT SDIO_STA_CMDACT +#define SDIO_FLAG_TXACT SDIO_STA_TXACT +#define SDIO_FLAG_RXACT SDIO_STA_RXACT +#define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE +#define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF +#define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF +#define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF +#define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE +#define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE +#define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL +#define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL +#define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT +#if defined(SDIO_CMD_CEATACMD) +#define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND +#endif +#define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\ + SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR |\ + SDIO_FLAG_CMDREND | SDIO_FLAG_CMDSENT | SDIO_FLAG_DATAEND |\ + SDIO_FLAG_DBCKEND | SDIO_FLAG_SDIOIT)) + +#define SDIO_STATIC_CMD_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND |\ + SDIO_FLAG_CMDSENT)) + +#define SDIO_STATIC_DATA_FLAGS ((uint32_t)(SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR |\ + SDIO_FLAG_RXOVERR | SDIO_FLAG_DATAEND | SDIO_FLAG_DBCKEND)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SDIO_LL_Exported_macros SDIO_LL Exported Macros + * @{ + */ + +/** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region + * @{ + */ +/* ------------ SDIO registers bit address in the alias region -------------- */ +#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) + +/* --- CLKCR Register ---*/ +/* Alias word address of CLKEN bit */ +#define CLKCR_OFFSET (SDIO_OFFSET + 0x04U) +#define CLKEN_BITNUMBER 0x08U +#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U)) + +/* --- CMD Register ---*/ +/* Alias word address of SDIOSUSPEND bit */ +#define CMD_OFFSET (SDIO_OFFSET + 0x0CU) +#define SDIOSUSPEND_BITNUMBER 0x0BU +#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U)) + +/* Alias word address of ENCMDCOMPL bit */ +#define ENCMDCOMPL_BITNUMBER 0x0CU +#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U)) + +/* Alias word address of NIEN bit */ +#define NIEN_BITNUMBER 0x0DU +#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U)) + +/* Alias word address of ATACMD bit */ +#define ATACMD_BITNUMBER 0x0EU +#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U)) + +/* --- DCTRL Register ---*/ +/* Alias word address of DMAEN bit */ +#define DCTRL_OFFSET (SDIO_OFFSET + 0x2CU) +#define DMAEN_BITNUMBER 0x03U +#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U)) + +/* Alias word address of RWSTART bit */ +#define RWSTART_BITNUMBER 0x08U +#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U)) + +/* Alias word address of RWSTOP bit */ +#define RWSTOP_BITNUMBER 0x09U +#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U)) + +/* Alias word address of RWMOD bit */ +#define RWMOD_BITNUMBER 0x0AU +#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U)) + +/* Alias word address of SDIOEN bit */ +#define SDIOEN_BITNUMBER 0x0BU +#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U)) +/** + * @} + */ + +/** @defgroup SDIO_LL_Register Bits And Addresses Definitions + * @brief SDIO_LL registers bit address in the alias region + * @{ + */ +/* ---------------------- SDIO registers bit mask --------------------------- */ +/* --- CLKCR Register ---*/ +/* CLKCR register clear mask */ +#define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\ + SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\ + SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN)) + +/* --- DCTRL Register ---*/ +/* SDIO DCTRL Clear Mask */ +#define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\ + SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE)) + +/* --- CMD Register ---*/ +/* CMD Register clear mask */ +#define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\ + SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\ + SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND)) + +/* SDIO Initialization Frequency (400KHz max) */ +#define SDIO_INIT_CLK_DIV ((uint8_t)0x76) /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */ + +/* SDIO Data Transfer Frequency (25MHz max) */ +#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0) /* 48MHz / (SDMMC_TRANSFER_CLK_DIV + 2) < 25MHz */ +/** + * @} + */ + +/** @defgroup SDIO_LL_Interrupt_Clock Interrupt And Clock Configuration + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ + +/** + * @brief Enable the SDIO device. + * @param __INSTANCE__: SDIO Instance + * @retval None + */ +#define __SDIO_ENABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE) + +/** + * @brief Disable the SDIO device. + * @param __INSTANCE__: SDIO Instance + * @retval None + */ +#define __SDIO_DISABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE) + +/** + * @brief Enable the SDIO DMA transfer. + * @param __INSTANCE__: SDIO Instance + * @retval None + */ +#define __SDIO_DMA_ENABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE) + +/** + * @brief Disable the SDIO DMA transfer. + * @param __INSTANCE__: SDIO Instance + * @retval None + */ +#define __SDIO_DMA_DISABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE) + +/** + * @brief Enable the SDIO device interrupt. + * @param __INSTANCE__ : Pointer to SDIO register base + * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt + * @retval None + */ +#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) + +/** + * @brief Disable the SDIO device interrupt. + * @param __INSTANCE__ : Pointer to SDIO register base + * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt + * @retval None + */ +#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) + +/** + * @brief Checks whether the specified SDIO flag is set or not. + * @param __INSTANCE__ : Pointer to SDIO register base + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_CMDACT: Command transfer in progress + * @arg SDIO_FLAG_TXACT: Data transmit in progress + * @arg SDIO_FLAG_RXACT: Data receive in progress + * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty + * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full + * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full + * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full + * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty + * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty + * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO + * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO + * @arg SDIO_FLAG_SDIOIT: SDIO interrupt received + * @retval The new state of SDIO_FLAG (SET or RESET). + */ +#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U) + + +/** + * @brief Clears the SDIO pending flags. + * @param __INSTANCE__ : Pointer to SDIO register base + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_SDIOIT: SDIO interrupt received + * @retval None + */ +#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) + +/** + * @brief Checks whether the specified SDIO interrupt has occurred or not. + * @param __INSTANCE__ : Pointer to SDIO register base + * @param __INTERRUPT__: specifies the SDIO interrupt source to check. + * This parameter can be one of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt + * @retval The new state of SDIO_IT (SET or RESET). + */ +#define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Clears the SDIO's interrupt pending bits. + * @param __INSTANCE__ : Pointer to SDIO register base + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt + * @retval None + */ +#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) + +/** + * @brief Enable Start the SD I/O Read Wait operation. + * @param __INSTANCE__ : Pointer to SDIO register base + * @retval None + */ +#define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE) + +/** + * @brief Disable Start the SD I/O Read Wait operations. + * @param __INSTANCE__ : Pointer to SDIO register base + * @retval None + */ +#define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE) + +/** + * @brief Enable Start the SD I/O Read Wait operation. + * @param __INSTANCE__ : Pointer to SDIO register base + * @retval None + */ +#define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE) + +/** + * @brief Disable Stop the SD I/O Read Wait operations. + * @param __INSTANCE__ : Pointer to SDIO register base + * @retval None + */ +#define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE) + +/** + * @brief Enable the SD I/O Mode Operation. + * @param __INSTANCE__ : Pointer to SDIO register base + * @retval None + */ +#define __SDIO_OPERATION_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE) + +/** + * @brief Disable the SD I/O Mode Operation. + * @param __INSTANCE__ : Pointer to SDIO register base + * @retval None + */ +#define __SDIO_OPERATION_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE) + +/** + * @brief Enable the SD I/O Suspend command sending. + * @param __INSTANCE__ : Pointer to SDIO register base + * @retval None + */ +#define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE) + +/** + * @brief Disable the SD I/O Suspend command sending. + * @param __INSTANCE__ : Pointer to SDIO register base + * @retval None + */ +#define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE) + +#if defined(SDIO_CMD_CEATACMD) +/** + * @brief Enable the command completion signal. + * @retval None + */ +#define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE) + +/** + * @brief Disable the command completion signal. + * @retval None + */ +#define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE) + +/** + * @brief Enable the CE-ATA interrupt. + * @retval None + */ +#define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0U) + +/** + * @brief Disable the CE-ATA interrupt. + * @retval None + */ +#define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1U) + +/** + * @brief Enable send CE-ATA command (CMD61). + * @retval None + */ +#define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE) + +/** + * @brief Disable send CE-ATA command (CMD61). + * @retval None + */ +#define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE) + +#endif +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SDMMC_LL_Exported_Functions + * @{ + */ + +/* Initialization/de-initialization functions **********************************/ +/** @addtogroup HAL_SDMMC_LL_Group1 + * @{ + */ +HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init); +/** + * @} + */ + +/* I/O operation functions *****************************************************/ +/** @addtogroup HAL_SDMMC_LL_Group2 + * @{ + */ +uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx); +HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData); +/** + * @} + */ + +/* Peripheral Control functions ************************************************/ +/** @addtogroup HAL_SDMMC_LL_Group3 + * @{ + */ +HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx); +HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx); +uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx); + +/* Command path state machine (CPSM) management functions */ +HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command); +uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx); +uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response); + +/* Data path state machine (DPSM) management functions */ +HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data); +uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx); +uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx); + +/* SDMMC Cards mode management functions */ +HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode); +/** + * @} + */ + +/* SDMMC Commands management functions */ +/** @addtogroup HAL_SDMMC_LL_Group4 + * @{ + */ +uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize); +uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd); +uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd); +uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd); +uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd); +uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd); +uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd); +uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd); +uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd); +uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx); +uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx); +uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr); +uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx); +uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx); +uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument); +uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t Argument); +uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth); +uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx); +uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx); +uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument); +uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA); +uint32_t SDMMC_CmdSetRelAddMmc(SDIO_TypeDef *SDIOx, uint16_t RCA); +uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument); +uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx); +uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument); +uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument); +uint32_t SDMMC_CmdSendEXTCSD(SDIO_TypeDef *SDIOx, uint32_t Argument); +/** + * @} + */ + +/* SDMMC Responses management functions *****************************************/ +/** @addtogroup HAL_SDMMC_LL_Group5 + * @{ + */ +uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout); +uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx); +uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx); +uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA); +uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* SDIO */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F4xx_LL_SDMMC_H */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.c new file mode 100644 index 0000000..433b27a --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.c @@ -0,0 +1,3207 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_mmc.c + * @author MCD Application Team + * @brief MMC card HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Secure Digital (MMC) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + MMC card Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver implements a high level communication layer for read and write from/to + this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by + the user in HAL_MMC_MspInit() function (MSP layer). + Basically, the MSP layer configuration should be the same as we provide in the + examples. + You can easily tailor this configuration according to hardware resources. + + [..] + This driver is a generic layered driver for SDMMC memories which uses the HAL + SDMMC driver functions to interface with MMC and eMMC cards devices. + It is used as follows: + + (#)Initialize the SDMMC low level resources by implement the HAL_MMC_MspInit() API: + (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE(); + (##) SDMMC pins configuration for MMC card + (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init() + and according to your pin assignment; + (##) DMA Configuration if you need to use DMA process (HAL_MMC_ReadBlocks_DMA() + and HAL_MMC_WriteBlocks_DMA() APIs). + (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE(); + (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. + (##) NVIC configuration if you need to use interrupt process when using DMA transfer. + (+++) Configure the SDMMC and DMA interrupt priorities using function HAL_NVIC_SetPriority(); + DMA priority is superior to SDMMC's priority + (+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ() + (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT() + and __HAL_MMC_DISABLE_IT() inside the communication process. + (+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT() + and __HAL_MMC_CLEAR_IT() + (##) NVIC configuration if you need to use interrupt process (HAL_MMC_ReadBlocks_IT() + and HAL_MMC_WriteBlocks_IT() APIs). + (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority(); + (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ() + (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT() + and __HAL_MMC_DISABLE_IT() inside the communication process. + (+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT() + and __HAL_MMC_CLEAR_IT() + (#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization + + + *** MMC Card Initialization and configuration *** + ================================================ + [..] + To initialize the MMC Card, use the HAL_MMC_Init() function. It Initializes + SDMMC Peripheral (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer). + This function provide the following operations: + + (#) Initialize the SDMMC peripheral interface with default configuration. + The initialization process is done at 400KHz. You can change or adapt + this frequency by adjusting the "ClockDiv" field. + The MMC Card frequency (SDMMC_CK) is computed as follows: + + SDMMC_CK = SDMMCCLK / (ClockDiv + 2) + + In initialization mode and according to the MMC Card standard, + make sure that the SDMMC_CK frequency doesn't exceed 400KHz. + + This phase of initialization is done through SDMMC_Init() and + SDMMC_PowerState_ON() SDMMC low level APIs. + + (#) Initialize the MMC card. The API used is HAL_MMC_InitCard(). + This phase allows the card initialization and identification + and check the MMC Card type (Standard Capacity or High Capacity) + The initialization flow is compatible with MMC standard. + + This API (HAL_MMC_InitCard()) could be used also to reinitialize the card in case + of plug-off plug-in. + + (#) Configure the MMC Card Data transfer frequency. By Default, the card transfer + frequency is set to 24MHz. You can change or adapt this frequency by adjusting + the "ClockDiv" field. + In transfer mode and according to the MMC Card standard, make sure that the + SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch. + To be able to use a frequency higher than 24MHz, you should use the SDMMC + peripheral in bypass mode. Refer to the corresponding reference manual + for more details. + + (#) Select the corresponding MMC Card according to the address read with the step 2. + + (#) Configure the MMC Card in wide bus mode: 4-bits data. + + *** MMC Card Read operation *** + ============================== + [..] + (+) You can read from MMC card in polling mode by using function HAL_MMC_ReadBlocks(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + + (+) You can read from MMC card in DMA mode by using function HAL_MMC_ReadBlocks_DMA(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + You could also check the DMA transfer process through the MMC Rx interrupt event. + + (+) You can read from MMC card in Interrupt mode by using function HAL_MMC_ReadBlocks_IT(). + This function allows the read of 512 bytes blocks. + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + You could also check the IT transfer process through the MMC Rx interrupt event. + + *** MMC Card Write operation *** + =============================== + [..] + (+) You can write to MMC card in polling mode by using function HAL_MMC_WriteBlocks(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + + (+) You can write to MMC card in DMA mode by using function HAL_MMC_WriteBlocks_DMA(). + This function support only 512-bytes block length (the block size should be + chosen as 512 byte). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + You could also check the DMA transfer process through the MMC Tx interrupt event. + + (+) You can write to MMC card in Interrupt mode by using function HAL_MMC_WriteBlocks_IT(). + This function allows the read of 512 bytes blocks. + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + You could also check the IT transfer process through the MMC Tx interrupt event. + + *** MMC card information *** + =========================== + [..] + (+) To get MMC card information, you can use the function HAL_MMC_GetCardInfo(). + It returns useful information about the MMC card such as block size, card type, + block number ... + + *** MMC card CSD register *** + ============================ + [..] + (+) The HAL_MMC_GetCardCSD() API allows to get the parameters of the CSD register. + Some of the CSD parameters are useful for card initialization and identification. + + *** MMC card CID register *** + ============================ + [..] + (+) The HAL_MMC_GetCardCID() API allows to get the parameters of the CID register. + Some of the CID parameters are useful for card initialization and identification. + + *** MMC HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in MMC HAL driver. + + (+) __HAL_MMC_ENABLE : Enable the MMC device + (+) __HAL_MMC_DISABLE : Disable the MMC device + (+) __HAL_MMC_DMA_ENABLE: Enable the SDMMC DMA transfer + (+) __HAL_MMC_DMA_DISABLE: Disable the SDMMC DMA transfer + (+) __HAL_MMC_ENABLE_IT: Enable the MMC device interrupt + (+) __HAL_MMC_DISABLE_IT: Disable the MMC device interrupt + (+) __HAL_MMC_GET_FLAG:Check whether the specified MMC flag is set or not + (+) __HAL_MMC_CLEAR_FLAG: Clear the MMC's pending flags + + [..] + (@) You can refer to the MMC HAL driver header file for more useful macros + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_MMC_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions HAL_MMC_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) MspInitCallback : MMC MspInit. + (+) MspDeInitCallback : MMC MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function HAL_MMC_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. It allows to reset following callbacks: + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) MspInitCallback : MMC MspInit. + (+) MspDeInitCallback : MMC MspDeInit. + This function) takes as parameters the HAL peripheral handle and the Callback ID. + + By default, after the HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the HAL_MMC_Init + and HAL_MMC_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_MMC_Init and HAL_MMC_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_MMC_RegisterCallback before calling HAL_MMC_DeInit + or HAL_MMC_Init function. + + When The compilation define USE_HAL_MMC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup MMC MMC + * @brief MMC HAL module driver + * @{ + */ + +#ifdef HAL_MMC_MODULE_ENABLED + +#if defined(SDIO) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup MMC_Private_Defines + * @{ + */ +#if defined (VDD_VALUE) && (VDD_VALUE <= 1950U) +#define MMC_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE + +#define MMC_EXT_CSD_PWR_CL_26_INDEX 201 +#define MMC_EXT_CSD_PWR_CL_52_INDEX 200 +#define MMC_EXT_CSD_PWR_CL_DDR_52_INDEX 238 + +#define MMC_EXT_CSD_PWR_CL_26_POS 8 +#define MMC_EXT_CSD_PWR_CL_52_POS 0 +#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 16 +#else +#define MMC_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE + +#define MMC_EXT_CSD_PWR_CL_26_INDEX 203 +#define MMC_EXT_CSD_PWR_CL_52_INDEX 202 +#define MMC_EXT_CSD_PWR_CL_DDR_52_INDEX 239 + +#define MMC_EXT_CSD_PWR_CL_26_POS 24 +#define MMC_EXT_CSD_PWR_CL_52_POS 16 +#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 24 +#endif + +/* Frequencies used in the driver for clock divider calculation */ +#define MMC_INIT_FREQ 400000U /* Initialization phase : 400 kHz max */ +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup MMC_Private_Functions MMC Private Functions + * @{ + */ +static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc); +static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc); +static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus); +static uint32_t MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout); +static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc); +static void MMC_Write_IT(MMC_HandleTypeDef *hmmc); +static void MMC_Read_IT(MMC_HandleTypeDef *hmmc); +static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void MMC_DMAError(DMA_HandleTypeDef *hdma); +static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma); +static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma); +static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide); +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup MMC_Exported_Functions + * @{ + */ + +/** @addtogroup MMC_Exported_Functions_Group1 + * @brief Initialization and de-initialization functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to initialize/de-initialize the MMC + card device to be ready for use. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the MMC according to the specified parameters in the + MMC_HandleTypeDef and create the associated handle. + * @param hmmc: Pointer to the MMC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) +{ + /* Check the MMC handle allocation */ + if(hmmc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SDIO_ALL_INSTANCE(hmmc->Instance)); + assert_param(IS_SDIO_CLOCK_EDGE(hmmc->Init.ClockEdge)); + assert_param(IS_SDIO_CLOCK_BYPASS(hmmc->Init.ClockBypass)); + assert_param(IS_SDIO_CLOCK_POWER_SAVE(hmmc->Init.ClockPowerSave)); + assert_param(IS_SDIO_BUS_WIDE(hmmc->Init.BusWide)); + assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(hmmc->Init.HardwareFlowControl)); + assert_param(IS_SDIO_CLKDIV(hmmc->Init.ClockDiv)); + + if(hmmc->State == HAL_MMC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hmmc->Lock = HAL_UNLOCKED; +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + /* Reset Callback pointers in HAL_MMC_STATE_RESET only */ + hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback; + hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback; + hmmc->ErrorCallback = HAL_MMC_ErrorCallback; + hmmc->AbortCpltCallback = HAL_MMC_AbortCallback; + + if(hmmc->MspInitCallback == NULL) + { + hmmc->MspInitCallback = HAL_MMC_MspInit; + } + + /* Init the low level hardware */ + hmmc->MspInitCallback(hmmc); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_MMC_MspInit(hmmc); +#endif + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize the Card parameters */ + if(HAL_MMC_InitCard(hmmc) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* Initialize the error code */ + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + /* Initialize the MMC operation */ + hmmc->Context = MMC_CONTEXT_NONE; + + /* Initialize the MMC state */ + hmmc->State = HAL_MMC_STATE_READY; + + /* Configure bus width */ + if (hmmc->Init.BusWide != SDIO_BUS_WIDE_1B) + { + if (HAL_MMC_ConfigWideBusOperation(hmmc, hmmc->Init.BusWide) != HAL_OK) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Initializes the MMC Card. + * @param hmmc: Pointer to MMC handle + * @note This function initializes the MMC card. It could be used when a card + re-initialization is needed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) +{ + uint32_t errorstate; + MMC_InitTypeDef Init; + HAL_StatusTypeDef status; + + /* Default SDIO peripheral configuration for MMC card initialization */ + Init.ClockEdge = SDIO_CLOCK_EDGE_RISING; + Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; + Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; + Init.BusWide = SDIO_BUS_WIDE_1B; + Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; + Init.ClockDiv = SDIO_INIT_CLK_DIV; + + /* Initialize SDIO peripheral interface with default configuration */ + status = SDIO_Init(hmmc->Instance, Init); + if(status == HAL_ERROR) + { + return HAL_ERROR; + } + + /* Disable SDIO Clock */ + __HAL_MMC_DISABLE(hmmc); + + /* Set Power State to ON */ + status = SDIO_PowerState_ON(hmmc->Instance); + if(status == HAL_ERROR) + { + return HAL_ERROR; + } + + /* Enable MMC Clock */ + __HAL_MMC_ENABLE(hmmc); + + /* Required power up waiting time before starting the MMC initialization sequence */ + HAL_Delay(2); + + /* Identify card operating voltage */ + errorstate = MMC_PowerON(hmmc); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->State = HAL_MMC_STATE_READY; + hmmc->ErrorCode |= errorstate; + return HAL_ERROR; + } + + /* Card initialization */ + errorstate = MMC_InitCard(hmmc); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->State = HAL_MMC_STATE_READY; + hmmc->ErrorCode |= errorstate; + return HAL_ERROR; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief De-Initializes the MMC card. + * @param hmmc: Pointer to MMC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc) +{ + /* Check the MMC handle allocation */ + if(hmmc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SDIO_ALL_INSTANCE(hmmc->Instance)); + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Set MMC power state to off */ + MMC_PowerOFF(hmmc); + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + if(hmmc->MspDeInitCallback == NULL) + { + hmmc->MspDeInitCallback = HAL_MMC_MspDeInit; + } + + /* DeInit the low level hardware */ + hmmc->MspDeInitCallback(hmmc); +#else + /* De-Initialize the MSP layer */ + HAL_MMC_MspDeInit(hmmc); +#endif + + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_RESET; + + return HAL_OK; +} + + +/** + * @brief Initializes the MMC MSP. + * @param hmmc: Pointer to MMC handle + * @retval None + */ +__weak void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MMC_MspInit could be implemented in the user file + */ +} + +/** + * @brief De-Initialize MMC MSP. + * @param hmmc: Pointer to MMC handle + * @retval None + */ +__weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MMC_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @addtogroup MMC_Exported_Functions_Group2 + * @brief Data transfer functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the data + transfer from/to MMC card. + +@endverbatim + * @{ + */ + +/** + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed by polling mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @param hmmc: Pointer to MMC handle + * @param pData: pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of MMC blocks to read + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) +{ + SDIO_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count, data, dataremaining; + uint32_t add = BlockAdd; + uint8_t *tempbuff = pData; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + add *= 512U; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + (void)SDIO_ConfigData(hmmc->Instance, &config); + + /* Read block(s) in polling mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add); + } + else + { + hmmc->Context = MMC_CONTEXT_READ_SINGLE_BLOCK; + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add); + } + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Poll on SDIO flags */ + dataremaining = config.DataLength; +#if defined(SDIO_STA_STBITERR) + while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR)) +#else /* SDIO_STA_STBITERR not defined */ + while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND)) +#endif /* SDIO_STA_STBITERR */ + { + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXFIFOHF) && (dataremaining > 0U)) + { + /* Read data from SDIO Rx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = SDIO_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + dataremaining--; + } + } + + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State= HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + + /* Send stop transmission command in case of multiblock read */ + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + { + /* Send stop transmission command */ + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + } + + /* Get error state */ + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Empty FIFO if there is still any data */ + while ((__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXDAVL)) && (dataremaining > 0U)) + { + data = SDIO_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + dataremaining--; + + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State= HAL_MMC_STATE_READY; + return HAL_ERROR; + } + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Allows to write block(s) to a specified address in a card. The Data + * transfer is managed by polling mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @param hmmc: Pointer to MMC handle + * @param pData: pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of MMC blocks to write + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) +{ + SDIO_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count, data, dataremaining; + uint32_t add = BlockAdd; + uint8_t *tempbuff = pData; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + add *= 512U; + } + + /* Write Blocks in Polling mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add); + } + else + { + hmmc->Context = MMC_CONTEXT_WRITE_SINGLE_BLOCK; + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add); + } + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + (void)SDIO_ConfigData(hmmc->Instance, &config); + + /* Write block(s) in polling mode */ + dataremaining = config.DataLength; +#if defined(SDIO_STA_STBITERR) + while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR)) +#else /* SDIO_STA_STBITERR not defined */ + while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND)) +#endif /* SDIO_STA_STBITERR */ + { + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXFIFOHE) && (dataremaining > 0U)) + { + /* Write data to SDIO Tx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = (uint32_t)(*tempbuff); + tempbuff++; + dataremaining--; + data |= ((uint32_t)(*tempbuff) << 8U); + tempbuff++; + dataremaining--; + data |= ((uint32_t)(*tempbuff) << 16U); + tempbuff++; + dataremaining--; + data |= ((uint32_t)(*tempbuff) << 24U); + tempbuff++; + dataremaining--; + (void)SDIO_WriteFIFO(hmmc->Instance, &data); + } + } + + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + + /* Send stop transmission command in case of multiblock write */ + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + { + /* Send stop transmission command */ + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + } + + /* Get error state */ + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed in interrupt mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @note You could also check the IT transfer process through the MMC Rx + * interrupt event. + * @param hmmc: Pointer to MMC handle + * @param pData: Pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of blocks to read. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDIO_DataInitTypeDef config; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + hmmc->pRxBuffPtr = pData; + hmmc->RxXferSize = MMC_BLOCKSIZE * NumberOfBlocks; + +#if defined(SDIO_STA_STBITERR) + __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_FLAG_RXFIFOHF | SDIO_IT_STBITERR)); +#else /* SDIO_STA_STBITERR not defined */ + __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_FLAG_RXFIFOHF)); +#endif /* SDIO_STA_STBITERR */ + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + add *= 512U; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + (void)SDIO_ConfigData(hmmc->Instance, &config); + + /* Read Blocks in IT mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_IT); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add); + } + else + { + hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_IT); + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add); + } + + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Writes block(s) to a specified address in a card. The Data transfer + * is managed in interrupt mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @note You could also check the IT transfer process through the MMC Tx + * interrupt event. + * @param hmmc: Pointer to MMC handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDIO_DataInitTypeDef config; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + hmmc->pTxBuffPtr = pData; + hmmc->TxXferSize = MMC_BLOCKSIZE * NumberOfBlocks; + + /* Enable transfer interrupts */ +#if defined(SDIO_STA_STBITERR) + __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE | SDIO_IT_STBITERR)); +#else /* SDIO_STA_STBITERR not defined */ + __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE)); +#endif /* SDIO_STA_STBITERR */ + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + add *= 512U; + } + + /* Write Blocks in Polling mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK| MMC_CONTEXT_IT); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add); + } + else + { + hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_IT); + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add); + } + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + (void)SDIO_ConfigData(hmmc->Instance, &config); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed by DMA mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @note You could also check the DMA transfer process through the MMC Rx + * interrupt event. + * @param hmmc: Pointer MMC handle + * @param pData: Pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of blocks to read. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDIO_DataInitTypeDef config; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + +#if defined(SDIO_STA_STBITERR) + __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_IT_STBITERR)); +#else /* SDIO_STA_STBITERR not defined */ + __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND)); +#endif /* SDIO_STA_STBITERR */ + + /* Set the DMA transfer complete callback */ + hmmc->hdmarx->XferCpltCallback = MMC_DMAReceiveCplt; + + /* Set the DMA error callback */ + hmmc->hdmarx->XferErrorCallback = MMC_DMAError; + + /* Set the DMA Abort callback */ + hmmc->hdmarx->XferAbortCallback = NULL; + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + add *= 512U; + } + + /* Force DMA Direction */ + hmmc->hdmarx->Init.Direction = DMA_PERIPH_TO_MEMORY; + MODIFY_REG(hmmc->hdmarx->Instance->CR, DMA_SxCR_DIR, hmmc->hdmarx->Init.Direction); + + /* Enable the DMA Channel */ + if(HAL_DMA_Start_IT(hmmc->hdmarx, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)pData, (uint32_t)(MMC_BLOCKSIZE * NumberOfBlocks)/4) != HAL_OK) + { + __HAL_MMC_DISABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND)); + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode = HAL_MMC_ERROR_DMA; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Enable MMC DMA transfer */ + __HAL_MMC_DMA_ENABLE(hmmc); + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + (void)SDIO_ConfigData(hmmc->Instance, &config); + + /* Read Blocks in DMA mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add); + } + else + { + hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_DMA); + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add); + } + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + __HAL_MMC_DISABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND)); + hmmc->ErrorCode = errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Writes block(s) to a specified address in a card. The Data transfer + * is managed by DMA mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @note You could also check the DMA transfer process through the MMC Tx + * interrupt event. + * @param hmmc: Pointer to MMC handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDIO_DataInitTypeDef config; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + /* Enable MMC Error interrupts */ +#if defined(SDIO_STA_STBITERR) + __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR)); +#else /* SDIO_STA_STBITERR not defined */ + __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR)); +#endif /* SDIO_STA_STBITERR */ + + /* Set the DMA transfer complete callback */ + hmmc->hdmatx->XferCpltCallback = MMC_DMATransmitCplt; + + /* Set the DMA error callback */ + hmmc->hdmatx->XferErrorCallback = MMC_DMAError; + + /* Set the DMA Abort callback */ + hmmc->hdmatx->XferAbortCallback = NULL; + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + add *= 512U; + } + + + /* Write Blocks in Polling mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add); + } + else + { + hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_DMA); + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add); + } + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + __HAL_MMC_DISABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND)); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Enable SDIO DMA transfer */ + __HAL_MMC_DMA_ENABLE(hmmc); + + /* Force DMA Direction */ + hmmc->hdmatx->Init.Direction = DMA_MEMORY_TO_PERIPH; + MODIFY_REG(hmmc->hdmatx->Instance->CR, DMA_SxCR_DIR, hmmc->hdmatx->Init.Direction); + + /* Enable the DMA Channel */ + if(HAL_DMA_Start_IT(hmmc->hdmatx, (uint32_t)pData, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)(MMC_BLOCKSIZE * NumberOfBlocks)/4) != HAL_OK) + { + __HAL_MMC_DISABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND)); + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DMA; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + (void)SDIO_ConfigData(hmmc->Instance, &config); + + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Erases the specified memory area of the given MMC card. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @param hmmc: Pointer to MMC handle + * @param BlockStartAdd: Start Block address + * @param BlockEndAdd: End Block address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd) +{ + uint32_t errorstate; + uint32_t start_add = BlockStartAdd; + uint32_t end_add = BlockEndAdd; + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + if(end_add < start_add) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(end_add > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Check if the card command class supports erase command */ + if(((hmmc->MmcCard.Class) & SDIO_CCCC_ERASE) == 0U) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + if((SDIO_GetResponse(hmmc->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_LOCK_UNLOCK_FAILED; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + start_add *= 512U; + end_add *= 512U; + } + + /* Send CMD35 MMC_ERASE_GRP_START with argument as addr */ + errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, start_add); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Send CMD36 MMC_ERASE_GRP_END with argument as addr */ + errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, end_add); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Send CMD38 ERASE */ + errorstate = SDMMC_CmdErase(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief This function handles MMC card interrupt request. + * @param hmmc: Pointer to MMC handle + * @retval None + */ +void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) +{ + uint32_t errorstate; + uint32_t context = hmmc->Context; + + /* Check for SDIO interrupt flags */ + if((__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXFIFOHF) != RESET) && ((context & MMC_CONTEXT_IT) != 0U)) + { + MMC_Read_IT(hmmc); + } + + else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DATAEND) != RESET) + { + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_FLAG_DATAEND); + +#if defined(SDIO_STA_STBITERR) + __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\ + SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR | SDIO_IT_STBITERR); +#else /* SDIO_STA_STBITERR not defined */ + __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT |\ + SDIO_IT_TXUNDERR | SDIO_IT_RXOVERR | SDIO_IT_TXFIFOHE |\ + SDIO_IT_RXFIFOHF); +#endif /* SDIO_STA_STBITERR */ + + hmmc->Instance->DCTRL &= ~(SDIO_DCTRL_DTEN); + + if((context & MMC_CONTEXT_DMA) != 0U) + { + if((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) + { + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->ErrorCallback(hmmc); +#else + HAL_MMC_ErrorCallback(hmmc); +#endif + } + } + if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) == 0U) && ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) == 0U)) + { + /* Disable the DMA transfer for transmit request by setting the DMAEN bit + in the MMC DCTRL register */ + hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN); + + hmmc->State = HAL_MMC_STATE_READY; + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->TxCpltCallback(hmmc); +#else + HAL_MMC_TxCpltCallback(hmmc); +#endif + } + } + else if((context & MMC_CONTEXT_IT) != 0U) + { + /* Stop Transfer for Write Multi blocks or Read Multi blocks */ + if(((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + { + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->ErrorCallback(hmmc); +#else + HAL_MMC_ErrorCallback(hmmc); +#endif + } + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->RxCpltCallback(hmmc); +#else + HAL_MMC_RxCpltCallback(hmmc); +#endif + } + else + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->TxCpltCallback(hmmc); +#else + HAL_MMC_TxCpltCallback(hmmc); +#endif + } + } + else + { + /* Nothing to do */ + } + } + + else if((__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXFIFOHE) != RESET) && ((context & MMC_CONTEXT_IT) != 0U)) + { + MMC_Write_IT(hmmc); + } + +#if defined(SDIO_STA_STBITERR) + else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_RXOVERR | SDIO_FLAG_TXUNDERR | SDIO_FLAG_STBITERR) != RESET) +#else /* SDIO_STA_STBITERR not defined */ + else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_RXOVERR | SDIO_FLAG_TXUNDERR) != RESET) +#endif /* SDIO_STA_STBITERR */ + { + /* Set Error code */ + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DCRCFAIL) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + } + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DTIMEOUT) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + } + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN; + } + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXUNDERR) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + } +#if defined(SDIO_STA_STBITERR) + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_STBITERR) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + } +#endif /* SDIO_STA_STBITERR */ + +#if defined(SDIO_STA_STBITERR) + /* Clear All flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS | SDIO_FLAG_STBITERR); + + /* Disable all interrupts */ + __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\ + SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR | SDIO_IT_STBITERR); +#else /* SDIO_STA_STBITERR */ + /* Clear All flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS); + + /* Disable all interrupts */ + __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\ + SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR); +#endif /* SDIO_STA_STBITERR */ + + hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance); + + if((context & MMC_CONTEXT_IT) != 0U) + { + /* Set the MMC state to ready to be able to start again the process */ + hmmc->State = HAL_MMC_STATE_READY; +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->ErrorCallback(hmmc); +#else + HAL_MMC_ErrorCallback(hmmc); +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ + } + else if((context & MMC_CONTEXT_DMA) != 0U) + { + /* Abort the MMC DMA Streams */ + if(((context & MMC_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + { + if(hmmc->hdmatx != NULL) + { + /* Set the DMA Tx abort callback */ + hmmc->hdmatx->XferAbortCallback = MMC_DMATxAbort; + /* Abort DMA in IT mode */ + if(HAL_DMA_Abort_IT(hmmc->hdmatx) != HAL_OK) + { + MMC_DMATxAbort(hmmc->hdmatx); + } + } + } + else if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + { + if(hmmc->hdmarx != NULL) + { + /* Set the DMA Rx abort callback */ + hmmc->hdmarx->XferAbortCallback = MMC_DMARxAbort; + /* Abort DMA in IT mode */ + if(HAL_DMA_Abort_IT(hmmc->hdmarx) != HAL_OK) + { + MMC_DMARxAbort(hmmc->hdmarx); + } + } + } + else + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_READY; +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->AbortCpltCallback(hmmc); +#else + HAL_MMC_AbortCallback(hmmc); +#endif + } + } + else + { + /* Nothing to do */ + } + } + + else + { + /* Nothing to do */ + } +} + +/** + * @brief return the MMC state + * @param hmmc: Pointer to mmc handle + * @retval HAL state + */ +HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc) +{ + return hmmc->State; +} + +/** +* @brief Return the MMC error code +* @param hmmc : Pointer to a MMC_HandleTypeDef structure that contains + * the configuration information. +* @retval MMC Error Code +*/ +uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc) +{ + return hmmc->ErrorCode; +} + +/** + * @brief Tx Transfer completed callbacks + * @param hmmc: Pointer to MMC handle + * @retval None + */ +__weak void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMC_TxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks + * @param hmmc: Pointer MMC handle + * @retval None + */ +__weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMC_RxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief MMC error callbacks + * @param hmmc: Pointer MMC handle + * @retval None + */ +__weak void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMC_ErrorCallback can be implemented in the user file + */ +} + +/** + * @brief MMC Abort callbacks + * @param hmmc: Pointer MMC handle + * @retval None + */ +__weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMC_AbortCallback can be implemented in the user file + */ +} + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User MMC Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hmmc : MMC handle + * @param CallbackId : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID + * @arg @ref HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID + * @arg @ref HAL_MMC_ERROR_CB_ID MMC Error Callback ID + * @arg @ref HAL_MMC_ABORT_CB_ID MMC Abort Callback ID + * @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID + * @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmmc); + + if(hmmc->State == HAL_MMC_STATE_READY) + { + switch (CallbackId) + { + case HAL_MMC_TX_CPLT_CB_ID : + hmmc->TxCpltCallback = pCallback; + break; + case HAL_MMC_RX_CPLT_CB_ID : + hmmc->RxCpltCallback = pCallback; + break; + case HAL_MMC_ERROR_CB_ID : + hmmc->ErrorCallback = pCallback; + break; + case HAL_MMC_ABORT_CB_ID : + hmmc->AbortCpltCallback = pCallback; + break; + case HAL_MMC_MSP_INIT_CB_ID : + hmmc->MspInitCallback = pCallback; + break; + case HAL_MMC_MSP_DEINIT_CB_ID : + hmmc->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hmmc->State == HAL_MMC_STATE_RESET) + { + switch (CallbackId) + { + case HAL_MMC_MSP_INIT_CB_ID : + hmmc->MspInitCallback = pCallback; + break; + case HAL_MMC_MSP_DEINIT_CB_ID : + hmmc->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hmmc); + return status; +} + +/** + * @brief Unregister a User MMC Callback + * MMC Callback is redirected to the weak (surcharged) predefined callback + * @param hmmc : MMC handle + * @param CallbackId : ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID + * @arg @ref HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID + * @arg @ref HAL_MMC_ERROR_CB_ID MMC Error Callback ID + * @arg @ref HAL_MMC_ABORT_CB_ID MMC Abort Callback ID + * @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID + * @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hmmc); + + if(hmmc->State == HAL_MMC_STATE_READY) + { + switch (CallbackId) + { + case HAL_MMC_TX_CPLT_CB_ID : + hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback; + break; + case HAL_MMC_RX_CPLT_CB_ID : + hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback; + break; + case HAL_MMC_ERROR_CB_ID : + hmmc->ErrorCallback = HAL_MMC_ErrorCallback; + break; + case HAL_MMC_ABORT_CB_ID : + hmmc->AbortCpltCallback = HAL_MMC_AbortCallback; + break; + case HAL_MMC_MSP_INIT_CB_ID : + hmmc->MspInitCallback = HAL_MMC_MspInit; + break; + case HAL_MMC_MSP_DEINIT_CB_ID : + hmmc->MspDeInitCallback = HAL_MMC_MspDeInit; + break; + default : + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hmmc->State == HAL_MMC_STATE_RESET) + { + switch (CallbackId) + { + case HAL_MMC_MSP_INIT_CB_ID : + hmmc->MspInitCallback = HAL_MMC_MspInit; + break; + case HAL_MMC_MSP_DEINIT_CB_ID : + hmmc->MspDeInitCallback = HAL_MMC_MspDeInit; + break; + default : + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hmmc); + return status; +} +#endif + +/** + * @} + */ + +/** @addtogroup MMC_Exported_Functions_Group3 + * @brief management functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the MMC card + operations and get the related information + +@endverbatim + * @{ + */ + +/** + * @brief Returns information the information of the card which are stored on + * the CID register. + * @param hmmc: Pointer to MMC handle + * @param pCID: Pointer to a HAL_MMC_CIDTypedef structure that + * contains all CID register parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID) +{ + pCID->ManufacturerID = (uint8_t)((hmmc->CID[0] & 0xFF000000U) >> 24U); + + pCID->OEM_AppliID = (uint16_t)((hmmc->CID[0] & 0x00FFFF00U) >> 8U); + + pCID->ProdName1 = (((hmmc->CID[0] & 0x000000FFU) << 24U) | ((hmmc->CID[1] & 0xFFFFFF00U) >> 8U)); + + pCID->ProdName2 = (uint8_t)(hmmc->CID[1] & 0x000000FFU); + + pCID->ProdRev = (uint8_t)((hmmc->CID[2] & 0xFF000000U) >> 24U); + + pCID->ProdSN = (((hmmc->CID[2] & 0x00FFFFFFU) << 8U) | ((hmmc->CID[3] & 0xFF000000U) >> 24U)); + + pCID->Reserved1 = (uint8_t)((hmmc->CID[3] & 0x00F00000U) >> 20U); + + pCID->ManufactDate = (uint16_t)((hmmc->CID[3] & 0x000FFF00U) >> 8U); + + pCID->CID_CRC = (uint8_t)((hmmc->CID[3] & 0x000000FEU) >> 1U); + + pCID->Reserved2 = 1U; + + return HAL_OK; +} + +/** + * @brief Returns information the information of the card which are stored on + * the CSD register. + * @param hmmc: Pointer to MMC handle + * @param pCSD: Pointer to a HAL_MMC_CardCSDTypeDef structure that + * contains all CSD register parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD) +{ + uint32_t block_nbr = 0; + + pCSD->CSDStruct = (uint8_t)((hmmc->CSD[0] & 0xC0000000U) >> 30U); + + pCSD->SysSpecVersion = (uint8_t)((hmmc->CSD[0] & 0x3C000000U) >> 26U); + + pCSD->Reserved1 = (uint8_t)((hmmc->CSD[0] & 0x03000000U) >> 24U); + + pCSD->TAAC = (uint8_t)((hmmc->CSD[0] & 0x00FF0000U) >> 16U); + + pCSD->NSAC = (uint8_t)((hmmc->CSD[0] & 0x0000FF00U) >> 8U); + + pCSD->MaxBusClkFrec = (uint8_t)(hmmc->CSD[0] & 0x000000FFU); + + pCSD->CardComdClasses = (uint16_t)((hmmc->CSD[1] & 0xFFF00000U) >> 20U); + + pCSD->RdBlockLen = (uint8_t)((hmmc->CSD[1] & 0x000F0000U) >> 16U); + + pCSD->PartBlockRead = (uint8_t)((hmmc->CSD[1] & 0x00008000U) >> 15U); + + pCSD->WrBlockMisalign = (uint8_t)((hmmc->CSD[1] & 0x00004000U) >> 14U); + + pCSD->RdBlockMisalign = (uint8_t)((hmmc->CSD[1] & 0x00002000U) >> 13U); + + pCSD->DSRImpl = (uint8_t)((hmmc->CSD[1] & 0x00001000U) >> 12U); + + pCSD->Reserved2 = 0U; /*!< Reserved */ + + pCSD->DeviceSize = (((hmmc->CSD[1] & 0x000003FFU) << 2U) | ((hmmc->CSD[2] & 0xC0000000U) >> 30U)); + + pCSD->MaxRdCurrentVDDMin = (uint8_t)((hmmc->CSD[2] & 0x38000000U) >> 27U); + + pCSD->MaxRdCurrentVDDMax = (uint8_t)((hmmc->CSD[2] & 0x07000000U) >> 24U); + + pCSD->MaxWrCurrentVDDMin = (uint8_t)((hmmc->CSD[2] & 0x00E00000U) >> 21U); + + pCSD->MaxWrCurrentVDDMax = (uint8_t)((hmmc->CSD[2] & 0x001C0000U) >> 18U); + + pCSD->DeviceSizeMul = (uint8_t)((hmmc->CSD[2] & 0x00038000U) >> 15U); + + if(MMC_ReadExtCSD(hmmc, &block_nbr, 212, 0x0FFFFFFFU) != HAL_OK) /* Field SEC_COUNT [215:212] */ + { + return HAL_ERROR; + } + + if(hmmc->MmcCard.CardType == MMC_LOW_CAPACITY_CARD) + { + hmmc->MmcCard.BlockNbr = (pCSD->DeviceSize + 1U) ; + hmmc->MmcCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); + hmmc->MmcCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); + hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U); + hmmc->MmcCard.LogBlockSize = 512U; + } + else if(hmmc->MmcCard.CardType == MMC_HIGH_CAPACITY_CARD) + { + hmmc->MmcCard.BlockNbr = block_nbr; + hmmc->MmcCard.LogBlockNbr = hmmc->MmcCard.BlockNbr; + hmmc->MmcCard.BlockSize = 512U; + hmmc->MmcCard.LogBlockSize = hmmc->MmcCard.BlockSize; + } + else + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + pCSD->EraseGrSize = (uint8_t)((hmmc->CSD[2] & 0x00004000U) >> 14U); + + pCSD->EraseGrMul = (uint8_t)((hmmc->CSD[2] & 0x00003F80U) >> 7U); + + pCSD->WrProtectGrSize = (uint8_t)(hmmc->CSD[2] & 0x0000007FU); + + pCSD->WrProtectGrEnable = (uint8_t)((hmmc->CSD[3] & 0x80000000U) >> 31U); + + pCSD->ManDeflECC = (uint8_t)((hmmc->CSD[3] & 0x60000000U) >> 29U); + + pCSD->WrSpeedFact = (uint8_t)((hmmc->CSD[3] & 0x1C000000U) >> 26U); + + pCSD->MaxWrBlockLen= (uint8_t)((hmmc->CSD[3] & 0x03C00000U) >> 22U); + + pCSD->WriteBlockPaPartial = (uint8_t)((hmmc->CSD[3] & 0x00200000U) >> 21U); + + pCSD->Reserved3 = 0; + + pCSD->ContentProtectAppli = (uint8_t)((hmmc->CSD[3] & 0x00010000U) >> 16U); + + pCSD->FileFormatGroup = (uint8_t)((hmmc->CSD[3] & 0x00008000U) >> 15U); + + pCSD->CopyFlag = (uint8_t)((hmmc->CSD[3] & 0x00004000U) >> 14U); + + pCSD->PermWrProtect = (uint8_t)((hmmc->CSD[3] & 0x00002000U) >> 13U); + + pCSD->TempWrProtect = (uint8_t)((hmmc->CSD[3] & 0x00001000U) >> 12U); + + pCSD->FileFormat = (uint8_t)((hmmc->CSD[3] & 0x00000C00U) >> 10U); + + pCSD->ECC= (uint8_t)((hmmc->CSD[3] & 0x00000300U) >> 8U); + + pCSD->CSD_CRC = (uint8_t)((hmmc->CSD[3] & 0x000000FEU) >> 1U); + + pCSD->Reserved4 = 1; + + return HAL_OK; +} + +/** + * @brief Gets the MMC card info. + * @param hmmc: Pointer to MMC handle + * @param pCardInfo: Pointer to the HAL_MMC_CardInfoTypeDef structure that + * will contain the MMC card status information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo) +{ + pCardInfo->CardType = (uint32_t)(hmmc->MmcCard.CardType); + pCardInfo->Class = (uint32_t)(hmmc->MmcCard.Class); + pCardInfo->RelCardAdd = (uint32_t)(hmmc->MmcCard.RelCardAdd); + pCardInfo->BlockNbr = (uint32_t)(hmmc->MmcCard.BlockNbr); + pCardInfo->BlockSize = (uint32_t)(hmmc->MmcCard.BlockSize); + pCardInfo->LogBlockNbr = (uint32_t)(hmmc->MmcCard.LogBlockNbr); + pCardInfo->LogBlockSize = (uint32_t)(hmmc->MmcCard.LogBlockSize); + + return HAL_OK; +} + +/** + * @brief Returns information the information of the card which are stored on + * the Extended CSD register. + * @param hmmc Pointer to MMC handle + * @param pExtCSD Pointer to a memory area (512 bytes) that contains all + * Extended CSD register parameters + * @param Timeout Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout) +{ + SDIO_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t *tmp_buf; + + if(NULL == pExtCSD) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0; + + /* Initiaize the destination pointer */ + tmp_buf = pExtCSD; + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = 512; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + (void)SDIO_ConfigData(hmmc->Instance, &config); + + /* Send ExtCSD Read command to Card */ + errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Poll on SDMMC flags */ + while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND)) + { + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXFIFOHF)) + { + /* Read data from SDMMC Rx FIFO */ + for(count = 0U; count < 8U; count++) + { + *tmp_buf = SDIO_ReadFIFO(hmmc->Instance); + tmp_buf++; + } + } + + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State= HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + + /* Get error state */ + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS); + hmmc->State = HAL_MMC_STATE_READY; + } + + return HAL_OK; +} + +/** + * @brief Enables wide bus operation for the requested card if supported by + * card. + * @param hmmc: Pointer to MMC handle + * @param WideMode: Specifies the MMC card wide bus mode + * This parameter can be one of the following values: + * @arg SDIO_BUS_WIDE_8B: 8-bit data transfer + * @arg SDIO_BUS_WIDE_4B: 4-bit data transfer + * @arg SDIO_BUS_WIDE_1B: 1-bit data transfer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode) +{ + uint32_t count; + SDIO_InitTypeDef Init; + uint32_t errorstate; + uint32_t response = 0U; + + /* Check the parameters */ + assert_param(IS_SDIO_BUS_WIDE(WideMode)); + + /* Change State */ + hmmc->State = HAL_MMC_STATE_BUSY; + + errorstate = MMC_PwrClassUpdate(hmmc, WideMode); + + if(errorstate == HAL_MMC_ERROR_NONE) + { + if(WideMode == SDIO_BUS_WIDE_8B) + { + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U); + } + else if(WideMode == SDIO_BUS_WIDE_4B) + { + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U); + } + else if(WideMode == SDIO_BUS_WIDE_1B) + { + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U); + } + else + { + /* WideMode is not a valid argument*/ + errorstate = HAL_MMC_ERROR_PARAM; + } + + /* Check for switch error and violation of the trial number of sending CMD 13 */ + if(errorstate == HAL_MMC_ERROR_NONE) + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1); + count--; + }while(((response & 0x100U) == 0U) && (count != 0U)); + + /* Check the status after the switch command execution */ + if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } + else + { + /* Configure the SDIO peripheral */ + Init = hmmc->Init; + Init.BusWide = WideMode; + (void)SDIO_Init(hmmc->Instance, Init); + } + } + else if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else + { + /* Nothing to do */ + } + } + } + + /* Change State */ + hmmc->State = HAL_MMC_STATE_READY; + + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Gets the current mmc card data state. + * @param hmmc: pointer to MMC handle + * @retval Card state + */ +HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc) +{ + uint32_t cardstate; + uint32_t errorstate; + uint32_t resp1 = 0U; + + errorstate = MMC_SendStatus(hmmc, &resp1); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + + cardstate = ((resp1 >> 9U) & 0x0FU); + + return (HAL_MMC_CardStateTypeDef)cardstate; +} + +/** + * @brief Abort the current transfer and disable the MMC. + * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains + * the configuration information for MMC module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc) +{ + HAL_MMC_CardStateTypeDef CardState; + + /* DIsable All interrupts */ + __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\ + SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR); + + /* Clear All flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS); + + if((hmmc->hdmatx != NULL) || (hmmc->hdmarx != NULL)) + { + /* Disable the MMC DMA request */ + hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN); + + /* Abort the MMC DMA Tx Stream */ + if(hmmc->hdmatx != NULL) + { + if(HAL_DMA_Abort(hmmc->hdmatx) != HAL_OK) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_DMA; + } + } + /* Abort the MMC DMA Rx Stream */ + if(hmmc->hdmarx != NULL) + { + if(HAL_DMA_Abort(hmmc->hdmarx) != HAL_OK) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_DMA; + } + } + } + + hmmc->State = HAL_MMC_STATE_READY; + + /* Initialize the MMC operation */ + hmmc->Context = MMC_CONTEXT_NONE; + + CardState = HAL_MMC_GetCardState(hmmc); + if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + { + hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance); + } + if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + { + return HAL_ERROR; + } + return HAL_OK; +} + +/** + * @brief Abort the current transfer and disable the MMC (IT mode). + * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains + * the configuration information for MMC module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc) +{ + HAL_MMC_CardStateTypeDef CardState; + + /* DIsable All interrupts */ + __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\ + SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR); + + /* Clear All flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS); + + if((hmmc->hdmatx != NULL) || (hmmc->hdmarx != NULL)) + { + /* Disable the MMC DMA request */ + hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN); + + /* Abort the MMC DMA Tx Stream */ + if(hmmc->hdmatx != NULL) + { + hmmc->hdmatx->XferAbortCallback = MMC_DMATxAbort; + if(HAL_DMA_Abort_IT(hmmc->hdmatx) != HAL_OK) + { + hmmc->hdmatx = NULL; + } + } + /* Abort the MMC DMA Rx Stream */ + if(hmmc->hdmarx != NULL) + { + hmmc->hdmarx->XferAbortCallback = MMC_DMARxAbort; + if(HAL_DMA_Abort_IT(hmmc->hdmarx) != HAL_OK) + { + hmmc->hdmarx = NULL; + } + } + } + + /* No transfer ongoing on both DMA channels*/ + if((hmmc->hdmatx == NULL) && (hmmc->hdmarx == NULL)) + { + CardState = HAL_MMC_GetCardState(hmmc); + hmmc->State = HAL_MMC_STATE_READY; + + if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + { + hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance); + } + if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + { + return HAL_ERROR; + } + else + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->AbortCpltCallback(hmmc); +#else + HAL_MMC_AbortCallback(hmmc); +#endif + } + } + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private function ----------------------------------------------------------*/ +/** @addtogroup MMC_Private_Functions + * @{ + */ + +/** + * @brief DMA MMC transmit process complete callback + * @param hdma: DMA handle + * @retval None + */ +static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); + + /* Enable DATAEND Interrupt */ + __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DATAEND)); +} + +/** + * @brief DMA MMC receive process complete callback + * @param hdma: DMA handle + * @retval None + */ +static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); + uint32_t errorstate; + + /* Send stop command in multiblock write */ + if(hmmc->Context == (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA)) + { + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->ErrorCallback(hmmc); +#else + HAL_MMC_ErrorCallback(hmmc); +#endif + } + } + + /* Disable the DMA transfer for transmit request by setting the DMAEN bit + in the MMC DCTRL register */ + hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN); + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->RxCpltCallback(hmmc); +#else + HAL_MMC_RxCpltCallback(hmmc); +#endif +} + +/** + * @brief DMA MMC communication error callback + * @param hdma: DMA handle + * @retval None + */ +static void MMC_DMAError(DMA_HandleTypeDef *hdma) +{ + MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); + HAL_MMC_CardStateTypeDef CardState; + uint32_t RxErrorCode, TxErrorCode; + + /* if DMA error is FIFO error ignore it */ + if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) + { + RxErrorCode = hmmc->hdmarx->ErrorCode; + TxErrorCode = hmmc->hdmatx->ErrorCode; + if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE)) + { + /* Clear All flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + + /* Disable All interrupts */ + __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\ + SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR); + + hmmc->ErrorCode |= HAL_MMC_ERROR_DMA; + CardState = HAL_MMC_GetCardState(hmmc); + if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + { + hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance); + } + + hmmc->State= HAL_MMC_STATE_READY; + } + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->ErrorCallback(hmmc); +#else + HAL_MMC_ErrorCallback(hmmc); +#endif + } +} + +/** + * @brief DMA MMC Tx Abort callback + * @param hdma: DMA handle + * @retval None + */ +static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma) +{ + MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); + HAL_MMC_CardStateTypeDef CardState; + + if(hmmc->hdmatx != NULL) + { + hmmc->hdmatx = NULL; + } + + /* All DMA channels are aborted */ + if(hmmc->hdmarx == NULL) + { + CardState = HAL_MMC_GetCardState(hmmc); + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_READY; + if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + { + hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance); + + if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->AbortCpltCallback(hmmc); +#else + HAL_MMC_AbortCallback(hmmc); +#endif + } + else + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->ErrorCallback(hmmc); +#else + HAL_MMC_ErrorCallback(hmmc); +#endif + } + } + } +} + +/** + * @brief DMA MMC Rx Abort callback + * @param hdma: DMA handle + * @retval None + */ +static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma) +{ + MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); + HAL_MMC_CardStateTypeDef CardState; + + if(hmmc->hdmarx != NULL) + { + hmmc->hdmarx = NULL; + } + + /* All DMA channels are aborted */ + if(hmmc->hdmatx == NULL) + { + CardState = HAL_MMC_GetCardState(hmmc); + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_READY; + if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + { + hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance); + + if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->AbortCpltCallback(hmmc); +#else + HAL_MMC_AbortCallback(hmmc); +#endif + } + else + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->ErrorCallback(hmmc); +#else + HAL_MMC_ErrorCallback(hmmc); +#endif + } + } + } +} + +/** + * @brief Initializes the mmc card. + * @param hmmc: Pointer to MMC handle + * @retval MMC Card error state + */ +static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) +{ + HAL_MMC_CardCSDTypeDef CSD; + uint32_t errorstate; + uint16_t mmc_rca = 2U; + MMC_InitTypeDef Init; + + /* Check the power State */ + if(SDIO_GetPowerState(hmmc->Instance) == 0U) + { + /* Power off */ + return HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; + } + + /* Send CMD2 ALL_SEND_CID */ + errorstate = SDMMC_CmdSendCID(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + else + { + /* Get Card identification number data */ + hmmc->CID[0U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1); + hmmc->CID[1U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP2); + hmmc->CID[2U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP3); + hmmc->CID[3U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP4); + } + + /* Send CMD3 SET_REL_ADDR with RCA = 2 (should be greater than 1) */ + /* MMC Card publishes its RCA. */ + errorstate = SDMMC_CmdSetRelAddMmc(hmmc->Instance, mmc_rca); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + + /* Get the MMC card RCA */ + hmmc->MmcCard.RelCardAdd = mmc_rca; + + /* Send CMD9 SEND_CSD with argument as card's RCA */ + errorstate = SDMMC_CmdSendCSD(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + else + { + /* Get Card Specific Data */ + hmmc->CSD[0U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1); + hmmc->CSD[1U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP2); + hmmc->CSD[2U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP3); + hmmc->CSD[3U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP4); + } + + /* Get the Card Class */ + hmmc->MmcCard.Class = (SDIO_GetResponse(hmmc->Instance, SDIO_RESP2) >> 20U); + + /* Select the Card */ + errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + + /* Get CSD parameters */ + if (HAL_MMC_GetCardCSD(hmmc, &CSD) != HAL_OK) + { + return hmmc->ErrorCode; + } + + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + + /* Get Extended CSD parameters */ + if (HAL_MMC_GetCardExtCSD(hmmc, hmmc->Ext_CSD, SDMMC_DATATIMEOUT) != HAL_OK) + { + return hmmc->ErrorCode; + } + + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + + /* Configure the SDIO peripheral */ + Init = hmmc->Init; + Init.BusWide = SDIO_BUS_WIDE_1B; + (void)SDIO_Init(hmmc->Instance, Init); + + /* All cards are initialized */ + return HAL_MMC_ERROR_NONE; +} + +/** + * @brief Enquires cards about their operating voltage and configures clock + * controls and stores MMC information that will be needed in future + * in the MMC handle. + * @param hmmc: Pointer to MMC handle + * @retval error state + */ +static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc) +{ + __IO uint32_t count = 0U; + uint32_t response = 0U, validvoltage = 0U; + uint32_t errorstate; + + /* CMD0: GO_IDLE_STATE */ + errorstate = SDMMC_CmdGoIdleState(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + + while(validvoltage == 0U) + { + if(count++ == SDMMC_MAX_VOLT_TRIAL) + { + return HAL_MMC_ERROR_INVALID_VOLTRANGE; + } + + /* SEND CMD1 APP_CMD with voltage range as argument */ + errorstate = SDMMC_CmdOpCondition(hmmc->Instance, MMC_VOLTAGE_RANGE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return HAL_MMC_ERROR_UNSUPPORTED_FEATURE; + } + + /* Get command response */ + response = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1); + + /* Get operating voltage*/ + validvoltage = (((response >> 31U) == 1U) ? 1U : 0U); + } + + /* When power routine is finished and command returns valid voltage */ + if (((response & (0xFF000000U)) >> 24U) == 0xC0U) + { + hmmc->MmcCard.CardType = MMC_HIGH_CAPACITY_CARD; + } + else + { + hmmc->MmcCard.CardType = MMC_LOW_CAPACITY_CARD; + } + + return HAL_MMC_ERROR_NONE; +} + +/** + * @brief Turns the SDIO output signals off. + * @param hmmc: Pointer to MMC handle + * @retval None + */ +static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc) +{ + /* Set Power State to OFF */ + (void)SDIO_PowerState_OFF(hmmc->Instance); +} + +/** + * @brief Returns the current card's status. + * @param hmmc: Pointer to MMC handle + * @param pCardStatus: pointer to the buffer that will contain the MMC card + * status (Card Status register) + * @retval error state + */ +static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus) +{ + uint32_t errorstate; + + if(pCardStatus == NULL) + { + return HAL_MMC_ERROR_PARAM; + } + + /* Send Status command */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + + /* Get MMC card status */ + *pCardStatus = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1); + + return HAL_MMC_ERROR_NONE; +} + +/** + * @brief Reads extended CSD register to get the sectors number of the device + * @param hmmc: Pointer to MMC handle + * @param pFieldData: Pointer to the read buffer + * @param FieldIndex: Index of the field to be read + * @param Timeout: Specify timeout value + * @retval HAL status + */ +static uint32_t MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout) +{ + SDIO_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t i = 0; + uint32_t tmp_data; + + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0; + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = 512; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + (void)SDIO_ConfigData(hmmc->Instance, &config); + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Poll on SDMMC flags */ + while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND)) + { + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXFIFOHF)) + { + /* Read data from SDMMC Rx FIFO */ + for(count = 0U; count < 8U; count++) + { + tmp_data = SDIO_ReadFIFO(hmmc->Instance); + /* eg : SEC_COUNT : FieldIndex = 212 => i+count = 53 */ + /* DEVICE_TYPE : FieldIndex = 196 => i+count = 49 */ + if ((i + count) == ((uint32_t)FieldIndex/4U)) + { + *pFieldData = tmp_data; + } + } + i += 8U; + } + + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State= HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; +} + + +/** + * @brief Wrap up reading in non-blocking mode. + * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains + * the configuration information. + * @retval None + */ +static void MMC_Read_IT(MMC_HandleTypeDef *hmmc) +{ + uint32_t count, data, dataremaining; + uint8_t* tmp; + + tmp = hmmc->pRxBuffPtr; + dataremaining = hmmc->RxXferSize; + + if (dataremaining > 0U) + { + /* Read data from SDIO Rx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = SDIO_ReadFIFO(hmmc->Instance); + *tmp = (uint8_t)(data & 0xFFU); + tmp++; + dataremaining--; + *tmp = (uint8_t)((data >> 8U) & 0xFFU); + tmp++; + dataremaining--; + *tmp = (uint8_t)((data >> 16U) & 0xFFU); + tmp++; + dataremaining--; + *tmp = (uint8_t)((data >> 24U) & 0xFFU); + tmp++; + dataremaining--; + } + + hmmc->pRxBuffPtr = tmp; + hmmc->RxXferSize = dataremaining; + } +} + +/** + * @brief Wrap up writing in non-blocking mode. + * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains + * the configuration information. + * @retval None + */ +static void MMC_Write_IT(MMC_HandleTypeDef *hmmc) +{ + uint32_t count, data, dataremaining; + uint8_t* tmp; + + tmp = hmmc->pTxBuffPtr; + dataremaining = hmmc->TxXferSize; + + if (dataremaining > 0U) + { + /* Write data to SDIO Tx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = (uint32_t)(*tmp); + tmp++; + dataremaining--; + data |= ((uint32_t)(*tmp) << 8U); + tmp++; + dataremaining--; + data |= ((uint32_t)(*tmp) << 16U); + tmp++; + dataremaining--; + data |= ((uint32_t)(*tmp) << 24U); + tmp++; + dataremaining--; + (void)SDIO_WriteFIFO(hmmc->Instance, &data); + } + + hmmc->pTxBuffPtr = tmp; + hmmc->TxXferSize = dataremaining; + } +} + +/** + * @brief Update the power class of the device. + * @param hmmc MMC handle + * @param Wide Wide of MMC bus + * @param Speed Speed of the MMC bus + * @retval MMC Card error state + */ +static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide) +{ + uint32_t count; + uint32_t response = 0U; + uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint32_t power_class, supported_pwr_class; + + if((Wide == SDIO_BUS_WIDE_8B) || (Wide == SDIO_BUS_WIDE_4B)) + { + power_class = 0U; /* Default value after power-on or software reset */ + + /* Read the PowerClass field of the Extended CSD register */ + if(MMC_ReadExtCSD(hmmc, &power_class, 187, SDMMC_DATATIMEOUT) != HAL_OK) /* Field POWER_CLASS [187] */ + { + errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } + else + { + power_class = ((power_class >> 24U) & 0x000000FFU); + } + + /* Get the supported PowerClass field of the Extended CSD register */ + /* Field PWR_CL_26_xxx [201 or 203] */ + supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_26_INDEX/4)] >> MMC_EXT_CSD_PWR_CL_26_POS) & 0x000000FFU); + + if(errorstate == HAL_MMC_ERROR_NONE) + { + if(Wide == SDIO_BUS_WIDE_8B) + { + /* Bit [7:4] : power class for 8-bits bus configuration - Bit [3:0] : power class for 4-bits bus configuration */ + supported_pwr_class = (supported_pwr_class >> 4U); + } + + if ((power_class & 0x0FU) != (supported_pwr_class & 0x0FU)) + { + /* Need to change current power class */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03BB0000U | ((supported_pwr_class & 0x0FU) << 8U))); + + if(errorstate == HAL_MMC_ERROR_NONE) + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1); + count--; + }while(((response & 0x100U) == 0U) && (count != 0U)); + + /* Check the status after the switch command execution */ + if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + } + else if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else + { + /* Nothing to do */ + } + } + } + } + } + + return errorstate; +} + +/** + * @} + */ + +#endif /* SDIO */ + +#endif /* HAL_MMC_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c new file mode 100644 index 0000000..8e27a52 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c @@ -0,0 +1,3288 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_sd.c + * @author MCD Application Team + * @brief SD card HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Secure Digital (SD) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver implements a high level communication layer for read and write from/to + this memory. The needed STM32 hardware resources (SDIO and GPIO) are performed by + the user in HAL_SD_MspInit() function (MSP layer). + Basically, the MSP layer configuration should be the same as we provide in the + examples. + You can easily tailor this configuration according to hardware resources. + + [..] + This driver is a generic layered driver for SDIO memories which uses the HAL + SDIO driver functions to interface with SD and uSD cards devices. + It is used as follows: + + (#)Initialize the SDIO low level resources by implementing the HAL_SD_MspInit() API: + (##) Enable the SDIO interface clock using __HAL_RCC_SDIO_CLK_ENABLE(); + (##) SDIO pins configuration for SD card + (+++) Enable the clock for the SDIO GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these SDIO pins as alternate function pull-up using HAL_GPIO_Init() + and according to your pin assignment; + (##) DMA configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA() + and HAL_SD_WriteBlocks_DMA() APIs). + (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE(); + (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. + (##) NVIC configuration if you need to use interrupt process when using DMA transfer. + (+++) Configure the SDIO and DMA interrupt priorities using functions + HAL_NVIC_SetPriority(); DMA priority is superior to SDIO's priority + (+++) Enable the NVIC DMA and SDIO IRQs using function HAL_NVIC_EnableIRQ() + (+++) SDIO interrupts are managed using the macros __HAL_SD_ENABLE_IT() + and __HAL_SD_DISABLE_IT() inside the communication process. + (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_GET_IT() + and __HAL_SD_CLEAR_IT() + (##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT() + and HAL_SD_WriteBlocks_IT() APIs). + (+++) Configure the SDIO interrupt priorities using function HAL_NVIC_SetPriority(); + (+++) Enable the NVIC SDIO IRQs using function HAL_NVIC_EnableIRQ() + (+++) SDIO interrupts are managed using the macros __HAL_SD_ENABLE_IT() + and __HAL_SD_DISABLE_IT() inside the communication process. + (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_GET_IT() + and __HAL_SD_CLEAR_IT() + (#) At this stage, you can perform SD read/write/erase operations after SD card initialization + + + *** SD Card Initialization and configuration *** + ================================================ + [..] + To initialize the SD Card, use the HAL_SD_Init() function. It Initializes + SDIO Peripheral(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer). + This function provide the following operations: + + (#) Apply the SD Card initialization process at 400KHz and check the SD Card + type (Standard Capacity or High Capacity). You can change or adapt this + frequency by adjusting the "ClockDiv" field. + The SD Card frequency (SDIO_CK) is computed as follows: + + SDIO_CK = SDIOCLK / (ClockDiv + 2) + + In initialization mode and according to the SD Card standard, + make sure that the SDIO_CK frequency doesn't exceed 400KHz. + + This phase of initialization is done through SDIO_Init() and + SDIO_PowerState_ON() SDIO low level APIs. + + (#) Initialize the SD card. The API used is HAL_SD_InitCard(). + This phase allows the card initialization and identification + and check the SD Card type (Standard Capacity or High Capacity) + The initialization flow is compatible with SD standard. + + This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case + of plug-off plug-in. + + (#) Configure the SD Card Data transfer frequency. You can change or adapt this + frequency by adjusting the "ClockDiv" field. + In transfer mode and according to the SD Card standard, make sure that the + SDIO_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch. + To be able to use a frequency higher than 24MHz, you should use the SDIO + peripheral in bypass mode. Refer to the corresponding reference manual + for more details. + + (#) Select the corresponding SD Card according to the address read with the step 2. + + (#) Configure the SD Card in wide bus mode: 4-bits data. + + *** SD Card Read operation *** + ============================== + [..] + (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + + (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + You could also check the DMA transfer process through the SD Rx interrupt event. + + (+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + You could also check the IT transfer process through the SD Rx interrupt event. + + *** SD Card Write operation *** + =============================== + [..] + (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + + (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + You could also check the DMA transfer process through the SD Tx interrupt event. + + (+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + You could also check the IT transfer process through the SD Tx interrupt event. + + *** SD card status *** + ====================== + [..] + (+) The SD Status contains status bits that are related to the SD Memory + Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus(). + + *** SD card information *** + =========================== + [..] + (+) To get SD card information, you can use the function HAL_SD_GetCardInfo(). + It returns useful information about the SD card such as block size, card type, + block number ... + + *** SD card CSD register *** + ============================ + (+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register. + Some of the CSD parameters are useful for card initialization and identification. + + *** SD card CID register *** + ============================ + (+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register. + Some of the CSD parameters are useful for card initialization and identification. + + *** SD HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in SD HAL driver. + + (+) __HAL_SD_ENABLE : Enable the SD device + (+) __HAL_SD_DISABLE : Disable the SD device + (+) __HAL_SD_DMA_ENABLE: Enable the SDIO DMA transfer + (+) __HAL_SD_DMA_DISABLE: Disable the SDIO DMA transfer + (+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt + (+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt + (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not + (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags + + (@) You can refer to the SD HAL driver header file for more useful macros + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_SD_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions HAL_SD_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) MspInitCallback : SD MspInit. + (+) MspDeInitCallback : SD MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function HAL_SD_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. It allows to reset following callbacks: + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) MspInitCallback : SD MspInit. + (+) MspDeInitCallback : SD MspDeInit. + This function) takes as parameters the HAL peripheral handle and the Callback ID. + + By default, after the HAL_SD_Init and if the state is HAL_SD_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the HAL_SD_Init + and HAL_SD_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SD_Init and HAL_SD_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_SD_RegisterCallback before calling HAL_SD_DeInit + or HAL_SD_Init function. + + When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +#if defined(SDIO) + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup SD + * @{ + */ + +#ifdef HAL_SD_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup SD_Private_Defines + * @{ + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup SD_Private_Functions SD Private Functions + * @{ + */ +static uint32_t SD_InitCard(SD_HandleTypeDef *hsd); +static uint32_t SD_PowerON(SD_HandleTypeDef *hsd); +static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus); +static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus); +static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd); +static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd); +static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR); +static void SD_PowerOFF(SD_HandleTypeDef *hsd); +static void SD_Write_IT(SD_HandleTypeDef *hsd); +static void SD_Read_IT(SD_HandleTypeDef *hsd); +static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void SD_DMAError(DMA_HandleTypeDef *hdma); +static void SD_DMATxAbort(DMA_HandleTypeDef *hdma); +static void SD_DMARxAbort(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SD_Exported_Functions + * @{ + */ + +/** @addtogroup SD_Exported_Functions_Group1 + * @brief Initialization and de-initialization functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to initialize/de-initialize the SD + card device to be ready for use. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the SD according to the specified parameters in the + SD_HandleTypeDef and create the associated handle. + * @param hsd: Pointer to the SD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) +{ + /* Check the SD handle allocation */ + if(hsd == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SDIO_ALL_INSTANCE(hsd->Instance)); + assert_param(IS_SDIO_CLOCK_EDGE(hsd->Init.ClockEdge)); + assert_param(IS_SDIO_CLOCK_BYPASS(hsd->Init.ClockBypass)); + assert_param(IS_SDIO_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave)); + assert_param(IS_SDIO_BUS_WIDE(hsd->Init.BusWide)); + assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl)); + assert_param(IS_SDIO_CLKDIV(hsd->Init.ClockDiv)); + + if(hsd->State == HAL_SD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hsd->Lock = HAL_UNLOCKED; +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + /* Reset Callback pointers in HAL_SD_STATE_RESET only */ + hsd->TxCpltCallback = HAL_SD_TxCpltCallback; + hsd->RxCpltCallback = HAL_SD_RxCpltCallback; + hsd->ErrorCallback = HAL_SD_ErrorCallback; + hsd->AbortCpltCallback = HAL_SD_AbortCallback; + + if(hsd->MspInitCallback == NULL) + { + hsd->MspInitCallback = HAL_SD_MspInit; + } + + /* Init the low level hardware */ + hsd->MspInitCallback(hsd); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_SD_MspInit(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize the Card parameters */ + if (HAL_SD_InitCard(hsd) != HAL_OK) + { + return HAL_ERROR; + } + + /* Initialize the error code */ + hsd->ErrorCode = HAL_SD_ERROR_NONE; + + /* Initialize the SD operation */ + hsd->Context = SD_CONTEXT_NONE; + + /* Initialize the SD state */ + hsd->State = HAL_SD_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Initializes the SD Card. + * @param hsd: Pointer to SD handle + * @note This function initializes the SD card. It could be used when a card + re-initialization is needed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) +{ + uint32_t errorstate; + SD_InitTypeDef Init; + + /* Default SDIO peripheral configuration for SD card initialization */ + Init.ClockEdge = SDIO_CLOCK_EDGE_RISING; + Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; + Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; + Init.BusWide = SDIO_BUS_WIDE_1B; + Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; + Init.ClockDiv = SDIO_INIT_CLK_DIV; + + /* Initialize SDIO peripheral interface with default configuration */ + SDIO_Init(hsd->Instance, Init); + + /* Disable SDIO Clock */ + __HAL_SD_DISABLE(hsd); + + /* Set Power State to ON */ + (void)SDIO_PowerState_ON(hsd->Instance); + + /* Enable SDIO Clock */ + __HAL_SD_ENABLE(hsd); + + /* Required power up waiting time before starting the SD initialization sequence */ + HAL_Delay(2); + + /* Identify card operating voltage */ + errorstate = SD_PowerON(hsd); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->State = HAL_SD_STATE_READY; + hsd->ErrorCode |= errorstate; + return HAL_ERROR; + } + + /* Card initialization */ + errorstate = SD_InitCard(hsd); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->State = HAL_SD_STATE_READY; + hsd->ErrorCode |= errorstate; + return HAL_ERROR; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief De-Initializes the SD card. + * @param hsd: Pointer to SD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) +{ + /* Check the SD handle allocation */ + if(hsd == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SDIO_ALL_INSTANCE(hsd->Instance)); + + hsd->State = HAL_SD_STATE_BUSY; + + /* Set SD power state to off */ + SD_PowerOFF(hsd); + +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + if(hsd->MspDeInitCallback == NULL) + { + hsd->MspDeInitCallback = HAL_SD_MspDeInit; + } + + /* DeInit the low level hardware */ + hsd->MspDeInitCallback(hsd); +#else + /* De-Initialize the MSP layer */ + HAL_SD_MspDeInit(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + + hsd->ErrorCode = HAL_SD_ERROR_NONE; + hsd->State = HAL_SD_STATE_RESET; + + return HAL_OK; +} + + +/** + * @brief Initializes the SD MSP. + * @param hsd: Pointer to SD handle + * @retval None + */ +__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_MspInit could be implemented in the user file + */ +} + +/** + * @brief De-Initialize SD MSP. + * @param hsd: Pointer to SD handle + * @retval None + */ +__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @addtogroup SD_Exported_Functions_Group2 + * @brief Data transfer functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the data + transfer from/to SD card. + +@endverbatim + * @{ + */ + +/** + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed by polling mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @param hsd: Pointer to SD handle + * @param pData: pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of SD blocks to read + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) +{ + SDIO_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count, data, dataremaining; + uint32_t add = BlockAdd; + uint8_t *tempbuff = pData; + + if(NULL == pData) + { + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; + } + + if(hsd->State == HAL_SD_STATE_READY) + { + hsd->ErrorCode = HAL_SD_ERROR_NONE; + + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0U; + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + add *= 512U; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * BLOCKSIZE; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + (void)SDIO_ConfigData(hsd->Instance, &config); + + /* Read block(s) in polling mode */ + if(NumberOfBlocks > 1U) + { + hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); + } + else + { + hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK; + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); + } + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + + /* Poll on SDIO flags */ + dataremaining = config.DataLength; +#if defined(SDIO_STA_STBITERR) + while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR)) +#else /* SDIO_STA_STBITERR not defined */ + while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND)) +#endif /* SDIO_STA_STBITERR */ + { + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF) && (dataremaining > 0U)) + { + /* Read data from SDIO Rx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = SDIO_ReadFIFO(hsd->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + dataremaining--; + } + } + + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT; + hsd->State= HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_TIMEOUT; + } + } + + /* Send stop transmission command in case of multiblock read */ + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + { + if(hsd->SdCard.CardType != CARD_SECURED) + { + /* Send stop transmission command */ + errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + } + } + + /* Get error state */ +#if defined(SDIO_STA_STBITERR) + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR))) +#else /* SDIO_STA_STBITERR not defined */ + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) +#endif /* SDIO_STA_STBITERR */ + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Empty FIFO if there is still any data */ + while ((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (dataremaining > 0U)) + { + data = SDIO_ReadFIFO(hsd->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + dataremaining--; + + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT; + hsd->State= HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + } + + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS); + + hsd->State = HAL_SD_STATE_READY; + + return HAL_OK; + } + else + { + hsd->ErrorCode |= HAL_SD_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Allows to write block(s) to a specified address in a card. The Data + * transfer is managed by polling mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @param hsd: Pointer to SD handle + * @param pData: pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of SD blocks to write + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) +{ + SDIO_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count, data, dataremaining; + uint32_t add = BlockAdd; + uint8_t *tempbuff = pData; + + if(NULL == pData) + { + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; + } + + if(hsd->State == HAL_SD_STATE_READY) + { + hsd->ErrorCode = HAL_SD_ERROR_NONE; + + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0U; + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + add *= 512U; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * BLOCKSIZE; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + (void)SDIO_ConfigData(hsd->Instance, &config); + + /* Write Blocks in Polling mode */ + if(NumberOfBlocks > 1U) + { + hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); + } + else + { + hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK; + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); + } + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + + /* Write block(s) in polling mode */ + dataremaining = config.DataLength; +#if defined(SDIO_STA_STBITERR) + while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR)) +#else /* SDIO_STA_STBITERR not defined */ + while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND)) +#endif /* SDIO_STA_STBITERR */ + { + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE) && (dataremaining > 0U)) + { + /* Write data to SDIO Tx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = (uint32_t)(*tempbuff); + tempbuff++; + dataremaining--; + data |= ((uint32_t)(*tempbuff) << 8U); + tempbuff++; + dataremaining--; + data |= ((uint32_t)(*tempbuff) << 16U); + tempbuff++; + dataremaining--; + data |= ((uint32_t)(*tempbuff) << 24U); + tempbuff++; + dataremaining--; + (void)SDIO_WriteFIFO(hsd->Instance, &data); + } + } + + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_TIMEOUT; + } + } + + /* Send stop transmission command in case of multiblock write */ + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + { + if(hsd->SdCard.CardType != CARD_SECURED) + { + /* Send stop transmission command */ + errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + } + } + + /* Get error state */ +#if defined(SDIO_STA_STBITERR) + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR))) +#else /* SDIO_STA_STBITERR not defined */ + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) +#endif /* SDIO_STA_STBITERR */ + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS); + + hsd->State = HAL_SD_STATE_READY; + + return HAL_OK; + } + else + { + hsd->ErrorCode |= HAL_SD_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed in interrupt mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @note You could also check the IT transfer process through the SD Rx + * interrupt event. + * @param hsd: Pointer to SD handle + * @param pData: Pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of blocks to read. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDIO_DataInitTypeDef config; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if(NULL == pData) + { + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; + } + + if(hsd->State == HAL_SD_STATE_READY) + { + hsd->ErrorCode = HAL_SD_ERROR_NONE; + + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0U; + + hsd->pRxBuffPtr = pData; + hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks; + +#if defined(SDIO_STA_STBITERR) + __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_FLAG_RXFIFOHF | SDIO_IT_STBITERR)); +#else /* SDIO_STA_STBITERR not defined */ + __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_FLAG_RXFIFOHF)); +#endif /* SDIO_STA_STBITERR */ + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + add *= 512U; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + (void)SDIO_ConfigData(hsd->Instance, &config); + + /* Read Blocks in IT mode */ + if(NumberOfBlocks > 1U) + { + hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); + } + else + { + hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT); + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); + } + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Writes block(s) to a specified address in a card. The Data transfer + * is managed in interrupt mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @note You could also check the IT transfer process through the SD Tx + * interrupt event. + * @param hsd: Pointer to SD handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDIO_DataInitTypeDef config; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if(NULL == pData) + { + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; + } + + if(hsd->State == HAL_SD_STATE_READY) + { + hsd->ErrorCode = HAL_SD_ERROR_NONE; + + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0U; + + hsd->pTxBuffPtr = pData; + hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks; + + /* Enable transfer interrupts */ +#if defined(SDIO_STA_STBITERR) + __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE | SDIO_IT_STBITERR)); +#else /* SDIO_STA_STBITERR not defined */ + __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE)); +#endif /* SDIO_STA_STBITERR */ + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + add *= 512U; + } + + /* Write Blocks in Polling mode */ + if(NumberOfBlocks > 1U) + { + hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); + } + else + { + hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT); + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); + } + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + (void)SDIO_ConfigData(hsd->Instance, &config); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed by DMA mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @note You could also check the DMA transfer process through the SD Rx + * interrupt event. + * @param hsd: Pointer SD handle + * @param pData: Pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of blocks to read. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDIO_DataInitTypeDef config; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if(NULL == pData) + { + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; + } + + if(hsd->State == HAL_SD_STATE_READY) + { + hsd->ErrorCode = HAL_SD_ERROR_NONE; + + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0U; + +#if defined(SDIO_STA_STBITERR) + __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_IT_STBITERR)); +#else /* SDIO_STA_STBITERR not defined */ + __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND)); +#endif /* SDIO_STA_STBITERR */ + + /* Set the DMA transfer complete callback */ + hsd->hdmarx->XferCpltCallback = SD_DMAReceiveCplt; + + /* Set the DMA error callback */ + hsd->hdmarx->XferErrorCallback = SD_DMAError; + + /* Set the DMA Abort callback */ + hsd->hdmarx->XferAbortCallback = NULL; + + /* Force DMA Direction */ + hsd->hdmarx->Init.Direction = DMA_PERIPH_TO_MEMORY; + MODIFY_REG(hsd->hdmarx->Instance->CR, DMA_SxCR_DIR, hsd->hdmarx->Init.Direction); + + /* Enable the DMA Channel */ + if(HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK) + { + __HAL_SD_DISABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND)); + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_DMA; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + else + { + /* Enable SD DMA transfer */ + __HAL_SD_DMA_ENABLE(hsd); + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + add *= 512U; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + (void)SDIO_ConfigData(hsd->Instance, &config); + + /* Read Blocks in DMA mode */ + if(NumberOfBlocks > 1U) + { + hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); + } + else + { + hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA); + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); + } + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Writes block(s) to a specified address in a card. The Data transfer + * is managed by DMA mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @note You could also check the DMA transfer process through the SD Tx + * interrupt event. + * @param hsd: Pointer to SD handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDIO_DataInitTypeDef config; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if(NULL == pData) + { + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; + } + + if(hsd->State == HAL_SD_STATE_READY) + { + hsd->ErrorCode = HAL_SD_ERROR_NONE; + + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0U; + + /* Enable SD Error interrupts */ +#if defined(SDIO_STA_STBITERR) + __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR)); +#else /* SDIO_STA_STBITERR not defined */ + __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR)); +#endif /* SDIO_STA_STBITERR */ + + /* Set the DMA transfer complete callback */ + hsd->hdmatx->XferCpltCallback = SD_DMATransmitCplt; + + /* Set the DMA error callback */ + hsd->hdmatx->XferErrorCallback = SD_DMAError; + + /* Set the DMA Abort callback */ + hsd->hdmatx->XferAbortCallback = NULL; + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + add *= 512U; + } + + /* Write Blocks in Polling mode */ + if(NumberOfBlocks > 1U) + { + hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); + } + else + { + hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA); + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); + } + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + + /* Enable SDIO DMA transfer */ + __HAL_SD_DMA_ENABLE(hsd); + + /* Force DMA Direction */ + hsd->hdmatx->Init.Direction = DMA_MEMORY_TO_PERIPH; + MODIFY_REG(hsd->hdmatx->Instance->CR, DMA_SxCR_DIR, hsd->hdmatx->Init.Direction); + + /* Enable the DMA Channel */ + if(HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK) + { +#if defined(SDIO_STA_STBITERR) + __HAL_SD_DISABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR)); +#else /* SDIO_STA_STBITERR not defined */ + __HAL_SD_DISABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR)); +#endif /* SDIO_STA_STBITERR */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_DMA; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + else + { + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + (void)SDIO_ConfigData(hsd->Instance, &config); + + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Erases the specified memory area of the given SD card. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @param hsd: Pointer to SD handle + * @param BlockStartAdd: Start Block address + * @param BlockEndAdd: End Block address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd) +{ + uint32_t errorstate; + uint32_t start_add = BlockStartAdd; + uint32_t end_add = BlockEndAdd; + + if(hsd->State == HAL_SD_STATE_READY) + { + hsd->ErrorCode = HAL_SD_ERROR_NONE; + + if(end_add < start_add) + { + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; + } + + if(end_add > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Check if the card command class supports erase command */ + if(((hsd->SdCard.Class) & SDIO_CCCC_ERASE) == 0U) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + /* Get start and end block for high capacity cards */ + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + start_add *= 512U; + end_add *= 512U; + } + + /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */ + if(hsd->SdCard.CardType != CARD_SECURED) + { + /* Send CMD32 SD_ERASE_GRP_START with argument as addr */ + errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, start_add); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + /* Send CMD33 SD_ERASE_GRP_END with argument as addr */ + errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, end_add); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + } + + /* Send CMD38 ERASE */ + errorstate = SDMMC_CmdErase(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief This function handles SD card interrupt request. + * @param hsd: Pointer to SD handle + * @retval None + */ +void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) +{ + uint32_t errorstate; + uint32_t context = hsd->Context; + + /* Check for SDIO interrupt flags */ + if((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U)) + { + SD_Read_IT(hsd); + } + + else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) != RESET) + { + __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DATAEND); + +#if defined(SDIO_STA_STBITERR) + __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\ + SDIO_IT_TXUNDERR | SDIO_IT_RXOVERR | SDIO_IT_TXFIFOHE |\ + SDIO_IT_RXFIFOHF | SDIO_IT_STBITERR); +#else /* SDIO_STA_STBITERR not defined */ + __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\ + SDIO_IT_TXUNDERR | SDIO_IT_RXOVERR | SDIO_IT_TXFIFOHE |\ + SDIO_IT_RXFIFOHF); +#endif /* SDIO_STA_STBITERR */ + + hsd->Instance->DCTRL &= ~(SDIO_DCTRL_DTEN); + + if((context & SD_CONTEXT_IT) != 0U) + { + if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + { + errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= errorstate; +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->ErrorCallback(hsd); +#else + HAL_SD_ErrorCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + } + + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS); + + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->RxCpltCallback(hsd); +#else + HAL_SD_RxCpltCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + else + { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->TxCpltCallback(hsd); +#else + HAL_SD_TxCpltCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + } + else if((context & SD_CONTEXT_DMA) != 0U) + { + if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) + { + errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= errorstate; +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->ErrorCallback(hsd); +#else + HAL_SD_ErrorCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + } + if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) == 0U) && ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == 0U)) + { + /* Disable the DMA transfer for transmit request by setting the DMAEN bit + in the SD DCTRL register */ + hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN); + + hsd->State = HAL_SD_STATE_READY; + +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->TxCpltCallback(hsd); +#else + HAL_SD_TxCpltCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + } + else + { + /* Nothing to do */ + } + } + + else if((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U)) + { + SD_Write_IT(hsd); + } + +#if defined(SDIO_STA_STBITERR) + else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_RXOVERR | SDIO_FLAG_TXUNDERR | SDIO_FLAG_STBITERR) != RESET) +#else /* SDIO_STA_STBITERR not defined */ + else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_RXOVERR | SDIO_FLAG_TXUNDERR) != RESET) +#endif /* SDIO_STA_STBITERR */ + { + /* Set Error code */ + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL) != RESET) + { + hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; + } + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) != RESET) + { + hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; + } + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR) != RESET) + { + hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN; + } + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR) != RESET) + { + hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; + } +#if defined(SDIO_STA_STBITERR) + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR) != RESET) + { + hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; + } +#endif /* SDIO_STA_STBITERR */ + +#if defined(SDIO_STA_STBITERR) + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS | SDIO_FLAG_STBITERR); + + /* Disable all interrupts */ + __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\ + SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR | SDIO_IT_STBITERR); +#else /* SDIO_STA_STBITERR not defined */ + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS); + + /* Disable all interrupts */ + __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\ + SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR); +#endif /* SDIO_STA_STBITERR */ + + hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); + + if((context & SD_CONTEXT_IT) != 0U) + { + /* Set the SD state to ready to be able to start again the process */ + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->ErrorCallback(hsd); +#else + HAL_SD_ErrorCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + else if((context & SD_CONTEXT_DMA) != 0U) + { + /* Abort the SD DMA channel */ + if(((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + { + /* Set the DMA Tx abort callback */ + hsd->hdmatx->XferAbortCallback = SD_DMATxAbort; + /* Abort DMA in IT mode */ + if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK) + { + SD_DMATxAbort(hsd->hdmatx); + } + } + else if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + { + /* Set the DMA Rx abort callback */ + hsd->hdmarx->XferAbortCallback = SD_DMARxAbort; + /* Abort DMA in IT mode */ + if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK) + { + SD_DMARxAbort(hsd->hdmarx); + } + } + else + { + hsd->ErrorCode = HAL_SD_ERROR_NONE; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->AbortCpltCallback(hsd); +#else + HAL_SD_AbortCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + } + else + { + /* Nothing to do */ + } + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief return the SD state + * @param hsd: Pointer to sd handle + * @retval HAL state + */ +HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd) +{ + return hsd->State; +} + +/** +* @brief Return the SD error code +* @param hsd : Pointer to a SD_HandleTypeDef structure that contains + * the configuration information. +* @retval SD Error Code +*/ +uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd) +{ + return hsd->ErrorCode; +} + +/** + * @brief Tx Transfer completed callbacks + * @param hsd: Pointer to SD handle + * @retval None + */ +__weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_TxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks + * @param hsd: Pointer SD handle + * @retval None + */ +__weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_RxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief SD error callbacks + * @param hsd: Pointer SD handle + * @retval None + */ +__weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_ErrorCallback can be implemented in the user file + */ +} + +/** + * @brief SD Abort callbacks + * @param hsd: Pointer SD handle + * @retval None + */ +__weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_AbortCallback can be implemented in the user file + */ +} + +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User SD Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hsd : SD handle + * @param CallbackID : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID + * @arg @ref HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID + * @arg @ref HAL_SD_ERROR_CB_ID SD Error Callback ID + * @arg @ref HAL_SD_ABORT_CB_ID SD Abort Callback ID + * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID + * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hsd); + + if(hsd->State == HAL_SD_STATE_READY) + { + switch (CallbackID) + { + case HAL_SD_TX_CPLT_CB_ID : + hsd->TxCpltCallback = pCallback; + break; + case HAL_SD_RX_CPLT_CB_ID : + hsd->RxCpltCallback = pCallback; + break; + case HAL_SD_ERROR_CB_ID : + hsd->ErrorCallback = pCallback; + break; + case HAL_SD_ABORT_CB_ID : + hsd->AbortCpltCallback = pCallback; + break; + case HAL_SD_MSP_INIT_CB_ID : + hsd->MspInitCallback = pCallback; + break; + case HAL_SD_MSP_DEINIT_CB_ID : + hsd->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hsd->State == HAL_SD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_SD_MSP_INIT_CB_ID : + hsd->MspInitCallback = pCallback; + break; + case HAL_SD_MSP_DEINIT_CB_ID : + hsd->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsd); + return status; +} + +/** + * @brief Unregister a User SD Callback + * SD Callback is redirected to the weak (surcharged) predefined callback + * @param hsd : SD handle + * @param CallbackID : ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID + * @arg @ref HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID + * @arg @ref HAL_SD_ERROR_CB_ID SD Error Callback ID + * @arg @ref HAL_SD_ABORT_CB_ID SD Abort Callback ID + * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID + * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hsd); + + if(hsd->State == HAL_SD_STATE_READY) + { + switch (CallbackID) + { + case HAL_SD_TX_CPLT_CB_ID : + hsd->TxCpltCallback = HAL_SD_TxCpltCallback; + break; + case HAL_SD_RX_CPLT_CB_ID : + hsd->RxCpltCallback = HAL_SD_RxCpltCallback; + break; + case HAL_SD_ERROR_CB_ID : + hsd->ErrorCallback = HAL_SD_ErrorCallback; + break; + case HAL_SD_ABORT_CB_ID : + hsd->AbortCpltCallback = HAL_SD_AbortCallback; + break; + case HAL_SD_MSP_INIT_CB_ID : + hsd->MspInitCallback = HAL_SD_MspInit; + break; + case HAL_SD_MSP_DEINIT_CB_ID : + hsd->MspDeInitCallback = HAL_SD_MspDeInit; + break; + default : + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hsd->State == HAL_SD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_SD_MSP_INIT_CB_ID : + hsd->MspInitCallback = HAL_SD_MspInit; + break; + case HAL_SD_MSP_DEINIT_CB_ID : + hsd->MspDeInitCallback = HAL_SD_MspDeInit; + break; + default : + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsd); + return status; +} +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup SD_Exported_Functions_Group3 + * @brief management functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the SD card + operations and get the related information + +@endverbatim + * @{ + */ + +/** + * @brief Returns information the information of the card which are stored on + * the CID register. + * @param hsd: Pointer to SD handle + * @param pCID: Pointer to a HAL_SD_CardCIDTypeDef structure that + * contains all CID register parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID) +{ + pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U); + + pCID->OEM_AppliID = (uint16_t)((hsd->CID[0] & 0x00FFFF00U) >> 8U); + + pCID->ProdName1 = (((hsd->CID[0] & 0x000000FFU) << 24U) | ((hsd->CID[1] & 0xFFFFFF00U) >> 8U)); + + pCID->ProdName2 = (uint8_t)(hsd->CID[1] & 0x000000FFU); + + pCID->ProdRev = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24U); + + pCID->ProdSN = (((hsd->CID[2] & 0x00FFFFFFU) << 8U) | ((hsd->CID[3] & 0xFF000000U) >> 24U)); + + pCID->Reserved1 = (uint8_t)((hsd->CID[3] & 0x00F00000U) >> 20U); + + pCID->ManufactDate = (uint16_t)((hsd->CID[3] & 0x000FFF00U) >> 8U); + + pCID->CID_CRC = (uint8_t)((hsd->CID[3] & 0x000000FEU) >> 1U); + + pCID->Reserved2 = 1U; + + return HAL_OK; +} + +/** + * @brief Returns information the information of the card which are stored on + * the CSD register. + * @param hsd: Pointer to SD handle + * @param pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that + * contains all CSD register parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD) +{ + pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U); + + pCSD->SysSpecVersion = (uint8_t)((hsd->CSD[0] & 0x3C000000U) >> 26U); + + pCSD->Reserved1 = (uint8_t)((hsd->CSD[0] & 0x03000000U) >> 24U); + + pCSD->TAAC = (uint8_t)((hsd->CSD[0] & 0x00FF0000U) >> 16U); + + pCSD->NSAC = (uint8_t)((hsd->CSD[0] & 0x0000FF00U) >> 8U); + + pCSD->MaxBusClkFrec = (uint8_t)(hsd->CSD[0] & 0x000000FFU); + + pCSD->CardComdClasses = (uint16_t)((hsd->CSD[1] & 0xFFF00000U) >> 20U); + + pCSD->RdBlockLen = (uint8_t)((hsd->CSD[1] & 0x000F0000U) >> 16U); + + pCSD->PartBlockRead = (uint8_t)((hsd->CSD[1] & 0x00008000U) >> 15U); + + pCSD->WrBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00004000U) >> 14U); + + pCSD->RdBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00002000U) >> 13U); + + pCSD->DSRImpl = (uint8_t)((hsd->CSD[1] & 0x00001000U) >> 12U); + + pCSD->Reserved2 = 0U; /*!< Reserved */ + + if(hsd->SdCard.CardType == CARD_SDSC) + { + pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U)); + + pCSD->MaxRdCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x38000000U) >> 27U); + + pCSD->MaxRdCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x07000000U) >> 24U); + + pCSD->MaxWrCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x00E00000U) >> 21U); + + pCSD->MaxWrCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x001C0000U) >> 18U); + + pCSD->DeviceSizeMul = (uint8_t)((hsd->CSD[2] & 0x00038000U) >> 15U); + + hsd->SdCard.BlockNbr = (pCSD->DeviceSize + 1U) ; + hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); + hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); + + hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U); + hsd->SdCard.LogBlockSize = 512U; + } + else if(hsd->SdCard.CardType == CARD_SDHC_SDXC) + { + /* Byte 7 */ + pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U)); + + hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U); + hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr; + hsd->SdCard.BlockSize = 512U; + hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize; + } + else + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + pCSD->EraseGrSize = (uint8_t)((hsd->CSD[2] & 0x00004000U) >> 14U); + + pCSD->EraseGrMul = (uint8_t)((hsd->CSD[2] & 0x00003F80U) >> 7U); + + pCSD->WrProtectGrSize = (uint8_t)(hsd->CSD[2] & 0x0000007FU); + + pCSD->WrProtectGrEnable = (uint8_t)((hsd->CSD[3] & 0x80000000U) >> 31U); + + pCSD->ManDeflECC = (uint8_t)((hsd->CSD[3] & 0x60000000U) >> 29U); + + pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U); + + pCSD->MaxWrBlockLen= (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U); + + pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U); + + pCSD->Reserved3 = 0; + + pCSD->ContentProtectAppli = (uint8_t)((hsd->CSD[3] & 0x00010000U) >> 16U); + + pCSD->FileFormatGroup = (uint8_t)((hsd->CSD[3] & 0x00008000U) >> 15U); + + pCSD->CopyFlag = (uint8_t)((hsd->CSD[3] & 0x00004000U) >> 14U); + + pCSD->PermWrProtect = (uint8_t)((hsd->CSD[3] & 0x00002000U) >> 13U); + + pCSD->TempWrProtect = (uint8_t)((hsd->CSD[3] & 0x00001000U) >> 12U); + + pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U); + + pCSD->ECC= (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U); + + pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U); + + pCSD->Reserved4 = 1; + + return HAL_OK; +} + +/** + * @brief Gets the SD status info. + * @param hsd: Pointer to SD handle + * @param pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that + * will contain the SD card status information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus) +{ + uint32_t sd_status[16]; + uint32_t errorstate; + HAL_StatusTypeDef status = HAL_OK; + + errorstate = SD_SendSDStatus(hsd, sd_status); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + status = HAL_ERROR; + } + else + { + pStatus->DataBusWidth = (uint8_t)((sd_status[0] & 0xC0U) >> 6U); + + pStatus->SecuredMode = (uint8_t)((sd_status[0] & 0x20U) >> 5U); + + pStatus->CardType = (uint16_t)(((sd_status[0] & 0x00FF0000U) >> 8U) | ((sd_status[0] & 0xFF000000U) >> 24U)); + + pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U) | ((sd_status[1] & 0xFF00U) << 8U) | + ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U) >> 24U)); + + pStatus->SpeedClass = (uint8_t)(sd_status[2] & 0xFFU); + + pStatus->PerformanceMove = (uint8_t)((sd_status[2] & 0xFF00U) >> 8U); + + pStatus->AllocationUnitSize = (uint8_t)((sd_status[2] & 0xF00000U) >> 20U); + + pStatus->EraseSize = (uint16_t)(((sd_status[2] & 0xFF000000U) >> 16U) | (sd_status[3] & 0xFFU)); + + pStatus->EraseTimeout = (uint8_t)((sd_status[3] & 0xFC00U) >> 10U); + + pStatus->EraseOffset = (uint8_t)((sd_status[3] & 0x0300U) >> 8U); + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode = errorstate; + hsd->State = HAL_SD_STATE_READY; + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Gets the SD card info. + * @param hsd: Pointer to SD handle + * @param pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that + * will contain the SD card status information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo) +{ + pCardInfo->CardType = (uint32_t)(hsd->SdCard.CardType); + pCardInfo->CardVersion = (uint32_t)(hsd->SdCard.CardVersion); + pCardInfo->Class = (uint32_t)(hsd->SdCard.Class); + pCardInfo->RelCardAdd = (uint32_t)(hsd->SdCard.RelCardAdd); + pCardInfo->BlockNbr = (uint32_t)(hsd->SdCard.BlockNbr); + pCardInfo->BlockSize = (uint32_t)(hsd->SdCard.BlockSize); + pCardInfo->LogBlockNbr = (uint32_t)(hsd->SdCard.LogBlockNbr); + pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize); + + return HAL_OK; +} + +/** + * @brief Enables wide bus operation for the requested card if supported by + * card. + * @param hsd: Pointer to SD handle + * @param WideMode: Specifies the SD card wide bus mode + * This parameter can be one of the following values: + * @arg SDIO_BUS_WIDE_8B: 8-bit data transfer + * @arg SDIO_BUS_WIDE_4B: 4-bit data transfer + * @arg SDIO_BUS_WIDE_1B: 1-bit data transfer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode) +{ + SDIO_InitTypeDef Init; + uint32_t errorstate; + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_SDIO_BUS_WIDE(WideMode)); + + /* Change State */ + hsd->State = HAL_SD_STATE_BUSY; + + if(hsd->SdCard.CardType != CARD_SECURED) + { + if(WideMode == SDIO_BUS_WIDE_8B) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + } + else if(WideMode == SDIO_BUS_WIDE_4B) + { + errorstate = SD_WideBus_Enable(hsd); + + hsd->ErrorCode |= errorstate; + } + else if(WideMode == SDIO_BUS_WIDE_1B) + { + errorstate = SD_WideBus_Disable(hsd); + + hsd->ErrorCode |= errorstate; + } + else + { + /* WideMode is not a valid argument*/ + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + } + } + else + { + /* MMC Card does not support this feature */ + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + } + + if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->State = HAL_SD_STATE_READY; + status = HAL_ERROR; + } + else + { + /* Configure the SDIO peripheral */ + Init.ClockEdge = hsd->Init.ClockEdge; + Init.ClockBypass = hsd->Init.ClockBypass; + Init.ClockPowerSave = hsd->Init.ClockPowerSave; + Init.BusWide = WideMode; + Init.HardwareFlowControl = hsd->Init.HardwareFlowControl; + Init.ClockDiv = hsd->Init.ClockDiv; + (void)SDIO_Init(hsd->Instance, Init); + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + status = HAL_ERROR; + } + + /* Change State */ + hsd->State = HAL_SD_STATE_READY; + + return status; +} + +/** + * @brief Gets the current sd card data state. + * @param hsd: pointer to SD handle + * @retval Card state + */ +HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) +{ + uint32_t cardstate; + uint32_t errorstate; + uint32_t resp1 = 0; + + errorstate = SD_SendStatus(hsd, &resp1); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= errorstate; + } + + cardstate = ((resp1 >> 9U) & 0x0FU); + + return (HAL_SD_CardStateTypeDef)cardstate; +} + +/** + * @brief Abort the current transfer and disable the SD. + * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * the configuration information for SD module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) +{ + HAL_SD_CardStateTypeDef CardState; + uint32_t context = hsd->Context; + + /* DIsable All interrupts */ + __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\ + SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR); + + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS); + + CLEAR_BIT(hsd->Instance->DCTRL, SDIO_DCTRL_DTEN); + + if ((context & SD_CONTEXT_DMA) != 0U) + { + /* Disable the SD DMA request */ + hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN); + + /* Abort the SD DMA Tx channel */ + if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + { + if(HAL_DMA_Abort(hsd->hdmatx) != HAL_OK) + { + hsd->ErrorCode |= HAL_SD_ERROR_DMA; + } + } + /* Abort the SD DMA Rx channel */ + else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + { + if(HAL_DMA_Abort(hsd->hdmarx) != HAL_OK) + { + hsd->ErrorCode |= HAL_SD_ERROR_DMA; + } + } + else + { + /* Nothing to do */ + } + } + + hsd->State = HAL_SD_STATE_READY; + + /* Initialize the SD operation */ + hsd->Context = SD_CONTEXT_NONE; + + CardState = HAL_SD_GetCardState(hsd); + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + { + hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance); + } + if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + { + return HAL_ERROR; + } + return HAL_OK; +} + +/** + * @brief Abort the current transfer and disable the SD (IT mode). + * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * the configuration information for SD module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) +{ + HAL_SD_CardStateTypeDef CardState; + uint32_t context = hsd->Context; + + /* Disable All interrupts */ + __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\ + SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR); + + CLEAR_BIT(hsd->Instance->DCTRL, SDIO_DCTRL_DTEN); + + if ((context & SD_CONTEXT_DMA) != 0U) + { + /* Disable the SD DMA request */ + hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN); + + /* Abort the SD DMA Tx channel */ + if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + { + hsd->hdmatx->XferAbortCallback = SD_DMATxAbort; + if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK) + { + hsd->hdmatx = NULL; + } + } + /* Abort the SD DMA Rx channel */ + else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + { + hsd->hdmarx->XferAbortCallback = SD_DMARxAbort; + if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK) + { + hsd->hdmarx = NULL; + } + } + else + { + /* Nothing to do */ + } + } + /* No transfer ongoing on both DMA channels*/ + else + { + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS); + + CardState = HAL_SD_GetCardState(hsd); + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + { + hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance); + } + if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + { + return HAL_ERROR; + } + else + { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->AbortCpltCallback(hsd); +#else + HAL_SD_AbortCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + } + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private function ----------------------------------------------------------*/ +/** @addtogroup SD_Private_Functions + * @{ + */ + +/** + * @brief DMA SD transmit process complete callback + * @param hdma: DMA handle + * @retval None + */ +static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); + + /* Enable DATAEND Interrupt */ + __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DATAEND)); +} + +/** + * @brief DMA SD receive process complete callback + * @param hdma: DMA handle + * @retval None + */ +static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); + uint32_t errorstate; + + /* Send stop command in multiblock write */ + if(hsd->Context == (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA)) + { + errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= errorstate; +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->ErrorCallback(hsd); +#else + HAL_SD_ErrorCallback(hsd); +#endif + } + } + + /* Disable the DMA transfer for transmit request by setting the DMAEN bit + in the SD DCTRL register */ + hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN); + + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS); + + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->RxCpltCallback(hsd); +#else + HAL_SD_RxCpltCallback(hsd); +#endif +} + +/** + * @brief DMA SD communication error callback + * @param hdma: DMA handle + * @retval None + */ +static void SD_DMAError(DMA_HandleTypeDef *hdma) +{ + SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); + HAL_SD_CardStateTypeDef CardState; + uint32_t RxErrorCode, TxErrorCode; + + /* if DMA error is FIFO error ignore it */ + if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) + { + RxErrorCode = hsd->hdmarx->ErrorCode; + TxErrorCode = hsd->hdmatx->ErrorCode; + if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE)) + { + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + + /* Disable All interrupts */ + __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\ + SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR); + + hsd->ErrorCode |= HAL_SD_ERROR_DMA; + CardState = HAL_SD_GetCardState(hsd); + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + { + hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); + } + + hsd->State= HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + } + +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->ErrorCallback(hsd); +#else + HAL_SD_ErrorCallback(hsd); +#endif + } +} + +/** + * @brief DMA SD Tx Abort callback + * @param hdma: DMA handle + * @retval None + */ +static void SD_DMATxAbort(DMA_HandleTypeDef *hdma) +{ + SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); + HAL_SD_CardStateTypeDef CardState; + + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS); + + CardState = HAL_SD_GetCardState(hsd); + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + { + hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); + } + + if(hsd->ErrorCode == HAL_SD_ERROR_NONE) + { +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->AbortCpltCallback(hsd); +#else + HAL_SD_AbortCallback(hsd); +#endif + } + else + { +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->ErrorCallback(hsd); +#else + HAL_SD_ErrorCallback(hsd); +#endif + } +} + +/** + * @brief DMA SD Rx Abort callback + * @param hdma: DMA handle + * @retval None + */ +static void SD_DMARxAbort(DMA_HandleTypeDef *hdma) +{ + SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); + HAL_SD_CardStateTypeDef CardState; + + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS); + + CardState = HAL_SD_GetCardState(hsd); + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + { + hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); + } + + if(hsd->ErrorCode == HAL_SD_ERROR_NONE) + { +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->AbortCpltCallback(hsd); +#else + HAL_SD_AbortCallback(hsd); +#endif + } + else + { +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->ErrorCallback(hsd); +#else + HAL_SD_ErrorCallback(hsd); +#endif + } +} + +/** + * @brief Initializes the sd card. + * @param hsd: Pointer to SD handle + * @retval SD Card error state + */ +static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) +{ + HAL_SD_CardCSDTypeDef CSD; + uint32_t errorstate; + uint16_t sd_rca = 1U; + + /* Check the power State */ + if(SDIO_GetPowerState(hsd->Instance) == 0U) + { + /* Power off */ + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + } + + if(hsd->SdCard.CardType != CARD_SECURED) + { + /* Send CMD2 ALL_SEND_CID */ + errorstate = SDMMC_CmdSendCID(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + else + { + /* Get Card identification number data */ + hsd->CID[0U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1); + hsd->CID[1U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2); + hsd->CID[2U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3); + hsd->CID[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4); + } + } + + if(hsd->SdCard.CardType != CARD_SECURED) + { + /* Send CMD3 SET_REL_ADDR with argument 0 */ + /* SD Card publishes its RCA. */ + errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + } + if(hsd->SdCard.CardType != CARD_SECURED) + { + /* Get the SD card RCA */ + hsd->SdCard.RelCardAdd = sd_rca; + + /* Send CMD9 SEND_CSD with argument as card's RCA */ + errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + else + { + /* Get Card Specific Data */ + hsd->CSD[0U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1); + hsd->CSD[1U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2); + hsd->CSD[2U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3); + hsd->CSD[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4); + } + } + + /* Get the Card Class */ + hsd->SdCard.Class = (SDIO_GetResponse(hsd->Instance, SDIO_RESP2) >> 20U); + + /* Get CSD parameters */ + if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK) + { + return HAL_SD_ERROR_UNSUPPORTED_FEATURE; + } + + /* Select the Card */ + errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U)); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Configure SDIO peripheral interface */ + (void)SDIO_Init(hsd->Instance, hsd->Init); + + /* All cards are initialized */ + return HAL_SD_ERROR_NONE; +} + +/** + * @brief Enquires cards about their operating voltage and configures clock + * controls and stores SD information that will be needed in future + * in the SD handle. + * @param hsd: Pointer to SD handle + * @retval error state + */ +static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) +{ + __IO uint32_t count = 0U; + uint32_t response = 0U, validvoltage = 0U; + uint32_t errorstate; + + /* CMD0: GO_IDLE_STATE */ + errorstate = SDMMC_CmdGoIdleState(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */ + errorstate = SDMMC_CmdOperCond(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->SdCard.CardVersion = CARD_V1_X; + /* CMD0: GO_IDLE_STATE */ + errorstate = SDMMC_CmdGoIdleState(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + } + else + { + hsd->SdCard.CardVersion = CARD_V2_X; + } + + if( hsd->SdCard.CardVersion == CARD_V2_X) + { + /* SEND CMD55 APP_CMD with RCA as 0 */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); + if(errorstate != HAL_SD_ERROR_NONE) + { + return HAL_SD_ERROR_UNSUPPORTED_FEATURE; + } + } + /* SD CARD */ + /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ + while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U)) + { + /* SEND CMD55 APP_CMD with RCA as 0 */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Send CMD41 */ + errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | SD_SWITCH_1_8V_CAPACITY); + if(errorstate != HAL_SD_ERROR_NONE) + { + return HAL_SD_ERROR_UNSUPPORTED_FEATURE; + } + + /* Get command response */ + response = SDIO_GetResponse(hsd->Instance, SDIO_RESP1); + + /* Get operating voltage*/ + validvoltage = (((response >> 31U) == 1U) ? 1U : 0U); + + count++; + } + + if(count >= SDMMC_MAX_VOLT_TRIAL) + { + return HAL_SD_ERROR_INVALID_VOLTRANGE; + } + + if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */ + { + hsd->SdCard.CardType = CARD_SDHC_SDXC; + } + else + { + hsd->SdCard.CardType = CARD_SDSC; + } + + + return HAL_SD_ERROR_NONE; +} + +/** + * @brief Turns the SDIO output signals off. + * @param hsd: Pointer to SD handle + * @retval None + */ +static void SD_PowerOFF(SD_HandleTypeDef *hsd) +{ + /* Set Power State to OFF */ + (void)SDIO_PowerState_OFF(hsd->Instance); +} + +/** + * @brief Send Status info command. + * @param hsd: pointer to SD handle + * @param pSDstatus: Pointer to the buffer that will contain the SD card status + * SD Status register) + * @retval error state + */ +static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) +{ + SDIO_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t *pData = pSDstatus; + + /* Check SD response */ + if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + { + return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; + } + + /* Set block size for card if it is not equal to current block size for card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_NONE; + return errorstate; + } + + /* Send CMD55 */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_NONE; + return errorstate; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = 64U; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_64B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + (void)SDIO_ConfigData(hsd->Instance, &config); + + /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */ + errorstate = SDMMC_CmdStatusRegister(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_NONE; + return errorstate; + } + + /* Get status data */ + while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND)) + { + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF)) + { + for(count = 0U; count < 8U; count++) + { + *pData = SDIO_ReadFIFO(hsd->Instance); + pData++; + } + } + + if((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) + { + return HAL_SD_ERROR_TIMEOUT; + } + } + +#if defined(SDIO_STA_STBITERR) + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR))) +#else /* SDIO_STA_STBITERR not defined */ + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) +#endif /* SDIO_STA_STBITERR */ + { + return HAL_SD_ERROR_DATA_TIMEOUT; + } + else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) + { + return HAL_SD_ERROR_DATA_CRC_FAIL; + } + else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR)) + { + return HAL_SD_ERROR_RX_OVERRUN; + } + else + { + /* Nothing to do */ + } + + while ((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL))) + { + *pData = SDIO_ReadFIFO(hsd->Instance); + pData++; + + if((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) + { + return HAL_SD_ERROR_TIMEOUT; + } + } + + /* Clear all the static status flags*/ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS); + + return HAL_SD_ERROR_NONE; +} + +/** + * @brief Returns the current card's status. + * @param hsd: Pointer to SD handle + * @param pCardStatus: pointer to the buffer that will contain the SD card + * status (Card Status register) + * @retval error state + */ +static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) +{ + uint32_t errorstate; + + if(pCardStatus == NULL) + { + return HAL_SD_ERROR_PARAM; + } + + /* Send Status command */ + errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Get SD card status */ + *pCardStatus = SDIO_GetResponse(hsd->Instance, SDIO_RESP1); + + return HAL_SD_ERROR_NONE; +} + +/** + * @brief Enables the SDIO wide bus mode. + * @param hsd: pointer to SD handle + * @retval error state + */ +static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) +{ + uint32_t scr[2U] = {0U, 0U}; + uint32_t errorstate; + + if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + { + return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; + } + + /* Get SCR Register */ + errorstate = SD_FindSCR(hsd, scr); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* If requested card supports wide bus operation */ + if((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO) + { + /* Send CMD55 APP_CMD with argument as card's RCA.*/ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ + errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + return HAL_SD_ERROR_NONE; + } + else + { + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + } +} + +/** + * @brief Disables the SDIO wide bus mode. + * @param hsd: Pointer to SD handle + * @retval error state + */ +static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) +{ + uint32_t scr[2U] = {0U, 0U}; + uint32_t errorstate; + + if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + { + return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; + } + + /* Get SCR Register */ + errorstate = SD_FindSCR(hsd, scr); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* If requested card supports 1 bit mode operation */ + if((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO) + { + /* Send CMD55 APP_CMD with argument as card's RCA */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */ + errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + return HAL_SD_ERROR_NONE; + } + else + { + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + } +} + + +/** + * @brief Finds the SD card SCR register value. + * @param hsd: Pointer to SD handle + * @param pSCR: pointer to the buffer that will contain the SCR value + * @retval error state + */ +static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) +{ + SDIO_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t index = 0U; + uint32_t tempscr[2U] = {0U, 0U}; + uint32_t *scr = pSCR; + + /* Set Block Size To 8 Bytes */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Send CMD55 APP_CMD with argument as card's RCA */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U)); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = 8U; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_8B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + (void)SDIO_ConfigData(hsd->Instance, &config); + + /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */ + errorstate = SDMMC_CmdSendSCR(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT)) + { + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) + { + *(tempscr + index) = SDIO_ReadFIFO(hsd->Instance); + index++; + } + else if(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXACT)) + { + break; + } + + if((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) + { + return HAL_SD_ERROR_TIMEOUT; + } + } + +#if defined(SDIO_STA_STBITERR) + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR))) +#else /* SDIO_STA_STBITERR not defined */ + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) +#endif /* SDIO_STA_STBITERR */ + { + __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT); + + return HAL_SD_ERROR_DATA_TIMEOUT; + } + else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL); + + return HAL_SD_ERROR_DATA_CRC_FAIL; + } + else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR); + + return HAL_SD_ERROR_RX_OVERRUN; + } + else + { + /* No error flag set */ + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS); + + *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\ + ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24)); + scr++; + *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\ + ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24)); + + } + + return HAL_SD_ERROR_NONE; +} + +/** + * @brief Wrap up reading in non-blocking mode. + * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * the configuration information. + * @retval None + */ +static void SD_Read_IT(SD_HandleTypeDef *hsd) +{ + uint32_t count, data, dataremaining; + uint8_t* tmp; + + tmp = hsd->pRxBuffPtr; + dataremaining = hsd->RxXferSize; + + if (dataremaining > 0U) + { + /* Read data from SDIO Rx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = SDIO_ReadFIFO(hsd->Instance); + *tmp = (uint8_t)(data & 0xFFU); + tmp++; + dataremaining--; + *tmp = (uint8_t)((data >> 8U) & 0xFFU); + tmp++; + dataremaining--; + *tmp = (uint8_t)((data >> 16U) & 0xFFU); + tmp++; + dataremaining--; + *tmp = (uint8_t)((data >> 24U) & 0xFFU); + tmp++; + dataremaining--; + } + + hsd->pRxBuffPtr = tmp; + hsd->RxXferSize = dataremaining; + } +} + +/** + * @brief Wrap up writing in non-blocking mode. + * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * the configuration information. + * @retval None + */ +static void SD_Write_IT(SD_HandleTypeDef *hsd) +{ + uint32_t count, data, dataremaining; + uint8_t* tmp; + + tmp = hsd->pTxBuffPtr; + dataremaining = hsd->TxXferSize; + + if (dataremaining > 0U) + { + /* Write data to SDIO Tx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = (uint32_t)(*tmp); + tmp++; + dataremaining--; + data |= ((uint32_t)(*tmp) << 8U); + tmp++; + dataremaining--; + data |= ((uint32_t)(*tmp) << 16U); + tmp++; + dataremaining--; + data |= ((uint32_t)(*tmp) << 24U); + tmp++; + dataremaining--; + (void)SDIO_WriteFIFO(hsd->Instance, &data); + } + + hsd->pTxBuffPtr = tmp; + hsd->TxXferSize = dataremaining; + } +} + +/** + * @} + */ + +#endif /* HAL_SD_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* SDIO */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c new file mode 100644 index 0000000..ab48303 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c @@ -0,0 +1,1578 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_sdmmc.c + * @author MCD Application Team + * @brief SDMMC Low Layer HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the SDMMC peripheral: + * + Initialization/de-initialization functions + * + I/O operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### SDMMC peripheral features ##### + ============================================================================== + [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the AHB + peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA + devices. + + [..] The SDMMC features include the following: + (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support + for three different databus modes: 1-bit (default), 4-bit and 8-bit + (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility) + (+) Full compliance with SD Memory Card Specifications Version 2.0 + (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two + different data bus modes: 1-bit (default) and 4-bit + (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol + Rev1.1) + (+) Data transfer up to 48 MHz for the 8 bit mode + (+) Data and command output enable signals to control external bidirectional drivers + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver is a considered as a driver of service for external devices drivers + that interfaces with the SDMMC peripheral. + According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs + is used in the device's driver to perform SDMMC operations and functionalities. + + This driver is almost transparent for the final user, it is only used to implement other + functionalities of the external device. + + [..] + (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output (MSI, PLLUSB1CLK, + PLLUSB2CLK). Before start working with SDMMC peripheral make sure that the + PLL is well configured. + The SDMMC peripheral uses two clock signals: + (++) SDMMC adapter clock (SDMMCCLK = 48 MHz) + (++) APB2 bus clock (PCLK2) + + -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition: + Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK)) + + (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC + peripheral. + + (+) Enable the Power ON State using the SDIO_PowerState_ON() + function and disable it using the function SDIO_PowerState_OFF(). + + (+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros. + + (+) Enable/Disable the peripheral interrupts using the macros __SDIO_ENABLE_IT() + and __SDIO_DISABLE_IT() if you need to use interrupt mode. + + (+) When using the DMA mode + (++) Configure the DMA in the MSP layer of the external device + (++) Active the needed channel Request + (++) Enable the DMA using __SDIO_DMA_ENABLE() macro or Disable it using the macro + __SDIO_DMA_DISABLE(). + + (+) To control the CPSM (Command Path State Machine) and send + commands to the card use the SDIO_SendCommand(), + SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has + to fill the command structure (pointer to SDIO_CmdInitTypeDef) according + to the selected command to be sent. + The parameters that should be filled are: + (++) Command Argument + (++) Command Index + (++) Command Response type + (++) Command Wait + (++) CPSM Status (Enable or Disable). + + -@@- To check if the command is well received, read the SDIO_CMDRESP + register using the SDIO_GetCommandResponse(). + The SDMMC responses registers (SDIO_RESP1 to SDIO_RESP2), use the + SDIO_GetResponse() function. + + (+) To control the DPSM (Data Path State Machine) and send/receive + data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), + SDIO_ReadFIFO(), SDIO_WriteFIFO() and SDIO_GetFIFOCount() functions. + + *** Read Operations *** + ======================= + [..] + (#) First, user has to fill the data structure (pointer to + SDIO_DataInitTypeDef) according to the selected data type to be received. + The parameters that should be filled are: + (++) Data TimeOut + (++) Data Length + (++) Data Block size + (++) Data Transfer direction: should be from card (To SDMMC) + (++) Data Transfer mode + (++) DPSM Status (Enable or Disable) + + (#) Configure the SDMMC resources to receive the data from the card + according to selected transfer mode (Refer to Step 8, 9 and 10). + + (#) Send the selected Read command (refer to step 11). + + (#) Use the SDIO flags/interrupts to check the transfer status. + + *** Write Operations *** + ======================== + [..] + (#) First, user has to fill the data structure (pointer to + SDIO_DataInitTypeDef) according to the selected data type to be received. + The parameters that should be filled are: + (++) Data TimeOut + (++) Data Length + (++) Data Block size + (++) Data Transfer direction: should be to card (To CARD) + (++) Data Transfer mode + (++) DPSM Status (Enable or Disable) + + (#) Configure the SDMMC resources to send the data to the card according to + selected transfer mode. + + (#) Send the selected Write command. + + (#) Use the SDIO flags/interrupts to check the transfer status. + + *** Command management operations *** + ===================================== + [..] + (#) The commands used for Read/Write/Erase operations are managed in + separate functions. + Each function allows to send the needed command with the related argument, + then check the response. + By the same approach, you could implement a command and check the response. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +#if defined(SDIO) + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup SDMMC_LL SDMMC Low Layer + * @brief Low layer module for SD + * @{ + */ + +#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx); + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions + * @{ + */ + +/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization/de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the SDMMC according to the specified + * parameters in the SDMMC_InitTypeDef and create the associated handle. + * @param SDIOx: Pointer to SDMMC register base + * @param Init: SDMMC initialization structure + * @retval HAL status + */ +HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_ALL_INSTANCE(SDIOx)); + assert_param(IS_SDIO_CLOCK_EDGE(Init.ClockEdge)); + assert_param(IS_SDIO_CLOCK_BYPASS(Init.ClockBypass)); + assert_param(IS_SDIO_CLOCK_POWER_SAVE(Init.ClockPowerSave)); + assert_param(IS_SDIO_BUS_WIDE(Init.BusWide)); + assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl)); + assert_param(IS_SDIO_CLKDIV(Init.ClockDiv)); + + /* Set SDMMC configuration parameters */ + tmpreg |= (Init.ClockEdge |\ + Init.ClockBypass |\ + Init.ClockPowerSave |\ + Init.BusWide |\ + Init.HardwareFlowControl |\ + Init.ClockDiv + ); + + /* Write to SDMMC CLKCR */ + MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, tmpreg); + + return HAL_OK; +} + + +/** + * @} + */ + +/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### I/O operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SDMMC data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Read data (word) from Rx FIFO in blocking mode (polling) + * @param SDIOx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx) +{ + /* Read data from Rx FIFO */ + return (SDIOx->FIFO); +} + +/** + * @brief Write data (word) to Tx FIFO in blocking mode (polling) + * @param SDIOx: Pointer to SDMMC register base + * @param pWriteData: pointer to data to write + * @retval HAL status + */ +HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData) +{ + /* Write data to FIFO */ + SDIOx->FIFO = *pWriteData; + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SDMMC data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Set SDMMC Power state to ON. + * @param SDIOx: Pointer to SDMMC register base + * @retval HAL status + */ +HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx) +{ + /* Set power state to ON */ + SDIOx->POWER = SDIO_POWER_PWRCTRL; + + return HAL_OK; +} + +/** + * @brief Set SDMMC Power state to OFF. + * @param SDIOx: Pointer to SDMMC register base + * @retval HAL status + */ +HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx) +{ + /* Set power state to OFF */ + SDIOx->POWER = (uint32_t)0x00000000; + + return HAL_OK; +} + +/** + * @brief Get SDMMC Power state. + * @param SDIOx: Pointer to SDMMC register base + * @retval Power status of the controller. The returned value can be one of the + * following values: + * - 0x00: Power OFF + * - 0x02: Power UP + * - 0x03: Power ON + */ +uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx) +{ + return (SDIOx->POWER & SDIO_POWER_PWRCTRL); +} + +/** + * @brief Configure the SDMMC command path according to the specified parameters in + * SDIO_CmdInitTypeDef structure and send the command + * @param SDIOx: Pointer to SDMMC register base + * @param Command: pointer to a SDIO_CmdInitTypeDef structure that contains + * the configuration information for the SDMMC command + * @retval HAL status + */ +HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_CMD_INDEX(Command->CmdIndex)); + assert_param(IS_SDIO_RESPONSE(Command->Response)); + assert_param(IS_SDIO_WAIT(Command->WaitForInterrupt)); + assert_param(IS_SDIO_CPSM(Command->CPSM)); + + /* Set the SDMMC Argument value */ + SDIOx->ARG = Command->Argument; + + /* Set SDMMC command parameters */ + tmpreg |= (uint32_t)(Command->CmdIndex |\ + Command->Response |\ + Command->WaitForInterrupt |\ + Command->CPSM); + + /* Write to SDMMC CMD register */ + MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, tmpreg); + + return HAL_OK; +} + +/** + * @brief Return the command index of last command for which response received + * @param SDIOx: Pointer to SDMMC register base + * @retval Command index of the last command response received + */ +uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx) +{ + return (uint8_t)(SDIOx->RESPCMD); +} + + +/** + * @brief Return the response received from the card for the last command + * @param SDIOx: Pointer to SDMMC register base + * @param Response: Specifies the SDMMC response register. + * This parameter can be one of the following values: + * @arg SDIO_RESP1: Response Register 1 + * @arg SDIO_RESP2: Response Register 2 + * @arg SDIO_RESP3: Response Register 3 + * @arg SDIO_RESP4: Response Register 4 + * @retval The Corresponding response register value + */ +uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_SDIO_RESP(Response)); + + /* Get the response */ + tmp = (uint32_t)(&(SDIOx->RESP1)) + Response; + + return (*(__IO uint32_t *) tmp); +} + +/** + * @brief Configure the SDMMC data path according to the specified + * parameters in the SDIO_DataInitTypeDef. + * @param SDIOx: Pointer to SDIO register base + * @param Data : pointer to a SDIO_DataInitTypeDef structure + * that contains the configuration information for the SDMMC data. + * @retval HAL status + */ +HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_DATA_LENGTH(Data->DataLength)); + assert_param(IS_SDIO_BLOCK_SIZE(Data->DataBlockSize)); + assert_param(IS_SDIO_TRANSFER_DIR(Data->TransferDir)); + assert_param(IS_SDIO_TRANSFER_MODE(Data->TransferMode)); + assert_param(IS_SDIO_DPSM(Data->DPSM)); + + /* Set the SDMMC Data TimeOut value */ + SDIOx->DTIMER = Data->DataTimeOut; + + /* Set the SDMMC DataLength value */ + SDIOx->DLEN = Data->DataLength; + + /* Set the SDMMC data configuration parameters */ + tmpreg |= (uint32_t)(Data->DataBlockSize |\ + Data->TransferDir |\ + Data->TransferMode |\ + Data->DPSM); + + /* Write to SDMMC DCTRL */ + MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, tmpreg); + + return HAL_OK; + +} + +/** + * @brief Returns number of remaining data bytes to be transferred. + * @param SDIOx: Pointer to SDIO register base + * @retval Number of remaining data bytes to be transferred + */ +uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx) +{ + return (SDIOx->DCOUNT); +} + +/** + * @brief Get the FIFO data + * @param SDIOx: Pointer to SDIO register base + * @retval Data received + */ +uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx) +{ + return (SDIOx->FIFO); +} + +/** + * @brief Sets one of the two options of inserting read wait interval. + * @param SDIOx: Pointer to SDIO register base + * @param SDIO_ReadWaitMode: SDMMC Read Wait operation mode. + * This parameter can be: + * @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK + * @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2 + * @retval None + */ +HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode) +{ + /* Check the parameters */ + assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); + + /* Set SDMMC read wait mode */ + MODIFY_REG(SDIOx->DCTRL, SDIO_DCTRL_RWMOD, SDIO_ReadWaitMode); + + return HAL_OK; +} + +/** + * @} + */ + + +/** @defgroup HAL_SDMMC_LL_Group4 Command management functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### Commands management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the needed commands. + +@endverbatim + * @{ + */ + +/** + * @brief Send the Data Block Length command and check the response + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)BlockSize; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCKLEN; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SET_BLOCKLEN, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Read Single Block command and check the response + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_SINGLE_BLOCK; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_SINGLE_BLOCK, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Read Multi Block command and check the response + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_MULT_BLOCK; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_MULT_BLOCK, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Write Single Block command and check the response + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_SINGLE_BLOCK; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Write Multi Block command and check the response + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_MULT_BLOCK; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_MULT_BLOCK, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Start Address Erase command for SD and check the response + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)StartAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_START; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_ERASE_GRP_START, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the End Address Erase command for SD and check the response + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)EndAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_END; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_ERASE_GRP_END, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Start Address Erase command and check the response + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)StartAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_START; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE_GRP_START, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the End Address Erase command and check the response + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)EndAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_END; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE_GRP_END, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Erase command and check the response + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = 0U; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE, SDIO_MAXERASETIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Stop Transfer command and check the response. + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD12 STOP_TRANSMISSION */ + sdmmc_cmdinit.Argument = 0U; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_STOP_TRANSMISSION; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_STOP_TRANSMISSION, SDIO_STOPTRANSFERTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Select Deselect command and check the response. + * @param SDIOx: Pointer to SDIO register base + * @param addr: Address of the card to be selected + * @retval HAL status + */ +uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD7 SDMMC_SEL_DESEL_CARD */ + sdmmc_cmdinit.Argument = (uint32_t)Addr; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEL_DESEL_CARD; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEL_DESEL_CARD, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Go Idle State command and check the response. + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = 0U; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE; + sdmmc_cmdinit.Response = SDIO_RESPONSE_NO; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdError(SDIOx); + + return errorstate; +} + +/** + * @brief Send the Operating Condition command and check the response. + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD8 to verify SD card interface operating condition */ + /* Argument: - [31:12]: Reserved (shall be set to '0') + - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) + - [7:0]: Check Pattern (recommended 0xAA) */ + /* CMD Response: R7 */ + sdmmc_cmdinit.Argument = SDMMC_CHECK_PATTERN; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp7(SDIOx); + + return errorstate; +} + +/** + * @brief Send the Application command to verify that that the next command + * is an application specific com-mand rather than a standard command + * and check the response. + * @param SDIOx: Pointer to SDIO register base + * @param Argument: Command Argument + * @retval HAL status + */ +uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = (uint32_t)Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_CMD; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + /* If there is a HAL_ERROR, it is a MMC card, else + it is a SD card: SD card 2.0 (voltage range mismatch) + or SD card 1.x */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_CMD, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the command asking the accessed card to send its operating + * condition register (OCR) + * @param SDIOx: Pointer to SDIO register base + * @param Argument: Command Argument + * @retval HAL status + */ +uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t Argument) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = SDMMC_VOLTAGE_WINDOW_SD | Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp3(SDIOx); + + return errorstate; +} + +/** + * @brief Send the Bus Width command and check the response. + * @param SDIOx: Pointer to SDIO register base + * @param BusWidth: BusWidth + * @retval HAL status + */ +uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = (uint32_t)BusWidth; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_SD_SET_BUSWIDTH; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Send SCR command and check the response. + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD51 SD_APP_SEND_SCR */ + sdmmc_cmdinit.Argument = 0U; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_SEND_SCR; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_SEND_SCR, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Send CID command and check the response. + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD2 ALL_SEND_CID */ + sdmmc_cmdinit.Argument = 0U; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ALL_SEND_CID; + sdmmc_cmdinit.Response = SDIO_RESPONSE_LONG; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp2(SDIOx); + + return errorstate; +} + +/** + * @brief Send the Send CSD command and check the response. + * @param SDIOx: Pointer to SDIO register base + * @param Argument: Command Argument + * @retval HAL status + */ +uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD9 SEND_CSD */ + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_CSD; + sdmmc_cmdinit.Response = SDIO_RESPONSE_LONG; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp2(SDIOx); + + return errorstate; +} + +/** + * @brief Send the Send CSD command and check the response. + * @param SDIOx: Pointer to SDIO register base + * @param pRCA: Card RCA + * @retval HAL status + */ +uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD3 SD_CMD_SET_REL_ADDR */ + sdmmc_cmdinit.Argument = 0U; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp6(SDIOx, SDMMC_CMD_SET_REL_ADDR, pRCA); + + return errorstate; +} + +/** + * @brief Send the Set Relative Address command to MMC card (not SD card). + * @param SDIOx Pointer to SDIO register base + * @param RCA Card RCA + * @retval HAL status + */ +uint32_t SDMMC_CmdSetRelAddMmc(SDIO_TypeDef *SDIOx, uint16_t RCA) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD3 SD_CMD_SET_REL_ADDR */ + sdmmc_cmdinit.Argument = ((uint32_t)RCA << 16U); + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SET_REL_ADDR, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Status command and check the response. + * @param SDIOx: Pointer to SDIO register base + * @param Argument: Command Argument + * @retval HAL status + */ +uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_STATUS; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEND_STATUS, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Status register command and check the response. + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = 0U; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_STATUS; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_STATUS, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Sends host capacity support information and activates the card's + * initialization process. Send SDMMC_CMD_SEND_OP_COND command + * @param SDIOx: Pointer to SDIO register base + * @parame Argument: Argument used for the command + * @retval HAL status + */ +uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_OP_COND; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp3(SDIOx); + + return errorstate; +} + +/** + * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH command + * @param SDIOx: Pointer to SDIO register base + * @parame Argument: Argument used for the command + * @retval HAL status + */ +uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD6 to activate SDR50 Mode and Power Limit 1.44W */ + /* CMD Response: R1 */ + sdmmc_cmdinit.Argument = Argument; /* SDMMC_SDR25_SWITCH_PATTERN */ + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SWITCH; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_HS_SWITCH, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Send EXT_CSD command and check the response. + * @param SDIOx Pointer to SDMMC register base + * @param Argument Command Argument + * @retval HAL status + */ +uint32_t SDMMC_CmdSendEXTCSD(SDIO_TypeDef *SDIOx, uint32_t Argument) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD9 SEND_CSD */ + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_HS_SEND_EXT_CSD,SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @} + */ + +/** @defgroup HAL_SDMMC_LL_Group5 Responses management functions + * @brief Responses functions + * +@verbatim + =============================================================================== + ##### Responses management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the needed responses. + +@endverbatim + * @{ + */ +/** + * @brief Checks for error conditions for R1 response. + * @param SDIOx Pointer to SDMMC register base + * @param SD_CMD: The sent command index + * @retval SD Card error state + */ +uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout) +{ + uint32_t response_r1; + uint32_t sta_reg; + + /* 8 is the number of required instructions cycles for the below loop statement. + The Timeout is expressed in ms */ + uint32_t count = Timeout * (SystemCoreClock / 8U /1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + sta_reg = SDIOx->STA; + }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDIO_FLAG_CMDACT) != 0U )); + + if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) + { + __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL)) + { + __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL); + + return SDMMC_ERROR_CMD_CRC_FAIL; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS); + + /* Check response received is of desired command */ + if(SDIO_GetCommandResponse(SDIOx) != SD_CMD) + { + return SDMMC_ERROR_CMD_CRC_FAIL; + } + + /* We have received response, retrieve it for analysis */ + response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1); + + if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO) + { + return SDMMC_ERROR_NONE; + } + else if((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE) + { + return SDMMC_ERROR_ADDR_OUT_OF_RANGE; + } + else if((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED) + { + return SDMMC_ERROR_ADDR_MISALIGNED; + } + else if((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR) + { + return SDMMC_ERROR_BLOCK_LEN_ERR; + } + else if((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR) + { + return SDMMC_ERROR_ERASE_SEQ_ERR; + } + else if((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM) + { + return SDMMC_ERROR_BAD_ERASE_PARAM; + } + else if((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION) + { + return SDMMC_ERROR_WRITE_PROT_VIOLATION; + } + else if((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED) + { + return SDMMC_ERROR_LOCK_UNLOCK_FAILED; + } + else if((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED) + { + return SDMMC_ERROR_COM_CRC_FAILED; + } + else if((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD) + { + return SDMMC_ERROR_ILLEGAL_CMD; + } + else if((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED) + { + return SDMMC_ERROR_CARD_ECC_FAILED; + } + else if((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR) + { + return SDMMC_ERROR_CC_ERR; + } + else if((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN) + { + return SDMMC_ERROR_STREAM_READ_UNDERRUN; + } + else if((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN) + { + return SDMMC_ERROR_STREAM_WRITE_OVERRUN; + } + else if((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE) + { + return SDMMC_ERROR_CID_CSD_OVERWRITE; + } + else if((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP) + { + return SDMMC_ERROR_WP_ERASE_SKIP; + } + else if((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED) + { + return SDMMC_ERROR_CARD_ECC_DISABLED; + } + else if((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET) + { + return SDMMC_ERROR_ERASE_RESET; + } + else if((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR) + { + return SDMMC_ERROR_AKE_SEQ_ERR; + } + else + { + return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } +} + +/** + * @brief Checks for error conditions for R2 (CID or CSD) response. + * @param SDIOx Pointer to SDMMC register base + * @retval SD Card error state + */ +uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx) +{ + uint32_t sta_reg; + /* 8 is the number of required instructions cycles for the below loop statement. + The SDIO_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + sta_reg = SDIOx->STA; + }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDIO_FLAG_CMDACT) != 0U )); + + if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) + { + __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL)) + { + __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL); + + return SDMMC_ERROR_CMD_CRC_FAIL; + } + else + { + /* No error flag set */ + /* Clear all the static flags */ + __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS); + } + + return SDMMC_ERROR_NONE; +} + +/** + * @brief Checks for error conditions for R3 (OCR) response. + * @param SDIOx Pointer to SDMMC register base + * @retval SD Card error state + */ +uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx) +{ + uint32_t sta_reg; + /* 8 is the number of required instructions cycles for the below loop statement. + The SDIO_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + sta_reg = SDIOx->STA; + }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDIO_FLAG_CMDACT) != 0U )); + + if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) + { + __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else + { + /* Clear all the static flags */ + __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS); + } + + return SDMMC_ERROR_NONE; +} + +/** + * @brief Checks for error conditions for R6 (RCA) response. + * @param SDIOx Pointer to SDMMC register base + * @param SD_CMD: The sent command index + * @param pRCA: Pointer to the variable that will contain the SD card relative + * address RCA + * @retval SD Card error state + */ +uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA) +{ + uint32_t response_r1; + uint32_t sta_reg; + + /* 8 is the number of required instructions cycles for the below loop statement. + The SDIO_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + sta_reg = SDIOx->STA; + }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDIO_FLAG_CMDACT) != 0U )); + + if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) + { + __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL)) + { + __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL); + + return SDMMC_ERROR_CMD_CRC_FAIL; + } + else + { + /* Nothing to do */ + } + + /* Check response received is of desired command */ + if(SDIO_GetCommandResponse(SDIOx) != SD_CMD) + { + return SDMMC_ERROR_CMD_CRC_FAIL; + } + + /* Clear all the static flags */ + __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS); + + /* We have received response, retrieve it. */ + response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1); + + if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO) + { + *pRCA = (uint16_t) (response_r1 >> 16); + + return SDMMC_ERROR_NONE; + } + else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD) + { + return SDMMC_ERROR_ILLEGAL_CMD; + } + else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED) + { + return SDMMC_ERROR_COM_CRC_FAILED; + } + else + { + return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } +} + +/** + * @brief Checks for error conditions for R7 response. + * @param SDIOx Pointer to SDMMC register base + * @retval SD Card error state + */ +uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx) +{ + uint32_t sta_reg; + /* 8 is the number of required instructions cycles for the below loop statement. + The SDIO_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + sta_reg = SDIOx->STA; + }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDIO_FLAG_CMDACT) != 0U )); + + if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) + { + /* Card is SD V2.0 compliant */ + __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL)) + { + /* Card is SD V2.0 compliant */ + __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL); + + return SDMMC_ERROR_CMD_CRC_FAIL; + } + else + { + /* Nothing to do */ + } + + if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDREND)) + { + /* Card is SD V2.0 compliant */ + __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CMDREND); + } + + return SDMMC_ERROR_NONE; + +} + +/** + * @} + */ + +/* Private function ----------------------------------------------------------*/ +/** @addtogroup SD_Private_Functions + * @{ + */ + +/** + * @brief Checks for error conditions for CMD0. + * @param SDIOx Pointer to SDMMC register base + * @retval SD Card error state + */ +static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx) +{ + /* 8 is the number of required instructions cycles for the below loop statement. + The SDIO_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + + }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDSENT)); + + /* Clear all the static flags */ + __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS); + + return SDMMC_ERROR_NONE; +} + + +/** + * @} + */ + +#endif /* HAL_SD_MODULE_ENABLED || HAL_MMC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* SDIO */ diff --git a/can_logger.ioc b/can_logger.ioc index 899e2c5..ee21eb6 100644 --- a/can_logger.ioc +++ b/can_logger.ioc @@ -2,14 +2,47 @@ CAD.formats= CAD.pinconfig= CAD.provider= -CAN1.CalculateBaudRate=333333 -CAN1.CalculateTimeBit=3000 -CAN1.CalculateTimeQuantum=1000.0 -CAN1.IPParameters=CalculateTimeQuantum,CalculateTimeBit,CalculateBaudRate -CAN2.CalculateBaudRate=333333 -CAN2.CalculateTimeBit=3000 -CAN2.CalculateTimeQuantum=1000.0 -CAN2.IPParameters=CalculateTimeQuantum,CalculateTimeBit,CalculateBaudRate +CAN1.BS1=CAN_BS1_1TQ +CAN1.BS2=CAN_BS2_1TQ +CAN1.CalculateBaudRate=875000 +CAN1.CalculateTimeBit=1142 +CAN1.CalculateTimeQuantum=380.95238095238096 +CAN1.IPParameters=CalculateTimeQuantum,CalculateTimeBit,CalculateBaudRate,BS1,BS2 +CAN2.BS1=CAN_BS1_1TQ +CAN2.BS2=CAN_BS2_1TQ +CAN2.CalculateBaudRate=875000 +CAN2.CalculateTimeBit=1142 +CAN2.CalculateTimeQuantum=380.95238095238096 +CAN2.IPParameters=CalculateTimeQuantum,CalculateTimeBit,CalculateBaudRate,BS1,BS2 +Dma.Request0=SDIO_RX +Dma.Request1=SDIO_TX +Dma.RequestsNb=2 +Dma.SDIO_RX.0.Direction=DMA_PERIPH_TO_MEMORY +Dma.SDIO_RX.0.FIFOMode=DMA_FIFOMODE_ENABLE +Dma.SDIO_RX.0.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL +Dma.SDIO_RX.0.Instance=DMA2_Stream3 +Dma.SDIO_RX.0.MemBurst=DMA_MBURST_INC4 +Dma.SDIO_RX.0.MemDataAlignment=DMA_MDATAALIGN_WORD +Dma.SDIO_RX.0.MemInc=DMA_MINC_ENABLE +Dma.SDIO_RX.0.Mode=DMA_PFCTRL +Dma.SDIO_RX.0.PeriphBurst=DMA_PBURST_INC4 +Dma.SDIO_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_WORD +Dma.SDIO_RX.0.PeriphInc=DMA_PINC_DISABLE +Dma.SDIO_RX.0.Priority=DMA_PRIORITY_LOW +Dma.SDIO_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst +Dma.SDIO_TX.1.Direction=DMA_MEMORY_TO_PERIPH +Dma.SDIO_TX.1.FIFOMode=DMA_FIFOMODE_ENABLE +Dma.SDIO_TX.1.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL +Dma.SDIO_TX.1.Instance=DMA2_Stream6 +Dma.SDIO_TX.1.MemBurst=DMA_MBURST_INC4 +Dma.SDIO_TX.1.MemDataAlignment=DMA_MDATAALIGN_WORD +Dma.SDIO_TX.1.MemInc=DMA_MINC_ENABLE +Dma.SDIO_TX.1.Mode=DMA_PFCTRL +Dma.SDIO_TX.1.PeriphBurst=DMA_PBURST_INC4 +Dma.SDIO_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_WORD +Dma.SDIO_TX.1.PeriphInc=DMA_PINC_DISABLE +Dma.SDIO_TX.1.Priority=DMA_PRIORITY_LOW +Dma.SDIO_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst FREERTOS.IPParameters=Tasks01,configUSE_NEWLIB_REENTRANT FREERTOS.Tasks01=defaultTask,24,128,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL FREERTOS.configUSE_NEWLIB_REENTRANT=1 @@ -20,26 +53,36 @@ Mcu.CPN=STM32F405RGT6 Mcu.Family=STM32F4 Mcu.IP0=CAN1 Mcu.IP1=CAN2 -Mcu.IP2=FREERTOS -Mcu.IP3=NVIC -Mcu.IP4=RCC -Mcu.IP5=SYS -Mcu.IPNb=6 +Mcu.IP2=DMA +Mcu.IP3=FREERTOS +Mcu.IP4=NVIC +Mcu.IP5=RCC +Mcu.IP6=SDIO +Mcu.IP7=SYS +Mcu.IPNb=8 Mcu.Name=STM32F405RGTx Mcu.Package=LQFP64 Mcu.Pin0=PB12 Mcu.Pin1=PB13 -Mcu.Pin2=PB8 -Mcu.Pin3=PB9 -Mcu.Pin4=VP_FREERTOS_VS_CMSIS_V2 -Mcu.Pin5=VP_SYS_VS_tim6 -Mcu.PinsNb=6 +Mcu.Pin10=VP_FREERTOS_VS_CMSIS_V2 +Mcu.Pin11=VP_SYS_VS_tim6 +Mcu.Pin2=PC8 +Mcu.Pin3=PC9 +Mcu.Pin4=PC10 +Mcu.Pin5=PC11 +Mcu.Pin6=PC12 +Mcu.Pin7=PD2 +Mcu.Pin8=PB8 +Mcu.Pin9=PB9 +Mcu.PinsNb=12 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F405RGTx MxCube.Version=6.17.0 MxDb.Version=DB.6.0.170 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +NVIC.DMA2_Stream3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true +NVIC.DMA2_Stream6_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false NVIC.ForceEnableDMAVector=true NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false @@ -47,6 +90,7 @@ NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\: NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false\:false NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SDIO_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false NVIC.SavedPendsvIrqHandlerGenerated=true NVIC.SavedSvcallIrqHandlerGenerated=true @@ -65,6 +109,16 @@ PB8.Signal=CAN1_RX PB9.Locked=true PB9.Mode=CAN_Activate PB9.Signal=CAN1_TX +PC10.Mode=SD_4_bits_Wide_bus +PC10.Signal=SDIO_D2 +PC11.Mode=SD_4_bits_Wide_bus +PC11.Signal=SDIO_D3 +PC12.Mode=SD_4_bits_Wide_bus +PC12.Signal=SDIO_CK +PC8.Mode=SD_4_bits_Wide_bus +PC8.Signal=SDIO_D0 +PC9.Mode=SD_4_bits_Wide_bus +PC9.Signal=SDIO_D1 PCC.Checker=false PCC.Display=Plot\: All Steps PCC.Line=STM32F405/415 @@ -73,6 +127,8 @@ PCC.PartNumber=STM32F405RGTx PCC.Series=STM32F4 PCC.Temperature=25 PCC.Vdd=3.3 +PD2.Mode=SD_4_bits_Wide_bus +PD2.Signal=SDIO_CMD PinOutPanel.RotationAngle=0 ProjectManager.AskForMigrate=true ProjectManager.BackupPrevious=true @@ -108,29 +164,42 @@ ProjectManager.ToolChainLocation= ProjectManager.UAScriptAfterPath= ProjectManager.UAScriptBeforePath= ProjectManager.UnderRoot=true -ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_CAN1_Init-CAN1-false-HAL-true,4-MX_CAN2_Init-CAN2-false-HAL-true -RCC.AHBFreq_Value=16000000 -RCC.APB1Freq_Value=16000000 -RCC.APB2Freq_Value=16000000 -RCC.CortexFreq_Value=16000000 +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_CAN1_Init-CAN1-false-HAL-true,5-MX_CAN2_Init-CAN2-false-HAL-true,6-MX_SDIO_SD_Init-SDIO-false-HAL-true +RCC.48MHZClocksFreq_Value=48000000 +RCC.AHBFreq_Value=168000000 +RCC.APB1CLKDivider=RCC_HCLK_DIV4 +RCC.APB1Freq_Value=42000000 +RCC.APB1TimFreq_Value=84000000 +RCC.APB2CLKDivider=RCC_HCLK_DIV4 +RCC.APB2Freq_Value=42000000 +RCC.APB2TimFreq_Value=84000000 +RCC.CortexFreq_Value=168000000 +RCC.EthernetFreq_Value=168000000 +RCC.FCLKCortexFreq_Value=168000000 RCC.FamilyName=M +RCC.HCLKFreq_Value=168000000 RCC.HSE_VALUE=25000000 RCC.HSI_VALUE=16000000 RCC.I2SClocksFreq_Value=96000000 -RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB2Freq_Value,CortexFreq_Value,FamilyName,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSE_VALUE,LSI_VALUE,PLLCLKFreq_Value,PLLQCLKFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S +RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSE_VALUE,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLN,PLLQ,PLLQCLKFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S RCC.LSE_VALUE=32768 RCC.LSI_VALUE=32000 -RCC.PLLCLKFreq_Value=96000000 +RCC.MCO2PinFreq_Value=168000000 +RCC.PLLCLKFreq_Value=168000000 +RCC.PLLN=336 +RCC.PLLQ=7 RCC.PLLQCLKFreq_Value=48000000 RCC.RTCFreq_Value=32000 RCC.RTCHSEDivFreq_Value=12500000 -RCC.SYSCLKFreq_VALUE=16000000 +RCC.SYSCLKFreq_VALUE=168000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK RCC.VCOI2SOutputFreq_Value=192000000 RCC.VCOInputFreq_Value=1000000 -RCC.VCOOutputFreq_Value=192000000 +RCC.VCOOutputFreq_Value=336000000 RCC.VcooutputI2S=96000000 VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2 VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2 VP_SYS_VS_tim6.Mode=TIM6 VP_SYS_VS_tim6.Signal=SYS_VS_tim6 board=custom +rtos.0.ip=FREERTOS