From 4967cd9b32113c4a40c4441a33b24154df5643e8 Mon Sep 17 00:00:00 2001 From: Erick Ahmed Date: Thu, 18 Jun 2026 06:20:14 +0200 Subject: [PATCH] Add USART DMA in Normal mode from CubeMX --- Core/Inc/stm32f4xx_it.h | 1 + Core/Src/canlog.c | 1 - Core/Src/main.c | 6 +++++- Core/Src/stm32f4xx_hal_msp.c | 23 +++++++++++++++++++++++ Core/Src/stm32f4xx_it.c | 15 +++++++++++++++ can_logger.ioc | 14 +++++++++++++- 6 files changed, 57 insertions(+), 3 deletions(-) diff --git a/Core/Inc/stm32f4xx_it.h b/Core/Inc/stm32f4xx_it.h index e20bc71..08a2693 100644 --- a/Core/Inc/stm32f4xx_it.h +++ b/Core/Inc/stm32f4xx_it.h @@ -56,6 +56,7 @@ void SDIO_IRQHandler(void); void TIM6_DAC_IRQHandler(void); void DMA2_Stream3_IRQHandler(void); void DMA2_Stream6_IRQHandler(void); +void DMA2_Stream7_IRQHandler(void); /* USER CODE BEGIN EFP */ /* USER CODE END EFP */ diff --git a/Core/Src/canlog.c b/Core/Src/canlog.c index 4909412..e6a9811 100644 --- a/Core/Src/canlog.c +++ b/Core/Src/canlog.c @@ -121,7 +121,6 @@ void vCANListener(void *argument) { // J1939 decoding - // RELAY: Push to the UART queue osMessageQueuePut(xUARTQueue, &message, 0U, 0U); } } diff --git a/Core/Src/main.c b/Core/Src/main.c index 8cce2e7..5d02bdd 100644 --- a/Core/Src/main.c +++ b/Core/Src/main.c @@ -46,6 +46,7 @@ DMA_HandleTypeDef hdma_sdio_rx; DMA_HandleTypeDef hdma_sdio_tx; UART_HandleTypeDef huart1; +DMA_HandleTypeDef hdma_usart1_tx; /* USER CODE BEGIN PV */ LED_Config led_can1 = {GPIOB, GPIO_PIN_5}; @@ -386,7 +387,7 @@ static void MX_USART1_UART_Init(void) /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; - huart1.Init.BaudRate = 1152000; + huart1.Init.BaudRate = 115200; huart1.Init.WordLength = UART_WORDLENGTH_8B; huart1.Init.StopBits = UART_STOPBITS_1; huart1.Init.Parity = UART_PARITY_NONE; @@ -419,6 +420,9 @@ static void MX_DMA_Init(void) /* DMA2_Stream6_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Stream6_IRQn, 5, 0); HAL_NVIC_EnableIRQ(DMA2_Stream6_IRQn); + /* DMA2_Stream7_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); /* USER CODE BEGIN MX_DMA_Init 1 */ DEBUG_PRINT("DMA initialized!\r\n"); diff --git a/Core/Src/stm32f4xx_hal_msp.c b/Core/Src/stm32f4xx_hal_msp.c index 6289a5a..61835fe 100644 --- a/Core/Src/stm32f4xx_hal_msp.c +++ b/Core/Src/stm32f4xx_hal_msp.c @@ -26,6 +26,8 @@ extern DMA_HandleTypeDef hdma_sdio_rx; extern DMA_HandleTypeDef hdma_sdio_tx; +extern DMA_HandleTypeDef hdma_usart1_tx; + /* Private typedef -----------------------------------------------------------*/ /* USER CODE BEGIN TD */ @@ -371,6 +373,25 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) GPIO_InitStruct.Alternate = GPIO_AF7_USART1; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + /* USART1 DMA Init */ + /* USART1_TX Init */ + hdma_usart1_tx.Instance = DMA2_Stream7; + hdma_usart1_tx.Init.Channel = DMA_CHANNEL_4; + hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE; + hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_usart1_tx.Init.Mode = DMA_NORMAL; + hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW; + hdma_usart1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(huart,hdmatx,hdma_usart1_tx); + /* USER CODE BEGIN USART1_MspInit 1 */ /* USER CODE END USART1_MspInit 1 */ @@ -401,6 +422,8 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); + /* USART1 DMA DeInit */ + HAL_DMA_DeInit(huart->hdmatx); /* USER CODE BEGIN USART1_MspDeInit 1 */ /* USER CODE END USART1_MspDeInit 1 */ diff --git a/Core/Src/stm32f4xx_it.c b/Core/Src/stm32f4xx_it.c index a10c042..410f57b 100644 --- a/Core/Src/stm32f4xx_it.c +++ b/Core/Src/stm32f4xx_it.c @@ -58,6 +58,7 @@ extern DMA_HandleTypeDef hdma_sdio_rx; extern DMA_HandleTypeDef hdma_sdio_tx; extern SD_HandleTypeDef hsd; +extern DMA_HandleTypeDef hdma_usart1_tx; extern TIM_HandleTypeDef htim6; /* USER CODE BEGIN EV */ @@ -218,6 +219,20 @@ void DMA2_Stream6_IRQHandler(void) /* USER CODE END DMA2_Stream6_IRQn 1 */ } +/** + * @brief This function handles DMA2 stream7 global interrupt. + */ +void DMA2_Stream7_IRQHandler(void) +{ + /* USER CODE BEGIN DMA2_Stream7_IRQn 0 */ + + /* USER CODE END DMA2_Stream7_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_usart1_tx); + /* USER CODE BEGIN DMA2_Stream7_IRQn 1 */ + + /* USER CODE END DMA2_Stream7_IRQn 1 */ +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/can_logger.ioc b/can_logger.ioc index d6945da..170b21c 100644 --- a/can_logger.ioc +++ b/can_logger.ioc @@ -20,7 +20,8 @@ CAN2.Mode=CAN_MODE_SILENT CAN2.Prescaler=8 Dma.Request0=SDIO_RX Dma.Request1=SDIO_TX -Dma.RequestsNb=2 +Dma.Request2=USART1_TX +Dma.RequestsNb=3 Dma.SDIO_RX.0.Direction=DMA_PERIPH_TO_MEMORY Dma.SDIO_RX.0.FIFOMode=DMA_FIFOMODE_ENABLE Dma.SDIO_RX.0.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL @@ -47,6 +48,16 @@ Dma.SDIO_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_WORD Dma.SDIO_TX.1.PeriphInc=DMA_PINC_DISABLE Dma.SDIO_TX.1.Priority=DMA_PRIORITY_LOW Dma.SDIO_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst +Dma.USART1_TX.2.Direction=DMA_MEMORY_TO_PERIPH +Dma.USART1_TX.2.FIFOMode=DMA_FIFOMODE_DISABLE +Dma.USART1_TX.2.Instance=DMA2_Stream7 +Dma.USART1_TX.2.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.USART1_TX.2.MemInc=DMA_MINC_ENABLE +Dma.USART1_TX.2.Mode=DMA_NORMAL +Dma.USART1_TX.2.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.USART1_TX.2.PeriphInc=DMA_PINC_DISABLE +Dma.USART1_TX.2.Priority=DMA_PRIORITY_LOW +Dma.USART1_TX.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode FREERTOS.FootprintOK=true FREERTOS.IPParameters=Tasks01,configUSE_NEWLIB_REENTRANT,FootprintOK FREERTOS.Tasks01=DefaultTask,49,128,can_listen,Default,NULL,Dynamic,NULL,NULL @@ -96,6 +107,7 @@ MxDb.Version=DB.6.0.170 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false NVIC.DMA2_Stream3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true NVIC.DMA2_Stream6_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true +NVIC.DMA2_Stream7_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false NVIC.ForceEnableDMAVector=true NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false