Add USART DMA in Normal mode from CubeMX

This commit is contained in:
2026-06-18 06:20:14 +02:00
parent 7b30c3cedd
commit 604e9e603b
5 changed files with 57 additions and 2 deletions
+13 -1
View File
@@ -20,7 +20,8 @@ CAN2.Mode=CAN_MODE_SILENT
CAN2.Prescaler=8
Dma.Request0=SDIO_RX
Dma.Request1=SDIO_TX
Dma.RequestsNb=2
Dma.Request2=USART1_TX
Dma.RequestsNb=3
Dma.SDIO_RX.0.Direction=DMA_PERIPH_TO_MEMORY
Dma.SDIO_RX.0.FIFOMode=DMA_FIFOMODE_ENABLE
Dma.SDIO_RX.0.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
@@ -47,6 +48,16 @@ Dma.SDIO_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_WORD
Dma.SDIO_TX.1.PeriphInc=DMA_PINC_DISABLE
Dma.SDIO_TX.1.Priority=DMA_PRIORITY_LOW
Dma.SDIO_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
Dma.USART1_TX.2.Direction=DMA_MEMORY_TO_PERIPH
Dma.USART1_TX.2.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART1_TX.2.Instance=DMA2_Stream7
Dma.USART1_TX.2.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART1_TX.2.MemInc=DMA_MINC_ENABLE
Dma.USART1_TX.2.Mode=DMA_NORMAL
Dma.USART1_TX.2.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART1_TX.2.PeriphInc=DMA_PINC_DISABLE
Dma.USART1_TX.2.Priority=DMA_PRIORITY_LOW
Dma.USART1_TX.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
FREERTOS.FootprintOK=true
FREERTOS.IPParameters=Tasks01,configUSE_NEWLIB_REENTRANT,FootprintOK
FREERTOS.Tasks01=DefaultTask,49,128,can_listen,Default,NULL,Dynamic,NULL,NULL
@@ -96,6 +107,7 @@ MxDb.Version=DB.6.0.170
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
NVIC.DMA2_Stream3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream6_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream7_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
NVIC.ForceEnableDMAVector=true
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false