7 Commits

Author SHA1 Message Date
eeeck 1ad8e5b04f Change define name
- "DEBUG" is also used by STM32 for... something...
2026-06-18 13:38:28 +02:00
eeeck ef034f3195 Add debug dummy CAN frame sent regularly
- Activated by defining DEBUG_DUMMY_FRAME
2026-06-18 13:37:10 +02:00
eeeck 825ddc6961 Add debug print after 1s of no CAN traffic 2026-06-18 08:28:56 +02:00
eeeck 604e9e603b Add USART DMA in Normal mode from CubeMX 2026-06-18 06:21:41 +02:00
eeeck 7b30c3cedd Fix declaration bug 2026-06-17 21:27:26 +02:00
eeeck 8d0b508ff6 Merge branch 'dev_debug' into dev_serial-send 2026-06-17 20:52:23 +02:00
eeeck 6ad1acc2ee Removing duplicate, again... 2026-06-17 18:07:22 +02:00
8 changed files with 86 additions and 7 deletions
+4 -2
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@@ -45,8 +45,10 @@ extern "C" {
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */ /* USER CODE BEGIN EM */
#define DEBUG #define DEBUG_ITM
#ifdef DEBUG #define DEBUG_DUMMY_FRAME
#ifdef DEBUG_ITM
#include <stdio.h> #include <stdio.h>
#define DEBUG_PRINT(...) printf(__VA_ARGS__) #define DEBUG_PRINT(...) printf(__VA_ARGS__)
#else #else
+1
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@@ -56,6 +56,7 @@ void SDIO_IRQHandler(void);
void TIM6_DAC_IRQHandler(void); void TIM6_DAC_IRQHandler(void);
void DMA2_Stream3_IRQHandler(void); void DMA2_Stream3_IRQHandler(void);
void DMA2_Stream6_IRQHandler(void); void DMA2_Stream6_IRQHandler(void);
void DMA2_Stream7_IRQHandler(void);
/* USER CODE BEGIN EFP */ /* USER CODE BEGIN EFP */
/* USER CODE END EFP */ /* USER CODE END EFP */
+3 -1
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@@ -117,13 +117,15 @@ void vCANListener(void *argument)
for (;;) for (;;)
{ {
if (osMessageQueueGet(queue, &message, NULL, osWaitForever) == osOK) if (osMessageQueueGet(queue, &message, NULL, 1000) == osOK)
{ {
// J1939 decoding // J1939 decoding
// RELAY: Push to the UART queue // RELAY: Push to the UART queue
osMessageQueuePut(xUARTQueue, &message, 0U, 0U); osMessageQueuePut(xUARTQueue, &message, 0U, 0U);
} }
else DEBUG_PRINT("No CAN yet!\r\n");
} }
} }
/* END vCANListener */ /* END vCANListener */
+21 -1
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@@ -104,17 +104,37 @@ void vUARTLogger(void *argument)
CanMessage_t message; CanMessage_t message;
char tx_buffer[45]; char tx_buffer[45];
#ifdef DEBUG_DUMMY_FRAME
CanMessage_t dummy_frame = {
.id = 0x0CF00400, // J1939 EEC1 ID
.dlc = 8, // 8 bytes of data
.isExtended = 1, // 29-bit Extended ID
.source = 1, // CAN1
.payload = {0xAA, 0xBB, 0xCC, 0xDD, 0xEE, 0xFF, 0x11, 0x22}
};
#endif
for (;;) for (;;)
{
DEBUG_PRINT("Waiting for CAN traffic...\r\n");
#ifdef DEBUG_DUMMY_FRAME
osMessageQueuePut(xUARTQueue, &dummy_frame, 0U, 0U);
osDelay(1000);
#endif
if (osMessageQueueGet(xUARTQueue, &message, NULL, osWaitForever) == osOK)
{ {
DEBUG_PRINT("Waiting for CAN traffic...\r\n"); DEBUG_PRINT("Waiting for CAN traffic...\r\n");
if (osMessageQueueGet(xUARTQueue, &message, NULL, osWaitForever) == osOK) if (osMessageQueueGet(xUARTQueue, &message, NULL, osWaitForever) == osOK)
{ {
DEBUG_PRINT("CAN frame detected\r\n"); DEBUG_PRINT("CAN frame detected\r\n");
format_can_message(tx_buffer, message.source, &message); int len = format_can_message(tx_buffer, message.source, &message);
HAL_UART_Transmit_DMA(&huart1, (uint8_t*)tx_buffer, len); HAL_UART_Transmit_DMA(&huart1, (uint8_t*)tx_buffer, len);
osSemaphoreAcquire(xUARTDMASemaphore, osWaitForever); osSemaphoreAcquire(xUARTDMASemaphore, osWaitForever);
DEBUG_PRINT("CAN frame sent via UART\r\n"); DEBUG_PRINT("CAN frame sent via UART\r\n");
} }
} }
} }
}
/* END vUARTLoggerListen */ /* END vUARTLoggerListen */
+5 -1
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@@ -46,6 +46,7 @@ DMA_HandleTypeDef hdma_sdio_rx;
DMA_HandleTypeDef hdma_sdio_tx; DMA_HandleTypeDef hdma_sdio_tx;
UART_HandleTypeDef huart1; UART_HandleTypeDef huart1;
DMA_HandleTypeDef hdma_usart1_tx;
/* USER CODE BEGIN PV */ /* USER CODE BEGIN PV */
LED_Config led_can1 = {GPIOB, GPIO_PIN_5}; LED_Config led_can1 = {GPIOB, GPIO_PIN_5};
@@ -386,7 +387,7 @@ static void MX_USART1_UART_Init(void)
/* USER CODE END USART1_Init 1 */ /* USER CODE END USART1_Init 1 */
huart1.Instance = USART1; huart1.Instance = USART1;
huart1.Init.BaudRate = 1152000; huart1.Init.BaudRate = 115200;
huart1.Init.WordLength = UART_WORDLENGTH_8B; huart1.Init.WordLength = UART_WORDLENGTH_8B;
huart1.Init.StopBits = UART_STOPBITS_1; huart1.Init.StopBits = UART_STOPBITS_1;
huart1.Init.Parity = UART_PARITY_NONE; huart1.Init.Parity = UART_PARITY_NONE;
@@ -419,6 +420,9 @@ static void MX_DMA_Init(void)
/* DMA2_Stream6_IRQn interrupt configuration */ /* DMA2_Stream6_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA2_Stream6_IRQn, 5, 0); HAL_NVIC_SetPriority(DMA2_Stream6_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(DMA2_Stream6_IRQn); HAL_NVIC_EnableIRQ(DMA2_Stream6_IRQn);
/* DMA2_Stream7_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn);
/* USER CODE BEGIN MX_DMA_Init 1 */ /* USER CODE BEGIN MX_DMA_Init 1 */
DEBUG_PRINT("DMA initialized!\r\n"); DEBUG_PRINT("DMA initialized!\r\n");
+23
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@@ -26,6 +26,8 @@ extern DMA_HandleTypeDef hdma_sdio_rx;
extern DMA_HandleTypeDef hdma_sdio_tx; extern DMA_HandleTypeDef hdma_sdio_tx;
extern DMA_HandleTypeDef hdma_usart1_tx;
/* Private typedef -----------------------------------------------------------*/ /* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */ /* USER CODE BEGIN TD */
@@ -371,6 +373,25 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart)
GPIO_InitStruct.Alternate = GPIO_AF7_USART1; GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USART1 DMA Init */
/* USART1_TX Init */
hdma_usart1_tx.Instance = DMA2_Stream7;
hdma_usart1_tx.Init.Channel = DMA_CHANNEL_4;
hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE;
hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
hdma_usart1_tx.Init.Mode = DMA_NORMAL;
hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW;
hdma_usart1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK)
{
Error_Handler();
}
__HAL_LINKDMA(huart,hdmatx,hdma_usart1_tx);
/* USER CODE BEGIN USART1_MspInit 1 */ /* USER CODE BEGIN USART1_MspInit 1 */
/* USER CODE END USART1_MspInit 1 */ /* USER CODE END USART1_MspInit 1 */
@@ -401,6 +422,8 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
*/ */
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10);
/* USART1 DMA DeInit */
HAL_DMA_DeInit(huart->hdmatx);
/* USER CODE BEGIN USART1_MspDeInit 1 */ /* USER CODE BEGIN USART1_MspDeInit 1 */
/* USER CODE END USART1_MspDeInit 1 */ /* USER CODE END USART1_MspDeInit 1 */
+15
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@@ -58,6 +58,7 @@
extern DMA_HandleTypeDef hdma_sdio_rx; extern DMA_HandleTypeDef hdma_sdio_rx;
extern DMA_HandleTypeDef hdma_sdio_tx; extern DMA_HandleTypeDef hdma_sdio_tx;
extern SD_HandleTypeDef hsd; extern SD_HandleTypeDef hsd;
extern DMA_HandleTypeDef hdma_usart1_tx;
extern TIM_HandleTypeDef htim6; extern TIM_HandleTypeDef htim6;
/* USER CODE BEGIN EV */ /* USER CODE BEGIN EV */
@@ -218,6 +219,20 @@ void DMA2_Stream6_IRQHandler(void)
/* USER CODE END DMA2_Stream6_IRQn 1 */ /* USER CODE END DMA2_Stream6_IRQn 1 */
} }
/**
* @brief This function handles DMA2 stream7 global interrupt.
*/
void DMA2_Stream7_IRQHandler(void)
{
/* USER CODE BEGIN DMA2_Stream7_IRQn 0 */
/* USER CODE END DMA2_Stream7_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_usart1_tx);
/* USER CODE BEGIN DMA2_Stream7_IRQn 1 */
/* USER CODE END DMA2_Stream7_IRQn 1 */
}
/* USER CODE BEGIN 1 */ /* USER CODE BEGIN 1 */
/* USER CODE END 1 */ /* USER CODE END 1 */
+13 -1
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@@ -20,7 +20,8 @@ CAN2.Mode=CAN_MODE_SILENT
CAN2.Prescaler=8 CAN2.Prescaler=8
Dma.Request0=SDIO_RX Dma.Request0=SDIO_RX
Dma.Request1=SDIO_TX Dma.Request1=SDIO_TX
Dma.RequestsNb=2 Dma.Request2=USART1_TX
Dma.RequestsNb=3
Dma.SDIO_RX.0.Direction=DMA_PERIPH_TO_MEMORY Dma.SDIO_RX.0.Direction=DMA_PERIPH_TO_MEMORY
Dma.SDIO_RX.0.FIFOMode=DMA_FIFOMODE_ENABLE Dma.SDIO_RX.0.FIFOMode=DMA_FIFOMODE_ENABLE
Dma.SDIO_RX.0.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL Dma.SDIO_RX.0.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
@@ -47,6 +48,16 @@ Dma.SDIO_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_WORD
Dma.SDIO_TX.1.PeriphInc=DMA_PINC_DISABLE Dma.SDIO_TX.1.PeriphInc=DMA_PINC_DISABLE
Dma.SDIO_TX.1.Priority=DMA_PRIORITY_LOW Dma.SDIO_TX.1.Priority=DMA_PRIORITY_LOW
Dma.SDIO_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst Dma.SDIO_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
Dma.USART1_TX.2.Direction=DMA_MEMORY_TO_PERIPH
Dma.USART1_TX.2.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART1_TX.2.Instance=DMA2_Stream7
Dma.USART1_TX.2.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART1_TX.2.MemInc=DMA_MINC_ENABLE
Dma.USART1_TX.2.Mode=DMA_NORMAL
Dma.USART1_TX.2.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART1_TX.2.PeriphInc=DMA_PINC_DISABLE
Dma.USART1_TX.2.Priority=DMA_PRIORITY_LOW
Dma.USART1_TX.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
FREERTOS.FootprintOK=true FREERTOS.FootprintOK=true
FREERTOS.IPParameters=Tasks01,configUSE_NEWLIB_REENTRANT,FootprintOK FREERTOS.IPParameters=Tasks01,configUSE_NEWLIB_REENTRANT,FootprintOK
FREERTOS.Tasks01=DefaultTask,49,128,can_listen,Default,NULL,Dynamic,NULL,NULL FREERTOS.Tasks01=DefaultTask,49,128,can_listen,Default,NULL,Dynamic,NULL,NULL
@@ -96,6 +107,7 @@ MxDb.Version=DB.6.0.170
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
NVIC.DMA2_Stream3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true NVIC.DMA2_Stream3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream6_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true NVIC.DMA2_Stream6_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream7_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
NVIC.ForceEnableDMAVector=true NVIC.ForceEnableDMAVector=true
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false