diff --git a/.gitignore b/.gitignore index d60185e..324b2e1 100644 --- a/.gitignore +++ b/.gitignore @@ -8,3 +8,6 @@ .metadata Core/Src/Backup/ Core/Inc/Backup/ +.bak +.gitignore +can_logger Debug.launch diff --git a/Core/Inc/canlog.h b/Core/Inc/canlog.h index 0636e2c..d741aff 100644 --- a/Core/Inc/canlog.h +++ b/Core/Inc/canlog.h @@ -1,7 +1,53 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : canlog.h + * @brief : Header for canlog.c file. + * This file contains the defines related to SAE J1939 CAN. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 Erick Ahmed. + * + * SPDX-License-Identifier: GPL-3.0-or-later + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ #ifndef CANLOG_H #define CANLOG_H #include "main.h" +#include "cmsis_os.h" + +extern osMessageQueueId_t xCAN1RxQueue; +extern osMessageQueueId_t xCAN2RxQueue; +extern osSemaphoreId_t xSemaphoreCAN1; +extern osSemaphoreId_t xSemaphoreCAN2; + +/* USER CODE BEGIN PTD */ +typedef struct { + GPIO_TypeDef* port; + uint16_t pin; +} LED_Config; + +typedef struct { + uint32_t id; + uint8_t payload[8]; + uint8_t dlc; + uint8_t isExtended; + //uint32_t timestamp; //Enable TIM2: 42 MHz / (41+1) = 1 MHz → 1 µs tick; 32bit autoreload freerunning + // this is for getting timestamps on can messages +} CanMessage_t; + +typedef struct { + LED_Config *led; + osSemaphoreId_t semaphore; + osTimerId_t timer; +} LEDContext; +/* USER CODE END PTD */ /** * @brief Initializes the CAN logger modules, OS threads, queues, and hardware. @@ -9,5 +55,8 @@ * @param hcan2 Pointer to the CAN2 handle */ void CAN_Logger_Init(CAN_HandleTypeDef *hcan1, CAN_HandleTypeDef *hcan2); +void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan); +void vCANLoggerListen(void *argument); +void vLEDHeartbeat(void *argument); #endif /* CANLOG_H */ diff --git a/Core/Inc/main.h b/Core/Inc/main.h index b31c169..a2e2207 100644 --- a/Core/Inc/main.h +++ b/Core/Inc/main.h @@ -8,11 +8,9 @@ * @attention * * Copyright (c) 2026 STMicroelectronics. - * All rights reserved. + * Copyright (c) 2026 Erick Ahmed. * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. + * SPDX-License-Identifier: GPL-3.0-or-later * ****************************************************************************** */ @@ -28,6 +26,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" +#include "canlog.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ diff --git a/Core/Src/ThreadSafe/newlib_lock_glue.c b/Core/Src/ThreadSafe/newlib_lock_glue.c deleted file mode 100644 index 744d87e..0000000 --- a/Core/Src/ThreadSafe/newlib_lock_glue.c +++ /dev/null @@ -1,435 +0,0 @@ -/** - ****************************************************************************** - * @file newlib_lock_glue.c - * @author STMicroelectronics - * @brief Implementation of newlib lock interface - * - * @details This file implements locking glue necessary to protect C library - * functions and initialization of local static objects in C++. - * Lock strategies are defined in stm32_lock.h that implements - * different level of thread-safety. - * - * For more information about which C functions need which of these - * low level functions, please consult the newlib libc manual, - * see https://sourceware.org/newlib/libc.html - * - * For more information about the one-time construction API for C++, - * see https://itanium-cxx-abi.github.io/cxx-abi/abi.html#once-ctor - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2026 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -#if !defined (__GNUC__) || defined (__CC_ARM) -#error "newlib_lock_glue.c" should be used with GNU Compilers only -#endif /* !defined (__GNUC__) || defined (__CC_ARM) */ - -/* Includes ------------------------------------------------------------------*/ -#include - -/* Private functions prototypes ----------------------------------------------*/ -__WEAK void Error_Handler(void); -/* Private functions ---------------------------------------------------------*/ - -/** - * @brief Global Error_Handler - */ -__WEAK void Error_Handler(void) -{ - /* Not used if it exists in project */ - while (1); -} - -#ifdef __SINGLE_THREAD__ -#warning C library is in single-threaded mode. Please take care when using C library functions in threaded contexts -#else - -/* Includes ------------------------------------------------------------------*/ -#include -#include -#include "stm32_lock.h" - -/** - * @defgroup _newlib_lock_functions newlib library locks - * @see https://sourceware.org/newlib/libc.html - * @{ - */ - -#if __NEWLIB__ >= 3 && defined (_RETARGETABLE_LOCKING) -#include -#include -#include - -/* Private macros ------------------------------------------------------------*/ -/** See struct __lock definition */ -#define STM32_LOCK_PARAMETER(lock) (&(lock)->lock_data) - -/* shared variables for bare metal allow lock ------------------------------------------------------*/ -#if defined(STM32_THREAD_SAFE_BAREMETAL_ALLOW_LOCKS) && (STM32_THREAD_SAFE_BAREMETAL_ALLOW_LOCKS != 0) -uint32_t gflag = 0; -uint32_t call_counter = 0; -#endif /* defined(STM32_THREAD_SAFE_BAREMETAL_ALLOW_LOCKS) && (STM32_THREAD_SAFE_BAREMETAL_ALLOW_LOCKS != 0) */ - -/* Private variables ---------------------------------------------------------*/ -struct __lock -{ - LockingData_t lock_data; /**< The STM32 lock instance */ -}; - -/** Implementing mutex from newlib/libc/misc/lock.c */ -struct __lock __lock___sinit_recursive_mutex = { LOCKING_DATA_INIT }; - -/** Implementing mutex from newlib/libc/misc/lock.c */ -struct __lock __lock___sfp_recursive_mutex = { LOCKING_DATA_INIT }; - -/** Implementing mutex from newlib/libc/misc/lock.c */ -struct __lock __lock___atexit_recursive_mutex = { LOCKING_DATA_INIT }; - -/** Implementing mutex from newlib/libc/misc/lock.c */ -struct __lock __lock___at_quick_exit_mutex = { LOCKING_DATA_INIT }; - -/** Implementing mutex from newlib/libc/misc/lock.c */ -struct __lock __lock___malloc_recursive_mutex = { LOCKING_DATA_INIT }; - -/** Implementing mutex from newlib/libc/misc/lock.c */ -struct __lock __lock___env_recursive_mutex = { LOCKING_DATA_INIT }; - -/** Implementing mutex from newlib/libc/misc/lock.c */ -struct __lock __lock___tz_mutex = { LOCKING_DATA_INIT }; - -/** Implementing mutex from newlib/libc/misc/lock.c */ -struct __lock __lock___dd_hash_mutex = { LOCKING_DATA_INIT }; - -/** Implementing mutex from newlib/libc/misc/lock.c */ -struct __lock __lock___arc4random_mutex = { LOCKING_DATA_INIT }; - -/* Private functions ---------------------------------------------------------*/ - -/** - * @brief Initialize lock - * @param lock The lock - */ -void __retarget_lock_init(_LOCK_T *lock) -{ - __retarget_lock_init_recursive(lock); -} - -/** - * @brief Initialize recursive lock - * @param lock The lock - */ -void __retarget_lock_init_recursive(_LOCK_T *lock) -{ - if (lock == NULL) - { - errno = EINVAL; - return; - } - - *lock = (_LOCK_T)malloc(sizeof(struct __lock)); - if (*lock != NULL) - { - stm32_lock_init(STM32_LOCK_PARAMETER(*lock)); - return; - } - - /* Unable to allocate memory */ - STM32_LOCK_BLOCK(); -} - -/** - * @brief Close lock - * @param lock The lock - */ -void __retarget_lock_close(_LOCK_T lock) -{ - __retarget_lock_close_recursive(lock); -} - -/** - * @brief Close recursive lock - * @param lock The lock - */ -void __retarget_lock_close_recursive(_LOCK_T lock) -{ - free(lock); -} - -/** - * @brief Acquire lock - * @param lock The lock - */ -void __retarget_lock_acquire(_LOCK_T lock) -{ - STM32_LOCK_BLOCK_IF_NULL_ARGUMENT(lock); - stm32_lock_acquire(STM32_LOCK_PARAMETER(lock)); -} - -/** - * @brief Acquire recursive lock - * @param lock The lock - */ -void __retarget_lock_acquire_recursive(_LOCK_T lock) -{ - STM32_LOCK_BLOCK_IF_NULL_ARGUMENT(lock); - stm32_lock_acquire(STM32_LOCK_PARAMETER(lock)); -} - -/** - * @brief Try acquire lock - * @param lock The lock - * @return 0 always - */ -int __retarget_lock_try_acquire(_LOCK_T lock) -{ - __retarget_lock_acquire(lock); - return 0; -} - -/** - * @brief Try acquire recursive lock - * @param lock The lock - * @return 0 always - */ -int __retarget_lock_try_acquire_recursive(_LOCK_T lock) -{ - __retarget_lock_acquire_recursive(lock); - return 0; -} - -/** - * @brief Release lock - * @param lock The lock - */ -void __retarget_lock_release(_LOCK_T lock) -{ - STM32_LOCK_BLOCK_IF_NULL_ARGUMENT(lock); - stm32_lock_release(STM32_LOCK_PARAMETER(lock)); -} - -/** - * @brief Release recursive lock - * @param lock The lock - */ -void __retarget_lock_release_recursive(_LOCK_T lock) -{ - STM32_LOCK_BLOCK_IF_NULL_ARGUMENT(lock); - stm32_lock_release(STM32_LOCK_PARAMETER(lock)); -} - -#else -#warning This makes malloc, env, and TZ calls thread-safe, not the entire newlib - -/* Includes ------------------------------------------------------------------*/ -#include - -/* Private variables ---------------------------------------------------------*/ -/** Mutex used in __malloc_lock and __malloc_unlock */ -static LockingData_t __lock___malloc_recursive_mutex = LOCKING_DATA_INIT; - -/** Mutex used in __env_lock and __env_unlock */ -static LockingData_t __lock___env_recursive_mutex = LOCKING_DATA_INIT; - -/** Mutex used in __tz_lock and __tz_unlock */ -static LockingData_t __lock___tz_mutex = LOCKING_DATA_INIT; - -/* Private functions ---------------------------------------------------------*/ - -#if __STD_C - -/** - * @brief Acquire malloc lock - * @param reent The reentrance struct - */ -void __malloc_lock(struct _reent *reent) -{ - STM32_LOCK_UNUSED(reent); - stm32_lock_acquire(&__lock___malloc_recursive_mutex); -} - -/** - * @brief Release malloc lock - * @param reent The reentrance struct - */ -void __malloc_unlock(struct _reent *reent) -{ - STM32_LOCK_UNUSED(reent); - stm32_lock_release(&__lock___malloc_recursive_mutex); -} - -#else - -/** - * @brief Acquire malloc lock - */ -void __malloc_lock() -{ - stm32_lock_acquire(&__lock___malloc_recursive_mutex); -} - -/** - * @brief Release malloc lock - */ -void __malloc_unlock() -{ - stm32_lock_release(&__lock___malloc_recursive_mutex); -} -#endif /* __STD_C */ - -/** - * @brief Acquire env lock - * @param reent The reentrance struct - */ -void __env_lock(struct _reent *reent) -{ - STM32_LOCK_UNUSED(reent); - stm32_lock_acquire(&__lock___env_recursive_mutex); -} - -/** - * @brief Release env lock - * @param reent The reentrance struct - */ -void __env_unlock(struct _reent *reent) -{ - STM32_LOCK_UNUSED(reent); - stm32_lock_release(&__lock___env_recursive_mutex); -} - -/** - * @brief Acquire tz lock - */ -void __tz_lock() -{ - stm32_lock_acquire(&__lock___tz_mutex); -} - -/** - * @brief Release tz lock - */ -void __tz_unlock() -{ - stm32_lock_release(&__lock___tz_mutex); -} - -#endif /* __NEWLIB__ >= 3 && defined (_RETARGETABLE_LOCKING) */ - -/** - * @} - */ - - -/** - * @defgroup __cxa_guard_ GNU C++ one-time construction API - * @see https://itanium-cxx-abi.github.io/cxx-abi/abi.html#once-ctor - * - * When building for C++, please make sure that -fno-threadsafe-statics is not passed to the compiler - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/** The guard object is created by the C++ compiler and is 32 bit for ARM EABI. */ -typedef struct -{ - atomic_uchar initialized; /**< Indicate if object is initialized */ - uint8_t acquired; /**< Ensure non-recursive lock */ - uint16_t unused; /**< Padding */ -} __attribute__((packed)) CxaGuardObject_t; - -/* Private variables ---------------------------------------------------------*/ -/** Mutex used in __cxa_guard_acquire, __cxa_guard_release and __cxa_guard_abort */ -static LockingData_t __cxa_guard_mutex = LOCKING_DATA_INIT; - -/* Private functions prototype ---------------------------------------------------------*/ -int __cxa_guard_acquire(CxaGuardObject_t *guard_object); -void __cxa_guard_abort(CxaGuardObject_t *guard_object); -void __cxa_guard_release(CxaGuardObject_t *guard_object); -/* Private functions ---------------------------------------------------------*/ - -/** - * @brief Acquire __cxa_guard mutex - * @param guard_object Guard object - * @return 0 if object is initialized, else initialization of object required - */ -int __cxa_guard_acquire(CxaGuardObject_t *guard_object) -{ - STM32_LOCK_BLOCK_IF_NULL_ARGUMENT(guard_object); - - if (atomic_load(&guard_object->initialized) == 0) - { - /* Object needs initialization, lock threading context */ - stm32_lock_acquire(&__cxa_guard_mutex); - if (atomic_load(&guard_object->initialized) == 0) - { - /* Object needs initialization */ - if (guard_object->acquired) - { - /* Object initialization already in progress */ - STM32_LOCK_BLOCK(); - } - - /* Lock acquired */ - guard_object->acquired = 1; - return 1; - } - else - { - /* Object initialized in another thread */ - stm32_lock_release(&__cxa_guard_mutex); - } - } - - /* Object already initialized */ - return 0; -} - -/** - * @brief Abort __cxa_guard mutex - * @param guard_object Guard object - */ -void __cxa_guard_abort(CxaGuardObject_t *guard_object) -{ - STM32_LOCK_BLOCK_IF_NULL_ARGUMENT(guard_object); - - if (guard_object->acquired) - { - /* Release lock */ - guard_object->acquired = 0; - stm32_lock_release(&__cxa_guard_mutex); - } - else - { - /* Trying to release non-acquired lock */ - STM32_LOCK_BLOCK(); - } -} - -/** - * @brief Release __cxa_guard mutex - * @param guard_object Guard object - */ -void __cxa_guard_release(CxaGuardObject_t *guard_object) -{ - STM32_LOCK_BLOCK_IF_NULL_ARGUMENT(guard_object); - - /* Object initialized */ - atomic_store(&guard_object->initialized, 1); - - /* Release lock */ - __cxa_guard_abort(guard_object); -} - -/** - * @} - */ - -#endif /* __SINGLE_THREAD__ */ diff --git a/Core/Src/canlog.c b/Core/Src/canlog.c index 8efc726..45b2935 100644 --- a/Core/Src/canlog.c +++ b/Core/Src/canlog.c @@ -1,40 +1,143 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : canlog.c + * @brief : SAE J1939 CAN Real Time listening and decoding + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 Erick Ahmed. + * + * SPDX-License-Identifier: GPL-3.0-or-later + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ #include "canlog.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ #include "cmsis_os.h" #include +/* USER CODE END Includes */ -/* Definitions for canBus1Listen */ -osThreadId_t canBus1ListenHandle; -const osThreadAttr_t canBus1Listen_attributes = { - .name = "canBus1Listen", - .stack_size = 128 * 4, - .priority = (osPriority_t) osPriorityRealtime1, -}; -/* Definitions for canBus2Listen */ -osThreadId_t canBus2ListenHandle; -const osThreadAttr_t canBus2Listen_attributes = { - .name = "canBus2Listen", - .stack_size = 128 * 4, - .priority = (osPriority_t) osPriorityRealtime, -}; +extern CAN_HandleTypeDef hcan1; +extern CAN_HandleTypeDef hcan2; /* Private function prototypes -----------------------------------------------*/ -void CAN_Logger_Init(CAN_HandleTypeDef *hcan1, CAN_HandleTypeDef *hcan2){} -static void CAN_Listen(void *argument){} - -/* BEGIN Header_CAN_Listen */ +/* USER CODE BEGIN FunctionPrototypes */ +/* BEGIN CAN_Logger_Init */ /** - * @brief Function implementing the canBus0Listen thread. + * @brief Initialize CAN bus logger. + * @param argument: hcan1, hcan2 + * @retval None + */ +void CAN_Logger_Init(CAN_HandleTypeDef *hcan1, CAN_HandleTypeDef *hcan2) +{ + CAN_FilterTypeDef filter = {0}; + filter.FilterMode = CAN_FILTERMODE_IDMASK; + filter.FilterScale = CAN_FILTERSCALE_32BIT; + filter.FilterIdHigh = 0x0000; + filter.FilterMaskIdHigh = 0x0000; + filter.FilterIdLow = 0x0000; + filter.FilterMaskIdLow = 0x0000; + filter.FilterFIFOAssignment = CAN_FILTER_FIFO0; + filter.FilterActivation = ENABLE; + filter.SlaveStartFilterBank = 14; + + filter.FilterBank = 0; + if (HAL_CAN_ConfigFilter(hcan1, &filter) != HAL_OK) Error_Handler(); + filter.FilterBank = 14; + if (HAL_CAN_ConfigFilter(hcan2, &filter) != HAL_OK) Error_Handler(); + + if (HAL_CAN_Start(hcan1) != HAL_OK) Error_Handler(); + if (HAL_CAN_Start(hcan2) != HAL_OK) Error_Handler(); + + if (HAL_CAN_ActivateNotification(hcan1, CAN_IT_RX_FIFO0_MSG_PENDING) != HAL_OK) Error_Handler(); + if (HAL_CAN_ActivateNotification(hcan2, CAN_IT_RX_FIFO0_MSG_PENDING) != HAL_OK) Error_Handler(); +} +/* END CAN_Logger_Init */ + +/* BEGIN HAL_CAN_RxFifo0MsgPendingCallback */ +/** + * @brief ISR for CAN message pending in FIFO0 + * @param argument: Can handle hcan (hcan1 or hcan2) + * @retval None + */ +void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + /* CODE BEGIN */ + CanMessage_t message; + CAN_RxHeaderTypeDef rxHeader; + uint8_t data[8]; + + if (HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO0, &rxHeader, data) != HAL_OK) Error_Handler(); + + message.id = rxHeader.ExtId; + message.dlc = rxHeader.DLC; + message.isExtended = (rxHeader.IDE == CAN_ID_EXT); + memcpy(message.payload, data, rxHeader.DLC); + + osMessageQueueId_t queue = (hcan->Instance == CAN1) ? xCAN1RxQueue : xCAN2RxQueue; + if (osMessageQueuePut(queue, &message, 0U, 0U) != osOK) + { + // TODO: better handling: flash error_led on osTimeout, call Error_Handler() when other errors + + // send errors like queue full via UART + } + /* CODE END */ +} +/* END HAL_CAN_RxFifo0MsgPendingCallback */ + +/* BEGIN vCANLoggerListen */ +/** + * @brief Log incoming CAN bus traffic in FIFO buffer * @param argument: Not used * @retval None */ -/* END Header_CAN_Listen */ -void CAN_Listen(void *argument) +void vCANLoggerListen(void *argument) +{ + /* CODE BEGIN */ + CAN_HandleTypeDef *hcan = (CAN_HandleTypeDef*)argument; + osMessageQueueId_t queue; + CanMessage_t message; + + queue = (hcan->Instance == CAN1) ? xCAN1RxQueue : xCAN2RxQueue; + + for (;;) + { + if (osMessageQueueGet(queue, &message, NULL, osWaitForever) == osOK) + { + osSemaphoreRelease( (hcan->Instance == CAN1) ? xSemaphoreCAN1 : xSemaphoreCAN2 ); + // TODO: use this semaphore + } + + } + /* CODE END */ +} +/* END vCANLoggerListen */ + +/* BEGIN vLEDHeartbeat */ +/** + * @brief Blink a LED in heartbeat mode when CAN traffic is detected + * @param argument: LED GPIO (port and pin) + * @retval None + */ +void vLEDHeartbeat(void *argument) { /* CODE BEGIN */ - /* Infinite loop */ - for(;;) + LEDContext *context = (LEDContext*)argument; + + if (osSemaphoreAcquire(context->semaphore, 0U) == osOK) { - osDelay(1); + HAL_GPIO_WritePin(context->led->port, context->led->pin, GPIO_PIN_SET); + osTimerStart(context->timer, 25U); + } + else + { + HAL_GPIO_WritePin(context->led->port, context->led->pin, GPIO_PIN_RESET); } /* CODE END */ } +/* END vLEDHeartbeat */ +/* USER CODE END FunctionPrototypes */ diff --git a/Core/Src/freertos.c b/Core/Src/freertos.c deleted file mode 100644 index 95f65a7..0000000 --- a/Core/Src/freertos.c +++ /dev/null @@ -1,59 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * File Name : freertos.c - * Description : Code for freertos applications - ****************************************************************************** - * @attention - * - * Copyright (c) 2026 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Includes ------------------------------------------------------------------*/ -#include "FreeRTOS.h" -#include "task.h" -#include "main.h" - -/* Private includes ----------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Private typedef -----------------------------------------------------------*/ -/* USER CODE BEGIN PTD */ - -/* USER CODE END PTD */ - -/* Private define ------------------------------------------------------------*/ -/* USER CODE BEGIN PD */ - -/* USER CODE END PD */ - -/* Private macro -------------------------------------------------------------*/ -/* USER CODE BEGIN PM */ - -/* USER CODE END PM */ - -/* Private variables ---------------------------------------------------------*/ -/* USER CODE BEGIN Variables */ - -/* USER CODE END Variables */ - -/* Private function prototypes -----------------------------------------------*/ -/* USER CODE BEGIN FunctionPrototypes */ - -/* USER CODE END FunctionPrototypes */ - -/* Private application code --------------------------------------------------*/ -/* USER CODE BEGIN Application */ - -/* USER CODE END Application */ - diff --git a/Core/Src/main.c b/Core/Src/main.c index 51368a2..ff7bb39 100644 --- a/Core/Src/main.c +++ b/Core/Src/main.c @@ -1,460 +1,526 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file : main.c - * @brief : Main program body - ****************************************************************************** - * @attention - * - * Copyright (c) 2026 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -/* USER CODE END Header */ -/* Includes ------------------------------------------------------------------*/ -#include "main.h" -#include "canlog.h" -#include "cmsis_os.h" - -/* Private includes ----------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Private typedef -----------------------------------------------------------*/ -/* USER CODE BEGIN PTD */ - -/* USER CODE END PTD */ - -/* Private define ------------------------------------------------------------*/ -/* USER CODE BEGIN PD */ - -/* USER CODE END PD */ - -/* Private macro -------------------------------------------------------------*/ -/* USER CODE BEGIN PM */ - -/* USER CODE END PM */ - -/* Private variables ---------------------------------------------------------*/ -CAN_HandleTypeDef hcan1; -CAN_HandleTypeDef hcan2; - -SD_HandleTypeDef hsd; -DMA_HandleTypeDef hdma_sdio_rx; -DMA_HandleTypeDef hdma_sdio_tx; - -/* USER CODE BEGIN PV */ - -/* USER CODE END PV */ - -/* Private function prototypes -----------------------------------------------*/ -void SystemClock_Config(void); -static void MX_GPIO_Init(void); -static void MX_DMA_Init(void); -static void MX_CAN1_Init(void); -static void MX_CAN2_Init(void); -static void MX_SDIO_SD_Init(void); - -/* USER CODE BEGIN PFP */ - -/* USER CODE END PFP */ - -/* Private user code ---------------------------------------------------------*/ -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/** - * @brief The application entry point. - * @retval int - */ -int main(void) -{ - - /* USER CODE BEGIN 1 */ - - /* USER CODE END 1 */ - - /* MCU Configuration--------------------------------------------------------*/ - - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - HAL_Init(); - - /* USER CODE BEGIN Init */ - - /* USER CODE END Init */ - - /* Configure the system clock */ - SystemClock_Config(); - - /* USER CODE BEGIN SysInit */ - - /* USER CODE END SysInit */ - - /* Initialize all configured peripherals */ - MX_GPIO_Init(); - MX_DMA_Init(); - MX_CAN1_Init(); - MX_CAN2_Init(); - MX_SDIO_SD_Init(); - /* USER CODE BEGIN 2 */ - - // Initialize CAN1 and CAN2 - CAN_Logger_Init(&hcan1, &hcan2); - - /* USER CODE END 2 */ - - /* Init scheduler */ - osKernelInitialize(); - - /* USER CODE BEGIN RTOS_MUTEX */ - /* add mutexes, ... */ - /* USER CODE END RTOS_MUTEX */ - - /* USER CODE BEGIN RTOS_SEMAPHORES */ - /* add semaphores, ... */ - /* USER CODE END RTOS_SEMAPHORES */ - - /* USER CODE BEGIN RTOS_TIMERS */ - /* start timers, add new ones, ... */ - /* USER CODE END RTOS_TIMERS */ - - /* USER CODE BEGIN RTOS_QUEUES */ - /* add queues, ... */ - /* USER CODE END RTOS_QUEUES */ - - /* USER CODE BEGIN RTOS_THREADS */ - /* add threads, ... */ - /* USER CODE END RTOS_THREADS */ - - /* USER CODE BEGIN RTOS_EVENTS */ - /* add events, ... */ - /* USER CODE END RTOS_EVENTS */ - - /* Start scheduler */ - osKernelStart(); - - /* We should never get here as control is now taken by the scheduler */ - - /* Infinite loop */ - /* USER CODE BEGIN WHILE */ - while (1) - { - /* USER CODE END WHILE */ - - /* USER CODE BEGIN 3 */ - } - /* USER CODE END 3 */ -} - -/** - * @brief System Clock Configuration - * @retval None - */ -void SystemClock_Config(void) -{ - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - - /** Configure the main internal regulator output voltage - */ - __HAL_RCC_PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - /** Initializes the RCC Oscillators according to the specified parameters - * in the RCC_OscInitTypeDef structure. - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PLLM = 16; - RCC_OscInitStruct.PLL.PLLN = 336; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 7; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - Error_Handler(); - } - - /** Initializes the CPU, AHB and APB buses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV4; - - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) - { - Error_Handler(); - } -} - -/** - * @brief CAN1 Initialization Function - * @param None - * @retval None - */ -static void MX_CAN1_Init(void) -{ - - /* USER CODE BEGIN CAN1_Init 0 */ - - /* USER CODE END CAN1_Init 0 */ - - /* USER CODE BEGIN CAN1_Init 1 */ - - /* USER CODE END CAN1_Init 1 */ - hcan1.Instance = CAN1; - hcan1.Init.Prescaler = 4; - hcan1.Init.Mode = CAN_MODE_SILENT; - hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ; - hcan1.Init.TimeSeg1 = CAN_BS1_16TQ; - hcan1.Init.TimeSeg2 = CAN_BS2_4TQ; - hcan1.Init.TimeTriggeredMode = DISABLE; - hcan1.Init.AutoBusOff = DISABLE; - hcan1.Init.AutoWakeUp = DISABLE; - hcan1.Init.AutoRetransmission = DISABLE; - hcan1.Init.ReceiveFifoLocked = DISABLE; - hcan1.Init.TransmitFifoPriority = DISABLE; - if (HAL_CAN_Init(&hcan1) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN CAN1_Init 2 */ - - /* USER CODE END CAN1_Init 2 */ - -} - -/** - * @brief CAN2 Initialization Function - * @param None - * @retval None - */ -static void MX_CAN2_Init(void) -{ - - /* USER CODE BEGIN CAN2_Init 0 */ - - /* USER CODE END CAN2_Init 0 */ - - /* USER CODE BEGIN CAN2_Init 1 */ - - /* USER CODE END CAN2_Init 1 */ - hcan2.Instance = CAN2; - hcan2.Init.Prescaler = 8; - hcan2.Init.Mode = CAN_MODE_SILENT; - hcan2.Init.SyncJumpWidth = CAN_SJW_1TQ; - hcan2.Init.TimeSeg1 = CAN_BS1_16TQ; - hcan2.Init.TimeSeg2 = CAN_BS2_4TQ; - hcan2.Init.TimeTriggeredMode = DISABLE; - hcan2.Init.AutoBusOff = DISABLE; - hcan2.Init.AutoWakeUp = DISABLE; - hcan2.Init.AutoRetransmission = DISABLE; - hcan2.Init.ReceiveFifoLocked = DISABLE; - hcan2.Init.TransmitFifoPriority = DISABLE; - if (HAL_CAN_Init(&hcan2) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN CAN2_Init 2 */ - - /* USER CODE END CAN2_Init 2 */ - -} - -/** - * @brief SDIO Initialization Function - * @param None - * @retval None - */ -static void MX_SDIO_SD_Init(void) -{ - - /* USER CODE BEGIN SDIO_Init 0 */ - - /* USER CODE END SDIO_Init 0 */ - - /* USER CODE BEGIN SDIO_Init 1 */ - - /* USER CODE END SDIO_Init 1 */ - hsd.Instance = SDIO; - hsd.Init.ClockEdge = SDIO_CLOCK_EDGE_RISING; - hsd.Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; - hsd.Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; - hsd.Init.BusWide = SDIO_BUS_WIDE_1B; - hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; - hsd.Init.ClockDiv = 0; - if (HAL_SD_Init(&hsd) != HAL_OK) - { - Error_Handler(); - } - if (HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN SDIO_Init 2 */ - - /* USER CODE END SDIO_Init 2 */ - -} - -/** - * Enable DMA controller clock - */ -static void MX_DMA_Init(void) -{ - - /* DMA controller clock enable */ - __HAL_RCC_DMA2_CLK_ENABLE(); - - /* DMA interrupt init */ - /* DMA2_Stream3_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(DMA2_Stream3_IRQn, 5, 0); - HAL_NVIC_EnableIRQ(DMA2_Stream3_IRQn); - /* DMA2_Stream6_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(DMA2_Stream6_IRQn, 5, 0); - HAL_NVIC_EnableIRQ(DMA2_Stream6_IRQn); - -} - -/** - * @brief GPIO Initialization Function - * @param None - * @retval None - */ -static void MX_GPIO_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - /* USER CODE BEGIN MX_GPIO_Init_1 */ - - /* USER CODE END MX_GPIO_Init_1 */ - - /* GPIO Ports Clock Enable */ - __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOH_CLK_ENABLE(); - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - __HAL_RCC_GPIOD_CLK_ENABLE(); - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOB, GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5, GPIO_PIN_RESET); - - /*Configure GPIO pins : PC13 PC14 PC15 PC0 - PC1 PC2 PC3 PC4 - PC5 PC6 PC7 */ - GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15|GPIO_PIN_0 - |GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4 - |GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /*Configure GPIO pins : PH0 PH1 */ - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); - - /*Configure GPIO pins : PA0 PA1 PA2 PA3 - PA4 PA5 PA6 PA7 - PA8 PA9 PA10 PA11 - PA12 PA13 PA14 PA15 */ - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7 - |GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 - |GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /*Configure GPIO pins : PB0 PB1 PB2 PB10 - PB11 PB14 PB15 PB6 - PB7 */ - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10 - |GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_15|GPIO_PIN_6 - |GPIO_PIN_7; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /*Configure GPIO pins : PB3 PB4 PB5 */ - GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /* USER CODE BEGIN MX_GPIO_Init_2 */ - - /* USER CODE END MX_GPIO_Init_2 */ -} - -/* USER CODE BEGIN 4 */ - -/* USER CODE END 4 */ - - - -/** - * @brief Period elapsed callback in non blocking mode - * @note This function is called when TIM6 interrupt took place, inside - * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment - * a global variable "uwTick" used as application time base. - * @param htim : TIM handle - * @retval None - */ -void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) -{ - /* USER CODE BEGIN Callback 0 */ - - /* USER CODE END Callback 0 */ - if (htim->Instance == TIM6) - { - HAL_IncTick(); - } - /* USER CODE BEGIN Callback 1 */ - - /* USER CODE END Callback 1 */ -} - -/** - * @brief This function is executed in case of error occurrence. - * @retval None - */ -void Error_Handler(void) -{ - /* USER CODE BEGIN Error_Handler_Debug */ - /* User can add his own implementation to report the HAL error return state */ - __disable_irq(); - while (1) - { - } - /* USER CODE END Error_Handler_Debug */ -} -#ifdef USE_FULL_ASSERT -/** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ -void assert_failed(uint8_t *file, uint32_t line) -{ - /* USER CODE BEGIN 6 */ - /* User can add his own implementation to report the file name and line number, - ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ - /* USER CODE END 6 */ -} -#endif /* USE_FULL_ASSERT */ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * Copyright (c) 2026 STMicroelectronics. + * Copyright (c) 2026 Erick Ahmed. + * + * SPDX-License-Identifier: GPL-3.0-or-later + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "cmsis_os.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include "canlog.h" +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +CAN_HandleTypeDef hcan1; +CAN_HandleTypeDef hcan2; + +SD_HandleTypeDef hsd; +DMA_HandleTypeDef hdma_sdio_rx; +DMA_HandleTypeDef hdma_sdio_tx; + +/* USER CODE BEGIN PV */ +LED_Config led_can1 = {GPIOB, GPIO_PIN_2}; +LED_Config led_can2 = {GPIOB, GPIO_PIN_5}; +LED_Config led_error = {GPIOB, GPIO_PIN_3}; + +LEDContext ledContextCAN1; +LEDContext ledContextCAN2; + +osSemaphoreId_t xSemaphoreCAN1; +osSemaphoreId_t xSemaphoreCAN2; + +osTimerId_t xHeartbeatTimerCAN1; +osTimerId_t xHeartbeatTimerCAN2; + +osMessageQueueId_t xCAN1RxQueue; +osMessageQueueId_t xCAN2RxQueue; +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_DMA_Init(void); +static void MX_CAN1_Init(void); +static void MX_CAN2_Init(void); +static void MX_SDIO_SD_Init(void); + +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_DMA_Init(); + MX_CAN1_Init(); + MX_CAN2_Init(); + MX_SDIO_SD_Init(); + + /* USER CODE BEGIN 2 */ + CAN_Logger_Init(&hcan1, &hcan2); + /* USER CODE END 2 */ + + /* Init scheduler */ + osKernelInitialize(); + + /* USER CODE BEGIN RTOS_TASKS */ + osThreadId_t xCAN1rx; + const osThreadAttr_t CAN1rxAttributes = { + .name = "CAN1rx", + .stack_size = 128 * 4, + .priority = (osPriority_t) osPriorityRealtime1, + }; + osThreadId_t xCAN2rx; + const osThreadAttr_t CAN2rxAttributes = { + .name = "CAN2rx", + .stack_size = 128 * 4, + .priority = (osPriority_t) osPriorityRealtime, + }; + /* USER END RTOS_TASKS */ + + /* USER CODE BEGIN RTOS_MUTEX */ + /* add mutexes, ... */ + /* USER CODE END RTOS_MUTEX */ + + /* USER CODE BEGIN RTOS_SEMAPHORES */ + xSemaphoreCAN1 = osSemaphoreNew(10, 0, NULL); + xSemaphoreCAN2 = osSemaphoreNew(10, 0, NULL); + + if (xSemaphoreCAN1 == NULL || xSemaphoreCAN2 == NULL) Error_Handler(); + + ledContextCAN1.led = &led_can1; + ledContextCAN1.semaphore = xSemaphoreCAN1; + ledContextCAN2.led = &led_can2; + ledContextCAN2.semaphore = xSemaphoreCAN2; + /* USER CODE END RTOS_SEMAPHORES */ + + /* USER CODE BEGIN RTOS_TIMERS */ + xHeartbeatTimerCAN1 = osTimerNew(vLEDHeartbeat, osTimerOnce, &ledContextCAN1, NULL); + xHeartbeatTimerCAN2 = osTimerNew(vLEDHeartbeat, osTimerOnce, &ledContextCAN2, NULL); + + osTimerStart(xHeartbeatTimerCAN1, 25U); + osTimerStart(xHeartbeatTimerCAN2, 25U); + + if (xHeartbeatTimerCAN1 == NULL || xHeartbeatTimerCAN2 == NULL) Error_Handler(); + + ledContextCAN1.timer = xHeartbeatTimerCAN1; + ledContextCAN2.timer = xHeartbeatTimerCAN2; + /* USER CODE END RTOS_TIMERS */ + + /* USER CODE BEGIN RTOS_QUEUES */ + xCAN1RxQueue = osMessageQueueNew(32, sizeof(CanMessage_t), NULL); + xCAN2RxQueue = osMessageQueueNew(32, sizeof(CanMessage_t), NULL); + + if (xCAN1RxQueue == NULL || xCAN2RxQueue == NULL) Error_Handler(); + /* USER CODE END RTOS_QUEUES */ + + /* USER CODE BEGIN RTOS_THREADS */ + xCAN1rx = osThreadNew(vCANLoggerListen, &hcan1, &CAN1rxAttributes); + xCAN2rx = osThreadNew(vCANLoggerListen, &hcan2, &CAN2rxAttributes); + /* USER CODE END RTOS_THREADS */ + + /* USER CODE BEGIN RTOS_EVENTS */ + /* add events, ... */ + /* USER CODE END RTOS_EVENTS */ + + /* USER CODE BEGIN 3 */ + ledContextCAN1.led = &led_can1; + ledContextCAN1.semaphore = xSemaphoreCAN1; + ledContextCAN1.timer = xHeartbeatTimerCAN1; + + ledContextCAN2.led = &led_can2; + ledContextCAN2.semaphore = xSemaphoreCAN2; + ledContextCAN2.timer = xHeartbeatTimerCAN2; + /* USER CODE END 3 */ + + /* Start scheduler */ + osKernelStart(); + + /* We should never get here as control is now taken by the scheduler */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 4 */ + } + /* USER CODE END 4 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 16; + RCC_OscInitStruct.PLL.PLLN = 336; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 7; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV4; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief CAN1 Initialization Function + * @param None + * @retval None + */ +static void MX_CAN1_Init(void) +{ + + /* USER CODE BEGIN CAN1_Init 0 */ + + /* USER CODE END CAN1_Init 0 */ + + /* USER CODE BEGIN CAN1_Init 1 */ + + /* USER CODE END CAN1_Init 1 */ + hcan1.Instance = CAN1; + hcan1.Init.Prescaler = 4; + hcan1.Init.Mode = CAN_MODE_SILENT; + hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ; + hcan1.Init.TimeSeg1 = CAN_BS1_16TQ; + hcan1.Init.TimeSeg2 = CAN_BS2_4TQ; + hcan1.Init.TimeTriggeredMode = DISABLE; + hcan1.Init.AutoBusOff = DISABLE; + hcan1.Init.AutoWakeUp = ENABLE; + hcan1.Init.AutoRetransmission = DISABLE; + hcan1.Init.ReceiveFifoLocked = DISABLE; + hcan1.Init.TransmitFifoPriority = DISABLE; + if (HAL_CAN_Init(&hcan1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN CAN1_Init 2 */ + + /* USER CODE END CAN1_Init 2 */ + +} + +/** + * @brief CAN2 Initialization Function + * @param None + * @retval None + */ +static void MX_CAN2_Init(void) +{ + + /* USER CODE BEGIN CAN2_Init 0 */ + + /* USER CODE END CAN2_Init 0 */ + + /* USER CODE BEGIN CAN2_Init 1 */ + + /* USER CODE END CAN2_Init 1 */ + hcan2.Instance = CAN2; + hcan2.Init.Prescaler = 8; + hcan2.Init.Mode = CAN_MODE_SILENT; + hcan2.Init.SyncJumpWidth = CAN_SJW_1TQ; + hcan2.Init.TimeSeg1 = CAN_BS1_16TQ; + hcan2.Init.TimeSeg2 = CAN_BS2_4TQ; + hcan2.Init.TimeTriggeredMode = DISABLE; + hcan2.Init.AutoBusOff = DISABLE; + hcan2.Init.AutoWakeUp = ENABLE; + hcan2.Init.AutoRetransmission = DISABLE; + hcan2.Init.ReceiveFifoLocked = DISABLE; + hcan2.Init.TransmitFifoPriority = DISABLE; + if (HAL_CAN_Init(&hcan2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN CAN2_Init 2 */ + + /* USER CODE END CAN2_Init 2 */ + +} + +/** + * @brief SDIO Initialization Function + * @param None + * @retval None + */ +static void MX_SDIO_SD_Init(void) +{ + + /* USER CODE BEGIN SDIO_Init 0 */ + + /* USER CODE END SDIO_Init 0 */ + + /* USER CODE BEGIN SDIO_Init 1 */ + + /* USER CODE END SDIO_Init 1 */ + hsd.Instance = SDIO; + hsd.Init.ClockEdge = SDIO_CLOCK_EDGE_RISING; + hsd.Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; + hsd.Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; + hsd.Init.BusWide = SDIO_BUS_WIDE_1B; + hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; + hsd.Init.ClockDiv = 0; + if (HAL_SD_Init(&hsd) != HAL_OK) + { + Error_Handler(); + } + if (HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SDIO_Init 2 */ + + /* USER CODE END SDIO_Init 2 */ + +} + +/** + * Enable DMA controller clock + */ +static void MX_DMA_Init(void) +{ + + /* DMA controller clock enable */ + __HAL_RCC_DMA2_CLK_ENABLE(); + + /* DMA interrupt init */ + /* DMA2_Stream3_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA2_Stream3_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream3_IRQn); + /* DMA2_Stream6_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA2_Stream6_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream6_IRQn); + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + /* USER CODE BEGIN MX_GPIO_Init_1 */ + + /* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5, GPIO_PIN_RESET); + + /*Configure GPIO pins : PC13 PC14 PC15 PC0 + PC1 PC2 PC3 PC4 + PC5 PC6 PC7 */ + GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15|GPIO_PIN_0 + |GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4 + |GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /*Configure GPIO pins : PH0 PH1 */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + + /*Configure GPIO pins : PA0 PA1 PA2 PA3 + PA4 PA5 PA6 PA7 + PA8 PA9 PA10 PA11 + PA12 PA13 PA14 PA15 */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7 + |GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*Configure GPIO pins : PB0 PB1 PB2 PB10 + PB11 PB14 PB15 PB6 + PB7 */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_15|GPIO_PIN_6 + |GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /*Configure GPIO pins : PB3 PB4 PB5 */ + GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN MX_GPIO_Init_2 */ + + /* USER CODE END MX_GPIO_Init_2 */ +} + +/* USER CODE BEGIN 5 */ + +/* USER CODE END 5 */ + +/** + * @brief Period elapsed callback in non blocking mode + * @note This function is called when TIM6 interrupt took place, inside + * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment + * a global variable "uwTick" used as application time base. + * @param htim : TIM handle + * @retval None + */ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* USER CODE BEGIN Callback 0 */ + + /* USER CODE END Callback 0 */ + if (htim->Instance == TIM6) + { + HAL_IncTick(); + } + /* USER CODE BEGIN Callback 1 */ + + /* USER CODE END Callback 1 */ +} + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + + //TODO: check if it is necessary to stop FreeRTOS + + uint32_t error_code_can1; + uint32_t error_code_can2; + + if (HAL_CAN_GetState(&hcan1) != HAL_CAN_STATE_READY) error_code_can1 = HAL_CAN_GetError(&hcan1); + if (HAL_CAN_GetState(&hcan2) != HAL_CAN_STATE_READY) error_code_can2 = HAL_CAN_GetError(&hcan2); + + // TODO: write error to SD and/or serial + + HAL_GPIO_WritePin(led_can1.port, led_can1.pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(led_can2.port, led_can2.pin, GPIO_PIN_RESET); + + while (1) + { + HAL_GPIO_TogglePin(led_error.port, led_error.pin); + HAL_Delay(250); + } + /* USER CODE END Error_Handler_Debug */ +} +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/Debug/Core/Src/freertos.d b/Debug/Core/Src/freertos.d index 97bd882..1be72de 100644 --- a/Debug/Core/Src/freertos.d +++ b/Debug/Core/Src/freertos.d @@ -34,8 +34,13 @@ Core/Src/freertos.o: ../Core/Src/freertos.c \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Core/Inc/canlog.h ../Core/Inc/main.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: ../Core/Inc/FreeRTOSConfig.h: ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: @@ -72,5 +77,11 @@ Core/Src/freertos.o: ../Core/Src/freertos.c \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Core/Inc/canlog.h: +../Core/Inc/main.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h: diff --git a/Debug/Core/Src/freertos.o b/Debug/Core/Src/freertos.o index daabdde..b3abc6d 100644 Binary files a/Debug/Core/Src/freertos.o and b/Debug/Core/Src/freertos.o differ diff --git a/Debug/Core/Src/main.cyclo b/Debug/Core/Src/main.cyclo index 74b58ae..69ea210 100644 --- a/Debug/Core/Src/main.cyclo +++ b/Debug/Core/Src/main.cyclo @@ -1,9 +1,10 @@ -../Core/Src/main.c:78:5:main 1 -../Core/Src/main.c:160:6:SystemClock_Config 3 -../Core/Src/main.c:202:13:MX_CAN1_Init 2 -../Core/Src/main.c:239:13:MX_CAN2_Init 2 -../Core/Src/main.c:276:13:MX_GPIO_Init 1 -../Core/Src/main.c:352:6:StartDefaultTask 1 -../Core/Src/main.c:371:6:HAL_TIM_PeriodElapsedCallback 2 -../Core/Src/main.c:389:6:Error_Handler 1 -../Core/Src/main.c:407:6:assert_failed 1 +../Core/Src/main.c:88:5:main 7 +../Core/Src/main.c:215:6:SystemClock_Config 3 +../Core/Src/main.c:262:13:MX_CAN1_Init 2 +../Core/Src/main.c:299:13:MX_CAN2_Init 2 +../Core/Src/main.c:336:13:MX_SDIO_SD_Init 3 +../Core/Src/main.c:370:13:MX_DMA_Init 1 +../Core/Src/main.c:391:13:MX_GPIO_Init 1 +../Core/Src/main.c:470:6:HAL_TIM_PeriodElapsedCallback 2 +../Core/Src/main.c:488:6:Error_Handler 3 +../Core/Src/main.c:522:6:assert_failed 1 diff --git a/Debug/Core/Src/main.d b/Debug/Core/Src/main.d index 321b6a6..6f27426 100644 --- a/Debug/Core/Src/main.d +++ b/Debug/Core/Src/main.d @@ -25,8 +25,11 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Core/Inc/canlog.h ../Core/Inc/main.h \ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h \ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ ../Core/Inc/FreeRTOSConfig.h \ @@ -37,7 +40,8 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ - ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h \ + ../Core/Inc/canlog.h ../Core/Inc/main.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: ../Core/Inc/stm32f4xx_hal_conf.h: @@ -65,8 +69,12 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Core/Inc/canlog.h: +../Core/Inc/main.h: ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h: ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: ../Core/Inc/FreeRTOSConfig.h: @@ -78,3 +86,4 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h: +../Core/Inc/canlog.h: diff --git a/Debug/Core/Src/main.o b/Debug/Core/Src/main.o index 28fe647..a192a49 100644 Binary files a/Debug/Core/Src/main.o and b/Debug/Core/Src/main.o differ diff --git a/Debug/Core/Src/main.su b/Debug/Core/Src/main.su index 2f7eac2..d3294f2 100644 --- a/Debug/Core/Src/main.su +++ b/Debug/Core/Src/main.su @@ -1,9 +1,10 @@ -../Core/Src/main.c:78:5:main 8 static -../Core/Src/main.c:160:6:SystemClock_Config 88 static -../Core/Src/main.c:202:13:MX_CAN1_Init 8 static -../Core/Src/main.c:239:13:MX_CAN2_Init 8 static -../Core/Src/main.c:276:13:MX_GPIO_Init 48 static -../Core/Src/main.c:352:6:StartDefaultTask 16 static -../Core/Src/main.c:371:6:HAL_TIM_PeriodElapsedCallback 16 static -../Core/Src/main.c:389:6:Error_Handler 4 static,ignoring_inline_asm -../Core/Src/main.c:407:6:assert_failed 16 static +../Core/Src/main.c:88:5:main 88 static +../Core/Src/main.c:215:6:SystemClock_Config 88 static +../Core/Src/main.c:262:13:MX_CAN1_Init 8 static +../Core/Src/main.c:299:13:MX_CAN2_Init 8 static +../Core/Src/main.c:336:13:MX_SDIO_SD_Init 8 static +../Core/Src/main.c:370:13:MX_DMA_Init 16 static +../Core/Src/main.c:391:13:MX_GPIO_Init 48 static +../Core/Src/main.c:470:6:HAL_TIM_PeriodElapsedCallback 16 static +../Core/Src/main.c:488:6:Error_Handler 16 static,ignoring_inline_asm +../Core/Src/main.c:522:6:assert_failed 16 static diff --git a/Debug/Core/Src/stm32f4xx_hal_msp.cyclo b/Debug/Core/Src/stm32f4xx_hal_msp.cyclo index ad85900..02c3e74 100644 --- a/Debug/Core/Src/stm32f4xx_hal_msp.cyclo +++ b/Debug/Core/Src/stm32f4xx_hal_msp.cyclo @@ -1,3 +1,5 @@ -../Core/Src/stm32f4xx_hal_msp.c:62:6:HAL_MspInit 1 -../Core/Src/stm32f4xx_hal_msp.c:89:6:HAL_CAN_MspInit 5 -../Core/Src/stm32f4xx_hal_msp.c:156:6:HAL_CAN_MspDeInit 5 +../Core/Src/stm32f4xx_hal_msp.c:65:6:HAL_MspInit 1 +../Core/Src/stm32f4xx_hal_msp.c:92:6:HAL_CAN_MspInit 5 +../Core/Src/stm32f4xx_hal_msp.c:159:6:HAL_CAN_MspDeInit 5 +../Core/Src/stm32f4xx_hal_msp.c:213:6:HAL_SD_MspInit 4 +../Core/Src/stm32f4xx_hal_msp.c:309:6:HAL_SD_MspDeInit 2 diff --git a/Debug/Core/Src/stm32f4xx_hal_msp.d b/Debug/Core/Src/stm32f4xx_hal_msp.d index 2c0e58f..e40466c 100644 --- a/Debug/Core/Src/stm32f4xx_hal_msp.d +++ b/Debug/Core/Src/stm32f4xx_hal_msp.d @@ -25,8 +25,22 @@ Core/Src/stm32f4xx_hal_msp.o: ../Core/Src/stm32f4xx_hal_msp.c \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Core/Inc/canlog.h ../Core/Inc/main.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h ../Core/Inc/main.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: ../Core/Inc/stm32f4xx_hal_conf.h: @@ -54,5 +68,20 @@ Core/Src/stm32f4xx_hal_msp.o: ../Core/Src/stm32f4xx_hal_msp.c \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Core/Inc/canlog.h: +../Core/Inc/main.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h: diff --git a/Debug/Core/Src/stm32f4xx_hal_msp.o b/Debug/Core/Src/stm32f4xx_hal_msp.o index 69c1500..cd9a61f 100644 Binary files a/Debug/Core/Src/stm32f4xx_hal_msp.o and b/Debug/Core/Src/stm32f4xx_hal_msp.o differ diff --git a/Debug/Core/Src/stm32f4xx_hal_msp.su b/Debug/Core/Src/stm32f4xx_hal_msp.su index 25a071a..ae116e1 100644 --- a/Debug/Core/Src/stm32f4xx_hal_msp.su +++ b/Debug/Core/Src/stm32f4xx_hal_msp.su @@ -1,3 +1,5 @@ -../Core/Src/stm32f4xx_hal_msp.c:62:6:HAL_MspInit 16 static -../Core/Src/stm32f4xx_hal_msp.c:89:6:HAL_CAN_MspInit 56 static -../Core/Src/stm32f4xx_hal_msp.c:156:6:HAL_CAN_MspDeInit 16 static +../Core/Src/stm32f4xx_hal_msp.c:65:6:HAL_MspInit 16 static +../Core/Src/stm32f4xx_hal_msp.c:92:6:HAL_CAN_MspInit 56 static +../Core/Src/stm32f4xx_hal_msp.c:159:6:HAL_CAN_MspDeInit 16 static +../Core/Src/stm32f4xx_hal_msp.c:213:6:HAL_SD_MspInit 48 static +../Core/Src/stm32f4xx_hal_msp.c:309:6:HAL_SD_MspDeInit 16 static diff --git a/Debug/Core/Src/stm32f4xx_hal_timebase_tim.d b/Debug/Core/Src/stm32f4xx_hal_timebase_tim.d index dbfb08e..4753c22 100644 --- a/Debug/Core/Src/stm32f4xx_hal_timebase_tim.d +++ b/Debug/Core/Src/stm32f4xx_hal_timebase_tim.d @@ -26,6 +26,8 @@ Core/Src/stm32f4xx_hal_timebase_tim.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: @@ -54,5 +56,7 @@ Core/Src/stm32f4xx_hal_timebase_tim.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Core/Src/stm32f4xx_hal_timebase_tim.o b/Debug/Core/Src/stm32f4xx_hal_timebase_tim.o index 71b1cc1..9758b56 100644 Binary files a/Debug/Core/Src/stm32f4xx_hal_timebase_tim.o and b/Debug/Core/Src/stm32f4xx_hal_timebase_tim.o differ diff --git a/Debug/Core/Src/stm32f4xx_it.cyclo b/Debug/Core/Src/stm32f4xx_it.cyclo index a6ea334..9b18d31 100644 --- a/Debug/Core/Src/stm32f4xx_it.cyclo +++ b/Debug/Core/Src/stm32f4xx_it.cyclo @@ -1,7 +1,10 @@ -../Core/Src/stm32f4xx_it.c:70:6:NMI_Handler 1 -../Core/Src/stm32f4xx_it.c:85:6:HardFault_Handler 1 -../Core/Src/stm32f4xx_it.c:100:6:MemManage_Handler 1 -../Core/Src/stm32f4xx_it.c:115:6:BusFault_Handler 1 -../Core/Src/stm32f4xx_it.c:130:6:UsageFault_Handler 1 -../Core/Src/stm32f4xx_it.c:145:6:DebugMon_Handler 1 -../Core/Src/stm32f4xx_it.c:165:6:TIM6_DAC_IRQHandler 1 +../Core/Src/stm32f4xx_it.c:73:6:NMI_Handler 1 +../Core/Src/stm32f4xx_it.c:88:6:HardFault_Handler 1 +../Core/Src/stm32f4xx_it.c:103:6:MemManage_Handler 1 +../Core/Src/stm32f4xx_it.c:118:6:BusFault_Handler 1 +../Core/Src/stm32f4xx_it.c:133:6:UsageFault_Handler 1 +../Core/Src/stm32f4xx_it.c:148:6:DebugMon_Handler 1 +../Core/Src/stm32f4xx_it.c:168:6:SDIO_IRQHandler 1 +../Core/Src/stm32f4xx_it.c:182:6:TIM6_DAC_IRQHandler 1 +../Core/Src/stm32f4xx_it.c:196:6:DMA2_Stream3_IRQHandler 1 +../Core/Src/stm32f4xx_it.c:210:6:DMA2_Stream6_IRQHandler 1 diff --git a/Debug/Core/Src/stm32f4xx_it.d b/Debug/Core/Src/stm32f4xx_it.d index 5f3a03d..767a1d8 100644 --- a/Debug/Core/Src/stm32f4xx_it.d +++ b/Debug/Core/Src/stm32f4xx_it.d @@ -25,8 +25,22 @@ Core/Src/stm32f4xx_it.o: ../Core/Src/stm32f4xx_it.c ../Core/Inc/main.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Core/Inc/canlog.h ../Core/Inc/main.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h \ ../Core/Inc/stm32f4xx_it.h ../Core/Inc/main.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: @@ -55,6 +69,21 @@ Core/Src/stm32f4xx_it.o: ../Core/Src/stm32f4xx_it.c ../Core/Inc/main.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Core/Inc/canlog.h: +../Core/Inc/main.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h: ../Core/Inc/stm32f4xx_it.h: diff --git a/Debug/Core/Src/stm32f4xx_it.o b/Debug/Core/Src/stm32f4xx_it.o index 610a081..303d75c 100644 Binary files a/Debug/Core/Src/stm32f4xx_it.o and b/Debug/Core/Src/stm32f4xx_it.o differ diff --git a/Debug/Core/Src/stm32f4xx_it.su b/Debug/Core/Src/stm32f4xx_it.su index f298b88..b21ea59 100644 --- a/Debug/Core/Src/stm32f4xx_it.su +++ b/Debug/Core/Src/stm32f4xx_it.su @@ -1,7 +1,10 @@ -../Core/Src/stm32f4xx_it.c:70:6:NMI_Handler 4 static -../Core/Src/stm32f4xx_it.c:85:6:HardFault_Handler 4 static -../Core/Src/stm32f4xx_it.c:100:6:MemManage_Handler 4 static -../Core/Src/stm32f4xx_it.c:115:6:BusFault_Handler 4 static -../Core/Src/stm32f4xx_it.c:130:6:UsageFault_Handler 4 static -../Core/Src/stm32f4xx_it.c:145:6:DebugMon_Handler 4 static -../Core/Src/stm32f4xx_it.c:165:6:TIM6_DAC_IRQHandler 8 static +../Core/Src/stm32f4xx_it.c:73:6:NMI_Handler 4 static +../Core/Src/stm32f4xx_it.c:88:6:HardFault_Handler 4 static +../Core/Src/stm32f4xx_it.c:103:6:MemManage_Handler 4 static +../Core/Src/stm32f4xx_it.c:118:6:BusFault_Handler 4 static +../Core/Src/stm32f4xx_it.c:133:6:UsageFault_Handler 4 static +../Core/Src/stm32f4xx_it.c:148:6:DebugMon_Handler 4 static +../Core/Src/stm32f4xx_it.c:168:6:SDIO_IRQHandler 8 static +../Core/Src/stm32f4xx_it.c:182:6:TIM6_DAC_IRQHandler 8 static +../Core/Src/stm32f4xx_it.c:196:6:DMA2_Stream3_IRQHandler 8 static +../Core/Src/stm32f4xx_it.c:210:6:DMA2_Stream6_IRQHandler 8 static diff --git a/Debug/Core/Src/subdir.mk b/Debug/Core/Src/subdir.mk index 3350efc..b79fab9 100644 --- a/Debug/Core/Src/subdir.mk +++ b/Debug/Core/Src/subdir.mk @@ -5,6 +5,7 @@ # Add inputs and outputs from these tool invocations to the build variables C_SRCS += \ +../Core/Src/canlog.c \ ../Core/Src/freertos.c \ ../Core/Src/main.c \ ../Core/Src/stm32f4xx_hal_msp.c \ @@ -15,6 +16,7 @@ C_SRCS += \ ../Core/Src/system_stm32f4xx.c OBJS += \ +./Core/Src/canlog.o \ ./Core/Src/freertos.o \ ./Core/Src/main.o \ ./Core/Src/stm32f4xx_hal_msp.o \ @@ -25,6 +27,7 @@ OBJS += \ ./Core/Src/system_stm32f4xx.o C_DEPS += \ +./Core/Src/canlog.d \ ./Core/Src/freertos.d \ ./Core/Src/main.d \ ./Core/Src/stm32f4xx_hal_msp.d \ @@ -37,12 +40,12 @@ C_DEPS += \ # Each subdirectory must supply rules for building sources it contributes Core/Src/%.o Core/Src/%.su Core/Src/%.cyclo: ../Core/Src/%.c Core/Src/subdir.mk - arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F405xx -DSTM32_THREAD_SAFE_STRATEGY=4 -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../Core/ThreadSafe -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F405xx -DSTM32_THREAD_SAFE_STRATEGY=4 -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../Core/ThreadSafe -I../Core/Src/ThreadSafe -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" clean: clean-Core-2f-Src clean-Core-2f-Src: - -$(RM) ./Core/Src/freertos.cyclo ./Core/Src/freertos.d ./Core/Src/freertos.o ./Core/Src/freertos.su ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/stm32f4xx_hal_msp.cyclo ./Core/Src/stm32f4xx_hal_msp.d ./Core/Src/stm32f4xx_hal_msp.o ./Core/Src/stm32f4xx_hal_msp.su ./Core/Src/stm32f4xx_hal_timebase_tim.cyclo ./Core/Src/stm32f4xx_hal_timebase_tim.d ./Core/Src/stm32f4xx_hal_timebase_tim.o ./Core/Src/stm32f4xx_hal_timebase_tim.su ./Core/Src/stm32f4xx_it.cyclo ./Core/Src/stm32f4xx_it.d ./Core/Src/stm32f4xx_it.o ./Core/Src/stm32f4xx_it.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32f4xx.cyclo ./Core/Src/system_stm32f4xx.d ./Core/Src/system_stm32f4xx.o ./Core/Src/system_stm32f4xx.su + -$(RM) ./Core/Src/canlog.cyclo ./Core/Src/canlog.d ./Core/Src/canlog.o ./Core/Src/canlog.su ./Core/Src/freertos.cyclo ./Core/Src/freertos.d ./Core/Src/freertos.o ./Core/Src/freertos.su ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/stm32f4xx_hal_msp.cyclo ./Core/Src/stm32f4xx_hal_msp.d ./Core/Src/stm32f4xx_hal_msp.o ./Core/Src/stm32f4xx_hal_msp.su ./Core/Src/stm32f4xx_hal_timebase_tim.cyclo ./Core/Src/stm32f4xx_hal_timebase_tim.d ./Core/Src/stm32f4xx_hal_timebase_tim.o ./Core/Src/stm32f4xx_hal_timebase_tim.su ./Core/Src/stm32f4xx_it.cyclo ./Core/Src/stm32f4xx_it.d ./Core/Src/stm32f4xx_it.o ./Core/Src/stm32f4xx_it.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32f4xx.cyclo ./Core/Src/system_stm32f4xx.d ./Core/Src/system_stm32f4xx.o ./Core/Src/system_stm32f4xx.su .PHONY: clean-Core-2f-Src diff --git a/Debug/Core/Src/syscalls.o b/Debug/Core/Src/syscalls.o index aff9b28..f53219d 100644 Binary files a/Debug/Core/Src/syscalls.o and b/Debug/Core/Src/syscalls.o differ diff --git a/Debug/Core/Src/sysmem.o b/Debug/Core/Src/sysmem.o index 914e537..24b811e 100644 Binary files a/Debug/Core/Src/sysmem.o and b/Debug/Core/Src/sysmem.o differ diff --git a/Debug/Core/Src/system_stm32f4xx.d b/Debug/Core/Src/system_stm32f4xx.d index 60d6202..fff1cc4 100644 --- a/Debug/Core/Src/system_stm32f4xx.d +++ b/Debug/Core/Src/system_stm32f4xx.d @@ -25,6 +25,8 @@ Core/Src/system_stm32f4xx.o: ../Core/Src/system_stm32f4xx.c \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: @@ -53,5 +55,7 @@ Core/Src/system_stm32f4xx.o: ../Core/Src/system_stm32f4xx.c \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Core/Src/system_stm32f4xx.o b/Debug/Core/Src/system_stm32f4xx.o index 3404dfa..1908cbe 100644 Binary files a/Debug/Core/Src/system_stm32f4xx.o and b/Debug/Core/Src/system_stm32f4xx.o differ diff --git a/Debug/Core/Startup/startup_stm32f405rgtx.o b/Debug/Core/Startup/startup_stm32f405rgtx.o index 6897669..afe0c80 100644 Binary files a/Debug/Core/Startup/startup_stm32f405rgtx.o and b/Debug/Core/Startup/startup_stm32f405rgtx.o differ diff --git a/Debug/Core/ThreadSafe/newlib_lock_glue.o b/Debug/Core/ThreadSafe/newlib_lock_glue.o index 1df886d..47f478b 100644 Binary files a/Debug/Core/ThreadSafe/newlib_lock_glue.o and b/Debug/Core/ThreadSafe/newlib_lock_glue.o differ diff --git a/Debug/Core/ThreadSafe/subdir.mk b/Debug/Core/ThreadSafe/subdir.mk index afb761c..de87315 100644 --- a/Debug/Core/ThreadSafe/subdir.mk +++ b/Debug/Core/ThreadSafe/subdir.mk @@ -16,7 +16,7 @@ C_DEPS += \ # Each subdirectory must supply rules for building sources it contributes Core/ThreadSafe/%.o Core/ThreadSafe/%.su Core/ThreadSafe/%.cyclo: ../Core/ThreadSafe/%.c Core/ThreadSafe/subdir.mk - arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F405xx -DSTM32_THREAD_SAFE_STRATEGY=4 -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../Core/ThreadSafe -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F405xx -DSTM32_THREAD_SAFE_STRATEGY=4 -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../Core/ThreadSafe -I../Core/Src/ThreadSafe -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" clean: clean-Core-2f-ThreadSafe diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d index 223de20..6b18705 100644 --- a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d @@ -26,6 +26,8 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: @@ -54,5 +56,7 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o index f57e6f6..56714b4 100644 Binary files a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.d index 314697e..d00d4ed 100644 --- a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.d +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.d @@ -26,6 +26,8 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: @@ -54,5 +56,7 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o index 9deb965..33c5f9f 100644 Binary files a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d index 995dc2b..b02b6d6 100644 --- a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d @@ -26,6 +26,8 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: @@ -54,5 +56,7 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o index 5649acd..2fb45e1 100644 Binary files a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d index a0798bf..5f712d0 100644 --- a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d @@ -26,6 +26,8 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: @@ -54,5 +56,7 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o index 9a691b7..ecb8ef3 100644 Binary files a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d index fe978db..efd1c74 100644 --- a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d @@ -26,6 +26,8 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: @@ -54,5 +56,7 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o index 1ebeaba..a3ec183 100644 Binary files a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d index dcdf540..8293ac6 100644 --- a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d @@ -26,6 +26,8 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: @@ -54,5 +56,7 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o index 394656a..03b444d 100644 Binary files a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d index 58f33bb..18aba06 100644 --- a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d @@ -26,6 +26,8 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: @@ -54,5 +56,7 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o index 5105b1e..467e715 100644 Binary files a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d index f3bf77e..e5fc7e5 100644 --- a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d @@ -26,6 +26,8 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: @@ -54,5 +56,7 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o index 1790c16..f5bd1a3 100644 Binary files a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d index c405e10..add142a 100644 --- a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d @@ -26,6 +26,8 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: @@ -54,5 +56,7 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o index f1ff828..b9bba3e 100644 Binary files a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d index 9281fb5..eb088b5 100644 --- a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d @@ -26,6 +26,8 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: @@ -54,5 +56,7 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o index 7dd2aee..499f8b9 100644 Binary files a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d index 3ce4d19..808630b 100644 --- a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d @@ -26,6 +26,8 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: @@ -54,5 +56,7 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o index e3e9b7e..7fe53f6 100644 Binary files a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d index 39a0de8..1a964ee 100644 --- a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d @@ -26,6 +26,8 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: @@ -54,5 +56,7 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o index 84943ab..eb9fe4a 100644 Binary files a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d index 9b9285a..f1dcbf8 100644 --- a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d @@ -26,6 +26,8 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: @@ -54,5 +56,7 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o index edd400f..07a5af5 100644 Binary files a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d index 5a4a9d2..1cd03ea 100644 --- a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d @@ -26,6 +26,8 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: @@ -54,5 +56,7 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o index 2c13eac..e69c010 100644 Binary files a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d index 2a238f0..16f2b67 100644 --- a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d @@ -26,6 +26,8 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: @@ -54,5 +56,7 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o index 3eb2919..dd48c6f 100644 Binary files a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d index 03c321d..faabd72 100644 --- a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d @@ -26,6 +26,8 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: @@ -54,5 +56,7 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o index e8b1c3e..d6b1ce7 100644 Binary files a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o and b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o differ diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk index c77e4db..e21fed4 100644 --- a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk @@ -15,12 +15,15 @@ C_SRCS += \ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c \ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c \ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.c \ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c \ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c \ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c \ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c \ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c \ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c OBJS += \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o \ @@ -33,12 +36,15 @@ OBJS += \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o C_DEPS += \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d \ @@ -51,22 +57,25 @@ C_DEPS += \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.d \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.d \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.d # Each subdirectory must supply rules for building sources it contributes Drivers/STM32F4xx_HAL_Driver/Src/%.o Drivers/STM32F4xx_HAL_Driver/Src/%.su Drivers/STM32F4xx_HAL_Driver/Src/%.cyclo: ../Drivers/STM32F4xx_HAL_Driver/Src/%.c Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk - arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F405xx -DSTM32_THREAD_SAFE_STRATEGY=4 -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../Core/ThreadSafe -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F405xx -DSTM32_THREAD_SAFE_STRATEGY=4 -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../Core/ThreadSafe -I../Core/Src/ThreadSafe -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" clean: clean-Drivers-2f-STM32F4xx_HAL_Driver-2f-Src clean-Drivers-2f-STM32F4xx_HAL_Driver-2f-Src: - -$(RM) ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su + -$(RM) ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.su .PHONY: clean-Drivers-2f-STM32F4xx_HAL_Driver-2f-Src diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.d b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.d index 1bca156..95dcac7 100644 --- a/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.d +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.d @@ -44,6 +44,8 @@ Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h: @@ -90,5 +92,7 @@ Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o index 2515034..1c00b04 100644 Binary files a/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o differ diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/subdir.mk b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/subdir.mk index 4dc3547..8c049de 100644 --- a/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/subdir.mk +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/subdir.mk @@ -16,7 +16,7 @@ C_DEPS += \ # Each subdirectory must supply rules for building sources it contributes Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/%.o Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/%.su Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/%.cyclo: ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/%.c Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/subdir.mk - arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F405xx -DSTM32_THREAD_SAFE_STRATEGY=4 -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../Core/ThreadSafe -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F405xx -DSTM32_THREAD_SAFE_STRATEGY=4 -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../Core/ThreadSafe -I../Core/Src/ThreadSafe -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" clean: clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-CMSIS_RTOS_V2 diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.o index b2a44df..12e62f9 100644 Binary files a/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.o and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.o differ diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.o index 828dbcd..154a520 100644 Binary files a/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.o and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.o differ diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.o index 958bd8a..0c56c8a 100644 Binary files a/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.o and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.o differ diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o index f121c7a..8855232 100644 Binary files a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o differ diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/subdir.mk b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/subdir.mk index 90b7257..468df6f 100644 --- a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/subdir.mk +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/subdir.mk @@ -16,7 +16,7 @@ C_DEPS += \ # Each subdirectory must supply rules for building sources it contributes Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/%.o Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/%.su Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/%.cyclo: ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/%.c Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/subdir.mk - arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F405xx -DSTM32_THREAD_SAFE_STRATEGY=4 -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../Core/ThreadSafe -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F405xx -DSTM32_THREAD_SAFE_STRATEGY=4 -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../Core/ThreadSafe -I../Core/Src/ThreadSafe -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" clean: clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-portable-2f-GCC-2f-ARM_CM4F diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o index 91bbc34..a3da882 100644 Binary files a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o differ diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk index 370a730..61c60dc 100644 --- a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk @@ -16,7 +16,7 @@ C_DEPS += \ # Each subdirectory must supply rules for building sources it contributes Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/%.o Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/%.su Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/%.cyclo: ../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/%.c Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk - arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F405xx -DSTM32_THREAD_SAFE_STRATEGY=4 -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../Core/ThreadSafe -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F405xx -DSTM32_THREAD_SAFE_STRATEGY=4 -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../Core/ThreadSafe -I../Core/Src/ThreadSafe -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" clean: clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-portable-2f-MemMang diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.o index 802f0b9..72d9c80 100644 Binary files a/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.o and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.o differ diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o index 19c1138..f7edca1 100644 Binary files a/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o differ diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/subdir.mk b/Debug/Middlewares/Third_Party/FreeRTOS/Source/subdir.mk index 3294f24..a078984 100644 --- a/Debug/Middlewares/Third_Party/FreeRTOS/Source/subdir.mk +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/subdir.mk @@ -34,7 +34,7 @@ C_DEPS += \ # Each subdirectory must supply rules for building sources it contributes Middlewares/Third_Party/FreeRTOS/Source/%.o Middlewares/Third_Party/FreeRTOS/Source/%.su Middlewares/Third_Party/FreeRTOS/Source/%.cyclo: ../Middlewares/Third_Party/FreeRTOS/Source/%.c Middlewares/Third_Party/FreeRTOS/Source/subdir.mk - arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F405xx -DSTM32_THREAD_SAFE_STRATEGY=4 -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../Core/ThreadSafe -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F405xx -DSTM32_THREAD_SAFE_STRATEGY=4 -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../Core/ThreadSafe -I../Core/Src/ThreadSafe -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" clean: clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.o index a714f20..045c9d4 100644 Binary files a/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.o and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.o differ diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.o index 7a262e3..3fc1744 100644 Binary files a/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.o and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.o differ diff --git a/Debug/can_logger.elf b/Debug/can_logger.elf index 46d9fde..1dbe28f 100755 Binary files a/Debug/can_logger.elf and b/Debug/can_logger.elf differ diff --git a/Debug/can_logger.list b/Debug/can_logger.list index 90e5163..4daf71f 100644 --- a/Debug/can_logger.list +++ b/Debug/can_logger.list @@ -5,49 +5,49 @@ Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 00000188 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA - 1 .text 00005a4c 08000190 08000190 00001190 2**4 + 1 .text 00009f1c 08000190 08000190 00001190 2**4 CONTENTS, ALLOC, LOAD, READONLY, CODE - 2 .rodata 00000180 08005bdc 08005bdc 00006bdc 2**2 + 2 .rodata 00000214 0800a0ac 0800a0ac 0000b0ac 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 3 .ARM.extab 00000000 08005d5c 08005d5c 00007060 2**0 + 3 .ARM.extab 00000000 0800a2c0 0800a2c0 0000c078 2**0 CONTENTS, READONLY - 4 .ARM 00000008 08005d5c 08005d5c 00006d5c 2**2 + 4 .ARM 00000008 0800a2c0 0800a2c0 0000b2c0 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 5 .preinit_array 00000000 08005d64 08005d64 00007060 2**0 + 5 .preinit_array 00000000 0800a2c8 0800a2c8 0000c078 2**0 CONTENTS, ALLOC, LOAD, DATA - 6 .init_array 00000004 08005d64 08005d64 00006d64 2**2 + 6 .init_array 00000004 0800a2c8 0800a2c8 0000b2c8 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 7 .fini_array 00000004 08005d68 08005d68 00006d68 2**2 + 7 .fini_array 00000004 0800a2cc 0800a2cc 0000b2cc 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 8 .data 00000060 20000000 08005d6c 00007000 2**2 + 8 .data 00000078 20000000 0800a2d0 0000c000 2**2 CONTENTS, ALLOC, LOAD, DATA - 9 .ccmram 00000000 10000000 10000000 00007060 2**0 + 9 .ccmram 00000000 10000000 10000000 0000c078 2**0 CONTENTS - 10 .bss 00004c68 20000060 20000060 00007060 2**2 + 10 .bss 00004dd8 20000078 20000078 0000c078 2**2 ALLOC - 11 ._user_heap_stack 00000600 20004cc8 20004cc8 00007060 2**0 + 11 ._user_heap_stack 00000600 20004e50 20004e50 0000c078 2**0 ALLOC - 12 .ARM.attributes 00000030 00000000 00000000 00007060 2**0 + 12 .ARM.attributes 00000030 00000000 00000000 0000c078 2**0 CONTENTS, READONLY - 13 .debug_info 00016399 00000000 00000000 00007090 2**0 + 13 .debug_info 0001baa1 00000000 00000000 0000c0a8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 14 .debug_abbrev 000033aa 00000000 00000000 0001d429 2**0 + 14 .debug_abbrev 00003dfb 00000000 00000000 00027b49 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 15 .debug_aranges 00001398 00000000 00000000 000207d8 2**3 + 15 .debug_aranges 00001780 00000000 00000000 0002b948 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS - 16 .debug_rnglists 00000f1d 00000000 00000000 00021b70 2**0 + 16 .debug_rnglists 00001226 00000000 00000000 0002d0c8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 17 .debug_macro 00003316 00000000 00000000 00022a8d 2**0 + 17 .debug_macro 00022ab1 00000000 00000000 0002e2ee 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 18 .debug_line 000183ed 00000000 00000000 00025da3 2**0 + 18 .debug_line 0001dba5 00000000 00000000 00050d9f 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 19 .debug_str 000cc536 00000000 00000000 0003e190 2**0 + 19 .debug_str 000d1f03 00000000 00000000 0006e944 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 20 .comment 00000043 00000000 00000000 0010a6c6 2**0 + 20 .comment 00000043 00000000 00000000 00140847 2**0 CONTENTS, READONLY - 21 .debug_frame 0000519c 00000000 00000000 0010a70c 2**2 + 21 .debug_frame 000061e8 00000000 00000000 0014088c 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS - 22 .debug_line_str 000000ba 00000000 00000000 0010f8a8 2**0 + 22 .debug_line_str 00000055 00000000 00000000 00146a74 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: @@ -64,9 +64,9 @@ Disassembly of section .text: 80001a2: 2301 movs r3, #1 80001a4: 7023 strb r3, [r4, #0] 80001a6: bd10 pop {r4, pc} - 80001a8: 20000060 .word 0x20000060 + 80001a8: 20000078 .word 0x20000078 80001ac: 00000000 .word 0x00000000 - 80001b0: 08005bc4 .word 0x08005bc4 + 80001b0: 0800a094 .word 0x0800a094 080001b4 : 80001b4: b508 push {r3, lr} @@ -77,8 +77,8 @@ Disassembly of section .text: 80001be: f3af 8000 nop.w 80001c2: bd08 pop {r3, pc} 80001c4: 00000000 .word 0x00000000 - 80001c8: 20000064 .word 0x20000064 - 80001cc: 08005bc4 .word 0x08005bc4 + 80001c8: 2000007c .word 0x2000007c + 80001cc: 0800a094 .word 0x0800a094 080001d0 <__aeabi_uldivmod>: 80001d0: b953 cbnz r3, 80001e8 <__aeabi_uldivmod+0x18> @@ -371,15320 +371,27346 @@ Disassembly of section .text: 80004f8: 4770 bx lr 80004fa: bf00 nop -080004fc
: +080004fc : + * @brief Initialize CAN bus logger. + * @param argument: hcan1, hcan2 + * @retval None + */ +void CAN_Logger_Init(CAN_HandleTypeDef *hcan1, CAN_HandleTypeDef *hcan2) +{ + 80004fc: b580 push {r7, lr} + 80004fe: b08c sub sp, #48 @ 0x30 + 8000500: af00 add r7, sp, #0 + 8000502: 6078 str r0, [r7, #4] + 8000504: 6039 str r1, [r7, #0] + CAN_FilterTypeDef filter = {0}; + 8000506: f107 0308 add.w r3, r7, #8 + 800050a: 2228 movs r2, #40 @ 0x28 + 800050c: 2100 movs r1, #0 + 800050e: 4618 mov r0, r3 + 8000510: f009 fcde bl 8009ed0 + filter.FilterMode = CAN_FILTERMODE_IDMASK; + 8000514: 2300 movs r3, #0 + 8000516: 623b str r3, [r7, #32] + filter.FilterScale = CAN_FILTERSCALE_32BIT; + 8000518: 2301 movs r3, #1 + 800051a: 627b str r3, [r7, #36] @ 0x24 + filter.FilterIdHigh = 0x0000; + 800051c: 2300 movs r3, #0 + 800051e: 60bb str r3, [r7, #8] + filter.FilterMaskIdHigh = 0x0000; + 8000520: 2300 movs r3, #0 + 8000522: 613b str r3, [r7, #16] + filter.FilterIdLow = 0x0000; + 8000524: 2300 movs r3, #0 + 8000526: 60fb str r3, [r7, #12] + filter.FilterMaskIdLow = 0x0000; + 8000528: 2300 movs r3, #0 + 800052a: 617b str r3, [r7, #20] + filter.FilterFIFOAssignment = CAN_FILTER_FIFO0; + 800052c: 2300 movs r3, #0 + 800052e: 61bb str r3, [r7, #24] + filter.FilterActivation = ENABLE; + 8000530: 2301 movs r3, #1 + 8000532: 62bb str r3, [r7, #40] @ 0x28 + filter.SlaveStartFilterBank = 14; + 8000534: 230e movs r3, #14 + 8000536: 62fb str r3, [r7, #44] @ 0x2c + + filter.FilterBank = 0; + 8000538: 2300 movs r3, #0 + 800053a: 61fb str r3, [r7, #28] + if (HAL_CAN_ConfigFilter(hcan1, &filter) != HAL_OK) Error_Handler(); + 800053c: f107 0308 add.w r3, r7, #8 + 8000540: 4619 mov r1, r3 + 8000542: 6878 ldr r0, [r7, #4] + 8000544: f001 fa12 bl 800196c + 8000548: 4603 mov r3, r0 + 800054a: 2b00 cmp r3, #0 + 800054c: d001 beq.n 8000552 + 800054e: f000 fbb1 bl 8000cb4 + filter.FilterBank = 14; + 8000552: 230e movs r3, #14 + 8000554: 61fb str r3, [r7, #28] + if (HAL_CAN_ConfigFilter(hcan2, &filter) != HAL_OK) Error_Handler(); + 8000556: f107 0308 add.w r3, r7, #8 + 800055a: 4619 mov r1, r3 + 800055c: 6838 ldr r0, [r7, #0] + 800055e: f001 fa05 bl 800196c + 8000562: 4603 mov r3, r0 + 8000564: 2b00 cmp r3, #0 + 8000566: d001 beq.n 800056c + 8000568: f000 fba4 bl 8000cb4 + + if (HAL_CAN_Start(hcan1) != HAL_OK) Error_Handler(); + 800056c: 6878 ldr r0, [r7, #4] + 800056e: f001 fb49 bl 8001c04 + 8000572: 4603 mov r3, r0 + 8000574: 2b00 cmp r3, #0 + 8000576: d001 beq.n 800057c + 8000578: f000 fb9c bl 8000cb4 + if (HAL_CAN_Start(hcan2) != HAL_OK) Error_Handler(); + 800057c: 6838 ldr r0, [r7, #0] + 800057e: f001 fb41 bl 8001c04 + 8000582: 4603 mov r3, r0 + 8000584: 2b00 cmp r3, #0 + 8000586: d001 beq.n 800058c + 8000588: f000 fb94 bl 8000cb4 + + if (HAL_CAN_ActivateNotification(hcan1, CAN_IT_RX_FIFO0_MSG_PENDING) != HAL_OK) Error_Handler(); + 800058c: 2102 movs r1, #2 + 800058e: 6878 ldr r0, [r7, #4] + 8000590: f001 fcaa bl 8001ee8 + 8000594: 4603 mov r3, r0 + 8000596: 2b00 cmp r3, #0 + 8000598: d001 beq.n 800059e + 800059a: f000 fb8b bl 8000cb4 + if (HAL_CAN_ActivateNotification(hcan2, CAN_IT_RX_FIFO0_MSG_PENDING) != HAL_OK) Error_Handler(); + 800059e: 2102 movs r1, #2 + 80005a0: 6838 ldr r0, [r7, #0] + 80005a2: f001 fca1 bl 8001ee8 + 80005a6: 4603 mov r3, r0 + 80005a8: 2b00 cmp r3, #0 + 80005aa: d001 beq.n 80005b0 + 80005ac: f000 fb82 bl 8000cb4 +} + 80005b0: bf00 nop + 80005b2: 3730 adds r7, #48 @ 0x30 + 80005b4: 46bd mov sp, r7 + 80005b6: bd80 pop {r7, pc} + +080005b8 : + * @brief ISR for CAN message pending in FIFO0 + * @param argument: Can handle hcan (hcan1 or hcan2) + * @retval None + */ +void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + 80005b8: b580 push {r7, lr} + 80005ba: b090 sub sp, #64 @ 0x40 + 80005bc: af00 add r7, sp, #0 + 80005be: 6078 str r0, [r7, #4] + /* CODE BEGIN */ + CanMessage_t message; + CAN_RxHeaderTypeDef rxHeader; + uint8_t data[8]; + + if (HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO0, &rxHeader, data) != HAL_OK) Error_Handler(); + 80005c0: f107 0308 add.w r3, r7, #8 + 80005c4: f107 0210 add.w r2, r7, #16 + 80005c8: 2100 movs r1, #0 + 80005ca: 6878 ldr r0, [r7, #4] + 80005cc: f001 fb5e bl 8001c8c + 80005d0: 4603 mov r3, r0 + 80005d2: 2b00 cmp r3, #0 + 80005d4: d001 beq.n 80005da + 80005d6: f000 fb6d bl 8000cb4 + + message.id = rxHeader.ExtId; + 80005da: 697b ldr r3, [r7, #20] + 80005dc: 62fb str r3, [r7, #44] @ 0x2c + message.dlc = rxHeader.DLC; + 80005de: 6a3b ldr r3, [r7, #32] + 80005e0: b2db uxtb r3, r3 + 80005e2: f887 3038 strb.w r3, [r7, #56] @ 0x38 + message.isExtended = (rxHeader.IDE == CAN_ID_EXT); + 80005e6: 69bb ldr r3, [r7, #24] + 80005e8: 2b04 cmp r3, #4 + 80005ea: bf0c ite eq + 80005ec: 2301 moveq r3, #1 + 80005ee: 2300 movne r3, #0 + 80005f0: b2db uxtb r3, r3 + 80005f2: f887 3039 strb.w r3, [r7, #57] @ 0x39 + memcpy(message.payload, data, rxHeader.DLC); + 80005f6: 6a3a ldr r2, [r7, #32] + 80005f8: f107 0108 add.w r1, r7, #8 + 80005fc: f107 032c add.w r3, r7, #44 @ 0x2c + 8000600: 3304 adds r3, #4 + 8000602: 4618 mov r0, r3 + 8000604: f009 fcee bl 8009fe4 + + osMessageQueueId_t queue = (hcan->Instance == CAN1) ? xCAN1RxQueue : xCAN2RxQueue; + 8000608: 687b ldr r3, [r7, #4] + 800060a: 681b ldr r3, [r3, #0] + 800060c: 4a09 ldr r2, [pc, #36] @ (8000634 ) + 800060e: 4293 cmp r3, r2 + 8000610: d102 bne.n 8000618 + 8000612: 4b09 ldr r3, [pc, #36] @ (8000638 ) + 8000614: 681b ldr r3, [r3, #0] + 8000616: e001 b.n 800061c + 8000618: 4b08 ldr r3, [pc, #32] @ (800063c ) + 800061a: 681b ldr r3, [r3, #0] + 800061c: 63fb str r3, [r7, #60] @ 0x3c + if (osMessageQueuePut(queue, &message, 0U, 0U) != osOK) + 800061e: f107 012c add.w r1, r7, #44 @ 0x2c + 8000622: 2300 movs r3, #0 + 8000624: 2200 movs r2, #0 + 8000626: 6bf8 ldr r0, [r7, #60] @ 0x3c + 8000628: f006 fa14 bl 8006a54 + // TODO: better handling: flash error_led on osTimeout, call Error_Handler() when other errors + + // send errors like queue full via UART + } + /* CODE END */ +} + 800062c: bf00 nop + 800062e: 3740 adds r7, #64 @ 0x40 + 8000630: 46bd mov sp, r7 + 8000632: bd80 pop {r7, pc} + 8000634: 40006400 .word 0x40006400 + 8000638: 200002c8 .word 0x200002c8 + 800063c: 200002cc .word 0x200002cc + +08000640 : + * @brief Log incoming CAN bus traffic in FIFO buffer + * @param argument: Not used + * @retval None + */ +void vCANLoggerListen(void *argument) +{ + 8000640: b580 push {r7, lr} + 8000642: b088 sub sp, #32 + 8000644: af00 add r7, sp, #0 + 8000646: 6078 str r0, [r7, #4] + /* CODE BEGIN */ + CAN_HandleTypeDef *hcan = (CAN_HandleTypeDef*)argument; + 8000648: 687b ldr r3, [r7, #4] + 800064a: 61fb str r3, [r7, #28] + osMessageQueueId_t queue; + CanMessage_t message; + + queue = (hcan->Instance == CAN1) ? xCAN1RxQueue : xCAN2RxQueue; + 800064c: 69fb ldr r3, [r7, #28] + 800064e: 681b ldr r3, [r3, #0] + 8000650: 4a10 ldr r2, [pc, #64] @ (8000694 ) + 8000652: 4293 cmp r3, r2 + 8000654: d102 bne.n 800065c + 8000656: 4b10 ldr r3, [pc, #64] @ (8000698 ) + 8000658: 681b ldr r3, [r3, #0] + 800065a: e001 b.n 8000660 + 800065c: 4b0f ldr r3, [pc, #60] @ (800069c ) + 800065e: 681b ldr r3, [r3, #0] + 8000660: 61bb str r3, [r7, #24] + + for (;;) + { + if (osMessageQueueGet(queue, &message, NULL, osWaitForever) == osOK) + 8000662: f107 0108 add.w r1, r7, #8 + 8000666: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800066a: 2200 movs r2, #0 + 800066c: 69b8 ldr r0, [r7, #24] + 800066e: f006 fa51 bl 8006b14 + 8000672: 4603 mov r3, r0 + 8000674: 2b00 cmp r3, #0 + 8000676: d1f4 bne.n 8000662 + { + osSemaphoreRelease( (hcan->Instance == CAN1) ? xSemaphoreCAN1 : xSemaphoreCAN2 ); + 8000678: 69fb ldr r3, [r7, #28] + 800067a: 681b ldr r3, [r3, #0] + 800067c: 4a05 ldr r2, [pc, #20] @ (8000694 ) + 800067e: 4293 cmp r3, r2 + 8000680: d102 bne.n 8000688 + 8000682: 4b07 ldr r3, [pc, #28] @ (80006a0 ) + 8000684: 681b ldr r3, [r3, #0] + 8000686: e001 b.n 800068c + 8000688: 4b06 ldr r3, [pc, #24] @ (80006a4 ) + 800068a: 681b ldr r3, [r3, #0] + 800068c: 4618 mov r0, r3 + 800068e: f006 f929 bl 80068e4 + if (osMessageQueueGet(queue, &message, NULL, osWaitForever) == osOK) + 8000692: e7e6 b.n 8000662 + 8000694: 40006400 .word 0x40006400 + 8000698: 200002c8 .word 0x200002c8 + 800069c: 200002cc .word 0x200002cc + 80006a0: 200002b8 .word 0x200002b8 + 80006a4: 200002bc .word 0x200002bc + +080006a8 : + * @brief Blink a LED in heartbeat mode when CAN traffic is detected + * @param argument: LED GPIO (port and pin) + * @retval None + */ +void vLEDHeartbeat(void *argument) +{ + 80006a8: b580 push {r7, lr} + 80006aa: b084 sub sp, #16 + 80006ac: af00 add r7, sp, #0 + 80006ae: 6078 str r0, [r7, #4] + /* CODE BEGIN */ + LEDContext *context = (LEDContext*)argument; + 80006b0: 687b ldr r3, [r7, #4] + 80006b2: 60fb str r3, [r7, #12] + + if (osSemaphoreAcquire(context->semaphore, 0U) == osOK) + 80006b4: 68fb ldr r3, [r7, #12] + 80006b6: 685b ldr r3, [r3, #4] + 80006b8: 2100 movs r1, #0 + 80006ba: 4618 mov r0, r3 + 80006bc: f006 f8c0 bl 8006840 + 80006c0: 4603 mov r3, r0 + 80006c2: 2b00 cmp r3, #0 + 80006c4: d110 bne.n 80006e8 + { + HAL_GPIO_WritePin(context->led->port, context->led->pin, GPIO_PIN_SET); + 80006c6: 68fb ldr r3, [r7, #12] + 80006c8: 681b ldr r3, [r3, #0] + 80006ca: 6818 ldr r0, [r3, #0] + 80006cc: 68fb ldr r3, [r7, #12] + 80006ce: 681b ldr r3, [r3, #0] + 80006d0: 889b ldrh r3, [r3, #4] + 80006d2: 2201 movs r2, #1 + 80006d4: 4619 mov r1, r3 + 80006d6: f002 fd43 bl 8003160 + osTimerStart(context->timer, 25U); + 80006da: 68fb ldr r3, [r7, #12] + 80006dc: 689b ldr r3, [r3, #8] + 80006de: 2119 movs r1, #25 + 80006e0: 4618 mov r0, r3 + 80006e2: f005 fff5 bl 80066d0 + else + { + HAL_GPIO_WritePin(context->led->port, context->led->pin, GPIO_PIN_RESET); + } + /* CODE END */ +} + 80006e6: e009 b.n 80006fc + HAL_GPIO_WritePin(context->led->port, context->led->pin, GPIO_PIN_RESET); + 80006e8: 68fb ldr r3, [r7, #12] + 80006ea: 681b ldr r3, [r3, #0] + 80006ec: 6818 ldr r0, [r3, #0] + 80006ee: 68fb ldr r3, [r7, #12] + 80006f0: 681b ldr r3, [r3, #0] + 80006f2: 889b ldrh r3, [r3, #4] + 80006f4: 2200 movs r2, #0 + 80006f6: 4619 mov r1, r3 + 80006f8: f002 fd32 bl 8003160 +} + 80006fc: bf00 nop + 80006fe: 3710 adds r7, #16 + 8000700: 46bd mov sp, r7 + 8000702: bd80 pop {r7, pc} + +08000704
: /** * @brief The application entry point. * @retval int */ int main(void) { - 80004fc: b580 push {r7, lr} - 80004fe: af00 add r7, sp, #0 + 8000704: b580 push {r7, lr} + 8000706: b094 sub sp, #80 @ 0x50 + 8000708: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); - 8000500: f000 fbe0 bl 8000cc4 + 800070a: f000 fe5f bl 80013cc /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); - 8000504: f000 f81a bl 800053c + 800070e: f000 f8e7 bl 80008e0 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); - 8000508: f000 f8de bl 80006c8 + 8000712: f000 fa17 bl 8000b44 + MX_DMA_Init(); + 8000716: f000 f9ed bl 8000af4 MX_CAN1_Init(); - 800050c: f000 f874 bl 80005f8 + 800071a: f000 f94b bl 80009b4 MX_CAN2_Init(); - 8000510: f000 f8a6 bl 8000660 - /* USER CODE BEGIN 2 */ + 800071e: f000 f981 bl 8000a24 + MX_SDIO_SD_Init(); + 8000722: f000 f9b7 bl 8000a94 + /* USER CODE BEGIN 2 */ + CAN_Logger_Init(&hcan1, &hcan2); + 8000726: 495e ldr r1, [pc, #376] @ (80008a0 ) + 8000728: 485e ldr r0, [pc, #376] @ (80008a4 ) + 800072a: f7ff fee7 bl 80004fc /* USER CODE END 2 */ /* Init scheduler */ osKernelInitialize(); - 8000514: f002 fcbc bl 8002e90 - /* add queues, ... */ + 800072e: f005 fe61 bl 80063f4 + + /* USER CODE BEGIN RTOS_TASKS */ + osThreadId_t xCAN1rx; + const osThreadAttr_t CAN1rxAttributes = { + 8000732: f107 0324 add.w r3, r7, #36 @ 0x24 + 8000736: 2224 movs r2, #36 @ 0x24 + 8000738: 2100 movs r1, #0 + 800073a: 4618 mov r0, r3 + 800073c: f009 fbc8 bl 8009ed0 + 8000740: 4b59 ldr r3, [pc, #356] @ (80008a8 ) + 8000742: 627b str r3, [r7, #36] @ 0x24 + 8000744: f44f 7300 mov.w r3, #512 @ 0x200 + 8000748: 63bb str r3, [r7, #56] @ 0x38 + 800074a: 2331 movs r3, #49 @ 0x31 + 800074c: 63fb str r3, [r7, #60] @ 0x3c + .name = "CAN1rx", + .stack_size = 128 * 4, + .priority = (osPriority_t) osPriorityRealtime1, + }; + osThreadId_t xCAN2rx; + const osThreadAttr_t CAN2rxAttributes = { + 800074e: 463b mov r3, r7 + 8000750: 2224 movs r2, #36 @ 0x24 + 8000752: 2100 movs r1, #0 + 8000754: 4618 mov r0, r3 + 8000756: f009 fbbb bl 8009ed0 + 800075a: 4b54 ldr r3, [pc, #336] @ (80008ac ) + 800075c: 603b str r3, [r7, #0] + 800075e: f44f 7300 mov.w r3, #512 @ 0x200 + 8000762: 617b str r3, [r7, #20] + 8000764: 2330 movs r3, #48 @ 0x30 + 8000766: 61bb str r3, [r7, #24] + /* USER CODE BEGIN RTOS_MUTEX */ + /* add mutexes, ... */ + /* USER CODE END RTOS_MUTEX */ + + /* USER CODE BEGIN RTOS_SEMAPHORES */ + xSemaphoreCAN1 = osSemaphoreNew(10, 0, NULL); + 8000768: 2200 movs r2, #0 + 800076a: 2100 movs r1, #0 + 800076c: 200a movs r0, #10 + 800076e: f005 ffdd bl 800672c + 8000772: 4603 mov r3, r0 + 8000774: 4a4e ldr r2, [pc, #312] @ (80008b0 ) + 8000776: 6013 str r3, [r2, #0] + xSemaphoreCAN2 = osSemaphoreNew(10, 0, NULL); + 8000778: 2200 movs r2, #0 + 800077a: 2100 movs r1, #0 + 800077c: 200a movs r0, #10 + 800077e: f005 ffd5 bl 800672c + 8000782: 4603 mov r3, r0 + 8000784: 4a4b ldr r2, [pc, #300] @ (80008b4 ) + 8000786: 6013 str r3, [r2, #0] + + if (xSemaphoreCAN1 == NULL || xSemaphoreCAN2 == NULL) Error_Handler(); + 8000788: 4b49 ldr r3, [pc, #292] @ (80008b0 ) + 800078a: 681b ldr r3, [r3, #0] + 800078c: 2b00 cmp r3, #0 + 800078e: d003 beq.n 8000798 + 8000790: 4b48 ldr r3, [pc, #288] @ (80008b4 ) + 8000792: 681b ldr r3, [r3, #0] + 8000794: 2b00 cmp r3, #0 + 8000796: d101 bne.n 800079c + 8000798: f000 fa8c bl 8000cb4 + + ledContextCAN1.led = &led_can1; + 800079c: 4b46 ldr r3, [pc, #280] @ (80008b8 ) + 800079e: 4a47 ldr r2, [pc, #284] @ (80008bc ) + 80007a0: 601a str r2, [r3, #0] + ledContextCAN1.semaphore = xSemaphoreCAN1; + 80007a2: 4b43 ldr r3, [pc, #268] @ (80008b0 ) + 80007a4: 681b ldr r3, [r3, #0] + 80007a6: 4a44 ldr r2, [pc, #272] @ (80008b8 ) + 80007a8: 6053 str r3, [r2, #4] + ledContextCAN2.led = &led_can2; + 80007aa: 4b45 ldr r3, [pc, #276] @ (80008c0 ) + 80007ac: 4a45 ldr r2, [pc, #276] @ (80008c4 ) + 80007ae: 601a str r2, [r3, #0] + ledContextCAN2.semaphore = xSemaphoreCAN2; + 80007b0: 4b40 ldr r3, [pc, #256] @ (80008b4 ) + 80007b2: 681b ldr r3, [r3, #0] + 80007b4: 4a42 ldr r2, [pc, #264] @ (80008c0 ) + 80007b6: 6053 str r3, [r2, #4] + /* USER CODE END RTOS_SEMAPHORES */ + + /* USER CODE BEGIN RTOS_TIMERS */ + xHeartbeatTimerCAN1 = osTimerNew(vLEDHeartbeat, osTimerOnce, &ledContextCAN1, NULL); + 80007b8: 2300 movs r3, #0 + 80007ba: 4a3f ldr r2, [pc, #252] @ (80008b8 ) + 80007bc: 2100 movs r1, #0 + 80007be: 4842 ldr r0, [pc, #264] @ (80008c8 ) + 80007c0: f005 ff0a bl 80065d8 + 80007c4: 4603 mov r3, r0 + 80007c6: 4a41 ldr r2, [pc, #260] @ (80008cc ) + 80007c8: 6013 str r3, [r2, #0] + xHeartbeatTimerCAN2 = osTimerNew(vLEDHeartbeat, osTimerOnce, &ledContextCAN2, NULL); + 80007ca: 2300 movs r3, #0 + 80007cc: 4a3c ldr r2, [pc, #240] @ (80008c0 ) + 80007ce: 2100 movs r1, #0 + 80007d0: 483d ldr r0, [pc, #244] @ (80008c8 ) + 80007d2: f005 ff01 bl 80065d8 + 80007d6: 4603 mov r3, r0 + 80007d8: 4a3d ldr r2, [pc, #244] @ (80008d0 ) + 80007da: 6013 str r3, [r2, #0] + + osTimerStart(xHeartbeatTimerCAN1, 25U); + 80007dc: 4b3b ldr r3, [pc, #236] @ (80008cc ) + 80007de: 681b ldr r3, [r3, #0] + 80007e0: 2119 movs r1, #25 + 80007e2: 4618 mov r0, r3 + 80007e4: f005 ff74 bl 80066d0 + osTimerStart(xHeartbeatTimerCAN2, 25U); + 80007e8: 4b39 ldr r3, [pc, #228] @ (80008d0 ) + 80007ea: 681b ldr r3, [r3, #0] + 80007ec: 2119 movs r1, #25 + 80007ee: 4618 mov r0, r3 + 80007f0: f005 ff6e bl 80066d0 + + if (xHeartbeatTimerCAN1 == NULL || xHeartbeatTimerCAN2 == NULL) Error_Handler(); + 80007f4: 4b35 ldr r3, [pc, #212] @ (80008cc ) + 80007f6: 681b ldr r3, [r3, #0] + 80007f8: 2b00 cmp r3, #0 + 80007fa: d003 beq.n 8000804 + 80007fc: 4b34 ldr r3, [pc, #208] @ (80008d0 ) + 80007fe: 681b ldr r3, [r3, #0] + 8000800: 2b00 cmp r3, #0 + 8000802: d101 bne.n 8000808 + 8000804: f000 fa56 bl 8000cb4 + + ledContextCAN1.timer = xHeartbeatTimerCAN1; + 8000808: 4b30 ldr r3, [pc, #192] @ (80008cc ) + 800080a: 681b ldr r3, [r3, #0] + 800080c: 4a2a ldr r2, [pc, #168] @ (80008b8 ) + 800080e: 6093 str r3, [r2, #8] + ledContextCAN2.timer = xHeartbeatTimerCAN2; + 8000810: 4b2f ldr r3, [pc, #188] @ (80008d0 ) + 8000812: 681b ldr r3, [r3, #0] + 8000814: 4a2a ldr r2, [pc, #168] @ (80008c0 ) + 8000816: 6093 str r3, [r2, #8] + /* USER CODE END RTOS_TIMERS */ + + /* USER CODE BEGIN RTOS_QUEUES */ + xCAN1RxQueue = osMessageQueueNew(32, sizeof(CanMessage_t), NULL); + 8000818: 2200 movs r2, #0 + 800081a: 2110 movs r1, #16 + 800081c: 2020 movs r0, #32 + 800081e: f006 f8a5 bl 800696c + 8000822: 4603 mov r3, r0 + 8000824: 4a2b ldr r2, [pc, #172] @ (80008d4 ) + 8000826: 6013 str r3, [r2, #0] + xCAN2RxQueue = osMessageQueueNew(32, sizeof(CanMessage_t), NULL); + 8000828: 2200 movs r2, #0 + 800082a: 2110 movs r1, #16 + 800082c: 2020 movs r0, #32 + 800082e: f006 f89d bl 800696c + 8000832: 4603 mov r3, r0 + 8000834: 4a28 ldr r2, [pc, #160] @ (80008d8 ) + 8000836: 6013 str r3, [r2, #0] + + if (xCAN1RxQueue == NULL || xCAN2RxQueue == NULL) Error_Handler(); + 8000838: 4b26 ldr r3, [pc, #152] @ (80008d4 ) + 800083a: 681b ldr r3, [r3, #0] + 800083c: 2b00 cmp r3, #0 + 800083e: d003 beq.n 8000848 + 8000840: 4b25 ldr r3, [pc, #148] @ (80008d8 ) + 8000842: 681b ldr r3, [r3, #0] + 8000844: 2b00 cmp r3, #0 + 8000846: d101 bne.n 800084c + 8000848: f000 fa34 bl 8000cb4 /* USER CODE END RTOS_QUEUES */ - /* Create the thread(s) */ - /* creation of defaultTask */ - defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes); - 8000518: 4a05 ldr r2, [pc, #20] @ (8000530 ) - 800051a: 2100 movs r1, #0 - 800051c: 4805 ldr r0, [pc, #20] @ (8000534 ) - 800051e: f002 fd01 bl 8002f24 - 8000522: 4603 mov r3, r0 - 8000524: 4a04 ldr r2, [pc, #16] @ (8000538 ) - 8000526: 6013 str r3, [r2, #0] + /* USER CODE BEGIN RTOS_THREADS */ + xCAN1rx = osThreadNew(vCANLoggerListen, &hcan1, &CAN1rxAttributes); + 800084c: f107 0324 add.w r3, r7, #36 @ 0x24 + 8000850: 461a mov r2, r3 + 8000852: 4914 ldr r1, [pc, #80] @ (80008a4 ) + 8000854: 4821 ldr r0, [pc, #132] @ (80008dc ) + 8000856: f005 fe17 bl 8006488 + 800085a: 64f8 str r0, [r7, #76] @ 0x4c + xCAN2rx = osThreadNew(vCANLoggerListen, &hcan2, &CAN2rxAttributes); + 800085c: 463b mov r3, r7 + 800085e: 461a mov r2, r3 + 8000860: 490f ldr r1, [pc, #60] @ (80008a0 ) + 8000862: 481e ldr r0, [pc, #120] @ (80008dc ) + 8000864: f005 fe10 bl 8006488 + 8000868: 64b8 str r0, [r7, #72] @ 0x48 /* USER CODE BEGIN RTOS_EVENTS */ /* add events, ... */ /* USER CODE END RTOS_EVENTS */ + /* USER CODE BEGIN 3 */ + ledContextCAN1.led = &led_can1; + 800086a: 4b13 ldr r3, [pc, #76] @ (80008b8 ) + 800086c: 4a13 ldr r2, [pc, #76] @ (80008bc ) + 800086e: 601a str r2, [r3, #0] + ledContextCAN1.semaphore = xSemaphoreCAN1; + 8000870: 4b0f ldr r3, [pc, #60] @ (80008b0 ) + 8000872: 681b ldr r3, [r3, #0] + 8000874: 4a10 ldr r2, [pc, #64] @ (80008b8 ) + 8000876: 6053 str r3, [r2, #4] + ledContextCAN1.timer = xHeartbeatTimerCAN1; + 8000878: 4b14 ldr r3, [pc, #80] @ (80008cc ) + 800087a: 681b ldr r3, [r3, #0] + 800087c: 4a0e ldr r2, [pc, #56] @ (80008b8 ) + 800087e: 6093 str r3, [r2, #8] + + ledContextCAN2.led = &led_can2; + 8000880: 4b0f ldr r3, [pc, #60] @ (80008c0 ) + 8000882: 4a10 ldr r2, [pc, #64] @ (80008c4 ) + 8000884: 601a str r2, [r3, #0] + ledContextCAN2.semaphore = xSemaphoreCAN2; + 8000886: 4b0b ldr r3, [pc, #44] @ (80008b4 ) + 8000888: 681b ldr r3, [r3, #0] + 800088a: 4a0d ldr r2, [pc, #52] @ (80008c0 ) + 800088c: 6053 str r3, [r2, #4] + ledContextCAN2.timer = xHeartbeatTimerCAN2; + 800088e: 4b10 ldr r3, [pc, #64] @ (80008d0 ) + 8000890: 681b ldr r3, [r3, #0] + 8000892: 4a0b ldr r2, [pc, #44] @ (80008c0 ) + 8000894: 6093 str r3, [r2, #8] + /* USER CODE END 3 */ + /* Start scheduler */ osKernelStart(); - 8000528: f002 fcd6 bl 8002ed8 + 8000896: f005 fdd1 bl 800643c /* We should never get here as control is now taken by the scheduler */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) - 800052c: bf00 nop - 800052e: e7fd b.n 800052c - 8000530: 08005d20 .word 0x08005d20 - 8000534: 08000809 .word 0x08000809 - 8000538: 20000144 .word 0x20000144 + 800089a: bf00 nop + 800089c: e7fd b.n 800089a + 800089e: bf00 nop + 80008a0: 200000f8 .word 0x200000f8 + 80008a4: 20000094 .word 0x20000094 + 80008a8: 0800a0ac .word 0x0800a0ac + 80008ac: 0800a0b4 .word 0x0800a0b4 + 80008b0: 200002b8 .word 0x200002b8 + 80008b4: 200002bc .word 0x200002bc + 80008b8: 200002a0 .word 0x200002a0 + 80008bc: 20000000 .word 0x20000000 + 80008c0: 200002ac .word 0x200002ac + 80008c4: 20000008 .word 0x20000008 + 80008c8: 080006a9 .word 0x080006a9 + 80008cc: 200002c0 .word 0x200002c0 + 80008d0: 200002c4 .word 0x200002c4 + 80008d4: 200002c8 .word 0x200002c8 + 80008d8: 200002cc .word 0x200002cc + 80008dc: 08000641 .word 0x08000641 -0800053c : +080008e0 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { - 800053c: b580 push {r7, lr} - 800053e: b094 sub sp, #80 @ 0x50 - 8000540: af00 add r7, sp, #0 + 80008e0: b580 push {r7, lr} + 80008e2: b094 sub sp, #80 @ 0x50 + 80008e4: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - 8000542: f107 0320 add.w r3, r7, #32 - 8000546: 2230 movs r2, #48 @ 0x30 - 8000548: 2100 movs r1, #0 - 800054a: 4618 mov r0, r3 - 800054c: f005 fa58 bl 8005a00 + 80008e6: f107 0320 add.w r3, r7, #32 + 80008ea: 2230 movs r2, #48 @ 0x30 + 80008ec: 2100 movs r1, #0 + 80008ee: 4618 mov r0, r3 + 80008f0: f009 faee bl 8009ed0 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - 8000550: f107 030c add.w r3, r7, #12 - 8000554: 2200 movs r2, #0 - 8000556: 601a str r2, [r3, #0] - 8000558: 605a str r2, [r3, #4] - 800055a: 609a str r2, [r3, #8] - 800055c: 60da str r2, [r3, #12] - 800055e: 611a str r2, [r3, #16] + 80008f4: f107 030c add.w r3, r7, #12 + 80008f8: 2200 movs r2, #0 + 80008fa: 601a str r2, [r3, #0] + 80008fc: 605a str r2, [r3, #4] + 80008fe: 609a str r2, [r3, #8] + 8000900: 60da str r2, [r3, #12] + 8000902: 611a str r2, [r3, #16] /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); - 8000560: 2300 movs r3, #0 - 8000562: 60bb str r3, [r7, #8] - 8000564: 4b22 ldr r3, [pc, #136] @ (80005f0 ) - 8000566: 6c1b ldr r3, [r3, #64] @ 0x40 - 8000568: 4a21 ldr r2, [pc, #132] @ (80005f0 ) - 800056a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 - 800056e: 6413 str r3, [r2, #64] @ 0x40 - 8000570: 4b1f ldr r3, [pc, #124] @ (80005f0 ) - 8000572: 6c1b ldr r3, [r3, #64] @ 0x40 - 8000574: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 8000578: 60bb str r3, [r7, #8] - 800057a: 68bb ldr r3, [r7, #8] + 8000904: 2300 movs r3, #0 + 8000906: 60bb str r3, [r7, #8] + 8000908: 4b28 ldr r3, [pc, #160] @ (80009ac ) + 800090a: 6c1b ldr r3, [r3, #64] @ 0x40 + 800090c: 4a27 ldr r2, [pc, #156] @ (80009ac ) + 800090e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8000912: 6413 str r3, [r2, #64] @ 0x40 + 8000914: 4b25 ldr r3, [pc, #148] @ (80009ac ) + 8000916: 6c1b ldr r3, [r3, #64] @ 0x40 + 8000918: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 800091c: 60bb str r3, [r7, #8] + 800091e: 68bb ldr r3, [r7, #8] __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - 800057c: 2300 movs r3, #0 - 800057e: 607b str r3, [r7, #4] - 8000580: 4b1c ldr r3, [pc, #112] @ (80005f4 ) - 8000582: 681b ldr r3, [r3, #0] - 8000584: 4a1b ldr r2, [pc, #108] @ (80005f4 ) - 8000586: f443 4380 orr.w r3, r3, #16384 @ 0x4000 - 800058a: 6013 str r3, [r2, #0] - 800058c: 4b19 ldr r3, [pc, #100] @ (80005f4 ) - 800058e: 681b ldr r3, [r3, #0] - 8000590: f403 4380 and.w r3, r3, #16384 @ 0x4000 - 8000594: 607b str r3, [r7, #4] - 8000596: 687b ldr r3, [r7, #4] + 8000920: 2300 movs r3, #0 + 8000922: 607b str r3, [r7, #4] + 8000924: 4b22 ldr r3, [pc, #136] @ (80009b0 ) + 8000926: 681b ldr r3, [r3, #0] + 8000928: 4a21 ldr r2, [pc, #132] @ (80009b0 ) + 800092a: f443 4380 orr.w r3, r3, #16384 @ 0x4000 + 800092e: 6013 str r3, [r2, #0] + 8000930: 4b1f ldr r3, [pc, #124] @ (80009b0 ) + 8000932: 681b ldr r3, [r3, #0] + 8000934: f403 4380 and.w r3, r3, #16384 @ 0x4000 + 8000938: 607b str r3, [r7, #4] + 800093a: 687b ldr r3, [r7, #4] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; - 8000598: 2302 movs r3, #2 - 800059a: 623b str r3, [r7, #32] + 800093c: 2302 movs r3, #2 + 800093e: 623b str r3, [r7, #32] RCC_OscInitStruct.HSIState = RCC_HSI_ON; - 800059c: 2301 movs r3, #1 - 800059e: 62fb str r3, [r7, #44] @ 0x2c + 8000940: 2301 movs r3, #1 + 8000942: 62fb str r3, [r7, #44] @ 0x2c RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - 80005a0: 2310 movs r3, #16 - 80005a2: 633b str r3, [r7, #48] @ 0x30 - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - 80005a4: 2300 movs r3, #0 - 80005a6: 63bb str r3, [r7, #56] @ 0x38 + 8000944: 2310 movs r3, #16 + 8000946: 633b str r3, [r7, #48] @ 0x30 + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + 8000948: 2302 movs r3, #2 + 800094a: 63bb str r3, [r7, #56] @ 0x38 + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + 800094c: 2300 movs r3, #0 + 800094e: 63fb str r3, [r7, #60] @ 0x3c + RCC_OscInitStruct.PLL.PLLM = 16; + 8000950: 2310 movs r3, #16 + 8000952: 643b str r3, [r7, #64] @ 0x40 + RCC_OscInitStruct.PLL.PLLN = 336; + 8000954: f44f 73a8 mov.w r3, #336 @ 0x150 + 8000958: 647b str r3, [r7, #68] @ 0x44 + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + 800095a: 2302 movs r3, #2 + 800095c: 64bb str r3, [r7, #72] @ 0x48 + RCC_OscInitStruct.PLL.PLLQ = 7; + 800095e: 2307 movs r3, #7 + 8000960: 64fb str r3, [r7, #76] @ 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - 80005a8: f107 0320 add.w r3, r7, #32 - 80005ac: 4618 mov r0, r3 - 80005ae: f001 fa9d bl 8001aec - 80005b2: 4603 mov r3, r0 - 80005b4: 2b00 cmp r3, #0 - 80005b6: d001 beq.n 80005bc + 8000962: f107 0320 add.w r3, r7, #32 + 8000966: 4618 mov r0, r3 + 8000968: f002 fc48 bl 80031fc + 800096c: 4603 mov r3, r0 + 800096e: 2b00 cmp r3, #0 + 8000970: d001 beq.n 8000976 { Error_Handler(); - 80005b8: f000 f940 bl 800083c + 8000972: f000 f99f bl 8000cb4 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - 80005bc: 230f movs r3, #15 - 80005be: 60fb str r3, [r7, #12] + 8000976: 230f movs r3, #15 + 8000978: 60fb str r3, [r7, #12] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; - 80005c0: 2300 movs r3, #0 - 80005c2: 613b str r3, [r7, #16] + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + 800097a: 2302 movs r3, #2 + 800097c: 613b str r3, [r7, #16] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - 80005c4: 2300 movs r3, #0 - 80005c6: 617b str r3, [r7, #20] - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - 80005c8: 2300 movs r3, #0 - 80005ca: 61bb str r3, [r7, #24] - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - 80005cc: 2300 movs r3, #0 - 80005ce: 61fb str r3, [r7, #28] + 800097e: 2300 movs r3, #0 + 8000980: 617b str r3, [r7, #20] + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + 8000982: f44f 53a0 mov.w r3, #5120 @ 0x1400 + 8000986: 61bb str r3, [r7, #24] + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV4; + 8000988: f44f 53a0 mov.w r3, #5120 @ 0x1400 + 800098c: 61fb str r3, [r7, #28] - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) - 80005d0: f107 030c add.w r3, r7, #12 - 80005d4: 2100 movs r1, #0 - 80005d6: 4618 mov r0, r3 - 80005d8: f001 fdb4 bl 8002144 - 80005dc: 4603 mov r3, r0 - 80005de: 2b00 cmp r3, #0 - 80005e0: d001 beq.n 80005e6 + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) + 800098e: f107 030c add.w r3, r7, #12 + 8000992: 2105 movs r1, #5 + 8000994: 4618 mov r0, r3 + 8000996: f002 ff5d bl 8003854 + 800099a: 4603 mov r3, r0 + 800099c: 2b00 cmp r3, #0 + 800099e: d001 beq.n 80009a4 { Error_Handler(); - 80005e2: f000 f92b bl 800083c + 80009a0: f000 f988 bl 8000cb4 } } - 80005e6: bf00 nop - 80005e8: 3750 adds r7, #80 @ 0x50 - 80005ea: 46bd mov sp, r7 - 80005ec: bd80 pop {r7, pc} - 80005ee: bf00 nop - 80005f0: 40023800 .word 0x40023800 - 80005f4: 40007000 .word 0x40007000 + 80009a4: bf00 nop + 80009a6: 3750 adds r7, #80 @ 0x50 + 80009a8: 46bd mov sp, r7 + 80009aa: bd80 pop {r7, pc} + 80009ac: 40023800 .word 0x40023800 + 80009b0: 40007000 .word 0x40007000 -080005f8 : +080009b4 : * @brief CAN1 Initialization Function * @param None * @retval None */ static void MX_CAN1_Init(void) { - 80005f8: b580 push {r7, lr} - 80005fa: af00 add r7, sp, #0 + 80009b4: b580 push {r7, lr} + 80009b6: af00 add r7, sp, #0 /* USER CODE END CAN1_Init 0 */ /* USER CODE BEGIN CAN1_Init 1 */ /* USER CODE END CAN1_Init 1 */ hcan1.Instance = CAN1; - 80005fc: 4b16 ldr r3, [pc, #88] @ (8000658 ) - 80005fe: 4a17 ldr r2, [pc, #92] @ (800065c ) - 8000600: 601a str r2, [r3, #0] - hcan1.Init.Prescaler = 16; - 8000602: 4b15 ldr r3, [pc, #84] @ (8000658 ) - 8000604: 2210 movs r2, #16 - 8000606: 605a str r2, [r3, #4] - hcan1.Init.Mode = CAN_MODE_NORMAL; - 8000608: 4b13 ldr r3, [pc, #76] @ (8000658 ) - 800060a: 2200 movs r2, #0 - 800060c: 609a str r2, [r3, #8] + 80009b8: 4b18 ldr r3, [pc, #96] @ (8000a1c ) + 80009ba: 4a19 ldr r2, [pc, #100] @ (8000a20 ) + 80009bc: 601a str r2, [r3, #0] + hcan1.Init.Prescaler = 4; + 80009be: 4b17 ldr r3, [pc, #92] @ (8000a1c ) + 80009c0: 2204 movs r2, #4 + 80009c2: 605a str r2, [r3, #4] + hcan1.Init.Mode = CAN_MODE_SILENT; + 80009c4: 4b15 ldr r3, [pc, #84] @ (8000a1c ) + 80009c6: f04f 4200 mov.w r2, #2147483648 @ 0x80000000 + 80009ca: 609a str r2, [r3, #8] hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ; - 800060e: 4b12 ldr r3, [pc, #72] @ (8000658 ) - 8000610: 2200 movs r2, #0 - 8000612: 60da str r2, [r3, #12] - hcan1.Init.TimeSeg1 = CAN_BS1_1TQ; - 8000614: 4b10 ldr r3, [pc, #64] @ (8000658 ) - 8000616: 2200 movs r2, #0 - 8000618: 611a str r2, [r3, #16] - hcan1.Init.TimeSeg2 = CAN_BS2_1TQ; - 800061a: 4b0f ldr r3, [pc, #60] @ (8000658 ) - 800061c: 2200 movs r2, #0 - 800061e: 615a str r2, [r3, #20] + 80009cc: 4b13 ldr r3, [pc, #76] @ (8000a1c ) + 80009ce: 2200 movs r2, #0 + 80009d0: 60da str r2, [r3, #12] + hcan1.Init.TimeSeg1 = CAN_BS1_16TQ; + 80009d2: 4b12 ldr r3, [pc, #72] @ (8000a1c ) + 80009d4: f44f 2270 mov.w r2, #983040 @ 0xf0000 + 80009d8: 611a str r2, [r3, #16] + hcan1.Init.TimeSeg2 = CAN_BS2_4TQ; + 80009da: 4b10 ldr r3, [pc, #64] @ (8000a1c ) + 80009dc: f44f 1240 mov.w r2, #3145728 @ 0x300000 + 80009e0: 615a str r2, [r3, #20] hcan1.Init.TimeTriggeredMode = DISABLE; - 8000620: 4b0d ldr r3, [pc, #52] @ (8000658 ) - 8000622: 2200 movs r2, #0 - 8000624: 761a strb r2, [r3, #24] + 80009e2: 4b0e ldr r3, [pc, #56] @ (8000a1c ) + 80009e4: 2200 movs r2, #0 + 80009e6: 761a strb r2, [r3, #24] hcan1.Init.AutoBusOff = DISABLE; - 8000626: 4b0c ldr r3, [pc, #48] @ (8000658 ) - 8000628: 2200 movs r2, #0 - 800062a: 765a strb r2, [r3, #25] - hcan1.Init.AutoWakeUp = DISABLE; - 800062c: 4b0a ldr r3, [pc, #40] @ (8000658 ) - 800062e: 2200 movs r2, #0 - 8000630: 769a strb r2, [r3, #26] + 80009e8: 4b0c ldr r3, [pc, #48] @ (8000a1c ) + 80009ea: 2200 movs r2, #0 + 80009ec: 765a strb r2, [r3, #25] + hcan1.Init.AutoWakeUp = ENABLE; + 80009ee: 4b0b ldr r3, [pc, #44] @ (8000a1c ) + 80009f0: 2201 movs r2, #1 + 80009f2: 769a strb r2, [r3, #26] hcan1.Init.AutoRetransmission = DISABLE; - 8000632: 4b09 ldr r3, [pc, #36] @ (8000658 ) - 8000634: 2200 movs r2, #0 - 8000636: 76da strb r2, [r3, #27] + 80009f4: 4b09 ldr r3, [pc, #36] @ (8000a1c ) + 80009f6: 2200 movs r2, #0 + 80009f8: 76da strb r2, [r3, #27] hcan1.Init.ReceiveFifoLocked = DISABLE; - 8000638: 4b07 ldr r3, [pc, #28] @ (8000658 ) - 800063a: 2200 movs r2, #0 - 800063c: 771a strb r2, [r3, #28] + 80009fa: 4b08 ldr r3, [pc, #32] @ (8000a1c ) + 80009fc: 2200 movs r2, #0 + 80009fe: 771a strb r2, [r3, #28] hcan1.Init.TransmitFifoPriority = DISABLE; - 800063e: 4b06 ldr r3, [pc, #24] @ (8000658 ) - 8000640: 2200 movs r2, #0 - 8000642: 775a strb r2, [r3, #29] + 8000a00: 4b06 ldr r3, [pc, #24] @ (8000a1c ) + 8000a02: 2200 movs r2, #0 + 8000a04: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan1) != HAL_OK) - 8000644: 4804 ldr r0, [pc, #16] @ (8000658 ) - 8000646: f000 fb7f bl 8000d48 - 800064a: 4603 mov r3, r0 - 800064c: 2b00 cmp r3, #0 - 800064e: d001 beq.n 8000654 + 8000a06: 4805 ldr r0, [pc, #20] @ (8000a1c ) + 8000a08: f000 fd46 bl 8001498 + 8000a0c: 4603 mov r3, r0 + 8000a0e: 2b00 cmp r3, #0 + 8000a10: d001 beq.n 8000a16 { Error_Handler(); - 8000650: f000 f8f4 bl 800083c + 8000a12: f000 f94f bl 8000cb4 } /* USER CODE BEGIN CAN1_Init 2 */ /* USER CODE END CAN1_Init 2 */ } - 8000654: bf00 nop - 8000656: bd80 pop {r7, pc} - 8000658: 2000007c .word 0x2000007c - 800065c: 40006400 .word 0x40006400 + 8000a16: bf00 nop + 8000a18: bd80 pop {r7, pc} + 8000a1a: bf00 nop + 8000a1c: 20000094 .word 0x20000094 + 8000a20: 40006400 .word 0x40006400 -08000660 : +08000a24 : * @brief CAN2 Initialization Function * @param None * @retval None */ static void MX_CAN2_Init(void) { - 8000660: b580 push {r7, lr} - 8000662: af00 add r7, sp, #0 + 8000a24: b580 push {r7, lr} + 8000a26: af00 add r7, sp, #0 /* USER CODE END CAN2_Init 0 */ /* USER CODE BEGIN CAN2_Init 1 */ /* USER CODE END CAN2_Init 1 */ hcan2.Instance = CAN2; - 8000664: 4b16 ldr r3, [pc, #88] @ (80006c0 ) - 8000666: 4a17 ldr r2, [pc, #92] @ (80006c4 ) - 8000668: 601a str r2, [r3, #0] - hcan2.Init.Prescaler = 16; - 800066a: 4b15 ldr r3, [pc, #84] @ (80006c0 ) - 800066c: 2210 movs r2, #16 - 800066e: 605a str r2, [r3, #4] - hcan2.Init.Mode = CAN_MODE_NORMAL; - 8000670: 4b13 ldr r3, [pc, #76] @ (80006c0 ) - 8000672: 2200 movs r2, #0 - 8000674: 609a str r2, [r3, #8] + 8000a28: 4b18 ldr r3, [pc, #96] @ (8000a8c ) + 8000a2a: 4a19 ldr r2, [pc, #100] @ (8000a90 ) + 8000a2c: 601a str r2, [r3, #0] + hcan2.Init.Prescaler = 8; + 8000a2e: 4b17 ldr r3, [pc, #92] @ (8000a8c ) + 8000a30: 2208 movs r2, #8 + 8000a32: 605a str r2, [r3, #4] + hcan2.Init.Mode = CAN_MODE_SILENT; + 8000a34: 4b15 ldr r3, [pc, #84] @ (8000a8c ) + 8000a36: f04f 4200 mov.w r2, #2147483648 @ 0x80000000 + 8000a3a: 609a str r2, [r3, #8] hcan2.Init.SyncJumpWidth = CAN_SJW_1TQ; - 8000676: 4b12 ldr r3, [pc, #72] @ (80006c0 ) - 8000678: 2200 movs r2, #0 - 800067a: 60da str r2, [r3, #12] - hcan2.Init.TimeSeg1 = CAN_BS1_1TQ; - 800067c: 4b10 ldr r3, [pc, #64] @ (80006c0 ) - 800067e: 2200 movs r2, #0 - 8000680: 611a str r2, [r3, #16] - hcan2.Init.TimeSeg2 = CAN_BS2_1TQ; - 8000682: 4b0f ldr r3, [pc, #60] @ (80006c0 ) - 8000684: 2200 movs r2, #0 - 8000686: 615a str r2, [r3, #20] + 8000a3c: 4b13 ldr r3, [pc, #76] @ (8000a8c ) + 8000a3e: 2200 movs r2, #0 + 8000a40: 60da str r2, [r3, #12] + hcan2.Init.TimeSeg1 = CAN_BS1_16TQ; + 8000a42: 4b12 ldr r3, [pc, #72] @ (8000a8c ) + 8000a44: f44f 2270 mov.w r2, #983040 @ 0xf0000 + 8000a48: 611a str r2, [r3, #16] + hcan2.Init.TimeSeg2 = CAN_BS2_4TQ; + 8000a4a: 4b10 ldr r3, [pc, #64] @ (8000a8c ) + 8000a4c: f44f 1240 mov.w r2, #3145728 @ 0x300000 + 8000a50: 615a str r2, [r3, #20] hcan2.Init.TimeTriggeredMode = DISABLE; - 8000688: 4b0d ldr r3, [pc, #52] @ (80006c0 ) - 800068a: 2200 movs r2, #0 - 800068c: 761a strb r2, [r3, #24] + 8000a52: 4b0e ldr r3, [pc, #56] @ (8000a8c ) + 8000a54: 2200 movs r2, #0 + 8000a56: 761a strb r2, [r3, #24] hcan2.Init.AutoBusOff = DISABLE; - 800068e: 4b0c ldr r3, [pc, #48] @ (80006c0 ) - 8000690: 2200 movs r2, #0 - 8000692: 765a strb r2, [r3, #25] - hcan2.Init.AutoWakeUp = DISABLE; - 8000694: 4b0a ldr r3, [pc, #40] @ (80006c0 ) - 8000696: 2200 movs r2, #0 - 8000698: 769a strb r2, [r3, #26] + 8000a58: 4b0c ldr r3, [pc, #48] @ (8000a8c ) + 8000a5a: 2200 movs r2, #0 + 8000a5c: 765a strb r2, [r3, #25] + hcan2.Init.AutoWakeUp = ENABLE; + 8000a5e: 4b0b ldr r3, [pc, #44] @ (8000a8c ) + 8000a60: 2201 movs r2, #1 + 8000a62: 769a strb r2, [r3, #26] hcan2.Init.AutoRetransmission = DISABLE; - 800069a: 4b09 ldr r3, [pc, #36] @ (80006c0 ) - 800069c: 2200 movs r2, #0 - 800069e: 76da strb r2, [r3, #27] + 8000a64: 4b09 ldr r3, [pc, #36] @ (8000a8c ) + 8000a66: 2200 movs r2, #0 + 8000a68: 76da strb r2, [r3, #27] hcan2.Init.ReceiveFifoLocked = DISABLE; - 80006a0: 4b07 ldr r3, [pc, #28] @ (80006c0 ) - 80006a2: 2200 movs r2, #0 - 80006a4: 771a strb r2, [r3, #28] + 8000a6a: 4b08 ldr r3, [pc, #32] @ (8000a8c ) + 8000a6c: 2200 movs r2, #0 + 8000a6e: 771a strb r2, [r3, #28] hcan2.Init.TransmitFifoPriority = DISABLE; - 80006a6: 4b06 ldr r3, [pc, #24] @ (80006c0 ) - 80006a8: 2200 movs r2, #0 - 80006aa: 775a strb r2, [r3, #29] + 8000a70: 4b06 ldr r3, [pc, #24] @ (8000a8c ) + 8000a72: 2200 movs r2, #0 + 8000a74: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan2) != HAL_OK) - 80006ac: 4804 ldr r0, [pc, #16] @ (80006c0 ) - 80006ae: f000 fb4b bl 8000d48 - 80006b2: 4603 mov r3, r0 - 80006b4: 2b00 cmp r3, #0 - 80006b6: d001 beq.n 80006bc + 8000a76: 4805 ldr r0, [pc, #20] @ (8000a8c ) + 8000a78: f000 fd0e bl 8001498 + 8000a7c: 4603 mov r3, r0 + 8000a7e: 2b00 cmp r3, #0 + 8000a80: d001 beq.n 8000a86 { Error_Handler(); - 80006b8: f000 f8c0 bl 800083c + 8000a82: f000 f917 bl 8000cb4 } /* USER CODE BEGIN CAN2_Init 2 */ /* USER CODE END CAN2_Init 2 */ } - 80006bc: bf00 nop - 80006be: bd80 pop {r7, pc} - 80006c0: 200000e0 .word 0x200000e0 - 80006c4: 40006800 .word 0x40006800 + 8000a86: bf00 nop + 8000a88: bd80 pop {r7, pc} + 8000a8a: bf00 nop + 8000a8c: 200000f8 .word 0x200000f8 + 8000a90: 40006800 .word 0x40006800 -080006c8 : +08000a94 : + * @brief SDIO Initialization Function + * @param None + * @retval None + */ +static void MX_SDIO_SD_Init(void) +{ + 8000a94: b580 push {r7, lr} + 8000a96: af00 add r7, sp, #0 + /* USER CODE END SDIO_Init 0 */ + + /* USER CODE BEGIN SDIO_Init 1 */ + + /* USER CODE END SDIO_Init 1 */ + hsd.Instance = SDIO; + 8000a98: 4b14 ldr r3, [pc, #80] @ (8000aec ) + 8000a9a: 4a15 ldr r2, [pc, #84] @ (8000af0 ) + 8000a9c: 601a str r2, [r3, #0] + hsd.Init.ClockEdge = SDIO_CLOCK_EDGE_RISING; + 8000a9e: 4b13 ldr r3, [pc, #76] @ (8000aec ) + 8000aa0: 2200 movs r2, #0 + 8000aa2: 605a str r2, [r3, #4] + hsd.Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; + 8000aa4: 4b11 ldr r3, [pc, #68] @ (8000aec ) + 8000aa6: 2200 movs r2, #0 + 8000aa8: 609a str r2, [r3, #8] + hsd.Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; + 8000aaa: 4b10 ldr r3, [pc, #64] @ (8000aec ) + 8000aac: 2200 movs r2, #0 + 8000aae: 60da str r2, [r3, #12] + hsd.Init.BusWide = SDIO_BUS_WIDE_1B; + 8000ab0: 4b0e ldr r3, [pc, #56] @ (8000aec ) + 8000ab2: 2200 movs r2, #0 + 8000ab4: 611a str r2, [r3, #16] + hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; + 8000ab6: 4b0d ldr r3, [pc, #52] @ (8000aec ) + 8000ab8: 2200 movs r2, #0 + 8000aba: 615a str r2, [r3, #20] + hsd.Init.ClockDiv = 0; + 8000abc: 4b0b ldr r3, [pc, #44] @ (8000aec ) + 8000abe: 2200 movs r2, #0 + 8000ac0: 619a str r2, [r3, #24] + if (HAL_SD_Init(&hsd) != HAL_OK) + 8000ac2: 480a ldr r0, [pc, #40] @ (8000aec ) + 8000ac4: f003 f96a bl 8003d9c + 8000ac8: 4603 mov r3, r0 + 8000aca: 2b00 cmp r3, #0 + 8000acc: d001 beq.n 8000ad2 + { + Error_Handler(); + 8000ace: f000 f8f1 bl 8000cb4 + } + if (HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B) != HAL_OK) + 8000ad2: f44f 6100 mov.w r1, #2048 @ 0x800 + 8000ad6: 4805 ldr r0, [pc, #20] @ (8000aec ) + 8000ad8: f003 fdbc bl 8004654 + 8000adc: 4603 mov r3, r0 + 8000ade: 2b00 cmp r3, #0 + 8000ae0: d001 beq.n 8000ae6 + { + Error_Handler(); + 8000ae2: f000 f8e7 bl 8000cb4 + } + /* USER CODE BEGIN SDIO_Init 2 */ + + /* USER CODE END SDIO_Init 2 */ + +} + 8000ae6: bf00 nop + 8000ae8: bd80 pop {r7, pc} + 8000aea: bf00 nop + 8000aec: 2000015c .word 0x2000015c + 8000af0: 40012c00 .word 0x40012c00 + +08000af4 : + +/** + * Enable DMA controller clock + */ +static void MX_DMA_Init(void) +{ + 8000af4: b580 push {r7, lr} + 8000af6: b082 sub sp, #8 + 8000af8: af00 add r7, sp, #0 + + /* DMA controller clock enable */ + __HAL_RCC_DMA2_CLK_ENABLE(); + 8000afa: 2300 movs r3, #0 + 8000afc: 607b str r3, [r7, #4] + 8000afe: 4b10 ldr r3, [pc, #64] @ (8000b40 ) + 8000b00: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000b02: 4a0f ldr r2, [pc, #60] @ (8000b40 ) + 8000b04: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 + 8000b08: 6313 str r3, [r2, #48] @ 0x30 + 8000b0a: 4b0d ldr r3, [pc, #52] @ (8000b40 ) + 8000b0c: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000b0e: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 8000b12: 607b str r3, [r7, #4] + 8000b14: 687b ldr r3, [r7, #4] + + /* DMA interrupt init */ + /* DMA2_Stream3_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA2_Stream3_IRQn, 5, 0); + 8000b16: 2200 movs r2, #0 + 8000b18: 2105 movs r1, #5 + 8000b1a: 203b movs r0, #59 @ 0x3b + 8000b1c: f001 fb90 bl 8002240 + HAL_NVIC_EnableIRQ(DMA2_Stream3_IRQn); + 8000b20: 203b movs r0, #59 @ 0x3b + 8000b22: f001 fbb9 bl 8002298 + /* DMA2_Stream6_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA2_Stream6_IRQn, 5, 0); + 8000b26: 2200 movs r2, #0 + 8000b28: 2105 movs r1, #5 + 8000b2a: 2045 movs r0, #69 @ 0x45 + 8000b2c: f001 fb88 bl 8002240 + HAL_NVIC_EnableIRQ(DMA2_Stream6_IRQn); + 8000b30: 2045 movs r0, #69 @ 0x45 + 8000b32: f001 fbb1 bl 8002298 + +} + 8000b36: bf00 nop + 8000b38: 3708 adds r7, #8 + 8000b3a: 46bd mov sp, r7 + 8000b3c: bd80 pop {r7, pc} + 8000b3e: bf00 nop + 8000b40: 40023800 .word 0x40023800 + +08000b44 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { - 80006c8: b580 push {r7, lr} - 80006ca: b08a sub sp, #40 @ 0x28 - 80006cc: af00 add r7, sp, #0 + 8000b44: b580 push {r7, lr} + 8000b46: b08a sub sp, #40 @ 0x28 + 8000b48: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; - 80006ce: f107 0314 add.w r3, r7, #20 - 80006d2: 2200 movs r2, #0 - 80006d4: 601a str r2, [r3, #0] - 80006d6: 605a str r2, [r3, #4] - 80006d8: 609a str r2, [r3, #8] - 80006da: 60da str r2, [r3, #12] - 80006dc: 611a str r2, [r3, #16] + 8000b4a: f107 0314 add.w r3, r7, #20 + 8000b4e: 2200 movs r2, #0 + 8000b50: 601a str r2, [r3, #0] + 8000b52: 605a str r2, [r3, #4] + 8000b54: 609a str r2, [r3, #8] + 8000b56: 60da str r2, [r3, #12] + 8000b58: 611a str r2, [r3, #16] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); - 80006de: 2300 movs r3, #0 - 80006e0: 613b str r3, [r7, #16] - 80006e2: 4b43 ldr r3, [pc, #268] @ (80007f0 ) - 80006e4: 6b1b ldr r3, [r3, #48] @ 0x30 - 80006e6: 4a42 ldr r2, [pc, #264] @ (80007f0 ) - 80006e8: f043 0304 orr.w r3, r3, #4 - 80006ec: 6313 str r3, [r2, #48] @ 0x30 - 80006ee: 4b40 ldr r3, [pc, #256] @ (80007f0 ) - 80006f0: 6b1b ldr r3, [r3, #48] @ 0x30 - 80006f2: f003 0304 and.w r3, r3, #4 - 80006f6: 613b str r3, [r7, #16] - 80006f8: 693b ldr r3, [r7, #16] + 8000b5a: 2300 movs r3, #0 + 8000b5c: 613b str r3, [r7, #16] + 8000b5e: 4b47 ldr r3, [pc, #284] @ (8000c7c ) + 8000b60: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000b62: 4a46 ldr r2, [pc, #280] @ (8000c7c ) + 8000b64: f043 0304 orr.w r3, r3, #4 + 8000b68: 6313 str r3, [r2, #48] @ 0x30 + 8000b6a: 4b44 ldr r3, [pc, #272] @ (8000c7c ) + 8000b6c: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000b6e: f003 0304 and.w r3, r3, #4 + 8000b72: 613b str r3, [r7, #16] + 8000b74: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOH_CLK_ENABLE(); - 80006fa: 2300 movs r3, #0 - 80006fc: 60fb str r3, [r7, #12] - 80006fe: 4b3c ldr r3, [pc, #240] @ (80007f0 ) - 8000700: 6b1b ldr r3, [r3, #48] @ 0x30 - 8000702: 4a3b ldr r2, [pc, #236] @ (80007f0 ) - 8000704: f043 0380 orr.w r3, r3, #128 @ 0x80 - 8000708: 6313 str r3, [r2, #48] @ 0x30 - 800070a: 4b39 ldr r3, [pc, #228] @ (80007f0 ) - 800070c: 6b1b ldr r3, [r3, #48] @ 0x30 - 800070e: f003 0380 and.w r3, r3, #128 @ 0x80 - 8000712: 60fb str r3, [r7, #12] - 8000714: 68fb ldr r3, [r7, #12] + 8000b76: 2300 movs r3, #0 + 8000b78: 60fb str r3, [r7, #12] + 8000b7a: 4b40 ldr r3, [pc, #256] @ (8000c7c ) + 8000b7c: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000b7e: 4a3f ldr r2, [pc, #252] @ (8000c7c ) + 8000b80: f043 0380 orr.w r3, r3, #128 @ 0x80 + 8000b84: 6313 str r3, [r2, #48] @ 0x30 + 8000b86: 4b3d ldr r3, [pc, #244] @ (8000c7c ) + 8000b88: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000b8a: f003 0380 and.w r3, r3, #128 @ 0x80 + 8000b8e: 60fb str r3, [r7, #12] + 8000b90: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); - 8000716: 2300 movs r3, #0 - 8000718: 60bb str r3, [r7, #8] - 800071a: 4b35 ldr r3, [pc, #212] @ (80007f0 ) - 800071c: 6b1b ldr r3, [r3, #48] @ 0x30 - 800071e: 4a34 ldr r2, [pc, #208] @ (80007f0 ) - 8000720: f043 0301 orr.w r3, r3, #1 - 8000724: 6313 str r3, [r2, #48] @ 0x30 - 8000726: 4b32 ldr r3, [pc, #200] @ (80007f0 ) - 8000728: 6b1b ldr r3, [r3, #48] @ 0x30 - 800072a: f003 0301 and.w r3, r3, #1 - 800072e: 60bb str r3, [r7, #8] - 8000730: 68bb ldr r3, [r7, #8] + 8000b92: 2300 movs r3, #0 + 8000b94: 60bb str r3, [r7, #8] + 8000b96: 4b39 ldr r3, [pc, #228] @ (8000c7c ) + 8000b98: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000b9a: 4a38 ldr r2, [pc, #224] @ (8000c7c ) + 8000b9c: f043 0301 orr.w r3, r3, #1 + 8000ba0: 6313 str r3, [r2, #48] @ 0x30 + 8000ba2: 4b36 ldr r3, [pc, #216] @ (8000c7c ) + 8000ba4: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000ba6: f003 0301 and.w r3, r3, #1 + 8000baa: 60bb str r3, [r7, #8] + 8000bac: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); - 8000732: 2300 movs r3, #0 - 8000734: 607b str r3, [r7, #4] - 8000736: 4b2e ldr r3, [pc, #184] @ (80007f0 ) - 8000738: 6b1b ldr r3, [r3, #48] @ 0x30 - 800073a: 4a2d ldr r2, [pc, #180] @ (80007f0 ) - 800073c: f043 0302 orr.w r3, r3, #2 - 8000740: 6313 str r3, [r2, #48] @ 0x30 - 8000742: 4b2b ldr r3, [pc, #172] @ (80007f0 ) - 8000744: 6b1b ldr r3, [r3, #48] @ 0x30 - 8000746: f003 0302 and.w r3, r3, #2 - 800074a: 607b str r3, [r7, #4] - 800074c: 687b ldr r3, [r7, #4] + 8000bae: 2300 movs r3, #0 + 8000bb0: 607b str r3, [r7, #4] + 8000bb2: 4b32 ldr r3, [pc, #200] @ (8000c7c ) + 8000bb4: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000bb6: 4a31 ldr r2, [pc, #196] @ (8000c7c ) + 8000bb8: f043 0302 orr.w r3, r3, #2 + 8000bbc: 6313 str r3, [r2, #48] @ 0x30 + 8000bbe: 4b2f ldr r3, [pc, #188] @ (8000c7c ) + 8000bc0: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000bc2: f003 0302 and.w r3, r3, #2 + 8000bc6: 607b str r3, [r7, #4] + 8000bc8: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOD_CLK_ENABLE(); - 800074e: 2300 movs r3, #0 - 8000750: 603b str r3, [r7, #0] - 8000752: 4b27 ldr r3, [pc, #156] @ (80007f0 ) - 8000754: 6b1b ldr r3, [r3, #48] @ 0x30 - 8000756: 4a26 ldr r2, [pc, #152] @ (80007f0 ) - 8000758: f043 0308 orr.w r3, r3, #8 - 800075c: 6313 str r3, [r2, #48] @ 0x30 - 800075e: 4b24 ldr r3, [pc, #144] @ (80007f0 ) - 8000760: 6b1b ldr r3, [r3, #48] @ 0x30 - 8000762: f003 0308 and.w r3, r3, #8 - 8000766: 603b str r3, [r7, #0] - 8000768: 683b ldr r3, [r7, #0] + 8000bca: 2300 movs r3, #0 + 8000bcc: 603b str r3, [r7, #0] + 8000bce: 4b2b ldr r3, [pc, #172] @ (8000c7c ) + 8000bd0: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000bd2: 4a2a ldr r2, [pc, #168] @ (8000c7c ) + 8000bd4: f043 0308 orr.w r3, r3, #8 + 8000bd8: 6313 str r3, [r2, #48] @ 0x30 + 8000bda: 4b28 ldr r3, [pc, #160] @ (8000c7c ) + 8000bdc: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000bde: f003 0308 and.w r3, r3, #8 + 8000be2: 603b str r3, [r7, #0] + 8000be4: 683b ldr r3, [r7, #0] + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5, GPIO_PIN_RESET); + 8000be6: 2200 movs r2, #0 + 8000be8: 2138 movs r1, #56 @ 0x38 + 8000bea: 4825 ldr r0, [pc, #148] @ (8000c80 ) + 8000bec: f002 fab8 bl 8003160 /*Configure GPIO pins : PC13 PC14 PC15 PC0 PC1 PC2 PC3 PC4 - PC5 PC6 PC7 PC8 - PC9 PC10 PC11 PC12 */ + PC5 PC6 PC7 */ GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15|GPIO_PIN_0 - 800076a: f64f 73ff movw r3, #65535 @ 0xffff - 800076e: 617b str r3, [r7, #20] + 8000bf0: f24e 03ff movw r3, #57599 @ 0xe0ff + 8000bf4: 617b str r3, [r7, #20] |GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4 - |GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8 - |GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12; + |GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - 8000770: 2303 movs r3, #3 - 8000772: 61bb str r3, [r7, #24] + 8000bf6: 2303 movs r3, #3 + 8000bf8: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; - 8000774: 2300 movs r3, #0 - 8000776: 61fb str r3, [r7, #28] + 8000bfa: 2300 movs r3, #0 + 8000bfc: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - 8000778: f107 0314 add.w r3, r7, #20 - 800077c: 4619 mov r1, r3 - 800077e: 481d ldr r0, [pc, #116] @ (80007f4 ) - 8000780: f000 fee0 bl 8001544 + 8000bfe: f107 0314 add.w r3, r7, #20 + 8000c02: 4619 mov r1, r3 + 8000c04: 481f ldr r0, [pc, #124] @ (8000c84 ) + 8000c06: f001 ffd7 bl 8002bb8 /*Configure GPIO pins : PH0 PH1 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; - 8000784: 2303 movs r3, #3 - 8000786: 617b str r3, [r7, #20] + 8000c0a: 2303 movs r3, #3 + 8000c0c: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - 8000788: 2303 movs r3, #3 - 800078a: 61bb str r3, [r7, #24] + 8000c0e: 2303 movs r3, #3 + 8000c10: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; - 800078c: 2300 movs r3, #0 - 800078e: 61fb str r3, [r7, #28] + 8000c12: 2300 movs r3, #0 + 8000c14: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); - 8000790: f107 0314 add.w r3, r7, #20 - 8000794: 4619 mov r1, r3 - 8000796: 4818 ldr r0, [pc, #96] @ (80007f8 ) - 8000798: f000 fed4 bl 8001544 + 8000c16: f107 0314 add.w r3, r7, #20 + 8000c1a: 4619 mov r1, r3 + 8000c1c: 481a ldr r0, [pc, #104] @ (8000c88 ) + 8000c1e: f001 ffcb bl 8002bb8 /*Configure GPIO pins : PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 - 800079c: f64f 73ff movw r3, #65535 @ 0xffff - 80007a0: 617b str r3, [r7, #20] + 8000c22: f64f 73ff movw r3, #65535 @ 0xffff + 8000c26: 617b str r3, [r7, #20] |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7 |GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - 80007a2: 2303 movs r3, #3 - 80007a4: 61bb str r3, [r7, #24] + 8000c28: 2303 movs r3, #3 + 8000c2a: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; - 80007a6: 2300 movs r3, #0 - 80007a8: 61fb str r3, [r7, #28] + 8000c2c: 2300 movs r3, #0 + 8000c2e: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - 80007aa: f107 0314 add.w r3, r7, #20 - 80007ae: 4619 mov r1, r3 - 80007b0: 4812 ldr r0, [pc, #72] @ (80007fc ) - 80007b2: f000 fec7 bl 8001544 + 8000c30: f107 0314 add.w r3, r7, #20 + 8000c34: 4619 mov r1, r3 + 8000c36: 4815 ldr r0, [pc, #84] @ (8000c8c ) + 8000c38: f001 ffbe bl 8002bb8 /*Configure GPIO pins : PB0 PB1 PB2 PB10 - PB11 PB14 PB15 PB3 - PB4 PB5 PB6 PB7 */ + PB11 PB14 PB15 PB6 + PB7 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10 - 80007b6: f64c 43ff movw r3, #52479 @ 0xccff - 80007ba: 617b str r3, [r7, #20] - |GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_15|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; + 8000c3c: f64c 43c7 movw r3, #52423 @ 0xccc7 + 8000c40: 617b str r3, [r7, #20] + |GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_15|GPIO_PIN_6 + |GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - 80007bc: 2303 movs r3, #3 - 80007be: 61bb str r3, [r7, #24] + 8000c42: 2303 movs r3, #3 + 8000c44: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; - 80007c0: 2300 movs r3, #0 - 80007c2: 61fb str r3, [r7, #28] + 8000c46: 2300 movs r3, #0 + 8000c48: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - 80007c4: f107 0314 add.w r3, r7, #20 - 80007c8: 4619 mov r1, r3 - 80007ca: 480d ldr r0, [pc, #52] @ (8000800 ) - 80007cc: f000 feba bl 8001544 + 8000c4a: f107 0314 add.w r3, r7, #20 + 8000c4e: 4619 mov r1, r3 + 8000c50: 480b ldr r0, [pc, #44] @ (8000c80 ) + 8000c52: f001 ffb1 bl 8002bb8 - /*Configure GPIO pin : PD2 */ - GPIO_InitStruct.Pin = GPIO_PIN_2; - 80007d0: 2304 movs r3, #4 - 80007d2: 617b str r3, [r7, #20] - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - 80007d4: 2303 movs r3, #3 - 80007d6: 61bb str r3, [r7, #24] + /*Configure GPIO pins : PB3 PB4 PB5 */ + GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5; + 8000c56: 2338 movs r3, #56 @ 0x38 + 8000c58: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8000c5a: 2301 movs r3, #1 + 8000c5c: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; - 80007d8: 2300 movs r3, #0 - 80007da: 61fb str r3, [r7, #28] - HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - 80007dc: f107 0314 add.w r3, r7, #20 - 80007e0: 4619 mov r1, r3 - 80007e2: 4808 ldr r0, [pc, #32] @ (8000804 ) - 80007e4: f000 feae bl 8001544 + 8000c5e: 2300 movs r3, #0 + 8000c60: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8000c62: 2300 movs r3, #0 + 8000c64: 623b str r3, [r7, #32] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8000c66: f107 0314 add.w r3, r7, #20 + 8000c6a: 4619 mov r1, r3 + 8000c6c: 4804 ldr r0, [pc, #16] @ (8000c80 ) + 8000c6e: f001 ffa3 bl 8002bb8 /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } - 80007e8: bf00 nop - 80007ea: 3728 adds r7, #40 @ 0x28 - 80007ec: 46bd mov sp, r7 - 80007ee: bd80 pop {r7, pc} - 80007f0: 40023800 .word 0x40023800 - 80007f4: 40020800 .word 0x40020800 - 80007f8: 40021c00 .word 0x40021c00 - 80007fc: 40020000 .word 0x40020000 - 8000800: 40020400 .word 0x40020400 - 8000804: 40020c00 .word 0x40020c00 + 8000c72: bf00 nop + 8000c74: 3728 adds r7, #40 @ 0x28 + 8000c76: 46bd mov sp, r7 + 8000c78: bd80 pop {r7, pc} + 8000c7a: bf00 nop + 8000c7c: 40023800 .word 0x40023800 + 8000c80: 40020400 .word 0x40020400 + 8000c84: 40020800 .word 0x40020800 + 8000c88: 40021c00 .word 0x40021c00 + 8000c8c: 40020000 .word 0x40020000 -08000808 : - * @param argument: Not used - * @retval None - */ -/* USER CODE END Header_StartDefaultTask */ -void StartDefaultTask(void *argument) -{ - 8000808: b580 push {r7, lr} - 800080a: b082 sub sp, #8 - 800080c: af00 add r7, sp, #0 - 800080e: 6078 str r0, [r7, #4] - /* USER CODE BEGIN 5 */ - /* Infinite loop */ - for(;;) - { - osDelay(1); - 8000810: 2001 movs r0, #1 - 8000812: f002 fc19 bl 8003048 - 8000816: e7fb b.n 8000810 - -08000818 : +08000c90 : * a global variable "uwTick" used as application time base. * @param htim : TIM handle * @retval None */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { - 8000818: b580 push {r7, lr} - 800081a: b082 sub sp, #8 - 800081c: af00 add r7, sp, #0 - 800081e: 6078 str r0, [r7, #4] + 8000c90: b580 push {r7, lr} + 8000c92: b082 sub sp, #8 + 8000c94: af00 add r7, sp, #0 + 8000c96: 6078 str r0, [r7, #4] /* USER CODE BEGIN Callback 0 */ /* USER CODE END Callback 0 */ if (htim->Instance == TIM6) - 8000820: 687b ldr r3, [r7, #4] - 8000822: 681b ldr r3, [r3, #0] - 8000824: 4a04 ldr r2, [pc, #16] @ (8000838 ) - 8000826: 4293 cmp r3, r2 - 8000828: d101 bne.n 800082e + 8000c98: 687b ldr r3, [r7, #4] + 8000c9a: 681b ldr r3, [r3, #0] + 8000c9c: 4a04 ldr r2, [pc, #16] @ (8000cb0 ) + 8000c9e: 4293 cmp r3, r2 + 8000ca0: d101 bne.n 8000ca6 { HAL_IncTick(); - 800082a: f000 fa6d bl 8000d08 + 8000ca2: f000 fbb5 bl 8001410 } /* USER CODE BEGIN Callback 1 */ /* USER CODE END Callback 1 */ } - 800082e: bf00 nop - 8000830: 3708 adds r7, #8 - 8000832: 46bd mov sp, r7 - 8000834: bd80 pop {r7, pc} - 8000836: bf00 nop - 8000838: 40001000 .word 0x40001000 + 8000ca6: bf00 nop + 8000ca8: 3708 adds r7, #8 + 8000caa: 46bd mov sp, r7 + 8000cac: bd80 pop {r7, pc} + 8000cae: bf00 nop + 8000cb0: 40001000 .word 0x40001000 -0800083c : +08000cb4 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { - 800083c: b480 push {r7} - 800083e: af00 add r7, sp, #0 + 8000cb4: b580 push {r7, lr} + 8000cb6: b082 sub sp, #8 + 8000cb8: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting special-purpose register PRIMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); - 8000840: b672 cpsid i + 8000cba: b672 cpsid i } - 8000842: bf00 nop - /* USER CODE BEGIN Error_Handler_Debug */ - /* User can add his own implementation to report the HAL error return state */ - __disable_irq(); - while (1) - 8000844: bf00 nop - 8000846: e7fd b.n 8000844 + 8000cbc: bf00 nop + //TODO: check if it is necessary to stop FreeRTOS -08000848 : + uint32_t error_code_can1; + uint32_t error_code_can2; + + if (HAL_CAN_GetState(&hcan1) != HAL_CAN_STATE_READY) error_code_can1 = HAL_CAN_GetError(&hcan1); + 8000cbe: 4818 ldr r0, [pc, #96] @ (8000d20 ) + 8000cc0: f001 f9bc bl 800203c + 8000cc4: 4603 mov r3, r0 + 8000cc6: 2b01 cmp r3, #1 + 8000cc8: d003 beq.n 8000cd2 + 8000cca: 4815 ldr r0, [pc, #84] @ (8000d20 ) + 8000ccc: f001 f9de bl 800208c + 8000cd0: 6078 str r0, [r7, #4] + if (HAL_CAN_GetState(&hcan2) != HAL_CAN_STATE_READY) error_code_can2 = HAL_CAN_GetError(&hcan2); + 8000cd2: 4814 ldr r0, [pc, #80] @ (8000d24 ) + 8000cd4: f001 f9b2 bl 800203c + 8000cd8: 4603 mov r3, r0 + 8000cda: 2b01 cmp r3, #1 + 8000cdc: d003 beq.n 8000ce6 + 8000cde: 4811 ldr r0, [pc, #68] @ (8000d24 ) + 8000ce0: f001 f9d4 bl 800208c + 8000ce4: 6038 str r0, [r7, #0] + + // TODO: write error to SD and/or serial + + HAL_GPIO_WritePin(led_can1.port, led_can1.pin, GPIO_PIN_RESET); + 8000ce6: 4b10 ldr r3, [pc, #64] @ (8000d28 ) + 8000ce8: 681b ldr r3, [r3, #0] + 8000cea: 4a0f ldr r2, [pc, #60] @ (8000d28 ) + 8000cec: 8891 ldrh r1, [r2, #4] + 8000cee: 2200 movs r2, #0 + 8000cf0: 4618 mov r0, r3 + 8000cf2: f002 fa35 bl 8003160 + HAL_GPIO_WritePin(led_can2.port, led_can2.pin, GPIO_PIN_RESET); + 8000cf6: 4b0d ldr r3, [pc, #52] @ (8000d2c ) + 8000cf8: 681b ldr r3, [r3, #0] + 8000cfa: 4a0c ldr r2, [pc, #48] @ (8000d2c ) + 8000cfc: 8891 ldrh r1, [r2, #4] + 8000cfe: 2200 movs r2, #0 + 8000d00: 4618 mov r0, r3 + 8000d02: f002 fa2d bl 8003160 + + while (1) + { + HAL_GPIO_TogglePin(led_error.port, led_error.pin); + 8000d06: 4b0a ldr r3, [pc, #40] @ (8000d30 ) + 8000d08: 681b ldr r3, [r3, #0] + 8000d0a: 4a09 ldr r2, [pc, #36] @ (8000d30 ) + 8000d0c: 8892 ldrh r2, [r2, #4] + 8000d0e: 4611 mov r1, r2 + 8000d10: 4618 mov r0, r3 + 8000d12: f002 fa51 bl 80031b8 + HAL_Delay(250); + 8000d16: 20fa movs r0, #250 @ 0xfa + 8000d18: f000 fb9a bl 8001450 + HAL_GPIO_TogglePin(led_error.port, led_error.pin); + 8000d1c: bf00 nop + 8000d1e: e7f2 b.n 8000d06 + 8000d20: 20000094 .word 0x20000094 + 8000d24: 200000f8 .word 0x200000f8 + 8000d28: 20000000 .word 0x20000000 + 8000d2c: 20000008 .word 0x20000008 + 8000d30: 20000010 .word 0x20000010 + +08000d34 : * @param file: pointer to the source file name * @param line: assert_param error line source number * @retval None */ void assert_failed(uint8_t *file, uint32_t line) { - 8000848: b480 push {r7} - 800084a: b083 sub sp, #12 - 800084c: af00 add r7, sp, #0 - 800084e: 6078 str r0, [r7, #4] - 8000850: 6039 str r1, [r7, #0] + 8000d34: b480 push {r7} + 8000d36: b083 sub sp, #12 + 8000d38: af00 add r7, sp, #0 + 8000d3a: 6078 str r0, [r7, #4] + 8000d3c: 6039 str r1, [r7, #0] /* USER CODE BEGIN 6 */ /* User can add his own implementation to report the file name and line number, ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ /* USER CODE END 6 */ } - 8000852: bf00 nop - 8000854: 370c adds r7, #12 - 8000856: 46bd mov sp, r7 - 8000858: f85d 7b04 ldr.w r7, [sp], #4 - 800085c: 4770 bx lr + 8000d3e: bf00 nop + 8000d40: 370c adds r7, #12 + 8000d42: 46bd mov sp, r7 + 8000d44: f85d 7b04 ldr.w r7, [sp], #4 + 8000d48: 4770 bx lr ... -08000860 : +08000d4c : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { - 8000860: b580 push {r7, lr} - 8000862: b082 sub sp, #8 - 8000864: af00 add r7, sp, #0 + 8000d4c: b580 push {r7, lr} + 8000d4e: b082 sub sp, #8 + 8000d50: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); - 8000866: 2300 movs r3, #0 - 8000868: 607b str r3, [r7, #4] - 800086a: 4b12 ldr r3, [pc, #72] @ (80008b4 ) - 800086c: 6c5b ldr r3, [r3, #68] @ 0x44 - 800086e: 4a11 ldr r2, [pc, #68] @ (80008b4 ) - 8000870: f443 4380 orr.w r3, r3, #16384 @ 0x4000 - 8000874: 6453 str r3, [r2, #68] @ 0x44 - 8000876: 4b0f ldr r3, [pc, #60] @ (80008b4 ) - 8000878: 6c5b ldr r3, [r3, #68] @ 0x44 - 800087a: f403 4380 and.w r3, r3, #16384 @ 0x4000 - 800087e: 607b str r3, [r7, #4] - 8000880: 687b ldr r3, [r7, #4] + 8000d52: 2300 movs r3, #0 + 8000d54: 607b str r3, [r7, #4] + 8000d56: 4b12 ldr r3, [pc, #72] @ (8000da0 ) + 8000d58: 6c5b ldr r3, [r3, #68] @ 0x44 + 8000d5a: 4a11 ldr r2, [pc, #68] @ (8000da0 ) + 8000d5c: f443 4380 orr.w r3, r3, #16384 @ 0x4000 + 8000d60: 6453 str r3, [r2, #68] @ 0x44 + 8000d62: 4b0f ldr r3, [pc, #60] @ (8000da0 ) + 8000d64: 6c5b ldr r3, [r3, #68] @ 0x44 + 8000d66: f403 4380 and.w r3, r3, #16384 @ 0x4000 + 8000d6a: 607b str r3, [r7, #4] + 8000d6c: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); - 8000882: 2300 movs r3, #0 - 8000884: 603b str r3, [r7, #0] - 8000886: 4b0b ldr r3, [pc, #44] @ (80008b4 ) - 8000888: 6c1b ldr r3, [r3, #64] @ 0x40 - 800088a: 4a0a ldr r2, [pc, #40] @ (80008b4 ) - 800088c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 - 8000890: 6413 str r3, [r2, #64] @ 0x40 - 8000892: 4b08 ldr r3, [pc, #32] @ (80008b4 ) - 8000894: 6c1b ldr r3, [r3, #64] @ 0x40 - 8000896: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 800089a: 603b str r3, [r7, #0] - 800089c: 683b ldr r3, [r7, #0] + 8000d6e: 2300 movs r3, #0 + 8000d70: 603b str r3, [r7, #0] + 8000d72: 4b0b ldr r3, [pc, #44] @ (8000da0 ) + 8000d74: 6c1b ldr r3, [r3, #64] @ 0x40 + 8000d76: 4a0a ldr r2, [pc, #40] @ (8000da0 ) + 8000d78: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8000d7c: 6413 str r3, [r2, #64] @ 0x40 + 8000d7e: 4b08 ldr r3, [pc, #32] @ (8000da0 ) + 8000d80: 6c1b ldr r3, [r3, #64] @ 0x40 + 8000d82: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8000d86: 603b str r3, [r7, #0] + 8000d88: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* PendSV_IRQn interrupt configuration */ HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); - 800089e: 2200 movs r2, #0 - 80008a0: 210f movs r1, #15 - 80008a2: f06f 0001 mvn.w r0, #1 - 80008a6: f000 fe09 bl 80014bc + 8000d8a: 2200 movs r2, #0 + 8000d8c: 210f movs r1, #15 + 8000d8e: f06f 0001 mvn.w r0, #1 + 8000d92: f001 fa55 bl 8002240 /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } - 80008aa: bf00 nop - 80008ac: 3708 adds r7, #8 - 80008ae: 46bd mov sp, r7 - 80008b0: bd80 pop {r7, pc} - 80008b2: bf00 nop - 80008b4: 40023800 .word 0x40023800 + 8000d96: bf00 nop + 8000d98: 3708 adds r7, #8 + 8000d9a: 46bd mov sp, r7 + 8000d9c: bd80 pop {r7, pc} + 8000d9e: bf00 nop + 8000da0: 40023800 .word 0x40023800 -080008b8 : +08000da4 : * This function configures the hardware resources used in this example * @param hcan: CAN handle pointer * @retval None */ void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) { - 80008b8: b580 push {r7, lr} - 80008ba: b08c sub sp, #48 @ 0x30 - 80008bc: af00 add r7, sp, #0 - 80008be: 6078 str r0, [r7, #4] + 8000da4: b580 push {r7, lr} + 8000da6: b08c sub sp, #48 @ 0x30 + 8000da8: af00 add r7, sp, #0 + 8000daa: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; - 80008c0: f107 031c add.w r3, r7, #28 - 80008c4: 2200 movs r2, #0 - 80008c6: 601a str r2, [r3, #0] - 80008c8: 605a str r2, [r3, #4] - 80008ca: 609a str r2, [r3, #8] - 80008cc: 60da str r2, [r3, #12] - 80008ce: 611a str r2, [r3, #16] + 8000dac: f107 031c add.w r3, r7, #28 + 8000db0: 2200 movs r2, #0 + 8000db2: 601a str r2, [r3, #0] + 8000db4: 605a str r2, [r3, #4] + 8000db6: 609a str r2, [r3, #8] + 8000db8: 60da str r2, [r3, #12] + 8000dba: 611a str r2, [r3, #16] if(hcan->Instance==CAN1) - 80008d0: 687b ldr r3, [r7, #4] - 80008d2: 681b ldr r3, [r3, #0] - 80008d4: 4a43 ldr r2, [pc, #268] @ (80009e4 ) - 80008d6: 4293 cmp r3, r2 - 80008d8: d136 bne.n 8000948 + 8000dbc: 687b ldr r3, [r7, #4] + 8000dbe: 681b ldr r3, [r3, #0] + 8000dc0: 4a43 ldr r2, [pc, #268] @ (8000ed0 ) + 8000dc2: 4293 cmp r3, r2 + 8000dc4: d136 bne.n 8000e34 { /* USER CODE BEGIN CAN1_MspInit 0 */ /* USER CODE END CAN1_MspInit 0 */ /* Peripheral clock enable */ HAL_RCC_CAN1_CLK_ENABLED++; - 80008da: 4b43 ldr r3, [pc, #268] @ (80009e8 ) - 80008dc: 681b ldr r3, [r3, #0] - 80008de: 3301 adds r3, #1 - 80008e0: 4a41 ldr r2, [pc, #260] @ (80009e8 ) - 80008e2: 6013 str r3, [r2, #0] + 8000dc6: 4b43 ldr r3, [pc, #268] @ (8000ed4 ) + 8000dc8: 681b ldr r3, [r3, #0] + 8000dca: 3301 adds r3, #1 + 8000dcc: 4a41 ldr r2, [pc, #260] @ (8000ed4 ) + 8000dce: 6013 str r3, [r2, #0] if(HAL_RCC_CAN1_CLK_ENABLED==1){ - 80008e4: 4b40 ldr r3, [pc, #256] @ (80009e8 ) - 80008e6: 681b ldr r3, [r3, #0] - 80008e8: 2b01 cmp r3, #1 - 80008ea: d10d bne.n 8000908 + 8000dd0: 4b40 ldr r3, [pc, #256] @ (8000ed4 ) + 8000dd2: 681b ldr r3, [r3, #0] + 8000dd4: 2b01 cmp r3, #1 + 8000dd6: d10d bne.n 8000df4 __HAL_RCC_CAN1_CLK_ENABLE(); - 80008ec: 2300 movs r3, #0 - 80008ee: 61bb str r3, [r7, #24] - 80008f0: 4b3e ldr r3, [pc, #248] @ (80009ec ) - 80008f2: 6c1b ldr r3, [r3, #64] @ 0x40 - 80008f4: 4a3d ldr r2, [pc, #244] @ (80009ec ) - 80008f6: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 - 80008fa: 6413 str r3, [r2, #64] @ 0x40 - 80008fc: 4b3b ldr r3, [pc, #236] @ (80009ec ) - 80008fe: 6c1b ldr r3, [r3, #64] @ 0x40 - 8000900: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 - 8000904: 61bb str r3, [r7, #24] - 8000906: 69bb ldr r3, [r7, #24] + 8000dd8: 2300 movs r3, #0 + 8000dda: 61bb str r3, [r7, #24] + 8000ddc: 4b3e ldr r3, [pc, #248] @ (8000ed8 ) + 8000dde: 6c1b ldr r3, [r3, #64] @ 0x40 + 8000de0: 4a3d ldr r2, [pc, #244] @ (8000ed8 ) + 8000de2: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 + 8000de6: 6413 str r3, [r2, #64] @ 0x40 + 8000de8: 4b3b ldr r3, [pc, #236] @ (8000ed8 ) + 8000dea: 6c1b ldr r3, [r3, #64] @ 0x40 + 8000dec: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8000df0: 61bb str r3, [r7, #24] + 8000df2: 69bb ldr r3, [r7, #24] } __HAL_RCC_GPIOB_CLK_ENABLE(); - 8000908: 2300 movs r3, #0 - 800090a: 617b str r3, [r7, #20] - 800090c: 4b37 ldr r3, [pc, #220] @ (80009ec ) - 800090e: 6b1b ldr r3, [r3, #48] @ 0x30 - 8000910: 4a36 ldr r2, [pc, #216] @ (80009ec ) - 8000912: f043 0302 orr.w r3, r3, #2 - 8000916: 6313 str r3, [r2, #48] @ 0x30 - 8000918: 4b34 ldr r3, [pc, #208] @ (80009ec ) - 800091a: 6b1b ldr r3, [r3, #48] @ 0x30 - 800091c: f003 0302 and.w r3, r3, #2 - 8000920: 617b str r3, [r7, #20] - 8000922: 697b ldr r3, [r7, #20] + 8000df4: 2300 movs r3, #0 + 8000df6: 617b str r3, [r7, #20] + 8000df8: 4b37 ldr r3, [pc, #220] @ (8000ed8 ) + 8000dfa: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000dfc: 4a36 ldr r2, [pc, #216] @ (8000ed8 ) + 8000dfe: f043 0302 orr.w r3, r3, #2 + 8000e02: 6313 str r3, [r2, #48] @ 0x30 + 8000e04: 4b34 ldr r3, [pc, #208] @ (8000ed8 ) + 8000e06: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000e08: f003 0302 and.w r3, r3, #2 + 8000e0c: 617b str r3, [r7, #20] + 8000e0e: 697b ldr r3, [r7, #20] /**CAN1 GPIO Configuration PB8 ------> CAN1_RX PB9 ------> CAN1_TX */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; - 8000924: f44f 7340 mov.w r3, #768 @ 0x300 - 8000928: 61fb str r3, [r7, #28] + 8000e10: f44f 7340 mov.w r3, #768 @ 0x300 + 8000e14: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - 800092a: 2302 movs r3, #2 - 800092c: 623b str r3, [r7, #32] + 8000e16: 2302 movs r3, #2 + 8000e18: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; - 800092e: 2300 movs r3, #0 - 8000930: 627b str r3, [r7, #36] @ 0x24 + 8000e1a: 2300 movs r3, #0 + 8000e1c: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - 8000932: 2303 movs r3, #3 - 8000934: 62bb str r3, [r7, #40] @ 0x28 + 8000e1e: 2303 movs r3, #3 + 8000e20: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Alternate = GPIO_AF9_CAN1; - 8000936: 2309 movs r3, #9 - 8000938: 62fb str r3, [r7, #44] @ 0x2c + 8000e22: 2309 movs r3, #9 + 8000e24: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - 800093a: f107 031c add.w r3, r7, #28 - 800093e: 4619 mov r1, r3 - 8000940: 482b ldr r0, [pc, #172] @ (80009f0 ) - 8000942: f000 fdff bl 8001544 + 8000e26: f107 031c add.w r3, r7, #28 + 8000e2a: 4619 mov r1, r3 + 8000e2c: 482b ldr r0, [pc, #172] @ (8000edc ) + 8000e2e: f001 fec3 bl 8002bb8 /* USER CODE BEGIN CAN2_MspInit 1 */ /* USER CODE END CAN2_MspInit 1 */ } } - 8000946: e048 b.n 80009da + 8000e32: e048 b.n 8000ec6 else if(hcan->Instance==CAN2) - 8000948: 687b ldr r3, [r7, #4] - 800094a: 681b ldr r3, [r3, #0] - 800094c: 4a29 ldr r2, [pc, #164] @ (80009f4 ) - 800094e: 4293 cmp r3, r2 - 8000950: d143 bne.n 80009da + 8000e34: 687b ldr r3, [r7, #4] + 8000e36: 681b ldr r3, [r3, #0] + 8000e38: 4a29 ldr r2, [pc, #164] @ (8000ee0 ) + 8000e3a: 4293 cmp r3, r2 + 8000e3c: d143 bne.n 8000ec6 __HAL_RCC_CAN2_CLK_ENABLE(); - 8000952: 2300 movs r3, #0 - 8000954: 613b str r3, [r7, #16] - 8000956: 4b25 ldr r3, [pc, #148] @ (80009ec ) - 8000958: 6c1b ldr r3, [r3, #64] @ 0x40 - 800095a: 4a24 ldr r2, [pc, #144] @ (80009ec ) - 800095c: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 - 8000960: 6413 str r3, [r2, #64] @ 0x40 - 8000962: 4b22 ldr r3, [pc, #136] @ (80009ec ) - 8000964: 6c1b ldr r3, [r3, #64] @ 0x40 - 8000966: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 - 800096a: 613b str r3, [r7, #16] - 800096c: 693b ldr r3, [r7, #16] + 8000e3e: 2300 movs r3, #0 + 8000e40: 613b str r3, [r7, #16] + 8000e42: 4b25 ldr r3, [pc, #148] @ (8000ed8 ) + 8000e44: 6c1b ldr r3, [r3, #64] @ 0x40 + 8000e46: 4a24 ldr r2, [pc, #144] @ (8000ed8 ) + 8000e48: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 + 8000e4c: 6413 str r3, [r2, #64] @ 0x40 + 8000e4e: 4b22 ldr r3, [pc, #136] @ (8000ed8 ) + 8000e50: 6c1b ldr r3, [r3, #64] @ 0x40 + 8000e52: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 + 8000e56: 613b str r3, [r7, #16] + 8000e58: 693b ldr r3, [r7, #16] HAL_RCC_CAN1_CLK_ENABLED++; - 800096e: 4b1e ldr r3, [pc, #120] @ (80009e8 ) - 8000970: 681b ldr r3, [r3, #0] - 8000972: 3301 adds r3, #1 - 8000974: 4a1c ldr r2, [pc, #112] @ (80009e8 ) - 8000976: 6013 str r3, [r2, #0] + 8000e5a: 4b1e ldr r3, [pc, #120] @ (8000ed4 ) + 8000e5c: 681b ldr r3, [r3, #0] + 8000e5e: 3301 adds r3, #1 + 8000e60: 4a1c ldr r2, [pc, #112] @ (8000ed4 ) + 8000e62: 6013 str r3, [r2, #0] if(HAL_RCC_CAN1_CLK_ENABLED==1){ - 8000978: 4b1b ldr r3, [pc, #108] @ (80009e8 ) - 800097a: 681b ldr r3, [r3, #0] - 800097c: 2b01 cmp r3, #1 - 800097e: d10d bne.n 800099c + 8000e64: 4b1b ldr r3, [pc, #108] @ (8000ed4 ) + 8000e66: 681b ldr r3, [r3, #0] + 8000e68: 2b01 cmp r3, #1 + 8000e6a: d10d bne.n 8000e88 __HAL_RCC_CAN1_CLK_ENABLE(); - 8000980: 2300 movs r3, #0 - 8000982: 60fb str r3, [r7, #12] - 8000984: 4b19 ldr r3, [pc, #100] @ (80009ec ) - 8000986: 6c1b ldr r3, [r3, #64] @ 0x40 - 8000988: 4a18 ldr r2, [pc, #96] @ (80009ec ) - 800098a: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 - 800098e: 6413 str r3, [r2, #64] @ 0x40 - 8000990: 4b16 ldr r3, [pc, #88] @ (80009ec ) - 8000992: 6c1b ldr r3, [r3, #64] @ 0x40 - 8000994: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 - 8000998: 60fb str r3, [r7, #12] - 800099a: 68fb ldr r3, [r7, #12] + 8000e6c: 2300 movs r3, #0 + 8000e6e: 60fb str r3, [r7, #12] + 8000e70: 4b19 ldr r3, [pc, #100] @ (8000ed8 ) + 8000e72: 6c1b ldr r3, [r3, #64] @ 0x40 + 8000e74: 4a18 ldr r2, [pc, #96] @ (8000ed8 ) + 8000e76: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 + 8000e7a: 6413 str r3, [r2, #64] @ 0x40 + 8000e7c: 4b16 ldr r3, [pc, #88] @ (8000ed8 ) + 8000e7e: 6c1b ldr r3, [r3, #64] @ 0x40 + 8000e80: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8000e84: 60fb str r3, [r7, #12] + 8000e86: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); - 800099c: 2300 movs r3, #0 - 800099e: 60bb str r3, [r7, #8] - 80009a0: 4b12 ldr r3, [pc, #72] @ (80009ec ) - 80009a2: 6b1b ldr r3, [r3, #48] @ 0x30 - 80009a4: 4a11 ldr r2, [pc, #68] @ (80009ec ) - 80009a6: f043 0302 orr.w r3, r3, #2 - 80009aa: 6313 str r3, [r2, #48] @ 0x30 - 80009ac: 4b0f ldr r3, [pc, #60] @ (80009ec ) - 80009ae: 6b1b ldr r3, [r3, #48] @ 0x30 - 80009b0: f003 0302 and.w r3, r3, #2 - 80009b4: 60bb str r3, [r7, #8] - 80009b6: 68bb ldr r3, [r7, #8] + 8000e88: 2300 movs r3, #0 + 8000e8a: 60bb str r3, [r7, #8] + 8000e8c: 4b12 ldr r3, [pc, #72] @ (8000ed8 ) + 8000e8e: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000e90: 4a11 ldr r2, [pc, #68] @ (8000ed8 ) + 8000e92: f043 0302 orr.w r3, r3, #2 + 8000e96: 6313 str r3, [r2, #48] @ 0x30 + 8000e98: 4b0f ldr r3, [pc, #60] @ (8000ed8 ) + 8000e9a: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000e9c: f003 0302 and.w r3, r3, #2 + 8000ea0: 60bb str r3, [r7, #8] + 8000ea2: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13; - 80009b8: f44f 5340 mov.w r3, #12288 @ 0x3000 - 80009bc: 61fb str r3, [r7, #28] + 8000ea4: f44f 5340 mov.w r3, #12288 @ 0x3000 + 8000ea8: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - 80009be: 2302 movs r3, #2 - 80009c0: 623b str r3, [r7, #32] + 8000eaa: 2302 movs r3, #2 + 8000eac: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; - 80009c2: 2300 movs r3, #0 - 80009c4: 627b str r3, [r7, #36] @ 0x24 + 8000eae: 2300 movs r3, #0 + 8000eb0: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - 80009c6: 2303 movs r3, #3 - 80009c8: 62bb str r3, [r7, #40] @ 0x28 + 8000eb2: 2303 movs r3, #3 + 8000eb4: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Alternate = GPIO_AF9_CAN2; - 80009ca: 2309 movs r3, #9 - 80009cc: 62fb str r3, [r7, #44] @ 0x2c + 8000eb6: 2309 movs r3, #9 + 8000eb8: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - 80009ce: f107 031c add.w r3, r7, #28 - 80009d2: 4619 mov r1, r3 - 80009d4: 4806 ldr r0, [pc, #24] @ (80009f0 ) - 80009d6: f000 fdb5 bl 8001544 + 8000eba: f107 031c add.w r3, r7, #28 + 8000ebe: 4619 mov r1, r3 + 8000ec0: 4806 ldr r0, [pc, #24] @ (8000edc ) + 8000ec2: f001 fe79 bl 8002bb8 } - 80009da: bf00 nop - 80009dc: 3730 adds r7, #48 @ 0x30 - 80009de: 46bd mov sp, r7 - 80009e0: bd80 pop {r7, pc} - 80009e2: bf00 nop - 80009e4: 40006400 .word 0x40006400 - 80009e8: 20000148 .word 0x20000148 - 80009ec: 40023800 .word 0x40023800 - 80009f0: 40020400 .word 0x40020400 - 80009f4: 40006800 .word 0x40006800 + 8000ec6: bf00 nop + 8000ec8: 3730 adds r7, #48 @ 0x30 + 8000eca: 46bd mov sp, r7 + 8000ecc: bd80 pop {r7, pc} + 8000ece: bf00 nop + 8000ed0: 40006400 .word 0x40006400 + 8000ed4: 200002d0 .word 0x200002d0 + 8000ed8: 40023800 .word 0x40023800 + 8000edc: 40020400 .word 0x40020400 + 8000ee0: 40006800 .word 0x40006800 -080009f8 : +08000ee4 : + * This function configures the hardware resources used in this example + * @param hsd: SD handle pointer + * @retval None + */ +void HAL_SD_MspInit(SD_HandleTypeDef* hsd) +{ + 8000ee4: b580 push {r7, lr} + 8000ee6: b08a sub sp, #40 @ 0x28 + 8000ee8: af00 add r7, sp, #0 + 8000eea: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000eec: f107 0314 add.w r3, r7, #20 + 8000ef0: 2200 movs r2, #0 + 8000ef2: 601a str r2, [r3, #0] + 8000ef4: 605a str r2, [r3, #4] + 8000ef6: 609a str r2, [r3, #8] + 8000ef8: 60da str r2, [r3, #12] + 8000efa: 611a str r2, [r3, #16] + if(hsd->Instance==SDIO) + 8000efc: 687b ldr r3, [r7, #4] + 8000efe: 681b ldr r3, [r3, #0] + 8000f00: 4a68 ldr r2, [pc, #416] @ (80010a4 ) + 8000f02: 4293 cmp r3, r2 + 8000f04: f040 80c9 bne.w 800109a + { + /* USER CODE BEGIN SDIO_MspInit 0 */ + + /* USER CODE END SDIO_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SDIO_CLK_ENABLE(); + 8000f08: 2300 movs r3, #0 + 8000f0a: 613b str r3, [r7, #16] + 8000f0c: 4b66 ldr r3, [pc, #408] @ (80010a8 ) + 8000f0e: 6c5b ldr r3, [r3, #68] @ 0x44 + 8000f10: 4a65 ldr r2, [pc, #404] @ (80010a8 ) + 8000f12: f443 6300 orr.w r3, r3, #2048 @ 0x800 + 8000f16: 6453 str r3, [r2, #68] @ 0x44 + 8000f18: 4b63 ldr r3, [pc, #396] @ (80010a8 ) + 8000f1a: 6c5b ldr r3, [r3, #68] @ 0x44 + 8000f1c: f403 6300 and.w r3, r3, #2048 @ 0x800 + 8000f20: 613b str r3, [r7, #16] + 8000f22: 693b ldr r3, [r7, #16] + + __HAL_RCC_GPIOC_CLK_ENABLE(); + 8000f24: 2300 movs r3, #0 + 8000f26: 60fb str r3, [r7, #12] + 8000f28: 4b5f ldr r3, [pc, #380] @ (80010a8 ) + 8000f2a: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000f2c: 4a5e ldr r2, [pc, #376] @ (80010a8 ) + 8000f2e: f043 0304 orr.w r3, r3, #4 + 8000f32: 6313 str r3, [r2, #48] @ 0x30 + 8000f34: 4b5c ldr r3, [pc, #368] @ (80010a8 ) + 8000f36: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000f38: f003 0304 and.w r3, r3, #4 + 8000f3c: 60fb str r3, [r7, #12] + 8000f3e: 68fb ldr r3, [r7, #12] + __HAL_RCC_GPIOD_CLK_ENABLE(); + 8000f40: 2300 movs r3, #0 + 8000f42: 60bb str r3, [r7, #8] + 8000f44: 4b58 ldr r3, [pc, #352] @ (80010a8 ) + 8000f46: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000f48: 4a57 ldr r2, [pc, #348] @ (80010a8 ) + 8000f4a: f043 0308 orr.w r3, r3, #8 + 8000f4e: 6313 str r3, [r2, #48] @ 0x30 + 8000f50: 4b55 ldr r3, [pc, #340] @ (80010a8 ) + 8000f52: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000f54: f003 0308 and.w r3, r3, #8 + 8000f58: 60bb str r3, [r7, #8] + 8000f5a: 68bb ldr r3, [r7, #8] + PC10 ------> SDIO_D2 + PC11 ------> SDIO_D3 + PC12 ------> SDIO_CK + PD2 ------> SDIO_CMD + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + 8000f5c: f44f 53f8 mov.w r3, #7936 @ 0x1f00 + 8000f60: 617b str r3, [r7, #20] + |GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8000f62: 2302 movs r3, #2 + 8000f64: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000f66: 2300 movs r3, #0 + 8000f68: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8000f6a: 2303 movs r3, #3 + 8000f6c: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF12_SDIO; + 8000f6e: 230c movs r3, #12 + 8000f70: 627b str r3, [r7, #36] @ 0x24 + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 8000f72: f107 0314 add.w r3, r7, #20 + 8000f76: 4619 mov r1, r3 + 8000f78: 484c ldr r0, [pc, #304] @ (80010ac ) + 8000f7a: f001 fe1d bl 8002bb8 + + GPIO_InitStruct.Pin = GPIO_PIN_2; + 8000f7e: 2304 movs r3, #4 + 8000f80: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8000f82: 2302 movs r3, #2 + 8000f84: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000f86: 2300 movs r3, #0 + 8000f88: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8000f8a: 2303 movs r3, #3 + 8000f8c: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF12_SDIO; + 8000f8e: 230c movs r3, #12 + 8000f90: 627b str r3, [r7, #36] @ 0x24 + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + 8000f92: f107 0314 add.w r3, r7, #20 + 8000f96: 4619 mov r1, r3 + 8000f98: 4845 ldr r0, [pc, #276] @ (80010b0 ) + 8000f9a: f001 fe0d bl 8002bb8 + + /* SDIO DMA Init */ + /* SDIO_RX Init */ + hdma_sdio_rx.Instance = DMA2_Stream3; + 8000f9e: 4b45 ldr r3, [pc, #276] @ (80010b4 ) + 8000fa0: 4a45 ldr r2, [pc, #276] @ (80010b8 ) + 8000fa2: 601a str r2, [r3, #0] + hdma_sdio_rx.Init.Channel = DMA_CHANNEL_4; + 8000fa4: 4b43 ldr r3, [pc, #268] @ (80010b4 ) + 8000fa6: f04f 6200 mov.w r2, #134217728 @ 0x8000000 + 8000faa: 605a str r2, [r3, #4] + hdma_sdio_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + 8000fac: 4b41 ldr r3, [pc, #260] @ (80010b4 ) + 8000fae: 2200 movs r2, #0 + 8000fb0: 609a str r2, [r3, #8] + hdma_sdio_rx.Init.PeriphInc = DMA_PINC_DISABLE; + 8000fb2: 4b40 ldr r3, [pc, #256] @ (80010b4 ) + 8000fb4: 2200 movs r2, #0 + 8000fb6: 60da str r2, [r3, #12] + hdma_sdio_rx.Init.MemInc = DMA_MINC_ENABLE; + 8000fb8: 4b3e ldr r3, [pc, #248] @ (80010b4 ) + 8000fba: f44f 6280 mov.w r2, #1024 @ 0x400 + 8000fbe: 611a str r2, [r3, #16] + hdma_sdio_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + 8000fc0: 4b3c ldr r3, [pc, #240] @ (80010b4 ) + 8000fc2: f44f 5280 mov.w r2, #4096 @ 0x1000 + 8000fc6: 615a str r2, [r3, #20] + hdma_sdio_rx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + 8000fc8: 4b3a ldr r3, [pc, #232] @ (80010b4 ) + 8000fca: f44f 4280 mov.w r2, #16384 @ 0x4000 + 8000fce: 619a str r2, [r3, #24] + hdma_sdio_rx.Init.Mode = DMA_PFCTRL; + 8000fd0: 4b38 ldr r3, [pc, #224] @ (80010b4 ) + 8000fd2: 2220 movs r2, #32 + 8000fd4: 61da str r2, [r3, #28] + hdma_sdio_rx.Init.Priority = DMA_PRIORITY_LOW; + 8000fd6: 4b37 ldr r3, [pc, #220] @ (80010b4 ) + 8000fd8: 2200 movs r2, #0 + 8000fda: 621a str r2, [r3, #32] + hdma_sdio_rx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + 8000fdc: 4b35 ldr r3, [pc, #212] @ (80010b4 ) + 8000fde: 2204 movs r2, #4 + 8000fe0: 625a str r2, [r3, #36] @ 0x24 + hdma_sdio_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + 8000fe2: 4b34 ldr r3, [pc, #208] @ (80010b4 ) + 8000fe4: 2203 movs r2, #3 + 8000fe6: 629a str r2, [r3, #40] @ 0x28 + hdma_sdio_rx.Init.MemBurst = DMA_MBURST_INC4; + 8000fe8: 4b32 ldr r3, [pc, #200] @ (80010b4 ) + 8000fea: f44f 0200 mov.w r2, #8388608 @ 0x800000 + 8000fee: 62da str r2, [r3, #44] @ 0x2c + hdma_sdio_rx.Init.PeriphBurst = DMA_PBURST_INC4; + 8000ff0: 4b30 ldr r3, [pc, #192] @ (80010b4 ) + 8000ff2: f44f 1200 mov.w r2, #2097152 @ 0x200000 + 8000ff6: 631a str r2, [r3, #48] @ 0x30 + if (HAL_DMA_Init(&hdma_sdio_rx) != HAL_OK) + 8000ff8: 482e ldr r0, [pc, #184] @ (80010b4 ) + 8000ffa: f001 f965 bl 80022c8 + 8000ffe: 4603 mov r3, r0 + 8001000: 2b00 cmp r3, #0 + 8001002: d001 beq.n 8001008 + { + Error_Handler(); + 8001004: f7ff fe56 bl 8000cb4 + } + + __HAL_LINKDMA(hsd,hdmarx,hdma_sdio_rx); + 8001008: 687b ldr r3, [r7, #4] + 800100a: 4a2a ldr r2, [pc, #168] @ (80010b4 ) + 800100c: 641a str r2, [r3, #64] @ 0x40 + 800100e: 4a29 ldr r2, [pc, #164] @ (80010b4 ) + 8001010: 687b ldr r3, [r7, #4] + 8001012: 6393 str r3, [r2, #56] @ 0x38 + + /* SDIO_TX Init */ + hdma_sdio_tx.Instance = DMA2_Stream6; + 8001014: 4b29 ldr r3, [pc, #164] @ (80010bc ) + 8001016: 4a2a ldr r2, [pc, #168] @ (80010c0 ) + 8001018: 601a str r2, [r3, #0] + hdma_sdio_tx.Init.Channel = DMA_CHANNEL_4; + 800101a: 4b28 ldr r3, [pc, #160] @ (80010bc ) + 800101c: f04f 6200 mov.w r2, #134217728 @ 0x8000000 + 8001020: 605a str r2, [r3, #4] + hdma_sdio_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + 8001022: 4b26 ldr r3, [pc, #152] @ (80010bc ) + 8001024: 2240 movs r2, #64 @ 0x40 + 8001026: 609a str r2, [r3, #8] + hdma_sdio_tx.Init.PeriphInc = DMA_PINC_DISABLE; + 8001028: 4b24 ldr r3, [pc, #144] @ (80010bc ) + 800102a: 2200 movs r2, #0 + 800102c: 60da str r2, [r3, #12] + hdma_sdio_tx.Init.MemInc = DMA_MINC_ENABLE; + 800102e: 4b23 ldr r3, [pc, #140] @ (80010bc ) + 8001030: f44f 6280 mov.w r2, #1024 @ 0x400 + 8001034: 611a str r2, [r3, #16] + hdma_sdio_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + 8001036: 4b21 ldr r3, [pc, #132] @ (80010bc ) + 8001038: f44f 5280 mov.w r2, #4096 @ 0x1000 + 800103c: 615a str r2, [r3, #20] + hdma_sdio_tx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + 800103e: 4b1f ldr r3, [pc, #124] @ (80010bc ) + 8001040: f44f 4280 mov.w r2, #16384 @ 0x4000 + 8001044: 619a str r2, [r3, #24] + hdma_sdio_tx.Init.Mode = DMA_PFCTRL; + 8001046: 4b1d ldr r3, [pc, #116] @ (80010bc ) + 8001048: 2220 movs r2, #32 + 800104a: 61da str r2, [r3, #28] + hdma_sdio_tx.Init.Priority = DMA_PRIORITY_LOW; + 800104c: 4b1b ldr r3, [pc, #108] @ (80010bc ) + 800104e: 2200 movs r2, #0 + 8001050: 621a str r2, [r3, #32] + hdma_sdio_tx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + 8001052: 4b1a ldr r3, [pc, #104] @ (80010bc ) + 8001054: 2204 movs r2, #4 + 8001056: 625a str r2, [r3, #36] @ 0x24 + hdma_sdio_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + 8001058: 4b18 ldr r3, [pc, #96] @ (80010bc ) + 800105a: 2203 movs r2, #3 + 800105c: 629a str r2, [r3, #40] @ 0x28 + hdma_sdio_tx.Init.MemBurst = DMA_MBURST_INC4; + 800105e: 4b17 ldr r3, [pc, #92] @ (80010bc ) + 8001060: f44f 0200 mov.w r2, #8388608 @ 0x800000 + 8001064: 62da str r2, [r3, #44] @ 0x2c + hdma_sdio_tx.Init.PeriphBurst = DMA_PBURST_INC4; + 8001066: 4b15 ldr r3, [pc, #84] @ (80010bc ) + 8001068: f44f 1200 mov.w r2, #2097152 @ 0x200000 + 800106c: 631a str r2, [r3, #48] @ 0x30 + if (HAL_DMA_Init(&hdma_sdio_tx) != HAL_OK) + 800106e: 4813 ldr r0, [pc, #76] @ (80010bc ) + 8001070: f001 f92a bl 80022c8 + 8001074: 4603 mov r3, r0 + 8001076: 2b00 cmp r3, #0 + 8001078: d001 beq.n 800107e + { + Error_Handler(); + 800107a: f7ff fe1b bl 8000cb4 + } + + __HAL_LINKDMA(hsd,hdmatx,hdma_sdio_tx); + 800107e: 687b ldr r3, [r7, #4] + 8001080: 4a0e ldr r2, [pc, #56] @ (80010bc ) + 8001082: 63da str r2, [r3, #60] @ 0x3c + 8001084: 4a0d ldr r2, [pc, #52] @ (80010bc ) + 8001086: 687b ldr r3, [r7, #4] + 8001088: 6393 str r3, [r2, #56] @ 0x38 + + /* SDIO interrupt Init */ + HAL_NVIC_SetPriority(SDIO_IRQn, 5, 0); + 800108a: 2200 movs r2, #0 + 800108c: 2105 movs r1, #5 + 800108e: 2031 movs r0, #49 @ 0x31 + 8001090: f001 f8d6 bl 8002240 + HAL_NVIC_EnableIRQ(SDIO_IRQn); + 8001094: 2031 movs r0, #49 @ 0x31 + 8001096: f001 f8ff bl 8002298 + + /* USER CODE END SDIO_MspInit 1 */ + + } + +} + 800109a: bf00 nop + 800109c: 3728 adds r7, #40 @ 0x28 + 800109e: 46bd mov sp, r7 + 80010a0: bd80 pop {r7, pc} + 80010a2: bf00 nop + 80010a4: 40012c00 .word 0x40012c00 + 80010a8: 40023800 .word 0x40023800 + 80010ac: 40020800 .word 0x40020800 + 80010b0: 40020c00 .word 0x40020c00 + 80010b4: 200001e0 .word 0x200001e0 + 80010b8: 40026458 .word 0x40026458 + 80010bc: 20000240 .word 0x20000240 + 80010c0: 400264a0 .word 0x400264a0 + +080010c4 : * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). * @param TickPriority: Tick interrupt priority. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { - 80009f8: b580 push {r7, lr} - 80009fa: b08e sub sp, #56 @ 0x38 - 80009fc: af00 add r7, sp, #0 - 80009fe: 6078 str r0, [r7, #4] + 80010c4: b580 push {r7, lr} + 80010c6: b08e sub sp, #56 @ 0x38 + 80010c8: af00 add r7, sp, #0 + 80010ca: 6078 str r0, [r7, #4] RCC_ClkInitTypeDef clkconfig; uint32_t uwTimclock, uwAPB1Prescaler = 0U; - 8000a00: 2300 movs r3, #0 - 8000a02: 62fb str r3, [r7, #44] @ 0x2c + 80010cc: 2300 movs r3, #0 + 80010ce: 62fb str r3, [r7, #44] @ 0x2c uint32_t uwPrescalerValue = 0U; - 8000a04: 2300 movs r3, #0 - 8000a06: 62bb str r3, [r7, #40] @ 0x28 + 80010d0: 2300 movs r3, #0 + 80010d2: 62bb str r3, [r7, #40] @ 0x28 uint32_t pFLatency; HAL_StatusTypeDef status; /* Enable TIM6 clock */ __HAL_RCC_TIM6_CLK_ENABLE(); - 8000a08: 2300 movs r3, #0 - 8000a0a: 60fb str r3, [r7, #12] - 8000a0c: 4b33 ldr r3, [pc, #204] @ (8000adc ) - 8000a0e: 6c1b ldr r3, [r3, #64] @ 0x40 - 8000a10: 4a32 ldr r2, [pc, #200] @ (8000adc ) - 8000a12: f043 0310 orr.w r3, r3, #16 - 8000a16: 6413 str r3, [r2, #64] @ 0x40 - 8000a18: 4b30 ldr r3, [pc, #192] @ (8000adc ) - 8000a1a: 6c1b ldr r3, [r3, #64] @ 0x40 - 8000a1c: f003 0310 and.w r3, r3, #16 - 8000a20: 60fb str r3, [r7, #12] - 8000a22: 68fb ldr r3, [r7, #12] + 80010d4: 2300 movs r3, #0 + 80010d6: 60fb str r3, [r7, #12] + 80010d8: 4b33 ldr r3, [pc, #204] @ (80011a8 ) + 80010da: 6c1b ldr r3, [r3, #64] @ 0x40 + 80010dc: 4a32 ldr r2, [pc, #200] @ (80011a8 ) + 80010de: f043 0310 orr.w r3, r3, #16 + 80010e2: 6413 str r3, [r2, #64] @ 0x40 + 80010e4: 4b30 ldr r3, [pc, #192] @ (80011a8 ) + 80010e6: 6c1b ldr r3, [r3, #64] @ 0x40 + 80010e8: f003 0310 and.w r3, r3, #16 + 80010ec: 60fb str r3, [r7, #12] + 80010ee: 68fb ldr r3, [r7, #12] /* Get clock configuration */ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); - 8000a24: f107 0210 add.w r2, r7, #16 - 8000a28: f107 0314 add.w r3, r7, #20 - 8000a2c: 4611 mov r1, r2 - 8000a2e: 4618 mov r0, r3 - 8000a30: f001 fdfa bl 8002628 + 80010f0: f107 0210 add.w r2, r7, #16 + 80010f4: f107 0314 add.w r3, r7, #20 + 80010f8: 4611 mov r1, r2 + 80010fa: 4618 mov r0, r3 + 80010fc: f002 fe1c bl 8003d38 /* Get APB1 prescaler */ uwAPB1Prescaler = clkconfig.APB1CLKDivider; - 8000a34: 6a3b ldr r3, [r7, #32] - 8000a36: 62fb str r3, [r7, #44] @ 0x2c + 8001100: 6a3b ldr r3, [r7, #32] + 8001102: 62fb str r3, [r7, #44] @ 0x2c /* Compute TIM6 clock */ if (uwAPB1Prescaler == RCC_HCLK_DIV1) - 8000a38: 6afb ldr r3, [r7, #44] @ 0x2c - 8000a3a: 2b00 cmp r3, #0 - 8000a3c: d103 bne.n 8000a46 + 8001104: 6afb ldr r3, [r7, #44] @ 0x2c + 8001106: 2b00 cmp r3, #0 + 8001108: d103 bne.n 8001112 { uwTimclock = HAL_RCC_GetPCLK1Freq(); - 8000a3e: f001 fddf bl 8002600 - 8000a42: 6378 str r0, [r7, #52] @ 0x34 - 8000a44: e004 b.n 8000a50 + 800110a: f002 fe01 bl 8003d10 + 800110e: 6378 str r0, [r7, #52] @ 0x34 + 8001110: e004 b.n 800111c } else { uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq(); - 8000a46: f001 fddb bl 8002600 - 8000a4a: 4603 mov r3, r0 - 8000a4c: 005b lsls r3, r3, #1 - 8000a4e: 637b str r3, [r7, #52] @ 0x34 + 8001112: f002 fdfd bl 8003d10 + 8001116: 4603 mov r3, r0 + 8001118: 005b lsls r3, r3, #1 + 800111a: 637b str r3, [r7, #52] @ 0x34 } /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */ uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); - 8000a50: 6b7b ldr r3, [r7, #52] @ 0x34 - 8000a52: 4a23 ldr r2, [pc, #140] @ (8000ae0 ) - 8000a54: fba2 2303 umull r2, r3, r2, r3 - 8000a58: 0c9b lsrs r3, r3, #18 - 8000a5a: 3b01 subs r3, #1 - 8000a5c: 62bb str r3, [r7, #40] @ 0x28 + 800111c: 6b7b ldr r3, [r7, #52] @ 0x34 + 800111e: 4a23 ldr r2, [pc, #140] @ (80011ac ) + 8001120: fba2 2303 umull r2, r3, r2, r3 + 8001124: 0c9b lsrs r3, r3, #18 + 8001126: 3b01 subs r3, #1 + 8001128: 62bb str r3, [r7, #40] @ 0x28 /* Initialize TIM6 */ htim6.Instance = TIM6; - 8000a5e: 4b21 ldr r3, [pc, #132] @ (8000ae4 ) - 8000a60: 4a21 ldr r2, [pc, #132] @ (8000ae8 ) - 8000a62: 601a str r2, [r3, #0] + 800112a: 4b21 ldr r3, [pc, #132] @ (80011b0 ) + 800112c: 4a21 ldr r2, [pc, #132] @ (80011b4 ) + 800112e: 601a str r2, [r3, #0] * Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base. * Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. * ClockDivision = 0 * Counter direction = Up */ htim6.Init.Period = (1000000U / 1000U) - 1U; - 8000a64: 4b1f ldr r3, [pc, #124] @ (8000ae4 ) - 8000a66: f240 32e7 movw r2, #999 @ 0x3e7 - 8000a6a: 60da str r2, [r3, #12] + 8001130: 4b1f ldr r3, [pc, #124] @ (80011b0 ) + 8001132: f240 32e7 movw r2, #999 @ 0x3e7 + 8001136: 60da str r2, [r3, #12] htim6.Init.Prescaler = uwPrescalerValue; - 8000a6c: 4a1d ldr r2, [pc, #116] @ (8000ae4 ) - 8000a6e: 6abb ldr r3, [r7, #40] @ 0x28 - 8000a70: 6053 str r3, [r2, #4] + 8001138: 4a1d ldr r2, [pc, #116] @ (80011b0 ) + 800113a: 6abb ldr r3, [r7, #40] @ 0x28 + 800113c: 6053 str r3, [r2, #4] htim6.Init.ClockDivision = 0; - 8000a72: 4b1c ldr r3, [pc, #112] @ (8000ae4 ) - 8000a74: 2200 movs r2, #0 - 8000a76: 611a str r2, [r3, #16] + 800113e: 4b1c ldr r3, [pc, #112] @ (80011b0 ) + 8001140: 2200 movs r2, #0 + 8001142: 611a str r2, [r3, #16] htim6.Init.CounterMode = TIM_COUNTERMODE_UP; - 8000a78: 4b1a ldr r3, [pc, #104] @ (8000ae4 ) - 8000a7a: 2200 movs r2, #0 - 8000a7c: 609a str r2, [r3, #8] + 8001144: 4b1a ldr r3, [pc, #104] @ (80011b0 ) + 8001146: 2200 movs r2, #0 + 8001148: 609a str r2, [r3, #8] htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - 8000a7e: 4b19 ldr r3, [pc, #100] @ (8000ae4 ) - 8000a80: 2200 movs r2, #0 - 8000a82: 619a str r2, [r3, #24] + 800114a: 4b19 ldr r3, [pc, #100] @ (80011b0 ) + 800114c: 2200 movs r2, #0 + 800114e: 619a str r2, [r3, #24] status = HAL_TIM_Base_Init(&htim6); - 8000a84: 4817 ldr r0, [pc, #92] @ (8000ae4 ) - 8000a86: f001 fe01 bl 800268c - 8000a8a: 4603 mov r3, r0 - 8000a8c: f887 3033 strb.w r3, [r7, #51] @ 0x33 + 8001150: 4817 ldr r0, [pc, #92] @ (80011b0 ) + 8001152: f003 ff53 bl 8004ffc + 8001156: 4603 mov r3, r0 + 8001158: f887 3033 strb.w r3, [r7, #51] @ 0x33 if (status == HAL_OK) - 8000a90: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 - 8000a94: 2b00 cmp r3, #0 - 8000a96: d11b bne.n 8000ad0 + 800115c: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 + 8001160: 2b00 cmp r3, #0 + 8001162: d11b bne.n 800119c { /* Start the TIM time Base generation in interrupt mode */ status = HAL_TIM_Base_Start_IT(&htim6); - 8000a98: 4812 ldr r0, [pc, #72] @ (8000ae4 ) - 8000a9a: f001 ff1d bl 80028d8 - 8000a9e: 4603 mov r3, r0 - 8000aa0: f887 3033 strb.w r3, [r7, #51] @ 0x33 + 8001164: 4812 ldr r0, [pc, #72] @ (80011b0 ) + 8001166: f004 f86f bl 8005248 + 800116a: 4603 mov r3, r0 + 800116c: f887 3033 strb.w r3, [r7, #51] @ 0x33 if (status == HAL_OK) - 8000aa4: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 - 8000aa8: 2b00 cmp r3, #0 - 8000aaa: d111 bne.n 8000ad0 + 8001170: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 + 8001174: 2b00 cmp r3, #0 + 8001176: d111 bne.n 800119c { /* Enable the TIM6 global Interrupt */ HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); - 8000aac: 2036 movs r0, #54 @ 0x36 - 8000aae: f000 fd31 bl 8001514 + 8001178: 2036 movs r0, #54 @ 0x36 + 800117a: f001 f88d bl 8002298 /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) - 8000ab2: 687b ldr r3, [r7, #4] - 8000ab4: 2b0f cmp r3, #15 - 8000ab6: d808 bhi.n 8000aca + 800117e: 687b ldr r3, [r7, #4] + 8001180: 2b0f cmp r3, #15 + 8001182: d808 bhi.n 8001196 { /* Configure the TIM IRQ priority */ HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority, 0U); - 8000ab8: 2200 movs r2, #0 - 8000aba: 6879 ldr r1, [r7, #4] - 8000abc: 2036 movs r0, #54 @ 0x36 - 8000abe: f000 fcfd bl 80014bc + 8001184: 2200 movs r2, #0 + 8001186: 6879 ldr r1, [r7, #4] + 8001188: 2036 movs r0, #54 @ 0x36 + 800118a: f001 f859 bl 8002240 uwTickPrio = TickPriority; - 8000ac2: 4a0a ldr r2, [pc, #40] @ (8000aec ) - 8000ac4: 687b ldr r3, [r7, #4] - 8000ac6: 6013 str r3, [r2, #0] - 8000ac8: e002 b.n 8000ad0 + 800118e: 4a0a ldr r2, [pc, #40] @ (80011b8 ) + 8001190: 687b ldr r3, [r7, #4] + 8001192: 6013 str r3, [r2, #0] + 8001194: e002 b.n 800119c } else { status = HAL_ERROR; - 8000aca: 2301 movs r3, #1 - 8000acc: f887 3033 strb.w r3, [r7, #51] @ 0x33 + 8001196: 2301 movs r3, #1 + 8001198: f887 3033 strb.w r3, [r7, #51] @ 0x33 } } } /* Return function status */ return status; - 8000ad0: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 + 800119c: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 } - 8000ad4: 4618 mov r0, r3 - 8000ad6: 3738 adds r7, #56 @ 0x38 - 8000ad8: 46bd mov sp, r7 - 8000ada: bd80 pop {r7, pc} - 8000adc: 40023800 .word 0x40023800 - 8000ae0: 431bde83 .word 0x431bde83 - 8000ae4: 2000014c .word 0x2000014c - 8000ae8: 40001000 .word 0x40001000 - 8000aec: 20000004 .word 0x20000004 + 80011a0: 4618 mov r0, r3 + 80011a2: 3738 adds r7, #56 @ 0x38 + 80011a4: 46bd mov sp, r7 + 80011a6: bd80 pop {r7, pc} + 80011a8: 40023800 .word 0x40023800 + 80011ac: 431bde83 .word 0x431bde83 + 80011b0: 200002d4 .word 0x200002d4 + 80011b4: 40001000 .word 0x40001000 + 80011b8: 2000001c .word 0x2000001c -08000af0 : +080011bc : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { - 8000af0: b480 push {r7} - 8000af2: af00 add r7, sp, #0 + 80011bc: b480 push {r7} + 80011be: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) - 8000af4: bf00 nop - 8000af6: e7fd b.n 8000af4 + 80011c0: bf00 nop + 80011c2: e7fd b.n 80011c0 -08000af8 : +080011c4 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { - 8000af8: b480 push {r7} - 8000afa: af00 add r7, sp, #0 + 80011c4: b480 push {r7} + 80011c6: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) - 8000afc: bf00 nop - 8000afe: e7fd b.n 8000afc + 80011c8: bf00 nop + 80011ca: e7fd b.n 80011c8 -08000b00 : +080011cc : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { - 8000b00: b480 push {r7} - 8000b02: af00 add r7, sp, #0 + 80011cc: b480 push {r7} + 80011ce: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) - 8000b04: bf00 nop - 8000b06: e7fd b.n 8000b04 + 80011d0: bf00 nop + 80011d2: e7fd b.n 80011d0 -08000b08 : +080011d4 : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { - 8000b08: b480 push {r7} - 8000b0a: af00 add r7, sp, #0 + 80011d4: b480 push {r7} + 80011d6: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) - 8000b0c: bf00 nop - 8000b0e: e7fd b.n 8000b0c + 80011d8: bf00 nop + 80011da: e7fd b.n 80011d8 -08000b10 : +080011dc : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { - 8000b10: b480 push {r7} - 8000b12: af00 add r7, sp, #0 + 80011dc: b480 push {r7} + 80011de: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) - 8000b14: bf00 nop - 8000b16: e7fd b.n 8000b14 + 80011e0: bf00 nop + 80011e2: e7fd b.n 80011e0 -08000b18 : +080011e4 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { - 8000b18: b480 push {r7} - 8000b1a: af00 add r7, sp, #0 + 80011e4: b480 push {r7} + 80011e6: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } - 8000b1c: bf00 nop - 8000b1e: 46bd mov sp, r7 - 8000b20: f85d 7b04 ldr.w r7, [sp], #4 - 8000b24: 4770 bx lr + 80011e8: bf00 nop + 80011ea: 46bd mov sp, r7 + 80011ec: f85d 7b04 ldr.w r7, [sp], #4 + 80011f0: 4770 bx lr ... -08000b28 : +080011f4 : + +/** + * @brief This function handles SDIO global interrupt. + */ +void SDIO_IRQHandler(void) +{ + 80011f4: b580 push {r7, lr} + 80011f6: af00 add r7, sp, #0 + /* USER CODE BEGIN SDIO_IRQn 0 */ + + /* USER CODE END SDIO_IRQn 0 */ + HAL_SD_IRQHandler(&hsd); + 80011f8: 4802 ldr r0, [pc, #8] @ (8001204 ) + 80011fa: f002 fed9 bl 8003fb0 + /* USER CODE BEGIN SDIO_IRQn 1 */ + + /* USER CODE END SDIO_IRQn 1 */ +} + 80011fe: bf00 nop + 8001200: bd80 pop {r7, pc} + 8001202: bf00 nop + 8001204: 2000015c .word 0x2000015c + +08001208 : /** * @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts. */ void TIM6_DAC_IRQHandler(void) { - 8000b28: b580 push {r7, lr} - 8000b2a: af00 add r7, sp, #0 + 8001208: b580 push {r7, lr} + 800120a: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ /* USER CODE END TIM6_DAC_IRQn 0 */ HAL_TIM_IRQHandler(&htim6); - 8000b2c: 4802 ldr r0, [pc, #8] @ (8000b38 ) - 8000b2e: f001 ff99 bl 8002a64 + 800120c: 4802 ldr r0, [pc, #8] @ (8001218 ) + 800120e: f004 f8e1 bl 80053d4 /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ /* USER CODE END TIM6_DAC_IRQn 1 */ } - 8000b32: bf00 nop - 8000b34: bd80 pop {r7, pc} - 8000b36: bf00 nop - 8000b38: 2000014c .word 0x2000014c + 8001212: bf00 nop + 8001214: bd80 pop {r7, pc} + 8001216: bf00 nop + 8001218: 200002d4 .word 0x200002d4 -08000b3c : +0800121c : + +/** + * @brief This function handles DMA2 stream3 global interrupt. + */ +void DMA2_Stream3_IRQHandler(void) +{ + 800121c: b580 push {r7, lr} + 800121e: af00 add r7, sp, #0 + /* USER CODE BEGIN DMA2_Stream3_IRQn 0 */ + + /* USER CODE END DMA2_Stream3_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_sdio_rx); + 8001220: 4802 ldr r0, [pc, #8] @ (800122c ) + 8001222: f001 fa8d bl 8002740 + /* USER CODE BEGIN DMA2_Stream3_IRQn 1 */ + + /* USER CODE END DMA2_Stream3_IRQn 1 */ +} + 8001226: bf00 nop + 8001228: bd80 pop {r7, pc} + 800122a: bf00 nop + 800122c: 200001e0 .word 0x200001e0 + +08001230 : + +/** + * @brief This function handles DMA2 stream6 global interrupt. + */ +void DMA2_Stream6_IRQHandler(void) +{ + 8001230: b580 push {r7, lr} + 8001232: af00 add r7, sp, #0 + /* USER CODE BEGIN DMA2_Stream6_IRQn 0 */ + + /* USER CODE END DMA2_Stream6_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_sdio_tx); + 8001234: 4802 ldr r0, [pc, #8] @ (8001240 ) + 8001236: f001 fa83 bl 8002740 + /* USER CODE BEGIN DMA2_Stream6_IRQn 1 */ + + /* USER CODE END DMA2_Stream6_IRQn 1 */ +} + 800123a: bf00 nop + 800123c: bd80 pop {r7, pc} + 800123e: bf00 nop + 8001240: 20000240 .word 0x20000240 + +08001244 : * configuration. * @param None * @retval None */ void SystemInit(void) { - 8000b3c: b480 push {r7} - 8000b3e: af00 add r7, sp, #0 + 8001244: b480 push {r7} + 8001246: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ - 8000b40: 4b06 ldr r3, [pc, #24] @ (8000b5c ) - 8000b42: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 - 8000b46: 4a05 ldr r2, [pc, #20] @ (8000b5c ) - 8000b48: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 - 8000b4c: f8c2 3088 str.w r3, [r2, #136] @ 0x88 + 8001248: 4b06 ldr r3, [pc, #24] @ (8001264 ) + 800124a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 800124e: 4a05 ldr r2, [pc, #20] @ (8001264 ) + 8001250: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 + 8001254: f8c2 3088 str.w r3, [r2, #136] @ 0x88 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } - 8000b50: bf00 nop - 8000b52: 46bd mov sp, r7 - 8000b54: f85d 7b04 ldr.w r7, [sp], #4 - 8000b58: 4770 bx lr - 8000b5a: bf00 nop - 8000b5c: e000ed00 .word 0xe000ed00 + 8001258: bf00 nop + 800125a: 46bd mov sp, r7 + 800125c: f85d 7b04 ldr.w r7, [sp], #4 + 8001260: 4770 bx lr + 8001262: bf00 nop + 8001264: e000ed00 .word 0xe000ed00 -08000b60 : +08001268 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ - 8000b60: f8df d034 ldr.w sp, [pc, #52] @ 8000b98 + 8001268: f8df d034 ldr.w sp, [pc, #52] @ 80012a0 /* Call the clock system initialization function.*/ bl SystemInit - 8000b64: f7ff ffea bl 8000b3c + 800126c: f7ff ffea bl 8001244 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata - 8000b68: 480c ldr r0, [pc, #48] @ (8000b9c ) + 8001270: 480c ldr r0, [pc, #48] @ (80012a4 ) ldr r1, =_edata - 8000b6a: 490d ldr r1, [pc, #52] @ (8000ba0 ) + 8001272: 490d ldr r1, [pc, #52] @ (80012a8 ) ldr r2, =_sidata - 8000b6c: 4a0d ldr r2, [pc, #52] @ (8000ba4 ) + 8001274: 4a0d ldr r2, [pc, #52] @ (80012ac ) movs r3, #0 - 8000b6e: 2300 movs r3, #0 + 8001276: 2300 movs r3, #0 b LoopCopyDataInit - 8000b70: e002 b.n 8000b78 + 8001278: e002 b.n 8001280 -08000b72 : +0800127a : CopyDataInit: ldr r4, [r2, r3] - 8000b72: 58d4 ldr r4, [r2, r3] + 800127a: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] - 8000b74: 50c4 str r4, [r0, r3] + 800127c: 50c4 str r4, [r0, r3] adds r3, r3, #4 - 8000b76: 3304 adds r3, #4 + 800127e: 3304 adds r3, #4 -08000b78 : +08001280 : LoopCopyDataInit: adds r4, r0, r3 - 8000b78: 18c4 adds r4, r0, r3 + 8001280: 18c4 adds r4, r0, r3 cmp r4, r1 - 8000b7a: 428c cmp r4, r1 + 8001282: 428c cmp r4, r1 bcc CopyDataInit - 8000b7c: d3f9 bcc.n 8000b72 + 8001284: d3f9 bcc.n 800127a /* Zero fill the bss segment. */ ldr r2, =_sbss - 8000b7e: 4a0a ldr r2, [pc, #40] @ (8000ba8 ) + 8001286: 4a0a ldr r2, [pc, #40] @ (80012b0 ) ldr r4, =_ebss - 8000b80: 4c0a ldr r4, [pc, #40] @ (8000bac ) + 8001288: 4c0a ldr r4, [pc, #40] @ (80012b4 ) movs r3, #0 - 8000b82: 2300 movs r3, #0 + 800128a: 2300 movs r3, #0 b LoopFillZerobss - 8000b84: e001 b.n 8000b8a + 800128c: e001 b.n 8001292 -08000b86 : +0800128e : FillZerobss: str r3, [r2] - 8000b86: 6013 str r3, [r2, #0] + 800128e: 6013 str r3, [r2, #0] adds r2, r2, #4 - 8000b88: 3204 adds r2, #4 + 8001290: 3204 adds r2, #4 -08000b8a : +08001292 : LoopFillZerobss: cmp r2, r4 - 8000b8a: 42a2 cmp r2, r4 + 8001292: 42a2 cmp r2, r4 bcc FillZerobss - 8000b8c: d3fb bcc.n 8000b86 + 8001294: d3fb bcc.n 800128e /* Call static constructors */ bl __libc_init_array - 8000b8e: f004 ff3f bl 8005a10 <__libc_init_array> + 8001296: f008 fe23 bl 8009ee0 <__libc_init_array> /* Call the application's entry point.*/ bl main - 8000b92: f7ff fcb3 bl 80004fc
+ 800129a: f7ff fa33 bl 8000704
bx lr - 8000b96: 4770 bx lr + 800129e: 4770 bx lr ldr sp, =_estack /* set stack pointer */ - 8000b98: 20020000 .word 0x20020000 + 80012a0: 20020000 .word 0x20020000 ldr r0, =_sdata - 8000b9c: 20000000 .word 0x20000000 + 80012a4: 20000000 .word 0x20000000 ldr r1, =_edata - 8000ba0: 20000060 .word 0x20000060 + 80012a8: 20000078 .word 0x20000078 ldr r2, =_sidata - 8000ba4: 08005d6c .word 0x08005d6c + 80012ac: 0800a2d0 .word 0x0800a2d0 ldr r2, =_sbss - 8000ba8: 20000060 .word 0x20000060 + 80012b0: 20000078 .word 0x20000078 ldr r4, =_ebss - 8000bac: 20004cc8 .word 0x20004cc8 + 80012b4: 20004e50 .word 0x20004e50 -08000bb0 : +080012b8 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop - 8000bb0: e7fe b.n 8000bb0 + 80012b8: e7fe b.n 80012b8 -08000bb2 : +080012ba : /** * @brief Acquire STM32 lock * @param lock The lock to acquire */ static inline void stm32_lock_acquire(LockingData_t *lock) { - 8000bb2: b580 push {r7, lr} - 8000bb4: b084 sub sp, #16 - 8000bb6: af00 add r7, sp, #0 - 8000bb8: 6078 str r0, [r7, #4] + 80012ba: b580 push {r7, lr} + 80012bc: b084 sub sp, #16 + 80012be: af00 add r7, sp, #0 + 80012c0: 6078 str r0, [r7, #4] STM32_LOCK_BLOCK_IF_NULL_ARGUMENT(lock); - 8000bba: 687b ldr r3, [r7, #4] - 8000bbc: 2b00 cmp r3, #0 - 8000bbe: d105 bne.n 8000bcc + 80012c2: 687b ldr r3, [r7, #4] + 80012c4: 2b00 cmp r3, #0 + 80012c6: d105 bne.n 80012d4 __ASM volatile ("cpsid i" : : : "memory"); - 8000bc0: b672 cpsid i + 80012c8: b672 cpsid i } - 8000bc2: bf00 nop - 8000bc4: f7ff fe3a bl 800083c - 8000bc8: bf00 nop - 8000bca: e7fd b.n 8000bc8 + 80012ca: bf00 nop + 80012cc: f7ff fcf2 bl 8000cb4 + 80012d0: bf00 nop + 80012d2: e7fd b.n 80012d0 STM32_LOCK_ASSERT_VALID_NESTING_LEVEL(lock); - 8000bcc: 687b ldr r3, [r7, #4] - 8000bce: 7a1b ldrb r3, [r3, #8] - 8000bd0: 2b01 cmp r3, #1 - 8000bd2: d905 bls.n 8000be0 + 80012d4: 687b ldr r3, [r7, #4] + 80012d6: 7a1b ldrb r3, [r3, #8] + 80012d8: 2b01 cmp r3, #1 + 80012da: d905 bls.n 80012e8 __ASM volatile ("cpsid i" : : : "memory"); - 8000bd4: b672 cpsid i + 80012dc: b672 cpsid i } - 8000bd6: bf00 nop - 8000bd8: f7ff fe30 bl 800083c - 8000bdc: bf00 nop - 8000bde: e7fd b.n 8000bdc + 80012de: bf00 nop + 80012e0: f7ff fce8 bl 8000cb4 + 80012e4: bf00 nop + 80012e6: e7fd b.n 80012e4 lock->basepri[lock->nesting_level++] = taskENTER_CRITICAL_FROM_ISR(); - 8000be0: 687b ldr r3, [r7, #4] - 8000be2: 7a1b ldrb r3, [r3, #8] - 8000be4: 1c5a adds r2, r3, #1 - 8000be6: b2d1 uxtb r1, r2 - 8000be8: 687a ldr r2, [r7, #4] - 8000bea: 7211 strb r1, [r2, #8] - 8000bec: 4619 mov r1, r3 + 80012e8: 687b ldr r3, [r7, #4] + 80012ea: 7a1b ldrb r3, [r3, #8] + 80012ec: 1c5a adds r2, r3, #1 + 80012ee: b2d1 uxtb r1, r2 + 80012f0: 687a ldr r2, [r7, #4] + 80012f2: 7211 strb r1, [r2, #8] + 80012f4: 4619 mov r1, r3 portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) { uint32_t ulOriginalBASEPRI, ulNewBASEPRI; __asm volatile - 8000bee: f3ef 8211 mrs r2, BASEPRI - 8000bf2: f04f 0350 mov.w r3, #80 @ 0x50 - 8000bf6: f383 8811 msr BASEPRI, r3 - 8000bfa: f3bf 8f6f isb sy - 8000bfe: f3bf 8f4f dsb sy - 8000c02: 60fa str r2, [r7, #12] - 8000c04: 60bb str r3, [r7, #8] + 80012f6: f3ef 8211 mrs r2, BASEPRI + 80012fa: f04f 0350 mov.w r3, #80 @ 0x50 + 80012fe: f383 8811 msr BASEPRI, r3 + 8001302: f3bf 8f6f isb sy + 8001306: f3bf 8f4f dsb sy + 800130a: 60fa str r2, [r7, #12] + 800130c: 60bb str r3, [r7, #8] :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); /* This return will not be reached but is necessary to prevent compiler warnings. */ return ulOriginalBASEPRI; - 8000c06: 68fa ldr r2, [r7, #12] - 8000c08: 687b ldr r3, [r7, #4] - 8000c0a: f843 2021 str.w r2, [r3, r1, lsl #2] + 800130e: 68fa ldr r2, [r7, #12] + 8001310: 687b ldr r3, [r7, #4] + 8001312: f843 2021 str.w r2, [r3, r1, lsl #2] } - 8000c0e: bf00 nop - 8000c10: 3710 adds r7, #16 - 8000c12: 46bd mov sp, r7 - 8000c14: bd80 pop {r7, pc} + 8001316: bf00 nop + 8001318: 3710 adds r7, #16 + 800131a: 46bd mov sp, r7 + 800131c: bd80 pop {r7, pc} -08000c16 : +0800131e : /** * @brief Release STM32 lock * @param lock The lock to release */ static inline void stm32_lock_release(LockingData_t *lock) { - 8000c16: b580 push {r7, lr} - 8000c18: b084 sub sp, #16 - 8000c1a: af00 add r7, sp, #0 - 8000c1c: 6078 str r0, [r7, #4] + 800131e: b580 push {r7, lr} + 8001320: b084 sub sp, #16 + 8001322: af00 add r7, sp, #0 + 8001324: 6078 str r0, [r7, #4] STM32_LOCK_BLOCK_IF_NULL_ARGUMENT(lock); - 8000c1e: 687b ldr r3, [r7, #4] - 8000c20: 2b00 cmp r3, #0 - 8000c22: d105 bne.n 8000c30 + 8001326: 687b ldr r3, [r7, #4] + 8001328: 2b00 cmp r3, #0 + 800132a: d105 bne.n 8001338 __ASM volatile ("cpsid i" : : : "memory"); - 8000c24: b672 cpsid i + 800132c: b672 cpsid i } - 8000c26: bf00 nop - 8000c28: f7ff fe08 bl 800083c - 8000c2c: bf00 nop - 8000c2e: e7fd b.n 8000c2c + 800132e: bf00 nop + 8001330: f7ff fcc0 bl 8000cb4 + 8001334: bf00 nop + 8001336: e7fd b.n 8001334 lock->nesting_level--; - 8000c30: 687b ldr r3, [r7, #4] - 8000c32: 7a1b ldrb r3, [r3, #8] - 8000c34: 3b01 subs r3, #1 - 8000c36: b2da uxtb r2, r3 - 8000c38: 687b ldr r3, [r7, #4] - 8000c3a: 721a strb r2, [r3, #8] + 8001338: 687b ldr r3, [r7, #4] + 800133a: 7a1b ldrb r3, [r3, #8] + 800133c: 3b01 subs r3, #1 + 800133e: b2da uxtb r2, r3 + 8001340: 687b ldr r3, [r7, #4] + 8001342: 721a strb r2, [r3, #8] STM32_LOCK_ASSERT_VALID_NESTING_LEVEL(lock); - 8000c3c: 687b ldr r3, [r7, #4] - 8000c3e: 7a1b ldrb r3, [r3, #8] - 8000c40: 2b01 cmp r3, #1 - 8000c42: d905 bls.n 8000c50 + 8001344: 687b ldr r3, [r7, #4] + 8001346: 7a1b ldrb r3, [r3, #8] + 8001348: 2b01 cmp r3, #1 + 800134a: d905 bls.n 8001358 __ASM volatile ("cpsid i" : : : "memory"); - 8000c44: b672 cpsid i + 800134c: b672 cpsid i } - 8000c46: bf00 nop - 8000c48: f7ff fdf8 bl 800083c - 8000c4c: bf00 nop - 8000c4e: e7fd b.n 8000c4c + 800134e: bf00 nop + 8001350: f7ff fcb0 bl 8000cb4 + 8001354: bf00 nop + 8001356: e7fd b.n 8001354 taskEXIT_CRITICAL_FROM_ISR(lock->basepri[lock->nesting_level]); - 8000c50: 687b ldr r3, [r7, #4] - 8000c52: 7a1b ldrb r3, [r3, #8] - 8000c54: 461a mov r2, r3 - 8000c56: 687b ldr r3, [r7, #4] - 8000c58: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 8000c5c: 60fb str r3, [r7, #12] + 8001358: 687b ldr r3, [r7, #4] + 800135a: 7a1b ldrb r3, [r3, #8] + 800135c: 461a mov r2, r3 + 800135e: 687b ldr r3, [r7, #4] + 8001360: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8001364: 60fb str r3, [r7, #12] } /*-----------------------------------------------------------*/ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) { __asm volatile - 8000c5e: 68fb ldr r3, [r7, #12] - 8000c60: f383 8811 msr BASEPRI, r3 + 8001366: 68fb ldr r3, [r7, #12] + 8001368: f383 8811 msr BASEPRI, r3 ( " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory" ); } - 8000c64: bf00 nop + 800136c: bf00 nop } - 8000c66: bf00 nop - 8000c68: 3710 adds r7, #16 - 8000c6a: 46bd mov sp, r7 - 8000c6c: bd80 pop {r7, pc} + 800136e: bf00 nop + 8001370: 3710 adds r7, #16 + 8001372: 46bd mov sp, r7 + 8001374: bd80 pop {r7, pc} -08000c6e <__retarget_lock_acquire_recursive>: +08001376 <__retarget_lock_acquire_recursive>: /** * @brief Acquire recursive lock * @param lock The lock */ void __retarget_lock_acquire_recursive(_LOCK_T lock) { - 8000c6e: b580 push {r7, lr} - 8000c70: b082 sub sp, #8 - 8000c72: af00 add r7, sp, #0 - 8000c74: 6078 str r0, [r7, #4] + 8001376: b580 push {r7, lr} + 8001378: b082 sub sp, #8 + 800137a: af00 add r7, sp, #0 + 800137c: 6078 str r0, [r7, #4] STM32_LOCK_BLOCK_IF_NULL_ARGUMENT(lock); - 8000c76: 687b ldr r3, [r7, #4] - 8000c78: 2b00 cmp r3, #0 - 8000c7a: d105 bne.n 8000c88 <__retarget_lock_acquire_recursive+0x1a> + 800137e: 687b ldr r3, [r7, #4] + 8001380: 2b00 cmp r3, #0 + 8001382: d105 bne.n 8001390 <__retarget_lock_acquire_recursive+0x1a> __ASM volatile ("cpsid i" : : : "memory"); - 8000c7c: b672 cpsid i + 8001384: b672 cpsid i } - 8000c7e: bf00 nop - 8000c80: f7ff fddc bl 800083c - 8000c84: bf00 nop - 8000c86: e7fd b.n 8000c84 <__retarget_lock_acquire_recursive+0x16> + 8001386: bf00 nop + 8001388: f7ff fc94 bl 8000cb4 + 800138c: bf00 nop + 800138e: e7fd b.n 800138c <__retarget_lock_acquire_recursive+0x16> stm32_lock_acquire(STM32_LOCK_PARAMETER(lock)); - 8000c88: 687b ldr r3, [r7, #4] - 8000c8a: 4618 mov r0, r3 - 8000c8c: f7ff ff91 bl 8000bb2 + 8001390: 687b ldr r3, [r7, #4] + 8001392: 4618 mov r0, r3 + 8001394: f7ff ff91 bl 80012ba } - 8000c90: bf00 nop - 8000c92: 3708 adds r7, #8 - 8000c94: 46bd mov sp, r7 - 8000c96: bd80 pop {r7, pc} + 8001398: bf00 nop + 800139a: 3708 adds r7, #8 + 800139c: 46bd mov sp, r7 + 800139e: bd80 pop {r7, pc} -08000c98 <__retarget_lock_release_recursive>: +080013a0 <__retarget_lock_release_recursive>: /** * @brief Release recursive lock * @param lock The lock */ void __retarget_lock_release_recursive(_LOCK_T lock) { - 8000c98: b580 push {r7, lr} - 8000c9a: b082 sub sp, #8 - 8000c9c: af00 add r7, sp, #0 - 8000c9e: 6078 str r0, [r7, #4] + 80013a0: b580 push {r7, lr} + 80013a2: b082 sub sp, #8 + 80013a4: af00 add r7, sp, #0 + 80013a6: 6078 str r0, [r7, #4] STM32_LOCK_BLOCK_IF_NULL_ARGUMENT(lock); - 8000ca0: 687b ldr r3, [r7, #4] - 8000ca2: 2b00 cmp r3, #0 - 8000ca4: d105 bne.n 8000cb2 <__retarget_lock_release_recursive+0x1a> + 80013a8: 687b ldr r3, [r7, #4] + 80013aa: 2b00 cmp r3, #0 + 80013ac: d105 bne.n 80013ba <__retarget_lock_release_recursive+0x1a> __ASM volatile ("cpsid i" : : : "memory"); - 8000ca6: b672 cpsid i + 80013ae: b672 cpsid i } - 8000ca8: bf00 nop - 8000caa: f7ff fdc7 bl 800083c - 8000cae: bf00 nop - 8000cb0: e7fd b.n 8000cae <__retarget_lock_release_recursive+0x16> + 80013b0: bf00 nop + 80013b2: f7ff fc7f bl 8000cb4 + 80013b6: bf00 nop + 80013b8: e7fd b.n 80013b6 <__retarget_lock_release_recursive+0x16> stm32_lock_release(STM32_LOCK_PARAMETER(lock)); - 8000cb2: 687b ldr r3, [r7, #4] - 8000cb4: 4618 mov r0, r3 - 8000cb6: f7ff ffae bl 8000c16 + 80013ba: 687b ldr r3, [r7, #4] + 80013bc: 4618 mov r0, r3 + 80013be: f7ff ffae bl 800131e } - 8000cba: bf00 nop - 8000cbc: 3708 adds r7, #8 - 8000cbe: 46bd mov sp, r7 - 8000cc0: bd80 pop {r7, pc} + 80013c2: bf00 nop + 80013c4: 3708 adds r7, #8 + 80013c6: 46bd mov sp, r7 + 80013c8: bd80 pop {r7, pc} ... -08000cc4 : +080013cc : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { - 8000cc4: b580 push {r7, lr} - 8000cc6: af00 add r7, sp, #0 + 80013cc: b580 push {r7, lr} + 80013ce: af00 add r7, sp, #0 /* Configure Flash prefetch, Instruction cache, Data cache */ #if (INSTRUCTION_CACHE_ENABLE != 0U) __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); - 8000cc8: 4b0e ldr r3, [pc, #56] @ (8000d04 ) - 8000cca: 681b ldr r3, [r3, #0] - 8000ccc: 4a0d ldr r2, [pc, #52] @ (8000d04 ) - 8000cce: f443 7300 orr.w r3, r3, #512 @ 0x200 - 8000cd2: 6013 str r3, [r2, #0] + 80013d0: 4b0e ldr r3, [pc, #56] @ (800140c ) + 80013d2: 681b ldr r3, [r3, #0] + 80013d4: 4a0d ldr r2, [pc, #52] @ (800140c ) + 80013d6: f443 7300 orr.w r3, r3, #512 @ 0x200 + 80013da: 6013 str r3, [r2, #0] #endif /* INSTRUCTION_CACHE_ENABLE */ #if (DATA_CACHE_ENABLE != 0U) __HAL_FLASH_DATA_CACHE_ENABLE(); - 8000cd4: 4b0b ldr r3, [pc, #44] @ (8000d04 ) - 8000cd6: 681b ldr r3, [r3, #0] - 8000cd8: 4a0a ldr r2, [pc, #40] @ (8000d04 ) - 8000cda: f443 6380 orr.w r3, r3, #1024 @ 0x400 - 8000cde: 6013 str r3, [r2, #0] + 80013dc: 4b0b ldr r3, [pc, #44] @ (800140c ) + 80013de: 681b ldr r3, [r3, #0] + 80013e0: 4a0a ldr r2, [pc, #40] @ (800140c ) + 80013e2: f443 6380 orr.w r3, r3, #1024 @ 0x400 + 80013e6: 6013 str r3, [r2, #0] #endif /* DATA_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); - 8000ce0: 4b08 ldr r3, [pc, #32] @ (8000d04 ) - 8000ce2: 681b ldr r3, [r3, #0] - 8000ce4: 4a07 ldr r2, [pc, #28] @ (8000d04 ) - 8000ce6: f443 7380 orr.w r3, r3, #256 @ 0x100 - 8000cea: 6013 str r3, [r2, #0] + 80013e8: 4b08 ldr r3, [pc, #32] @ (800140c ) + 80013ea: 681b ldr r3, [r3, #0] + 80013ec: 4a07 ldr r2, [pc, #28] @ (800140c ) + 80013ee: f443 7380 orr.w r3, r3, #256 @ 0x100 + 80013f2: 6013 str r3, [r2, #0] #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); - 8000cec: 2003 movs r0, #3 - 8000cee: f000 fbc5 bl 800147c + 80013f4: 2003 movs r0, #3 + 80013f6: f000 ff03 bl 8002200 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); - 8000cf2: 200f movs r0, #15 - 8000cf4: f7ff fe80 bl 80009f8 + 80013fa: 200f movs r0, #15 + 80013fc: f7ff fe62 bl 80010c4 /* Init the low level hardware */ HAL_MspInit(); - 8000cf8: f7ff fdb2 bl 8000860 + 8001400: f7ff fca4 bl 8000d4c /* Return function status */ return HAL_OK; - 8000cfc: 2300 movs r3, #0 + 8001404: 2300 movs r3, #0 } - 8000cfe: 4618 mov r0, r3 - 8000d00: bd80 pop {r7, pc} - 8000d02: bf00 nop - 8000d04: 40023c00 .word 0x40023c00 + 8001406: 4618 mov r0, r3 + 8001408: bd80 pop {r7, pc} + 800140a: bf00 nop + 800140c: 40023c00 .word 0x40023c00 -08000d08 : +08001410 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { - 8000d08: b480 push {r7} - 8000d0a: af00 add r7, sp, #0 + 8001410: b480 push {r7} + 8001412: af00 add r7, sp, #0 uwTick += uwTickFreq; - 8000d0c: 4b06 ldr r3, [pc, #24] @ (8000d28 ) - 8000d0e: 781b ldrb r3, [r3, #0] - 8000d10: 461a mov r2, r3 - 8000d12: 4b06 ldr r3, [pc, #24] @ (8000d2c ) - 8000d14: 681b ldr r3, [r3, #0] - 8000d16: 4413 add r3, r2 - 8000d18: 4a04 ldr r2, [pc, #16] @ (8000d2c ) - 8000d1a: 6013 str r3, [r2, #0] + 8001414: 4b06 ldr r3, [pc, #24] @ (8001430 ) + 8001416: 781b ldrb r3, [r3, #0] + 8001418: 461a mov r2, r3 + 800141a: 4b06 ldr r3, [pc, #24] @ (8001434 ) + 800141c: 681b ldr r3, [r3, #0] + 800141e: 4413 add r3, r2 + 8001420: 4a04 ldr r2, [pc, #16] @ (8001434 ) + 8001422: 6013 str r3, [r2, #0] } - 8000d1c: bf00 nop - 8000d1e: 46bd mov sp, r7 - 8000d20: f85d 7b04 ldr.w r7, [sp], #4 - 8000d24: 4770 bx lr - 8000d26: bf00 nop - 8000d28: 20000008 .word 0x20000008 - 8000d2c: 200001a0 .word 0x200001a0 + 8001424: bf00 nop + 8001426: 46bd mov sp, r7 + 8001428: f85d 7b04 ldr.w r7, [sp], #4 + 800142c: 4770 bx lr + 800142e: bf00 nop + 8001430: 20000020 .word 0x20000020 + 8001434: 20000328 .word 0x20000328 -08000d30 : +08001438 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { - 8000d30: b480 push {r7} - 8000d32: af00 add r7, sp, #0 + 8001438: b480 push {r7} + 800143a: af00 add r7, sp, #0 return uwTick; - 8000d34: 4b03 ldr r3, [pc, #12] @ (8000d44 ) - 8000d36: 681b ldr r3, [r3, #0] + 800143c: 4b03 ldr r3, [pc, #12] @ (800144c ) + 800143e: 681b ldr r3, [r3, #0] } - 8000d38: 4618 mov r0, r3 - 8000d3a: 46bd mov sp, r7 - 8000d3c: f85d 7b04 ldr.w r7, [sp], #4 - 8000d40: 4770 bx lr - 8000d42: bf00 nop - 8000d44: 200001a0 .word 0x200001a0 + 8001440: 4618 mov r0, r3 + 8001442: 46bd mov sp, r7 + 8001444: f85d 7b04 ldr.w r7, [sp], #4 + 8001448: 4770 bx lr + 800144a: bf00 nop + 800144c: 20000328 .word 0x20000328 -08000d48 : +08001450 : + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + 8001450: b580 push {r7, lr} + 8001452: b084 sub sp, #16 + 8001454: af00 add r7, sp, #0 + 8001456: 6078 str r0, [r7, #4] + uint32_t tickstart = HAL_GetTick(); + 8001458: f7ff ffee bl 8001438 + 800145c: 60b8 str r0, [r7, #8] + uint32_t wait = Delay; + 800145e: 687b ldr r3, [r7, #4] + 8001460: 60fb str r3, [r7, #12] + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + 8001462: 68fb ldr r3, [r7, #12] + 8001464: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8001468: d005 beq.n 8001476 + { + wait += (uint32_t)(uwTickFreq); + 800146a: 4b0a ldr r3, [pc, #40] @ (8001494 ) + 800146c: 781b ldrb r3, [r3, #0] + 800146e: 461a mov r2, r3 + 8001470: 68fb ldr r3, [r7, #12] + 8001472: 4413 add r3, r2 + 8001474: 60fb str r3, [r7, #12] + } + + while((HAL_GetTick() - tickstart) < wait) + 8001476: bf00 nop + 8001478: f7ff ffde bl 8001438 + 800147c: 4602 mov r2, r0 + 800147e: 68bb ldr r3, [r7, #8] + 8001480: 1ad3 subs r3, r2, r3 + 8001482: 68fa ldr r2, [r7, #12] + 8001484: 429a cmp r2, r3 + 8001486: d8f7 bhi.n 8001478 + { + } +} + 8001488: bf00 nop + 800148a: bf00 nop + 800148c: 3710 adds r7, #16 + 800148e: 46bd mov sp, r7 + 8001490: bd80 pop {r7, pc} + 8001492: bf00 nop + 8001494: 20000020 .word 0x20000020 + +08001498 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { - 8000d48: b580 push {r7, lr} - 8000d4a: b084 sub sp, #16 - 8000d4c: af00 add r7, sp, #0 - 8000d4e: 6078 str r0, [r7, #4] + 8001498: b580 push {r7, lr} + 800149a: b084 sub sp, #16 + 800149c: af00 add r7, sp, #0 + 800149e: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check CAN handle */ if (hcan == NULL) - 8000d50: 687b ldr r3, [r7, #4] - 8000d52: 2b00 cmp r3, #0 - 8000d54: d101 bne.n 8000d5a + 80014a0: 687b ldr r3, [r7, #4] + 80014a2: 2b00 cmp r3, #0 + 80014a4: d101 bne.n 80014aa { return HAL_ERROR; - 8000d56: 2301 movs r3, #1 - 8000d58: e243 b.n 80011e2 + 80014a6: 2301 movs r3, #1 + 80014a8: e243 b.n 8001932 } /* Check the parameters */ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); - 8000d5a: 687b ldr r3, [r7, #4] - 8000d5c: 681b ldr r3, [r3, #0] - 8000d5e: 4a93 ldr r2, [pc, #588] @ (8000fac ) - 8000d60: 4293 cmp r3, r2 - 8000d62: d009 beq.n 8000d78 - 8000d64: 687b ldr r3, [r7, #4] - 8000d66: 681b ldr r3, [r3, #0] - 8000d68: 4a91 ldr r2, [pc, #580] @ (8000fb0 ) - 8000d6a: 4293 cmp r3, r2 - 8000d6c: d004 beq.n 8000d78 - 8000d6e: f44f 718f mov.w r1, #286 @ 0x11e - 8000d72: 4890 ldr r0, [pc, #576] @ (8000fb4 ) - 8000d74: f7ff fd68 bl 8000848 + 80014aa: 687b ldr r3, [r7, #4] + 80014ac: 681b ldr r3, [r3, #0] + 80014ae: 4a93 ldr r2, [pc, #588] @ (80016fc ) + 80014b0: 4293 cmp r3, r2 + 80014b2: d009 beq.n 80014c8 + 80014b4: 687b ldr r3, [r7, #4] + 80014b6: 681b ldr r3, [r3, #0] + 80014b8: 4a91 ldr r2, [pc, #580] @ (8001700 ) + 80014ba: 4293 cmp r3, r2 + 80014bc: d004 beq.n 80014c8 + 80014be: f44f 718f mov.w r1, #286 @ 0x11e + 80014c2: 4890 ldr r0, [pc, #576] @ (8001704 ) + 80014c4: f7ff fc36 bl 8000d34 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode)); - 8000d78: 687b ldr r3, [r7, #4] - 8000d7a: 7e1b ldrb r3, [r3, #24] - 8000d7c: 2b00 cmp r3, #0 - 8000d7e: d008 beq.n 8000d92 - 8000d80: 687b ldr r3, [r7, #4] - 8000d82: 7e1b ldrb r3, [r3, #24] - 8000d84: 2b01 cmp r3, #1 - 8000d86: d004 beq.n 8000d92 - 8000d88: f240 111f movw r1, #287 @ 0x11f - 8000d8c: 4889 ldr r0, [pc, #548] @ (8000fb4 ) - 8000d8e: f7ff fd5b bl 8000848 + 80014c8: 687b ldr r3, [r7, #4] + 80014ca: 7e1b ldrb r3, [r3, #24] + 80014cc: 2b00 cmp r3, #0 + 80014ce: d008 beq.n 80014e2 + 80014d0: 687b ldr r3, [r7, #4] + 80014d2: 7e1b ldrb r3, [r3, #24] + 80014d4: 2b01 cmp r3, #1 + 80014d6: d004 beq.n 80014e2 + 80014d8: f240 111f movw r1, #287 @ 0x11f + 80014dc: 4889 ldr r0, [pc, #548] @ (8001704 ) + 80014de: f7ff fc29 bl 8000d34 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff)); - 8000d92: 687b ldr r3, [r7, #4] - 8000d94: 7e5b ldrb r3, [r3, #25] - 8000d96: 2b00 cmp r3, #0 - 8000d98: d008 beq.n 8000dac - 8000d9a: 687b ldr r3, [r7, #4] - 8000d9c: 7e5b ldrb r3, [r3, #25] - 8000d9e: 2b01 cmp r3, #1 - 8000da0: d004 beq.n 8000dac - 8000da2: f44f 7190 mov.w r1, #288 @ 0x120 - 8000da6: 4883 ldr r0, [pc, #524] @ (8000fb4 ) - 8000da8: f7ff fd4e bl 8000848 + 80014e2: 687b ldr r3, [r7, #4] + 80014e4: 7e5b ldrb r3, [r3, #25] + 80014e6: 2b00 cmp r3, #0 + 80014e8: d008 beq.n 80014fc + 80014ea: 687b ldr r3, [r7, #4] + 80014ec: 7e5b ldrb r3, [r3, #25] + 80014ee: 2b01 cmp r3, #1 + 80014f0: d004 beq.n 80014fc + 80014f2: f44f 7190 mov.w r1, #288 @ 0x120 + 80014f6: 4883 ldr r0, [pc, #524] @ (8001704 ) + 80014f8: f7ff fc1c bl 8000d34 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp)); - 8000dac: 687b ldr r3, [r7, #4] - 8000dae: 7e9b ldrb r3, [r3, #26] - 8000db0: 2b00 cmp r3, #0 - 8000db2: d008 beq.n 8000dc6 - 8000db4: 687b ldr r3, [r7, #4] - 8000db6: 7e9b ldrb r3, [r3, #26] - 8000db8: 2b01 cmp r3, #1 - 8000dba: d004 beq.n 8000dc6 - 8000dbc: f240 1121 movw r1, #289 @ 0x121 - 8000dc0: 487c ldr r0, [pc, #496] @ (8000fb4 ) - 8000dc2: f7ff fd41 bl 8000848 + 80014fc: 687b ldr r3, [r7, #4] + 80014fe: 7e9b ldrb r3, [r3, #26] + 8001500: 2b00 cmp r3, #0 + 8001502: d008 beq.n 8001516 + 8001504: 687b ldr r3, [r7, #4] + 8001506: 7e9b ldrb r3, [r3, #26] + 8001508: 2b01 cmp r3, #1 + 800150a: d004 beq.n 8001516 + 800150c: f240 1121 movw r1, #289 @ 0x121 + 8001510: 487c ldr r0, [pc, #496] @ (8001704 ) + 8001512: f7ff fc0f bl 8000d34 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission)); - 8000dc6: 687b ldr r3, [r7, #4] - 8000dc8: 7edb ldrb r3, [r3, #27] - 8000dca: 2b00 cmp r3, #0 - 8000dcc: d008 beq.n 8000de0 - 8000dce: 687b ldr r3, [r7, #4] - 8000dd0: 7edb ldrb r3, [r3, #27] - 8000dd2: 2b01 cmp r3, #1 - 8000dd4: d004 beq.n 8000de0 - 8000dd6: f44f 7191 mov.w r1, #290 @ 0x122 - 8000dda: 4876 ldr r0, [pc, #472] @ (8000fb4 ) - 8000ddc: f7ff fd34 bl 8000848 + 8001516: 687b ldr r3, [r7, #4] + 8001518: 7edb ldrb r3, [r3, #27] + 800151a: 2b00 cmp r3, #0 + 800151c: d008 beq.n 8001530 + 800151e: 687b ldr r3, [r7, #4] + 8001520: 7edb ldrb r3, [r3, #27] + 8001522: 2b01 cmp r3, #1 + 8001524: d004 beq.n 8001530 + 8001526: f44f 7191 mov.w r1, #290 @ 0x122 + 800152a: 4876 ldr r0, [pc, #472] @ (8001704 ) + 800152c: f7ff fc02 bl 8000d34 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked)); - 8000de0: 687b ldr r3, [r7, #4] - 8000de2: 7f1b ldrb r3, [r3, #28] - 8000de4: 2b00 cmp r3, #0 - 8000de6: d008 beq.n 8000dfa - 8000de8: 687b ldr r3, [r7, #4] - 8000dea: 7f1b ldrb r3, [r3, #28] - 8000dec: 2b01 cmp r3, #1 - 8000dee: d004 beq.n 8000dfa - 8000df0: f240 1123 movw r1, #291 @ 0x123 - 8000df4: 486f ldr r0, [pc, #444] @ (8000fb4 ) - 8000df6: f7ff fd27 bl 8000848 + 8001530: 687b ldr r3, [r7, #4] + 8001532: 7f1b ldrb r3, [r3, #28] + 8001534: 2b00 cmp r3, #0 + 8001536: d008 beq.n 800154a + 8001538: 687b ldr r3, [r7, #4] + 800153a: 7f1b ldrb r3, [r3, #28] + 800153c: 2b01 cmp r3, #1 + 800153e: d004 beq.n 800154a + 8001540: f240 1123 movw r1, #291 @ 0x123 + 8001544: 486f ldr r0, [pc, #444] @ (8001704 ) + 8001546: f7ff fbf5 bl 8000d34 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority)); - 8000dfa: 687b ldr r3, [r7, #4] - 8000dfc: 7f5b ldrb r3, [r3, #29] - 8000dfe: 2b00 cmp r3, #0 - 8000e00: d008 beq.n 8000e14 - 8000e02: 687b ldr r3, [r7, #4] - 8000e04: 7f5b ldrb r3, [r3, #29] - 8000e06: 2b01 cmp r3, #1 - 8000e08: d004 beq.n 8000e14 - 8000e0a: f44f 7192 mov.w r1, #292 @ 0x124 - 8000e0e: 4869 ldr r0, [pc, #420] @ (8000fb4 ) - 8000e10: f7ff fd1a bl 8000848 + 800154a: 687b ldr r3, [r7, #4] + 800154c: 7f5b ldrb r3, [r3, #29] + 800154e: 2b00 cmp r3, #0 + 8001550: d008 beq.n 8001564 + 8001552: 687b ldr r3, [r7, #4] + 8001554: 7f5b ldrb r3, [r3, #29] + 8001556: 2b01 cmp r3, #1 + 8001558: d004 beq.n 8001564 + 800155a: f44f 7192 mov.w r1, #292 @ 0x124 + 800155e: 4869 ldr r0, [pc, #420] @ (8001704 ) + 8001560: f7ff fbe8 bl 8000d34 assert_param(IS_CAN_MODE(hcan->Init.Mode)); - 8000e14: 687b ldr r3, [r7, #4] - 8000e16: 689b ldr r3, [r3, #8] - 8000e18: 2b00 cmp r3, #0 - 8000e1a: d013 beq.n 8000e44 - 8000e1c: 687b ldr r3, [r7, #4] - 8000e1e: 689b ldr r3, [r3, #8] - 8000e20: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 - 8000e24: d00e beq.n 8000e44 - 8000e26: 687b ldr r3, [r7, #4] - 8000e28: 689b ldr r3, [r3, #8] - 8000e2a: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 - 8000e2e: d009 beq.n 8000e44 - 8000e30: 687b ldr r3, [r7, #4] - 8000e32: 689b ldr r3, [r3, #8] - 8000e34: f1b3 4f40 cmp.w r3, #3221225472 @ 0xc0000000 - 8000e38: d004 beq.n 8000e44 - 8000e3a: f240 1125 movw r1, #293 @ 0x125 - 8000e3e: 485d ldr r0, [pc, #372] @ (8000fb4 ) - 8000e40: f7ff fd02 bl 8000848 + 8001564: 687b ldr r3, [r7, #4] + 8001566: 689b ldr r3, [r3, #8] + 8001568: 2b00 cmp r3, #0 + 800156a: d013 beq.n 8001594 + 800156c: 687b ldr r3, [r7, #4] + 800156e: 689b ldr r3, [r3, #8] + 8001570: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8001574: d00e beq.n 8001594 + 8001576: 687b ldr r3, [r7, #4] + 8001578: 689b ldr r3, [r3, #8] + 800157a: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 + 800157e: d009 beq.n 8001594 + 8001580: 687b ldr r3, [r7, #4] + 8001582: 689b ldr r3, [r3, #8] + 8001584: f1b3 4f40 cmp.w r3, #3221225472 @ 0xc0000000 + 8001588: d004 beq.n 8001594 + 800158a: f240 1125 movw r1, #293 @ 0x125 + 800158e: 485d ldr r0, [pc, #372] @ (8001704 ) + 8001590: f7ff fbd0 bl 8000d34 assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth)); - 8000e44: 687b ldr r3, [r7, #4] - 8000e46: 68db ldr r3, [r3, #12] - 8000e48: 2b00 cmp r3, #0 - 8000e4a: d013 beq.n 8000e74 - 8000e4c: 687b ldr r3, [r7, #4] - 8000e4e: 68db ldr r3, [r3, #12] - 8000e50: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 - 8000e54: d00e beq.n 8000e74 - 8000e56: 687b ldr r3, [r7, #4] - 8000e58: 68db ldr r3, [r3, #12] - 8000e5a: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 - 8000e5e: d009 beq.n 8000e74 - 8000e60: 687b ldr r3, [r7, #4] - 8000e62: 68db ldr r3, [r3, #12] - 8000e64: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 - 8000e68: d004 beq.n 8000e74 - 8000e6a: f44f 7193 mov.w r1, #294 @ 0x126 - 8000e6e: 4851 ldr r0, [pc, #324] @ (8000fb4 ) - 8000e70: f7ff fcea bl 8000848 + 8001594: 687b ldr r3, [r7, #4] + 8001596: 68db ldr r3, [r3, #12] + 8001598: 2b00 cmp r3, #0 + 800159a: d013 beq.n 80015c4 + 800159c: 687b ldr r3, [r7, #4] + 800159e: 68db ldr r3, [r3, #12] + 80015a0: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 + 80015a4: d00e beq.n 80015c4 + 80015a6: 687b ldr r3, [r7, #4] + 80015a8: 68db ldr r3, [r3, #12] + 80015aa: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 + 80015ae: d009 beq.n 80015c4 + 80015b0: 687b ldr r3, [r7, #4] + 80015b2: 68db ldr r3, [r3, #12] + 80015b4: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 + 80015b8: d004 beq.n 80015c4 + 80015ba: f44f 7193 mov.w r1, #294 @ 0x126 + 80015be: 4851 ldr r0, [pc, #324] @ (8001704 ) + 80015c0: f7ff fbb8 bl 8000d34 assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1)); - 8000e74: 687b ldr r3, [r7, #4] - 8000e76: 691b ldr r3, [r3, #16] - 8000e78: 2b00 cmp r3, #0 - 8000e7a: d04f beq.n 8000f1c - 8000e7c: 687b ldr r3, [r7, #4] - 8000e7e: 691b ldr r3, [r3, #16] - 8000e80: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 - 8000e84: d04a beq.n 8000f1c - 8000e86: 687b ldr r3, [r7, #4] - 8000e88: 691b ldr r3, [r3, #16] - 8000e8a: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 - 8000e8e: d045 beq.n 8000f1c - 8000e90: 687b ldr r3, [r7, #4] - 8000e92: 691b ldr r3, [r3, #16] - 8000e94: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 - 8000e98: d040 beq.n 8000f1c - 8000e9a: 687b ldr r3, [r7, #4] - 8000e9c: 691b ldr r3, [r3, #16] - 8000e9e: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 - 8000ea2: d03b beq.n 8000f1c - 8000ea4: 687b ldr r3, [r7, #4] - 8000ea6: 691b ldr r3, [r3, #16] - 8000ea8: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 - 8000eac: d036 beq.n 8000f1c - 8000eae: 687b ldr r3, [r7, #4] - 8000eb0: 691b ldr r3, [r3, #16] - 8000eb2: f5b3 2fc0 cmp.w r3, #393216 @ 0x60000 - 8000eb6: d031 beq.n 8000f1c - 8000eb8: 687b ldr r3, [r7, #4] - 8000eba: 691b ldr r3, [r3, #16] - 8000ebc: f5b3 2fe0 cmp.w r3, #458752 @ 0x70000 - 8000ec0: d02c beq.n 8000f1c - 8000ec2: 687b ldr r3, [r7, #4] - 8000ec4: 691b ldr r3, [r3, #16] - 8000ec6: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 - 8000eca: d027 beq.n 8000f1c - 8000ecc: 687b ldr r3, [r7, #4] - 8000ece: 691b ldr r3, [r3, #16] - 8000ed0: f5b3 2f10 cmp.w r3, #589824 @ 0x90000 - 8000ed4: d022 beq.n 8000f1c - 8000ed6: 687b ldr r3, [r7, #4] - 8000ed8: 691b ldr r3, [r3, #16] - 8000eda: f5b3 2f20 cmp.w r3, #655360 @ 0xa0000 - 8000ede: d01d beq.n 8000f1c - 8000ee0: 687b ldr r3, [r7, #4] - 8000ee2: 691b ldr r3, [r3, #16] - 8000ee4: f5b3 2f30 cmp.w r3, #720896 @ 0xb0000 - 8000ee8: d018 beq.n 8000f1c - 8000eea: 687b ldr r3, [r7, #4] - 8000eec: 691b ldr r3, [r3, #16] - 8000eee: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 - 8000ef2: d013 beq.n 8000f1c - 8000ef4: 687b ldr r3, [r7, #4] - 8000ef6: 691b ldr r3, [r3, #16] - 8000ef8: f5b3 2f50 cmp.w r3, #851968 @ 0xd0000 - 8000efc: d00e beq.n 8000f1c - 8000efe: 687b ldr r3, [r7, #4] - 8000f00: 691b ldr r3, [r3, #16] - 8000f02: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 - 8000f06: d009 beq.n 8000f1c - 8000f08: 687b ldr r3, [r7, #4] - 8000f0a: 691b ldr r3, [r3, #16] - 8000f0c: f5b3 2f70 cmp.w r3, #983040 @ 0xf0000 - 8000f10: d004 beq.n 8000f1c - 8000f12: f240 1127 movw r1, #295 @ 0x127 - 8000f16: 4827 ldr r0, [pc, #156] @ (8000fb4 ) - 8000f18: f7ff fc96 bl 8000848 + 80015c4: 687b ldr r3, [r7, #4] + 80015c6: 691b ldr r3, [r3, #16] + 80015c8: 2b00 cmp r3, #0 + 80015ca: d04f beq.n 800166c + 80015cc: 687b ldr r3, [r7, #4] + 80015ce: 691b ldr r3, [r3, #16] + 80015d0: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 80015d4: d04a beq.n 800166c + 80015d6: 687b ldr r3, [r7, #4] + 80015d8: 691b ldr r3, [r3, #16] + 80015da: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 + 80015de: d045 beq.n 800166c + 80015e0: 687b ldr r3, [r7, #4] + 80015e2: 691b ldr r3, [r3, #16] + 80015e4: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 + 80015e8: d040 beq.n 800166c + 80015ea: 687b ldr r3, [r7, #4] + 80015ec: 691b ldr r3, [r3, #16] + 80015ee: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 + 80015f2: d03b beq.n 800166c + 80015f4: 687b ldr r3, [r7, #4] + 80015f6: 691b ldr r3, [r3, #16] + 80015f8: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 + 80015fc: d036 beq.n 800166c + 80015fe: 687b ldr r3, [r7, #4] + 8001600: 691b ldr r3, [r3, #16] + 8001602: f5b3 2fc0 cmp.w r3, #393216 @ 0x60000 + 8001606: d031 beq.n 800166c + 8001608: 687b ldr r3, [r7, #4] + 800160a: 691b ldr r3, [r3, #16] + 800160c: f5b3 2fe0 cmp.w r3, #458752 @ 0x70000 + 8001610: d02c beq.n 800166c + 8001612: 687b ldr r3, [r7, #4] + 8001614: 691b ldr r3, [r3, #16] + 8001616: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 + 800161a: d027 beq.n 800166c + 800161c: 687b ldr r3, [r7, #4] + 800161e: 691b ldr r3, [r3, #16] + 8001620: f5b3 2f10 cmp.w r3, #589824 @ 0x90000 + 8001624: d022 beq.n 800166c + 8001626: 687b ldr r3, [r7, #4] + 8001628: 691b ldr r3, [r3, #16] + 800162a: f5b3 2f20 cmp.w r3, #655360 @ 0xa0000 + 800162e: d01d beq.n 800166c + 8001630: 687b ldr r3, [r7, #4] + 8001632: 691b ldr r3, [r3, #16] + 8001634: f5b3 2f30 cmp.w r3, #720896 @ 0xb0000 + 8001638: d018 beq.n 800166c + 800163a: 687b ldr r3, [r7, #4] + 800163c: 691b ldr r3, [r3, #16] + 800163e: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 + 8001642: d013 beq.n 800166c + 8001644: 687b ldr r3, [r7, #4] + 8001646: 691b ldr r3, [r3, #16] + 8001648: f5b3 2f50 cmp.w r3, #851968 @ 0xd0000 + 800164c: d00e beq.n 800166c + 800164e: 687b ldr r3, [r7, #4] + 8001650: 691b ldr r3, [r3, #16] + 8001652: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 + 8001656: d009 beq.n 800166c + 8001658: 687b ldr r3, [r7, #4] + 800165a: 691b ldr r3, [r3, #16] + 800165c: f5b3 2f70 cmp.w r3, #983040 @ 0xf0000 + 8001660: d004 beq.n 800166c + 8001662: f240 1127 movw r1, #295 @ 0x127 + 8001666: 4827 ldr r0, [pc, #156] @ (8001704 ) + 8001668: f7ff fb64 bl 8000d34 assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2)); - 8000f1c: 687b ldr r3, [r7, #4] - 8000f1e: 695b ldr r3, [r3, #20] - 8000f20: 2b00 cmp r3, #0 - 8000f22: d027 beq.n 8000f74 - 8000f24: 687b ldr r3, [r7, #4] - 8000f26: 695b ldr r3, [r3, #20] - 8000f28: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 - 8000f2c: d022 beq.n 8000f74 - 8000f2e: 687b ldr r3, [r7, #4] - 8000f30: 695b ldr r3, [r3, #20] - 8000f32: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 - 8000f36: d01d beq.n 8000f74 - 8000f38: 687b ldr r3, [r7, #4] - 8000f3a: 695b ldr r3, [r3, #20] - 8000f3c: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 - 8000f40: d018 beq.n 8000f74 - 8000f42: 687b ldr r3, [r7, #4] - 8000f44: 695b ldr r3, [r3, #20] - 8000f46: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 - 8000f4a: d013 beq.n 8000f74 - 8000f4c: 687b ldr r3, [r7, #4] - 8000f4e: 695b ldr r3, [r3, #20] - 8000f50: f5b3 0fa0 cmp.w r3, #5242880 @ 0x500000 - 8000f54: d00e beq.n 8000f74 - 8000f56: 687b ldr r3, [r7, #4] - 8000f58: 695b ldr r3, [r3, #20] - 8000f5a: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 - 8000f5e: d009 beq.n 8000f74 - 8000f60: 687b ldr r3, [r7, #4] - 8000f62: 695b ldr r3, [r3, #20] - 8000f64: f5b3 0fe0 cmp.w r3, #7340032 @ 0x700000 - 8000f68: d004 beq.n 8000f74 - 8000f6a: f44f 7194 mov.w r1, #296 @ 0x128 - 8000f6e: 4811 ldr r0, [pc, #68] @ (8000fb4 ) - 8000f70: f7ff fc6a bl 8000848 + 800166c: 687b ldr r3, [r7, #4] + 800166e: 695b ldr r3, [r3, #20] + 8001670: 2b00 cmp r3, #0 + 8001672: d027 beq.n 80016c4 + 8001674: 687b ldr r3, [r7, #4] + 8001676: 695b ldr r3, [r3, #20] + 8001678: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 + 800167c: d022 beq.n 80016c4 + 800167e: 687b ldr r3, [r7, #4] + 8001680: 695b ldr r3, [r3, #20] + 8001682: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 + 8001686: d01d beq.n 80016c4 + 8001688: 687b ldr r3, [r7, #4] + 800168a: 695b ldr r3, [r3, #20] + 800168c: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 + 8001690: d018 beq.n 80016c4 + 8001692: 687b ldr r3, [r7, #4] + 8001694: 695b ldr r3, [r3, #20] + 8001696: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 + 800169a: d013 beq.n 80016c4 + 800169c: 687b ldr r3, [r7, #4] + 800169e: 695b ldr r3, [r3, #20] + 80016a0: f5b3 0fa0 cmp.w r3, #5242880 @ 0x500000 + 80016a4: d00e beq.n 80016c4 + 80016a6: 687b ldr r3, [r7, #4] + 80016a8: 695b ldr r3, [r3, #20] + 80016aa: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 + 80016ae: d009 beq.n 80016c4 + 80016b0: 687b ldr r3, [r7, #4] + 80016b2: 695b ldr r3, [r3, #20] + 80016b4: f5b3 0fe0 cmp.w r3, #7340032 @ 0x700000 + 80016b8: d004 beq.n 80016c4 + 80016ba: f44f 7194 mov.w r1, #296 @ 0x128 + 80016be: 4811 ldr r0, [pc, #68] @ (8001704 ) + 80016c0: f7ff fb38 bl 8000d34 assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); - 8000f74: 687b ldr r3, [r7, #4] - 8000f76: 685b ldr r3, [r3, #4] - 8000f78: 2b00 cmp r3, #0 - 8000f7a: d004 beq.n 8000f86 - 8000f7c: 687b ldr r3, [r7, #4] - 8000f7e: 685b ldr r3, [r3, #4] - 8000f80: f5b3 6f80 cmp.w r3, #1024 @ 0x400 - 8000f84: d904 bls.n 8000f90 - 8000f86: f240 1129 movw r1, #297 @ 0x129 - 8000f8a: 480a ldr r0, [pc, #40] @ (8000fb4 ) - 8000f8c: f7ff fc5c bl 8000848 + 80016c4: 687b ldr r3, [r7, #4] + 80016c6: 685b ldr r3, [r3, #4] + 80016c8: 2b00 cmp r3, #0 + 80016ca: d004 beq.n 80016d6 + 80016cc: 687b ldr r3, [r7, #4] + 80016ce: 685b ldr r3, [r3, #4] + 80016d0: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 80016d4: d904 bls.n 80016e0 + 80016d6: f240 1129 movw r1, #297 @ 0x129 + 80016da: 480a ldr r0, [pc, #40] @ (8001704 ) + 80016dc: f7ff fb2a bl 8000d34 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 if (hcan->State == HAL_CAN_STATE_RESET) - 8000f90: 687b ldr r3, [r7, #4] - 8000f92: f893 3020 ldrb.w r3, [r3, #32] - 8000f96: b2db uxtb r3, r3 - 8000f98: 2b00 cmp r3, #0 - 8000f9a: d13d bne.n 8001018 + 80016e0: 687b ldr r3, [r7, #4] + 80016e2: f893 3020 ldrb.w r3, [r3, #32] + 80016e6: b2db uxtb r3, r3 + 80016e8: 2b00 cmp r3, #0 + 80016ea: d13d bne.n 8001768 { /* Reset callbacks to legacy functions */ hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; /* Legacy weak RxFifo0MsgPendingCallback */ - 8000f9c: 687b ldr r3, [r7, #4] - 8000f9e: 4a06 ldr r2, [pc, #24] @ (8000fb8 ) - 8000fa0: 641a str r2, [r3, #64] @ 0x40 + 80016ec: 687b ldr r3, [r7, #4] + 80016ee: 4a06 ldr r2, [pc, #24] @ (8001708 ) + 80016f0: 641a str r2, [r3, #64] @ 0x40 hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; /* Legacy weak RxFifo0FullCallback */ - 8000fa2: 687b ldr r3, [r7, #4] - 8000fa4: 4a05 ldr r2, [pc, #20] @ (8000fbc ) - 8000fa6: 645a str r2, [r3, #68] @ 0x44 - 8000fa8: e00a b.n 8000fc0 - 8000faa: bf00 nop - 8000fac: 40006400 .word 0x40006400 - 8000fb0: 40006800 .word 0x40006800 - 8000fb4: 08005be8 .word 0x08005be8 - 8000fb8: 08001295 .word 0x08001295 - 8000fbc: 080012a9 .word 0x080012a9 + 80016f2: 687b ldr r3, [r7, #4] + 80016f4: 4a05 ldr r2, [pc, #20] @ (800170c ) + 80016f6: 645a str r2, [r3, #68] @ 0x44 + 80016f8: e00a b.n 8001710 + 80016fa: bf00 nop + 80016fc: 40006400 .word 0x40006400 + 8001700: 40006800 .word 0x40006800 + 8001704: 0800a0bc .word 0x0800a0bc + 8001708: 080005b9 .word 0x080005b9 + 800170c: 08001fc5 .word 0x08001fc5 hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; /* Legacy weak RxFifo1MsgPendingCallback */ - 8000fc0: 687b ldr r3, [r7, #4] - 8000fc2: 4a8a ldr r2, [pc, #552] @ (80011ec ) - 8000fc4: 649a str r2, [r3, #72] @ 0x48 + 8001710: 687b ldr r3, [r7, #4] + 8001712: 4a8a ldr r2, [pc, #552] @ (800193c ) + 8001714: 649a str r2, [r3, #72] @ 0x48 hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; /* Legacy weak RxFifo1FullCallback */ - 8000fc6: 687b ldr r3, [r7, #4] - 8000fc8: 4a89 ldr r2, [pc, #548] @ (80011f0 ) - 8000fca: 64da str r2, [r3, #76] @ 0x4c + 8001716: 687b ldr r3, [r7, #4] + 8001718: 4a89 ldr r2, [pc, #548] @ (8001940 ) + 800171a: 64da str r2, [r3, #76] @ 0x4c hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; /* Legacy weak TxMailbox0CompleteCallback */ - 8000fcc: 687b ldr r3, [r7, #4] - 8000fce: 4a89 ldr r2, [pc, #548] @ (80011f4 ) - 8000fd0: 629a str r2, [r3, #40] @ 0x28 + 800171c: 687b ldr r3, [r7, #4] + 800171e: 4a89 ldr r2, [pc, #548] @ (8001944 ) + 8001720: 629a str r2, [r3, #40] @ 0x28 hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; /* Legacy weak TxMailbox1CompleteCallback */ - 8000fd2: 687b ldr r3, [r7, #4] - 8000fd4: 4a88 ldr r2, [pc, #544] @ (80011f8 ) - 8000fd6: 62da str r2, [r3, #44] @ 0x2c + 8001722: 687b ldr r3, [r7, #4] + 8001724: 4a88 ldr r2, [pc, #544] @ (8001948 ) + 8001726: 62da str r2, [r3, #44] @ 0x2c hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; /* Legacy weak TxMailbox2CompleteCallback */ - 8000fd8: 687b ldr r3, [r7, #4] - 8000fda: 4a88 ldr r2, [pc, #544] @ (80011fc ) - 8000fdc: 631a str r2, [r3, #48] @ 0x30 + 8001728: 687b ldr r3, [r7, #4] + 800172a: 4a88 ldr r2, [pc, #544] @ (800194c ) + 800172c: 631a str r2, [r3, #48] @ 0x30 hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; /* Legacy weak TxMailbox0AbortCallback */ - 8000fde: 687b ldr r3, [r7, #4] - 8000fe0: 4a87 ldr r2, [pc, #540] @ (8001200 ) - 8000fe2: 635a str r2, [r3, #52] @ 0x34 + 800172e: 687b ldr r3, [r7, #4] + 8001730: 4a87 ldr r2, [pc, #540] @ (8001950 ) + 8001732: 635a str r2, [r3, #52] @ 0x34 hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; /* Legacy weak TxMailbox1AbortCallback */ - 8000fe4: 687b ldr r3, [r7, #4] - 8000fe6: 4a87 ldr r2, [pc, #540] @ (8001204 ) - 8000fe8: 639a str r2, [r3, #56] @ 0x38 + 8001734: 687b ldr r3, [r7, #4] + 8001736: 4a87 ldr r2, [pc, #540] @ (8001954 ) + 8001738: 639a str r2, [r3, #56] @ 0x38 hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; /* Legacy weak TxMailbox2AbortCallback */ - 8000fea: 687b ldr r3, [r7, #4] - 8000fec: 4a86 ldr r2, [pc, #536] @ (8001208 ) - 8000fee: 63da str r2, [r3, #60] @ 0x3c + 800173a: 687b ldr r3, [r7, #4] + 800173c: 4a86 ldr r2, [pc, #536] @ (8001958 ) + 800173e: 63da str r2, [r3, #60] @ 0x3c hcan->SleepCallback = HAL_CAN_SleepCallback; /* Legacy weak SleepCallback */ - 8000ff0: 687b ldr r3, [r7, #4] - 8000ff2: 4a86 ldr r2, [pc, #536] @ (800120c ) - 8000ff4: 651a str r2, [r3, #80] @ 0x50 + 8001740: 687b ldr r3, [r7, #4] + 8001742: 4a86 ldr r2, [pc, #536] @ (800195c ) + 8001744: 651a str r2, [r3, #80] @ 0x50 hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; /* Legacy weak WakeUpFromRxMsgCallback */ - 8000ff6: 687b ldr r3, [r7, #4] - 8000ff8: 4a85 ldr r2, [pc, #532] @ (8001210 ) - 8000ffa: 655a str r2, [r3, #84] @ 0x54 + 8001746: 687b ldr r3, [r7, #4] + 8001748: 4a85 ldr r2, [pc, #532] @ (8001960 ) + 800174a: 655a str r2, [r3, #84] @ 0x54 hcan->ErrorCallback = HAL_CAN_ErrorCallback; /* Legacy weak ErrorCallback */ - 8000ffc: 687b ldr r3, [r7, #4] - 8000ffe: 4a85 ldr r2, [pc, #532] @ (8001214 ) - 8001000: 659a str r2, [r3, #88] @ 0x58 + 800174c: 687b ldr r3, [r7, #4] + 800174e: 4a85 ldr r2, [pc, #532] @ (8001964 ) + 8001750: 659a str r2, [r3, #88] @ 0x58 if (hcan->MspInitCallback == NULL) - 8001002: 687b ldr r3, [r7, #4] - 8001004: 6ddb ldr r3, [r3, #92] @ 0x5c - 8001006: 2b00 cmp r3, #0 - 8001008: d102 bne.n 8001010 + 8001752: 687b ldr r3, [r7, #4] + 8001754: 6ddb ldr r3, [r3, #92] @ 0x5c + 8001756: 2b00 cmp r3, #0 + 8001758: d102 bne.n 8001760 { hcan->MspInitCallback = HAL_CAN_MspInit; /* Legacy weak MspInit */ - 800100a: 687b ldr r3, [r7, #4] - 800100c: 4a82 ldr r2, [pc, #520] @ (8001218 ) - 800100e: 65da str r2, [r3, #92] @ 0x5c + 800175a: 687b ldr r3, [r7, #4] + 800175c: 4a82 ldr r2, [pc, #520] @ (8001968 ) + 800175e: 65da str r2, [r3, #92] @ 0x5c } /* Init the low level hardware: CLOCK, NVIC */ hcan->MspInitCallback(hcan); - 8001010: 687b ldr r3, [r7, #4] - 8001012: 6ddb ldr r3, [r3, #92] @ 0x5c - 8001014: 6878 ldr r0, [r7, #4] - 8001016: 4798 blx r3 + 8001760: 687b ldr r3, [r7, #4] + 8001762: 6ddb ldr r3, [r3, #92] @ 0x5c + 8001764: 6878 ldr r0, [r7, #4] + 8001766: 4798 blx r3 HAL_CAN_MspInit(hcan); } #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - 8001018: 687b ldr r3, [r7, #4] - 800101a: 681b ldr r3, [r3, #0] - 800101c: 681a ldr r2, [r3, #0] - 800101e: 687b ldr r3, [r7, #4] - 8001020: 681b ldr r3, [r3, #0] - 8001022: f042 0201 orr.w r2, r2, #1 - 8001026: 601a str r2, [r3, #0] + 8001768: 687b ldr r3, [r7, #4] + 800176a: 681b ldr r3, [r3, #0] + 800176c: 681a ldr r2, [r3, #0] + 800176e: 687b ldr r3, [r7, #4] + 8001770: 681b ldr r3, [r3, #0] + 8001772: f042 0201 orr.w r2, r2, #1 + 8001776: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); - 8001028: f7ff fe82 bl 8000d30 - 800102c: 60f8 str r0, [r7, #12] + 8001778: f7ff fe5e bl 8001438 + 800177c: 60f8 str r0, [r7, #12] /* Wait initialisation acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) - 800102e: e012 b.n 8001056 + 800177e: e012 b.n 80017a6 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - 8001030: f7ff fe7e bl 8000d30 - 8001034: 4602 mov r2, r0 - 8001036: 68fb ldr r3, [r7, #12] - 8001038: 1ad3 subs r3, r2, r3 - 800103a: 2b0a cmp r3, #10 - 800103c: d90b bls.n 8001056 + 8001780: f7ff fe5a bl 8001438 + 8001784: 4602 mov r2, r0 + 8001786: 68fb ldr r3, [r7, #12] + 8001788: 1ad3 subs r3, r2, r3 + 800178a: 2b0a cmp r3, #10 + 800178c: d90b bls.n 80017a6 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - 800103e: 687b ldr r3, [r7, #4] - 8001040: 6a5b ldr r3, [r3, #36] @ 0x24 - 8001042: f443 3200 orr.w r2, r3, #131072 @ 0x20000 - 8001046: 687b ldr r3, [r7, #4] - 8001048: 625a str r2, [r3, #36] @ 0x24 + 800178e: 687b ldr r3, [r7, #4] + 8001790: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001792: f443 3200 orr.w r2, r3, #131072 @ 0x20000 + 8001796: 687b ldr r3, [r7, #4] + 8001798: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; - 800104a: 687b ldr r3, [r7, #4] - 800104c: 2205 movs r2, #5 - 800104e: f883 2020 strb.w r2, [r3, #32] + 800179a: 687b ldr r3, [r7, #4] + 800179c: 2205 movs r2, #5 + 800179e: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; - 8001052: 2301 movs r3, #1 - 8001054: e0c5 b.n 80011e2 + 80017a2: 2301 movs r3, #1 + 80017a4: e0c5 b.n 8001932 while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) - 8001056: 687b ldr r3, [r7, #4] - 8001058: 681b ldr r3, [r3, #0] - 800105a: 685b ldr r3, [r3, #4] - 800105c: f003 0301 and.w r3, r3, #1 - 8001060: 2b00 cmp r3, #0 - 8001062: d0e5 beq.n 8001030 + 80017a6: 687b ldr r3, [r7, #4] + 80017a8: 681b ldr r3, [r3, #0] + 80017aa: 685b ldr r3, [r3, #4] + 80017ac: f003 0301 and.w r3, r3, #1 + 80017b0: 2b00 cmp r3, #0 + 80017b2: d0e5 beq.n 8001780 } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); - 8001064: 687b ldr r3, [r7, #4] - 8001066: 681b ldr r3, [r3, #0] - 8001068: 681a ldr r2, [r3, #0] - 800106a: 687b ldr r3, [r7, #4] - 800106c: 681b ldr r3, [r3, #0] - 800106e: f022 0202 bic.w r2, r2, #2 - 8001072: 601a str r2, [r3, #0] + 80017b4: 687b ldr r3, [r7, #4] + 80017b6: 681b ldr r3, [r3, #0] + 80017b8: 681a ldr r2, [r3, #0] + 80017ba: 687b ldr r3, [r7, #4] + 80017bc: 681b ldr r3, [r3, #0] + 80017be: f022 0202 bic.w r2, r2, #2 + 80017c2: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); - 8001074: f7ff fe5c bl 8000d30 - 8001078: 60f8 str r0, [r7, #12] + 80017c4: f7ff fe38 bl 8001438 + 80017c8: 60f8 str r0, [r7, #12] /* Check Sleep mode leave acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) - 800107a: e012 b.n 80010a2 + 80017ca: e012 b.n 80017f2 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - 800107c: f7ff fe58 bl 8000d30 - 8001080: 4602 mov r2, r0 - 8001082: 68fb ldr r3, [r7, #12] - 8001084: 1ad3 subs r3, r2, r3 - 8001086: 2b0a cmp r3, #10 - 8001088: d90b bls.n 80010a2 + 80017cc: f7ff fe34 bl 8001438 + 80017d0: 4602 mov r2, r0 + 80017d2: 68fb ldr r3, [r7, #12] + 80017d4: 1ad3 subs r3, r2, r3 + 80017d6: 2b0a cmp r3, #10 + 80017d8: d90b bls.n 80017f2 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - 800108a: 687b ldr r3, [r7, #4] - 800108c: 6a5b ldr r3, [r3, #36] @ 0x24 - 800108e: f443 3200 orr.w r2, r3, #131072 @ 0x20000 - 8001092: 687b ldr r3, [r7, #4] - 8001094: 625a str r2, [r3, #36] @ 0x24 + 80017da: 687b ldr r3, [r7, #4] + 80017dc: 6a5b ldr r3, [r3, #36] @ 0x24 + 80017de: f443 3200 orr.w r2, r3, #131072 @ 0x20000 + 80017e2: 687b ldr r3, [r7, #4] + 80017e4: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; - 8001096: 687b ldr r3, [r7, #4] - 8001098: 2205 movs r2, #5 - 800109a: f883 2020 strb.w r2, [r3, #32] + 80017e6: 687b ldr r3, [r7, #4] + 80017e8: 2205 movs r2, #5 + 80017ea: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; - 800109e: 2301 movs r3, #1 - 80010a0: e09f b.n 80011e2 + 80017ee: 2301 movs r3, #1 + 80017f0: e09f b.n 8001932 while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) - 80010a2: 687b ldr r3, [r7, #4] - 80010a4: 681b ldr r3, [r3, #0] - 80010a6: 685b ldr r3, [r3, #4] - 80010a8: f003 0302 and.w r3, r3, #2 - 80010ac: 2b00 cmp r3, #0 - 80010ae: d1e5 bne.n 800107c + 80017f2: 687b ldr r3, [r7, #4] + 80017f4: 681b ldr r3, [r3, #0] + 80017f6: 685b ldr r3, [r3, #4] + 80017f8: f003 0302 and.w r3, r3, #2 + 80017fc: 2b00 cmp r3, #0 + 80017fe: d1e5 bne.n 80017cc } } /* Set the time triggered communication mode */ if (hcan->Init.TimeTriggeredMode == ENABLE) - 80010b0: 687b ldr r3, [r7, #4] - 80010b2: 7e1b ldrb r3, [r3, #24] - 80010b4: 2b01 cmp r3, #1 - 80010b6: d108 bne.n 80010ca + 8001800: 687b ldr r3, [r7, #4] + 8001802: 7e1b ldrb r3, [r3, #24] + 8001804: 2b01 cmp r3, #1 + 8001806: d108 bne.n 800181a { SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); - 80010b8: 687b ldr r3, [r7, #4] - 80010ba: 681b ldr r3, [r3, #0] - 80010bc: 681a ldr r2, [r3, #0] - 80010be: 687b ldr r3, [r7, #4] - 80010c0: 681b ldr r3, [r3, #0] - 80010c2: f042 0280 orr.w r2, r2, #128 @ 0x80 - 80010c6: 601a str r2, [r3, #0] - 80010c8: e007 b.n 80010da + 8001808: 687b ldr r3, [r7, #4] + 800180a: 681b ldr r3, [r3, #0] + 800180c: 681a ldr r2, [r3, #0] + 800180e: 687b ldr r3, [r7, #4] + 8001810: 681b ldr r3, [r3, #0] + 8001812: f042 0280 orr.w r2, r2, #128 @ 0x80 + 8001816: 601a str r2, [r3, #0] + 8001818: e007 b.n 800182a } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); - 80010ca: 687b ldr r3, [r7, #4] - 80010cc: 681b ldr r3, [r3, #0] - 80010ce: 681a ldr r2, [r3, #0] - 80010d0: 687b ldr r3, [r7, #4] - 80010d2: 681b ldr r3, [r3, #0] - 80010d4: f022 0280 bic.w r2, r2, #128 @ 0x80 - 80010d8: 601a str r2, [r3, #0] + 800181a: 687b ldr r3, [r7, #4] + 800181c: 681b ldr r3, [r3, #0] + 800181e: 681a ldr r2, [r3, #0] + 8001820: 687b ldr r3, [r7, #4] + 8001822: 681b ldr r3, [r3, #0] + 8001824: f022 0280 bic.w r2, r2, #128 @ 0x80 + 8001828: 601a str r2, [r3, #0] } /* Set the automatic bus-off management */ if (hcan->Init.AutoBusOff == ENABLE) - 80010da: 687b ldr r3, [r7, #4] - 80010dc: 7e5b ldrb r3, [r3, #25] - 80010de: 2b01 cmp r3, #1 - 80010e0: d108 bne.n 80010f4 + 800182a: 687b ldr r3, [r7, #4] + 800182c: 7e5b ldrb r3, [r3, #25] + 800182e: 2b01 cmp r3, #1 + 8001830: d108 bne.n 8001844 { SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); - 80010e2: 687b ldr r3, [r7, #4] - 80010e4: 681b ldr r3, [r3, #0] - 80010e6: 681a ldr r2, [r3, #0] - 80010e8: 687b ldr r3, [r7, #4] - 80010ea: 681b ldr r3, [r3, #0] - 80010ec: f042 0240 orr.w r2, r2, #64 @ 0x40 - 80010f0: 601a str r2, [r3, #0] - 80010f2: e007 b.n 8001104 + 8001832: 687b ldr r3, [r7, #4] + 8001834: 681b ldr r3, [r3, #0] + 8001836: 681a ldr r2, [r3, #0] + 8001838: 687b ldr r3, [r7, #4] + 800183a: 681b ldr r3, [r3, #0] + 800183c: f042 0240 orr.w r2, r2, #64 @ 0x40 + 8001840: 601a str r2, [r3, #0] + 8001842: e007 b.n 8001854 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); - 80010f4: 687b ldr r3, [r7, #4] - 80010f6: 681b ldr r3, [r3, #0] - 80010f8: 681a ldr r2, [r3, #0] - 80010fa: 687b ldr r3, [r7, #4] - 80010fc: 681b ldr r3, [r3, #0] - 80010fe: f022 0240 bic.w r2, r2, #64 @ 0x40 - 8001102: 601a str r2, [r3, #0] + 8001844: 687b ldr r3, [r7, #4] + 8001846: 681b ldr r3, [r3, #0] + 8001848: 681a ldr r2, [r3, #0] + 800184a: 687b ldr r3, [r7, #4] + 800184c: 681b ldr r3, [r3, #0] + 800184e: f022 0240 bic.w r2, r2, #64 @ 0x40 + 8001852: 601a str r2, [r3, #0] } /* Set the automatic wake-up mode */ if (hcan->Init.AutoWakeUp == ENABLE) - 8001104: 687b ldr r3, [r7, #4] - 8001106: 7e9b ldrb r3, [r3, #26] - 8001108: 2b01 cmp r3, #1 - 800110a: d108 bne.n 800111e + 8001854: 687b ldr r3, [r7, #4] + 8001856: 7e9b ldrb r3, [r3, #26] + 8001858: 2b01 cmp r3, #1 + 800185a: d108 bne.n 800186e { SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); - 800110c: 687b ldr r3, [r7, #4] - 800110e: 681b ldr r3, [r3, #0] - 8001110: 681a ldr r2, [r3, #0] - 8001112: 687b ldr r3, [r7, #4] - 8001114: 681b ldr r3, [r3, #0] - 8001116: f042 0220 orr.w r2, r2, #32 - 800111a: 601a str r2, [r3, #0] - 800111c: e007 b.n 800112e + 800185c: 687b ldr r3, [r7, #4] + 800185e: 681b ldr r3, [r3, #0] + 8001860: 681a ldr r2, [r3, #0] + 8001862: 687b ldr r3, [r7, #4] + 8001864: 681b ldr r3, [r3, #0] + 8001866: f042 0220 orr.w r2, r2, #32 + 800186a: 601a str r2, [r3, #0] + 800186c: e007 b.n 800187e } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); - 800111e: 687b ldr r3, [r7, #4] - 8001120: 681b ldr r3, [r3, #0] - 8001122: 681a ldr r2, [r3, #0] - 8001124: 687b ldr r3, [r7, #4] - 8001126: 681b ldr r3, [r3, #0] - 8001128: f022 0220 bic.w r2, r2, #32 - 800112c: 601a str r2, [r3, #0] + 800186e: 687b ldr r3, [r7, #4] + 8001870: 681b ldr r3, [r3, #0] + 8001872: 681a ldr r2, [r3, #0] + 8001874: 687b ldr r3, [r7, #4] + 8001876: 681b ldr r3, [r3, #0] + 8001878: f022 0220 bic.w r2, r2, #32 + 800187c: 601a str r2, [r3, #0] } /* Set the automatic retransmission */ if (hcan->Init.AutoRetransmission == ENABLE) - 800112e: 687b ldr r3, [r7, #4] - 8001130: 7edb ldrb r3, [r3, #27] - 8001132: 2b01 cmp r3, #1 - 8001134: d108 bne.n 8001148 + 800187e: 687b ldr r3, [r7, #4] + 8001880: 7edb ldrb r3, [r3, #27] + 8001882: 2b01 cmp r3, #1 + 8001884: d108 bne.n 8001898 { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); - 8001136: 687b ldr r3, [r7, #4] - 8001138: 681b ldr r3, [r3, #0] - 800113a: 681a ldr r2, [r3, #0] - 800113c: 687b ldr r3, [r7, #4] - 800113e: 681b ldr r3, [r3, #0] - 8001140: f022 0210 bic.w r2, r2, #16 - 8001144: 601a str r2, [r3, #0] - 8001146: e007 b.n 8001158 + 8001886: 687b ldr r3, [r7, #4] + 8001888: 681b ldr r3, [r3, #0] + 800188a: 681a ldr r2, [r3, #0] + 800188c: 687b ldr r3, [r7, #4] + 800188e: 681b ldr r3, [r3, #0] + 8001890: f022 0210 bic.w r2, r2, #16 + 8001894: 601a str r2, [r3, #0] + 8001896: e007 b.n 80018a8 } else { SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); - 8001148: 687b ldr r3, [r7, #4] - 800114a: 681b ldr r3, [r3, #0] - 800114c: 681a ldr r2, [r3, #0] - 800114e: 687b ldr r3, [r7, #4] - 8001150: 681b ldr r3, [r3, #0] - 8001152: f042 0210 orr.w r2, r2, #16 - 8001156: 601a str r2, [r3, #0] + 8001898: 687b ldr r3, [r7, #4] + 800189a: 681b ldr r3, [r3, #0] + 800189c: 681a ldr r2, [r3, #0] + 800189e: 687b ldr r3, [r7, #4] + 80018a0: 681b ldr r3, [r3, #0] + 80018a2: f042 0210 orr.w r2, r2, #16 + 80018a6: 601a str r2, [r3, #0] } /* Set the receive FIFO locked mode */ if (hcan->Init.ReceiveFifoLocked == ENABLE) - 8001158: 687b ldr r3, [r7, #4] - 800115a: 7f1b ldrb r3, [r3, #28] - 800115c: 2b01 cmp r3, #1 - 800115e: d108 bne.n 8001172 + 80018a8: 687b ldr r3, [r7, #4] + 80018aa: 7f1b ldrb r3, [r3, #28] + 80018ac: 2b01 cmp r3, #1 + 80018ae: d108 bne.n 80018c2 { SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); - 8001160: 687b ldr r3, [r7, #4] - 8001162: 681b ldr r3, [r3, #0] - 8001164: 681a ldr r2, [r3, #0] - 8001166: 687b ldr r3, [r7, #4] - 8001168: 681b ldr r3, [r3, #0] - 800116a: f042 0208 orr.w r2, r2, #8 - 800116e: 601a str r2, [r3, #0] - 8001170: e007 b.n 8001182 + 80018b0: 687b ldr r3, [r7, #4] + 80018b2: 681b ldr r3, [r3, #0] + 80018b4: 681a ldr r2, [r3, #0] + 80018b6: 687b ldr r3, [r7, #4] + 80018b8: 681b ldr r3, [r3, #0] + 80018ba: f042 0208 orr.w r2, r2, #8 + 80018be: 601a str r2, [r3, #0] + 80018c0: e007 b.n 80018d2 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); - 8001172: 687b ldr r3, [r7, #4] - 8001174: 681b ldr r3, [r3, #0] - 8001176: 681a ldr r2, [r3, #0] - 8001178: 687b ldr r3, [r7, #4] - 800117a: 681b ldr r3, [r3, #0] - 800117c: f022 0208 bic.w r2, r2, #8 - 8001180: 601a str r2, [r3, #0] + 80018c2: 687b ldr r3, [r7, #4] + 80018c4: 681b ldr r3, [r3, #0] + 80018c6: 681a ldr r2, [r3, #0] + 80018c8: 687b ldr r3, [r7, #4] + 80018ca: 681b ldr r3, [r3, #0] + 80018cc: f022 0208 bic.w r2, r2, #8 + 80018d0: 601a str r2, [r3, #0] } /* Set the transmit FIFO priority */ if (hcan->Init.TransmitFifoPriority == ENABLE) - 8001182: 687b ldr r3, [r7, #4] - 8001184: 7f5b ldrb r3, [r3, #29] - 8001186: 2b01 cmp r3, #1 - 8001188: d108 bne.n 800119c + 80018d2: 687b ldr r3, [r7, #4] + 80018d4: 7f5b ldrb r3, [r3, #29] + 80018d6: 2b01 cmp r3, #1 + 80018d8: d108 bne.n 80018ec { SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); - 800118a: 687b ldr r3, [r7, #4] - 800118c: 681b ldr r3, [r3, #0] - 800118e: 681a ldr r2, [r3, #0] - 8001190: 687b ldr r3, [r7, #4] - 8001192: 681b ldr r3, [r3, #0] - 8001194: f042 0204 orr.w r2, r2, #4 - 8001198: 601a str r2, [r3, #0] - 800119a: e007 b.n 80011ac + 80018da: 687b ldr r3, [r7, #4] + 80018dc: 681b ldr r3, [r3, #0] + 80018de: 681a ldr r2, [r3, #0] + 80018e0: 687b ldr r3, [r7, #4] + 80018e2: 681b ldr r3, [r3, #0] + 80018e4: f042 0204 orr.w r2, r2, #4 + 80018e8: 601a str r2, [r3, #0] + 80018ea: e007 b.n 80018fc } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); - 800119c: 687b ldr r3, [r7, #4] - 800119e: 681b ldr r3, [r3, #0] - 80011a0: 681a ldr r2, [r3, #0] - 80011a2: 687b ldr r3, [r7, #4] - 80011a4: 681b ldr r3, [r3, #0] - 80011a6: f022 0204 bic.w r2, r2, #4 - 80011aa: 601a str r2, [r3, #0] + 80018ec: 687b ldr r3, [r7, #4] + 80018ee: 681b ldr r3, [r3, #0] + 80018f0: 681a ldr r2, [r3, #0] + 80018f2: 687b ldr r3, [r7, #4] + 80018f4: 681b ldr r3, [r3, #0] + 80018f6: f022 0204 bic.w r2, r2, #4 + 80018fa: 601a str r2, [r3, #0] } /* Set the bit timing register */ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | - 80011ac: 687b ldr r3, [r7, #4] - 80011ae: 689a ldr r2, [r3, #8] - 80011b0: 687b ldr r3, [r7, #4] - 80011b2: 68db ldr r3, [r3, #12] - 80011b4: 431a orrs r2, r3 - 80011b6: 687b ldr r3, [r7, #4] - 80011b8: 691b ldr r3, [r3, #16] - 80011ba: 431a orrs r2, r3 - 80011bc: 687b ldr r3, [r7, #4] - 80011be: 695b ldr r3, [r3, #20] - 80011c0: ea42 0103 orr.w r1, r2, r3 - 80011c4: 687b ldr r3, [r7, #4] - 80011c6: 685b ldr r3, [r3, #4] - 80011c8: 1e5a subs r2, r3, #1 - 80011ca: 687b ldr r3, [r7, #4] - 80011cc: 681b ldr r3, [r3, #0] - 80011ce: 430a orrs r2, r1 - 80011d0: 61da str r2, [r3, #28] + 80018fc: 687b ldr r3, [r7, #4] + 80018fe: 689a ldr r2, [r3, #8] + 8001900: 687b ldr r3, [r7, #4] + 8001902: 68db ldr r3, [r3, #12] + 8001904: 431a orrs r2, r3 + 8001906: 687b ldr r3, [r7, #4] + 8001908: 691b ldr r3, [r3, #16] + 800190a: 431a orrs r2, r3 + 800190c: 687b ldr r3, [r7, #4] + 800190e: 695b ldr r3, [r3, #20] + 8001910: ea42 0103 orr.w r1, r2, r3 + 8001914: 687b ldr r3, [r7, #4] + 8001916: 685b ldr r3, [r3, #4] + 8001918: 1e5a subs r2, r3, #1 + 800191a: 687b ldr r3, [r7, #4] + 800191c: 681b ldr r3, [r3, #0] + 800191e: 430a orrs r2, r1 + 8001920: 61da str r2, [r3, #28] hcan->Init.TimeSeg1 | hcan->Init.TimeSeg2 | (hcan->Init.Prescaler - 1U))); /* Initialize the error code */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; - 80011d2: 687b ldr r3, [r7, #4] - 80011d4: 2200 movs r2, #0 - 80011d6: 625a str r2, [r3, #36] @ 0x24 + 8001922: 687b ldr r3, [r7, #4] + 8001924: 2200 movs r2, #0 + 8001926: 625a str r2, [r3, #36] @ 0x24 /* Initialize the CAN state */ hcan->State = HAL_CAN_STATE_READY; - 80011d8: 687b ldr r3, [r7, #4] - 80011da: 2201 movs r2, #1 - 80011dc: f883 2020 strb.w r2, [r3, #32] + 8001928: 687b ldr r3, [r7, #4] + 800192a: 2201 movs r2, #1 + 800192c: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; - 80011e0: 2300 movs r3, #0 + 8001930: 2300 movs r3, #0 } - 80011e2: 4618 mov r0, r3 - 80011e4: 3710 adds r7, #16 - 80011e6: 46bd mov sp, r7 - 80011e8: bd80 pop {r7, pc} - 80011ea: bf00 nop - 80011ec: 080012bd .word 0x080012bd - 80011f0: 080012d1 .word 0x080012d1 - 80011f4: 0800121d .word 0x0800121d - 80011f8: 08001231 .word 0x08001231 - 80011fc: 08001245 .word 0x08001245 - 8001200: 08001259 .word 0x08001259 - 8001204: 0800126d .word 0x0800126d - 8001208: 08001281 .word 0x08001281 - 800120c: 080012e5 .word 0x080012e5 - 8001210: 080012f9 .word 0x080012f9 - 8001214: 0800130d .word 0x0800130d - 8001218: 080008b9 .word 0x080008b9 + 8001932: 4618 mov r0, r3 + 8001934: 3710 adds r7, #16 + 8001936: 46bd mov sp, r7 + 8001938: bd80 pop {r7, pc} + 800193a: bf00 nop + 800193c: 08001fd9 .word 0x08001fd9 + 8001940: 08001fed .word 0x08001fed + 8001944: 08001f4d .word 0x08001f4d + 8001948: 08001f61 .word 0x08001f61 + 800194c: 08001f75 .word 0x08001f75 + 8001950: 08001f89 .word 0x08001f89 + 8001954: 08001f9d .word 0x08001f9d + 8001958: 08001fb1 .word 0x08001fb1 + 800195c: 08002001 .word 0x08002001 + 8001960: 08002015 .word 0x08002015 + 8001964: 08002029 .word 0x08002029 + 8001968: 08000da5 .word 0x08000da5 -0800121c : +0800196c : + * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that + * contains the filter configuration information. + * @retval None + */ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig) +{ + 800196c: b580 push {r7, lr} + 800196e: b086 sub sp, #24 + 8001970: af00 add r7, sp, #0 + 8001972: 6078 str r0, [r7, #4] + 8001974: 6039 str r1, [r7, #0] + uint32_t filternbrbitpos; + CAN_TypeDef *can_ip; + HAL_CAN_StateTypeDef state = hcan->State; + 8001976: 687b ldr r3, [r7, #4] + 8001978: f893 3020 ldrb.w r3, [r3, #32] + 800197c: 75fb strb r3, [r7, #23] + + if ((state == HAL_CAN_STATE_READY) || + 800197e: 7dfb ldrb r3, [r7, #23] + 8001980: 2b01 cmp r3, #1 + 8001982: d003 beq.n 800198c + 8001984: 7dfb ldrb r3, [r7, #23] + 8001986: 2b02 cmp r3, #2 + 8001988: f040 812c bne.w 8001be4 + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check the parameters */ + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh)); + 800198c: 683b ldr r3, [r7, #0] + 800198e: 681b ldr r3, [r3, #0] + 8001990: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8001994: d304 bcc.n 80019a0 + 8001996: f240 3152 movw r1, #850 @ 0x352 + 800199a: 4898 ldr r0, [pc, #608] @ (8001bfc ) + 800199c: f7ff f9ca bl 8000d34 + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow)); + 80019a0: 683b ldr r3, [r7, #0] + 80019a2: 685b ldr r3, [r3, #4] + 80019a4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 80019a8: d304 bcc.n 80019b4 + 80019aa: f240 3153 movw r1, #851 @ 0x353 + 80019ae: 4893 ldr r0, [pc, #588] @ (8001bfc ) + 80019b0: f7ff f9c0 bl 8000d34 + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh)); + 80019b4: 683b ldr r3, [r7, #0] + 80019b6: 689b ldr r3, [r3, #8] + 80019b8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 80019bc: d304 bcc.n 80019c8 + 80019be: f44f 7155 mov.w r1, #852 @ 0x354 + 80019c2: 488e ldr r0, [pc, #568] @ (8001bfc ) + 80019c4: f7ff f9b6 bl 8000d34 + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow)); + 80019c8: 683b ldr r3, [r7, #0] + 80019ca: 68db ldr r3, [r3, #12] + 80019cc: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 80019d0: d304 bcc.n 80019dc + 80019d2: f240 3155 movw r1, #853 @ 0x355 + 80019d6: 4889 ldr r0, [pc, #548] @ (8001bfc ) + 80019d8: f7ff f9ac bl 8000d34 + assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); + 80019dc: 683b ldr r3, [r7, #0] + 80019de: 699b ldr r3, [r3, #24] + 80019e0: 2b00 cmp r3, #0 + 80019e2: d008 beq.n 80019f6 + 80019e4: 683b ldr r3, [r7, #0] + 80019e6: 699b ldr r3, [r3, #24] + 80019e8: 2b01 cmp r3, #1 + 80019ea: d004 beq.n 80019f6 + 80019ec: f240 3156 movw r1, #854 @ 0x356 + 80019f0: 4882 ldr r0, [pc, #520] @ (8001bfc ) + 80019f2: f7ff f99f bl 8000d34 + assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); + 80019f6: 683b ldr r3, [r7, #0] + 80019f8: 69db ldr r3, [r3, #28] + 80019fa: 2b00 cmp r3, #0 + 80019fc: d008 beq.n 8001a10 + 80019fe: 683b ldr r3, [r7, #0] + 8001a00: 69db ldr r3, [r3, #28] + 8001a02: 2b01 cmp r3, #1 + 8001a04: d004 beq.n 8001a10 + 8001a06: f240 3157 movw r1, #855 @ 0x357 + 8001a0a: 487c ldr r0, [pc, #496] @ (8001bfc ) + 8001a0c: f7ff f992 bl 8000d34 + assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); + 8001a10: 683b ldr r3, [r7, #0] + 8001a12: 691b ldr r3, [r3, #16] + 8001a14: 2b00 cmp r3, #0 + 8001a16: d008 beq.n 8001a2a + 8001a18: 683b ldr r3, [r7, #0] + 8001a1a: 691b ldr r3, [r3, #16] + 8001a1c: 2b01 cmp r3, #1 + 8001a1e: d004 beq.n 8001a2a + 8001a20: f44f 7156 mov.w r1, #856 @ 0x358 + 8001a24: 4875 ldr r0, [pc, #468] @ (8001bfc ) + 8001a26: f7ff f985 bl 8000d34 + assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); + 8001a2a: 683b ldr r3, [r7, #0] + 8001a2c: 6a1b ldr r3, [r3, #32] + 8001a2e: 2b00 cmp r3, #0 + 8001a30: d008 beq.n 8001a44 + 8001a32: 683b ldr r3, [r7, #0] + 8001a34: 6a1b ldr r3, [r3, #32] + 8001a36: 2b01 cmp r3, #1 + 8001a38: d004 beq.n 8001a44 + 8001a3a: f240 3159 movw r1, #857 @ 0x359 + 8001a3e: 486f ldr r0, [pc, #444] @ (8001bfc ) + 8001a40: f7ff f978 bl 8000d34 + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank)); + } +#elif defined(CAN2) + /* CAN1 and CAN2 are dual instances with 28 common filters banks */ + /* Select master instance to access the filter banks */ + can_ip = CAN1; + 8001a44: 4b6e ldr r3, [pc, #440] @ (8001c00 ) + 8001a46: 613b str r3, [r7, #16] + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank)); + 8001a48: 683b ldr r3, [r7, #0] + 8001a4a: 695b ldr r3, [r3, #20] + 8001a4c: 2b1b cmp r3, #27 + 8001a4e: d904 bls.n 8001a5a + 8001a50: f240 3175 movw r1, #885 @ 0x375 + 8001a54: 4869 ldr r0, [pc, #420] @ (8001bfc ) + 8001a56: f7ff f96d bl 8000d34 + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank)); + 8001a5a: 683b ldr r3, [r7, #0] + 8001a5c: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001a5e: 2b1b cmp r3, #27 + 8001a60: d904 bls.n 8001a6c + 8001a62: f240 3176 movw r1, #886 @ 0x376 + 8001a66: 4865 ldr r0, [pc, #404] @ (8001bfc ) + 8001a68: f7ff f964 bl 8000d34 + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); +#endif /* CAN3 */ + + /* Initialisation mode for the filter */ + SET_BIT(can_ip->FMR, CAN_FMR_FINIT); + 8001a6c: 693b ldr r3, [r7, #16] + 8001a6e: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 + 8001a72: f043 0201 orr.w r2, r3, #1 + 8001a76: 693b ldr r3, [r7, #16] + 8001a78: f8c3 2200 str.w r2, [r3, #512] @ 0x200 + SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); + } + +#elif defined(CAN2) + /* Select the start filter number of CAN2 slave instance */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); + 8001a7c: 693b ldr r3, [r7, #16] + 8001a7e: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 + 8001a82: f423 527c bic.w r2, r3, #16128 @ 0x3f00 + 8001a86: 693b ldr r3, [r7, #16] + 8001a88: f8c3 2200 str.w r2, [r3, #512] @ 0x200 + SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); + 8001a8c: 693b ldr r3, [r7, #16] + 8001a8e: f8d3 2200 ldr.w r2, [r3, #512] @ 0x200 + 8001a92: 683b ldr r3, [r7, #0] + 8001a94: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001a96: 021b lsls r3, r3, #8 + 8001a98: 431a orrs r2, r3 + 8001a9a: 693b ldr r3, [r7, #16] + 8001a9c: f8c3 2200 str.w r2, [r3, #512] @ 0x200 + +#endif /* CAN3 */ + /* Convert filter number into bit position */ + filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); + 8001aa0: 683b ldr r3, [r7, #0] + 8001aa2: 695b ldr r3, [r3, #20] + 8001aa4: f003 031f and.w r3, r3, #31 + 8001aa8: 2201 movs r2, #1 + 8001aaa: fa02 f303 lsl.w r3, r2, r3 + 8001aae: 60fb str r3, [r7, #12] + + /* Filter Deactivation */ + CLEAR_BIT(can_ip->FA1R, filternbrbitpos); + 8001ab0: 693b ldr r3, [r7, #16] + 8001ab2: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c + 8001ab6: 68fb ldr r3, [r7, #12] + 8001ab8: 43db mvns r3, r3 + 8001aba: 401a ands r2, r3 + 8001abc: 693b ldr r3, [r7, #16] + 8001abe: f8c3 221c str.w r2, [r3, #540] @ 0x21c + + /* Filter Scale */ + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) + 8001ac2: 683b ldr r3, [r7, #0] + 8001ac4: 69db ldr r3, [r3, #28] + 8001ac6: 2b00 cmp r3, #0 + 8001ac8: d123 bne.n 8001b12 + { + /* 16-bit scale for the filter */ + CLEAR_BIT(can_ip->FS1R, filternbrbitpos); + 8001aca: 693b ldr r3, [r7, #16] + 8001acc: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c + 8001ad0: 68fb ldr r3, [r7, #12] + 8001ad2: 43db mvns r3, r3 + 8001ad4: 401a ands r2, r3 + 8001ad6: 693b ldr r3, [r7, #16] + 8001ad8: f8c3 220c str.w r2, [r3, #524] @ 0x20c + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + 8001adc: 683b ldr r3, [r7, #0] + 8001ade: 68db ldr r3, [r3, #12] + 8001ae0: 0419 lsls r1, r3, #16 + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + 8001ae2: 683b ldr r3, [r7, #0] + 8001ae4: 685b ldr r3, [r3, #4] + 8001ae6: b29b uxth r3, r3 + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + 8001ae8: 683a ldr r2, [r7, #0] + 8001aea: 6952 ldr r2, [r2, #20] + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + 8001aec: 4319 orrs r1, r3 + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + 8001aee: 693b ldr r3, [r7, #16] + 8001af0: 3248 adds r2, #72 @ 0x48 + 8001af2: f843 1032 str.w r1, [r3, r2, lsl #3] + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + 8001af6: 683b ldr r3, [r7, #0] + 8001af8: 689b ldr r3, [r3, #8] + 8001afa: 0419 lsls r1, r3, #16 + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); + 8001afc: 683b ldr r3, [r7, #0] + 8001afe: 681b ldr r3, [r3, #0] + 8001b00: b29a uxth r2, r3 + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + 8001b02: 683b ldr r3, [r7, #0] + 8001b04: 695b ldr r3, [r3, #20] + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + 8001b06: 430a orrs r2, r1 + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + 8001b08: 6939 ldr r1, [r7, #16] + 8001b0a: 3348 adds r3, #72 @ 0x48 + 8001b0c: 00db lsls r3, r3, #3 + 8001b0e: 440b add r3, r1 + 8001b10: 605a str r2, [r3, #4] + } + + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) + 8001b12: 683b ldr r3, [r7, #0] + 8001b14: 69db ldr r3, [r3, #28] + 8001b16: 2b01 cmp r3, #1 + 8001b18: d122 bne.n 8001b60 + { + /* 32-bit scale for the filter */ + SET_BIT(can_ip->FS1R, filternbrbitpos); + 8001b1a: 693b ldr r3, [r7, #16] + 8001b1c: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c + 8001b20: 68fb ldr r3, [r7, #12] + 8001b22: 431a orrs r2, r3 + 8001b24: 693b ldr r3, [r7, #16] + 8001b26: f8c3 220c str.w r2, [r3, #524] @ 0x20c + + /* 32-bit identifier or First 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + 8001b2a: 683b ldr r3, [r7, #0] + 8001b2c: 681b ldr r3, [r3, #0] + 8001b2e: 0419 lsls r1, r3, #16 + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + 8001b30: 683b ldr r3, [r7, #0] + 8001b32: 685b ldr r3, [r3, #4] + 8001b34: b29b uxth r3, r3 + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + 8001b36: 683a ldr r2, [r7, #0] + 8001b38: 6952 ldr r2, [r2, #20] + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + 8001b3a: 4319 orrs r1, r3 + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + 8001b3c: 693b ldr r3, [r7, #16] + 8001b3e: 3248 adds r2, #72 @ 0x48 + 8001b40: f843 1032 str.w r1, [r3, r2, lsl #3] + + /* 32-bit mask or Second 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + 8001b44: 683b ldr r3, [r7, #0] + 8001b46: 689b ldr r3, [r3, #8] + 8001b48: 0419 lsls r1, r3, #16 + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); + 8001b4a: 683b ldr r3, [r7, #0] + 8001b4c: 68db ldr r3, [r3, #12] + 8001b4e: b29a uxth r2, r3 + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + 8001b50: 683b ldr r3, [r7, #0] + 8001b52: 695b ldr r3, [r3, #20] + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + 8001b54: 430a orrs r2, r1 + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + 8001b56: 6939 ldr r1, [r7, #16] + 8001b58: 3348 adds r3, #72 @ 0x48 + 8001b5a: 00db lsls r3, r3, #3 + 8001b5c: 440b add r3, r1 + 8001b5e: 605a str r2, [r3, #4] + } + + /* Filter Mode */ + if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) + 8001b60: 683b ldr r3, [r7, #0] + 8001b62: 699b ldr r3, [r3, #24] + 8001b64: 2b00 cmp r3, #0 + 8001b66: d109 bne.n 8001b7c + { + /* Id/Mask mode for the filter*/ + CLEAR_BIT(can_ip->FM1R, filternbrbitpos); + 8001b68: 693b ldr r3, [r7, #16] + 8001b6a: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 + 8001b6e: 68fb ldr r3, [r7, #12] + 8001b70: 43db mvns r3, r3 + 8001b72: 401a ands r2, r3 + 8001b74: 693b ldr r3, [r7, #16] + 8001b76: f8c3 2204 str.w r2, [r3, #516] @ 0x204 + 8001b7a: e007 b.n 8001b8c + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /* Identifier list mode for the filter*/ + SET_BIT(can_ip->FM1R, filternbrbitpos); + 8001b7c: 693b ldr r3, [r7, #16] + 8001b7e: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 + 8001b82: 68fb ldr r3, [r7, #12] + 8001b84: 431a orrs r2, r3 + 8001b86: 693b ldr r3, [r7, #16] + 8001b88: f8c3 2204 str.w r2, [r3, #516] @ 0x204 + } + + /* Filter FIFO assignment */ + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + 8001b8c: 683b ldr r3, [r7, #0] + 8001b8e: 691b ldr r3, [r3, #16] + 8001b90: 2b00 cmp r3, #0 + 8001b92: d109 bne.n 8001ba8 + { + /* FIFO 0 assignation for the filter */ + CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); + 8001b94: 693b ldr r3, [r7, #16] + 8001b96: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 + 8001b9a: 68fb ldr r3, [r7, #12] + 8001b9c: 43db mvns r3, r3 + 8001b9e: 401a ands r2, r3 + 8001ba0: 693b ldr r3, [r7, #16] + 8001ba2: f8c3 2214 str.w r2, [r3, #532] @ 0x214 + 8001ba6: e007 b.n 8001bb8 + } + else + { + /* FIFO 1 assignation for the filter */ + SET_BIT(can_ip->FFA1R, filternbrbitpos); + 8001ba8: 693b ldr r3, [r7, #16] + 8001baa: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 + 8001bae: 68fb ldr r3, [r7, #12] + 8001bb0: 431a orrs r2, r3 + 8001bb2: 693b ldr r3, [r7, #16] + 8001bb4: f8c3 2214 str.w r2, [r3, #532] @ 0x214 + } + + /* Filter activation */ + if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) + 8001bb8: 683b ldr r3, [r7, #0] + 8001bba: 6a1b ldr r3, [r3, #32] + 8001bbc: 2b01 cmp r3, #1 + 8001bbe: d107 bne.n 8001bd0 + { + SET_BIT(can_ip->FA1R, filternbrbitpos); + 8001bc0: 693b ldr r3, [r7, #16] + 8001bc2: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c + 8001bc6: 68fb ldr r3, [r7, #12] + 8001bc8: 431a orrs r2, r3 + 8001bca: 693b ldr r3, [r7, #16] + 8001bcc: f8c3 221c str.w r2, [r3, #540] @ 0x21c + } + + /* Leave the initialisation mode for the filter */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); + 8001bd0: 693b ldr r3, [r7, #16] + 8001bd2: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 + 8001bd6: f023 0201 bic.w r2, r3, #1 + 8001bda: 693b ldr r3, [r7, #16] + 8001bdc: f8c3 2200 str.w r2, [r3, #512] @ 0x200 + + /* Return function status */ + return HAL_OK; + 8001be0: 2300 movs r3, #0 + 8001be2: e006 b.n 8001bf2 + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + 8001be4: 687b ldr r3, [r7, #4] + 8001be6: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001be8: f443 2280 orr.w r2, r3, #262144 @ 0x40000 + 8001bec: 687b ldr r3, [r7, #4] + 8001bee: 625a str r2, [r3, #36] @ 0x24 + + return HAL_ERROR; + 8001bf0: 2301 movs r3, #1 + } +} + 8001bf2: 4618 mov r0, r3 + 8001bf4: 3718 adds r7, #24 + 8001bf6: 46bd mov sp, r7 + 8001bf8: bd80 pop {r7, pc} + 8001bfa: bf00 nop + 8001bfc: 0800a0bc .word 0x0800a0bc + 8001c00: 40006400 .word 0x40006400 + +08001c04 : + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) +{ + 8001c04: b580 push {r7, lr} + 8001c06: b084 sub sp, #16 + 8001c08: af00 add r7, sp, #0 + 8001c0a: 6078 str r0, [r7, #4] + uint32_t tickstart; + + if (hcan->State == HAL_CAN_STATE_READY) + 8001c0c: 687b ldr r3, [r7, #4] + 8001c0e: f893 3020 ldrb.w r3, [r3, #32] + 8001c12: b2db uxtb r3, r3 + 8001c14: 2b01 cmp r3, #1 + 8001c16: d12e bne.n 8001c76 + { + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_LISTENING; + 8001c18: 687b ldr r3, [r7, #4] + 8001c1a: 2202 movs r2, #2 + 8001c1c: f883 2020 strb.w r2, [r3, #32] + + /* Request leave initialisation */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + 8001c20: 687b ldr r3, [r7, #4] + 8001c22: 681b ldr r3, [r3, #0] + 8001c24: 681a ldr r2, [r3, #0] + 8001c26: 687b ldr r3, [r7, #4] + 8001c28: 681b ldr r3, [r3, #0] + 8001c2a: f022 0201 bic.w r2, r2, #1 + 8001c2e: 601a str r2, [r3, #0] + + /* Get tick */ + tickstart = HAL_GetTick(); + 8001c30: f7ff fc02 bl 8001438 + 8001c34: 60f8 str r0, [r7, #12] + + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) + 8001c36: e012 b.n 8001c5e + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + 8001c38: f7ff fbfe bl 8001438 + 8001c3c: 4602 mov r2, r0 + 8001c3e: 68fb ldr r3, [r7, #12] + 8001c40: 1ad3 subs r3, r2, r3 + 8001c42: 2b0a cmp r3, #10 + 8001c44: d90b bls.n 8001c5e + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + 8001c46: 687b ldr r3, [r7, #4] + 8001c48: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001c4a: f443 3200 orr.w r2, r3, #131072 @ 0x20000 + 8001c4e: 687b ldr r3, [r7, #4] + 8001c50: 625a str r2, [r3, #36] @ 0x24 + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + 8001c52: 687b ldr r3, [r7, #4] + 8001c54: 2205 movs r2, #5 + 8001c56: f883 2020 strb.w r2, [r3, #32] + + return HAL_ERROR; + 8001c5a: 2301 movs r3, #1 + 8001c5c: e012 b.n 8001c84 + while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) + 8001c5e: 687b ldr r3, [r7, #4] + 8001c60: 681b ldr r3, [r3, #0] + 8001c62: 685b ldr r3, [r3, #4] + 8001c64: f003 0301 and.w r3, r3, #1 + 8001c68: 2b00 cmp r3, #0 + 8001c6a: d1e5 bne.n 8001c38 + } + } + + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + 8001c6c: 687b ldr r3, [r7, #4] + 8001c6e: 2200 movs r2, #0 + 8001c70: 625a str r2, [r3, #36] @ 0x24 + + /* Return function status */ + return HAL_OK; + 8001c72: 2300 movs r3, #0 + 8001c74: e006 b.n 8001c84 + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; + 8001c76: 687b ldr r3, [r7, #4] + 8001c78: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001c7a: f443 2200 orr.w r2, r3, #524288 @ 0x80000 + 8001c7e: 687b ldr r3, [r7, #4] + 8001c80: 625a str r2, [r3, #36] @ 0x24 + + return HAL_ERROR; + 8001c82: 2301 movs r3, #1 + } +} + 8001c84: 4618 mov r0, r3 + 8001c86: 3710 adds r7, #16 + 8001c88: 46bd mov sp, r7 + 8001c8a: bd80 pop {r7, pc} + +08001c8c : + * @param aData array where the payload of the Rx frame will be stored. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, + CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) +{ + 8001c8c: b580 push {r7, lr} + 8001c8e: b086 sub sp, #24 + 8001c90: af00 add r7, sp, #0 + 8001c92: 60f8 str r0, [r7, #12] + 8001c94: 60b9 str r1, [r7, #8] + 8001c96: 607a str r2, [r7, #4] + 8001c98: 603b str r3, [r7, #0] + HAL_CAN_StateTypeDef state = hcan->State; + 8001c9a: 68fb ldr r3, [r7, #12] + 8001c9c: f893 3020 ldrb.w r3, [r3, #32] + 8001ca0: 75fb strb r3, [r7, #23] + + assert_param(IS_CAN_RX_FIFO(RxFifo)); + 8001ca2: 68bb ldr r3, [r7, #8] + 8001ca4: 2b00 cmp r3, #0 + 8001ca6: d007 beq.n 8001cb8 + 8001ca8: 68bb ldr r3, [r7, #8] + 8001caa: 2b01 cmp r3, #1 + 8001cac: d004 beq.n 8001cb8 + 8001cae: f240 51eb movw r1, #1515 @ 0x5eb + 8001cb2: 488c ldr r0, [pc, #560] @ (8001ee4 ) + 8001cb4: f7ff f83e bl 8000d34 + + if ((state == HAL_CAN_STATE_READY) || + 8001cb8: 7dfb ldrb r3, [r7, #23] + 8001cba: 2b01 cmp r3, #1 + 8001cbc: d003 beq.n 8001cc6 + 8001cbe: 7dfb ldrb r3, [r7, #23] + 8001cc0: 2b02 cmp r3, #2 + 8001cc2: f040 8103 bne.w 8001ecc + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check the Rx FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + 8001cc6: 68bb ldr r3, [r7, #8] + 8001cc8: 2b00 cmp r3, #0 + 8001cca: d10e bne.n 8001cea + { + /* Check that the Rx FIFO 0 is not empty */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) + 8001ccc: 68fb ldr r3, [r7, #12] + 8001cce: 681b ldr r3, [r3, #0] + 8001cd0: 68db ldr r3, [r3, #12] + 8001cd2: f003 0303 and.w r3, r3, #3 + 8001cd6: 2b00 cmp r3, #0 + 8001cd8: d116 bne.n 8001d08 + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + 8001cda: 68fb ldr r3, [r7, #12] + 8001cdc: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001cde: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 + 8001ce2: 68fb ldr r3, [r7, #12] + 8001ce4: 625a str r2, [r3, #36] @ 0x24 + + return HAL_ERROR; + 8001ce6: 2301 movs r3, #1 + 8001ce8: e0f7 b.n 8001eda + } + } + else /* Rx element is assigned to Rx FIFO 1 */ + { + /* Check that the Rx FIFO 1 is not empty */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) + 8001cea: 68fb ldr r3, [r7, #12] + 8001cec: 681b ldr r3, [r3, #0] + 8001cee: 691b ldr r3, [r3, #16] + 8001cf0: f003 0303 and.w r3, r3, #3 + 8001cf4: 2b00 cmp r3, #0 + 8001cf6: d107 bne.n 8001d08 + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + 8001cf8: 68fb ldr r3, [r7, #12] + 8001cfa: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001cfc: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 + 8001d00: 68fb ldr r3, [r7, #12] + 8001d02: 625a str r2, [r3, #36] @ 0x24 + + return HAL_ERROR; + 8001d04: 2301 movs r3, #1 + 8001d06: e0e8 b.n 8001eda + } + } + + /* Get the header */ + pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; + 8001d08: 68fb ldr r3, [r7, #12] + 8001d0a: 681a ldr r2, [r3, #0] + 8001d0c: 68bb ldr r3, [r7, #8] + 8001d0e: 331b adds r3, #27 + 8001d10: 011b lsls r3, r3, #4 + 8001d12: 4413 add r3, r2 + 8001d14: 681b ldr r3, [r3, #0] + 8001d16: f003 0204 and.w r2, r3, #4 + 8001d1a: 687b ldr r3, [r7, #4] + 8001d1c: 609a str r2, [r3, #8] + if (pHeader->IDE == CAN_ID_STD) + 8001d1e: 687b ldr r3, [r7, #4] + 8001d20: 689b ldr r3, [r3, #8] + 8001d22: 2b00 cmp r3, #0 + 8001d24: d10c bne.n 8001d40 + { + pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; + 8001d26: 68fb ldr r3, [r7, #12] + 8001d28: 681a ldr r2, [r3, #0] + 8001d2a: 68bb ldr r3, [r7, #8] + 8001d2c: 331b adds r3, #27 + 8001d2e: 011b lsls r3, r3, #4 + 8001d30: 4413 add r3, r2 + 8001d32: 681b ldr r3, [r3, #0] + 8001d34: 0d5b lsrs r3, r3, #21 + 8001d36: f3c3 020a ubfx r2, r3, #0, #11 + 8001d3a: 687b ldr r3, [r7, #4] + 8001d3c: 601a str r2, [r3, #0] + 8001d3e: e00b b.n 8001d58 + } + else + { + pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & + hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; + 8001d40: 68fb ldr r3, [r7, #12] + 8001d42: 681a ldr r2, [r3, #0] + 8001d44: 68bb ldr r3, [r7, #8] + 8001d46: 331b adds r3, #27 + 8001d48: 011b lsls r3, r3, #4 + 8001d4a: 4413 add r3, r2 + 8001d4c: 681b ldr r3, [r3, #0] + 8001d4e: 08db lsrs r3, r3, #3 + 8001d50: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000 + pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & + 8001d54: 687b ldr r3, [r7, #4] + 8001d56: 605a str r2, [r3, #4] + } + pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); + 8001d58: 68fb ldr r3, [r7, #12] + 8001d5a: 681a ldr r2, [r3, #0] + 8001d5c: 68bb ldr r3, [r7, #8] + 8001d5e: 331b adds r3, #27 + 8001d60: 011b lsls r3, r3, #4 + 8001d62: 4413 add r3, r2 + 8001d64: 681b ldr r3, [r3, #0] + 8001d66: f003 0202 and.w r2, r3, #2 + 8001d6a: 687b ldr r3, [r7, #4] + 8001d6c: 60da str r2, [r3, #12] + if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U) + 8001d6e: 68fb ldr r3, [r7, #12] + 8001d70: 681a ldr r2, [r3, #0] + 8001d72: 68bb ldr r3, [r7, #8] + 8001d74: 331b adds r3, #27 + 8001d76: 011b lsls r3, r3, #4 + 8001d78: 4413 add r3, r2 + 8001d7a: 3304 adds r3, #4 + 8001d7c: 681b ldr r3, [r3, #0] + 8001d7e: f003 0308 and.w r3, r3, #8 + 8001d82: 2b00 cmp r3, #0 + 8001d84: d003 beq.n 8001d8e + { + /* Truncate DLC to 8 if received field is over range */ + pHeader->DLC = 8U; + 8001d86: 687b ldr r3, [r7, #4] + 8001d88: 2208 movs r2, #8 + 8001d8a: 611a str r2, [r3, #16] + 8001d8c: e00b b.n 8001da6 + } + else + { + pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; + 8001d8e: 68fb ldr r3, [r7, #12] + 8001d90: 681a ldr r2, [r3, #0] + 8001d92: 68bb ldr r3, [r7, #8] + 8001d94: 331b adds r3, #27 + 8001d96: 011b lsls r3, r3, #4 + 8001d98: 4413 add r3, r2 + 8001d9a: 3304 adds r3, #4 + 8001d9c: 681b ldr r3, [r3, #0] + 8001d9e: f003 020f and.w r2, r3, #15 + 8001da2: 687b ldr r3, [r7, #4] + 8001da4: 611a str r2, [r3, #16] + } + pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; + 8001da6: 68fb ldr r3, [r7, #12] + 8001da8: 681a ldr r2, [r3, #0] + 8001daa: 68bb ldr r3, [r7, #8] + 8001dac: 331b adds r3, #27 + 8001dae: 011b lsls r3, r3, #4 + 8001db0: 4413 add r3, r2 + 8001db2: 3304 adds r3, #4 + 8001db4: 681b ldr r3, [r3, #0] + 8001db6: 0a1b lsrs r3, r3, #8 + 8001db8: b2da uxtb r2, r3 + 8001dba: 687b ldr r3, [r7, #4] + 8001dbc: 619a str r2, [r3, #24] + pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; + 8001dbe: 68fb ldr r3, [r7, #12] + 8001dc0: 681a ldr r2, [r3, #0] + 8001dc2: 68bb ldr r3, [r7, #8] + 8001dc4: 331b adds r3, #27 + 8001dc6: 011b lsls r3, r3, #4 + 8001dc8: 4413 add r3, r2 + 8001dca: 3304 adds r3, #4 + 8001dcc: 681b ldr r3, [r3, #0] + 8001dce: 0c1b lsrs r3, r3, #16 + 8001dd0: b29a uxth r2, r3 + 8001dd2: 687b ldr r3, [r7, #4] + 8001dd4: 615a str r2, [r3, #20] + + /* Get the data */ + aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); + 8001dd6: 68fb ldr r3, [r7, #12] + 8001dd8: 681a ldr r2, [r3, #0] + 8001dda: 68bb ldr r3, [r7, #8] + 8001ddc: 011b lsls r3, r3, #4 + 8001dde: 4413 add r3, r2 + 8001de0: f503 73dc add.w r3, r3, #440 @ 0x1b8 + 8001de4: 681b ldr r3, [r3, #0] + 8001de6: b2da uxtb r2, r3 + 8001de8: 683b ldr r3, [r7, #0] + 8001dea: 701a strb r2, [r3, #0] + aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); + 8001dec: 68fb ldr r3, [r7, #12] + 8001dee: 681a ldr r2, [r3, #0] + 8001df0: 68bb ldr r3, [r7, #8] + 8001df2: 011b lsls r3, r3, #4 + 8001df4: 4413 add r3, r2 + 8001df6: f503 73dc add.w r3, r3, #440 @ 0x1b8 + 8001dfa: 681b ldr r3, [r3, #0] + 8001dfc: 0a1a lsrs r2, r3, #8 + 8001dfe: 683b ldr r3, [r7, #0] + 8001e00: 3301 adds r3, #1 + 8001e02: b2d2 uxtb r2, r2 + 8001e04: 701a strb r2, [r3, #0] + aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); + 8001e06: 68fb ldr r3, [r7, #12] + 8001e08: 681a ldr r2, [r3, #0] + 8001e0a: 68bb ldr r3, [r7, #8] + 8001e0c: 011b lsls r3, r3, #4 + 8001e0e: 4413 add r3, r2 + 8001e10: f503 73dc add.w r3, r3, #440 @ 0x1b8 + 8001e14: 681b ldr r3, [r3, #0] + 8001e16: 0c1a lsrs r2, r3, #16 + 8001e18: 683b ldr r3, [r7, #0] + 8001e1a: 3302 adds r3, #2 + 8001e1c: b2d2 uxtb r2, r2 + 8001e1e: 701a strb r2, [r3, #0] + aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); + 8001e20: 68fb ldr r3, [r7, #12] + 8001e22: 681a ldr r2, [r3, #0] + 8001e24: 68bb ldr r3, [r7, #8] + 8001e26: 011b lsls r3, r3, #4 + 8001e28: 4413 add r3, r2 + 8001e2a: f503 73dc add.w r3, r3, #440 @ 0x1b8 + 8001e2e: 681b ldr r3, [r3, #0] + 8001e30: 0e1a lsrs r2, r3, #24 + 8001e32: 683b ldr r3, [r7, #0] + 8001e34: 3303 adds r3, #3 + 8001e36: b2d2 uxtb r2, r2 + 8001e38: 701a strb r2, [r3, #0] + aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); + 8001e3a: 68fb ldr r3, [r7, #12] + 8001e3c: 681a ldr r2, [r3, #0] + 8001e3e: 68bb ldr r3, [r7, #8] + 8001e40: 011b lsls r3, r3, #4 + 8001e42: 4413 add r3, r2 + 8001e44: f503 73de add.w r3, r3, #444 @ 0x1bc + 8001e48: 681a ldr r2, [r3, #0] + 8001e4a: 683b ldr r3, [r7, #0] + 8001e4c: 3304 adds r3, #4 + 8001e4e: b2d2 uxtb r2, r2 + 8001e50: 701a strb r2, [r3, #0] + aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); + 8001e52: 68fb ldr r3, [r7, #12] + 8001e54: 681a ldr r2, [r3, #0] + 8001e56: 68bb ldr r3, [r7, #8] + 8001e58: 011b lsls r3, r3, #4 + 8001e5a: 4413 add r3, r2 + 8001e5c: f503 73de add.w r3, r3, #444 @ 0x1bc + 8001e60: 681b ldr r3, [r3, #0] + 8001e62: 0a1a lsrs r2, r3, #8 + 8001e64: 683b ldr r3, [r7, #0] + 8001e66: 3305 adds r3, #5 + 8001e68: b2d2 uxtb r2, r2 + 8001e6a: 701a strb r2, [r3, #0] + aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); + 8001e6c: 68fb ldr r3, [r7, #12] + 8001e6e: 681a ldr r2, [r3, #0] + 8001e70: 68bb ldr r3, [r7, #8] + 8001e72: 011b lsls r3, r3, #4 + 8001e74: 4413 add r3, r2 + 8001e76: f503 73de add.w r3, r3, #444 @ 0x1bc + 8001e7a: 681b ldr r3, [r3, #0] + 8001e7c: 0c1a lsrs r2, r3, #16 + 8001e7e: 683b ldr r3, [r7, #0] + 8001e80: 3306 adds r3, #6 + 8001e82: b2d2 uxtb r2, r2 + 8001e84: 701a strb r2, [r3, #0] + aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); + 8001e86: 68fb ldr r3, [r7, #12] + 8001e88: 681a ldr r2, [r3, #0] + 8001e8a: 68bb ldr r3, [r7, #8] + 8001e8c: 011b lsls r3, r3, #4 + 8001e8e: 4413 add r3, r2 + 8001e90: f503 73de add.w r3, r3, #444 @ 0x1bc + 8001e94: 681b ldr r3, [r3, #0] + 8001e96: 0e1a lsrs r2, r3, #24 + 8001e98: 683b ldr r3, [r7, #0] + 8001e9a: 3307 adds r3, #7 + 8001e9c: b2d2 uxtb r2, r2 + 8001e9e: 701a strb r2, [r3, #0] + + /* Release the FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + 8001ea0: 68bb ldr r3, [r7, #8] + 8001ea2: 2b00 cmp r3, #0 + 8001ea4: d108 bne.n 8001eb8 + { + /* Release RX FIFO 0 */ + SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); + 8001ea6: 68fb ldr r3, [r7, #12] + 8001ea8: 681b ldr r3, [r3, #0] + 8001eaa: 68da ldr r2, [r3, #12] + 8001eac: 68fb ldr r3, [r7, #12] + 8001eae: 681b ldr r3, [r3, #0] + 8001eb0: f042 0220 orr.w r2, r2, #32 + 8001eb4: 60da str r2, [r3, #12] + 8001eb6: e007 b.n 8001ec8 + } + else /* Rx element is assigned to Rx FIFO 1 */ + { + /* Release RX FIFO 1 */ + SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); + 8001eb8: 68fb ldr r3, [r7, #12] + 8001eba: 681b ldr r3, [r3, #0] + 8001ebc: 691a ldr r2, [r3, #16] + 8001ebe: 68fb ldr r3, [r7, #12] + 8001ec0: 681b ldr r3, [r3, #0] + 8001ec2: f042 0220 orr.w r2, r2, #32 + 8001ec6: 611a str r2, [r3, #16] + } + + /* Return function status */ + return HAL_OK; + 8001ec8: 2300 movs r3, #0 + 8001eca: e006 b.n 8001eda + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + 8001ecc: 68fb ldr r3, [r7, #12] + 8001ece: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001ed0: f443 2280 orr.w r2, r3, #262144 @ 0x40000 + 8001ed4: 68fb ldr r3, [r7, #12] + 8001ed6: 625a str r2, [r3, #36] @ 0x24 + + return HAL_ERROR; + 8001ed8: 2301 movs r3, #1 + } +} + 8001eda: 4618 mov r0, r3 + 8001edc: 3718 adds r7, #24 + 8001ede: 46bd mov sp, r7 + 8001ee0: bd80 pop {r7, pc} + 8001ee2: bf00 nop + 8001ee4: 0800a0bc .word 0x0800a0bc + +08001ee8 : + * @param ActiveITs indicates which interrupts will be enabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) +{ + 8001ee8: b580 push {r7, lr} + 8001eea: b084 sub sp, #16 + 8001eec: af00 add r7, sp, #0 + 8001eee: 6078 str r0, [r7, #4] + 8001ef0: 6039 str r1, [r7, #0] + HAL_CAN_StateTypeDef state = hcan->State; + 8001ef2: 687b ldr r3, [r7, #4] + 8001ef4: f893 3020 ldrb.w r3, [r3, #32] + 8001ef8: 73fb strb r3, [r7, #15] + + /* Check function parameters */ + assert_param(IS_CAN_IT(ActiveITs)); + 8001efa: 683b ldr r3, [r7, #0] + 8001efc: 4a11 ldr r2, [pc, #68] @ (8001f44 ) + 8001efe: 4293 cmp r3, r2 + 8001f00: d904 bls.n 8001f0c + 8001f02: f240 6184 movw r1, #1668 @ 0x684 + 8001f06: 4810 ldr r0, [pc, #64] @ (8001f48 ) + 8001f08: f7fe ff14 bl 8000d34 + + if ((state == HAL_CAN_STATE_READY) || + 8001f0c: 7bfb ldrb r3, [r7, #15] + 8001f0e: 2b01 cmp r3, #1 + 8001f10: d002 beq.n 8001f18 + 8001f12: 7bfb ldrb r3, [r7, #15] + 8001f14: 2b02 cmp r3, #2 + 8001f16: d109 bne.n 8001f2c + (state == HAL_CAN_STATE_LISTENING)) + { + /* Enable the selected interrupts */ + __HAL_CAN_ENABLE_IT(hcan, ActiveITs); + 8001f18: 687b ldr r3, [r7, #4] + 8001f1a: 681b ldr r3, [r3, #0] + 8001f1c: 6959 ldr r1, [r3, #20] + 8001f1e: 687b ldr r3, [r7, #4] + 8001f20: 681b ldr r3, [r3, #0] + 8001f22: 683a ldr r2, [r7, #0] + 8001f24: 430a orrs r2, r1 + 8001f26: 615a str r2, [r3, #20] + + /* Return function status */ + return HAL_OK; + 8001f28: 2300 movs r3, #0 + 8001f2a: e006 b.n 8001f3a + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + 8001f2c: 687b ldr r3, [r7, #4] + 8001f2e: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001f30: f443 2280 orr.w r2, r3, #262144 @ 0x40000 + 8001f34: 687b ldr r3, [r7, #4] + 8001f36: 625a str r2, [r3, #36] @ 0x24 + + return HAL_ERROR; + 8001f38: 2301 movs r3, #1 + } +} + 8001f3a: 4618 mov r0, r3 + 8001f3c: 3710 adds r7, #16 + 8001f3e: 46bd mov sp, r7 + 8001f40: bd80 pop {r7, pc} + 8001f42: bf00 nop + 8001f44: 00038f7f .word 0x00038f7f + 8001f48: 0800a0bc .word 0x0800a0bc + +08001f4c : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) { - 800121c: b480 push {r7} - 800121e: b083 sub sp, #12 - 8001220: af00 add r7, sp, #0 - 8001222: 6078 str r0, [r7, #4] + 8001f4c: b480 push {r7} + 8001f4e: b083 sub sp, #12 + 8001f50: af00 add r7, sp, #0 + 8001f52: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the user file */ } - 8001224: bf00 nop - 8001226: 370c adds r7, #12 - 8001228: 46bd mov sp, r7 - 800122a: f85d 7b04 ldr.w r7, [sp], #4 - 800122e: 4770 bx lr + 8001f54: bf00 nop + 8001f56: 370c adds r7, #12 + 8001f58: 46bd mov sp, r7 + 8001f5a: f85d 7b04 ldr.w r7, [sp], #4 + 8001f5e: 4770 bx lr -08001230 : +08001f60 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) { - 8001230: b480 push {r7} - 8001232: b083 sub sp, #12 - 8001234: af00 add r7, sp, #0 - 8001236: 6078 str r0, [r7, #4] + 8001f60: b480 push {r7} + 8001f62: b083 sub sp, #12 + 8001f64: af00 add r7, sp, #0 + 8001f66: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the user file */ } - 8001238: bf00 nop - 800123a: 370c adds r7, #12 - 800123c: 46bd mov sp, r7 - 800123e: f85d 7b04 ldr.w r7, [sp], #4 - 8001242: 4770 bx lr + 8001f68: bf00 nop + 8001f6a: 370c adds r7, #12 + 8001f6c: 46bd mov sp, r7 + 8001f6e: f85d 7b04 ldr.w r7, [sp], #4 + 8001f72: 4770 bx lr -08001244 : +08001f74 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) { - 8001244: b480 push {r7} - 8001246: b083 sub sp, #12 - 8001248: af00 add r7, sp, #0 - 800124a: 6078 str r0, [r7, #4] + 8001f74: b480 push {r7} + 8001f76: b083 sub sp, #12 + 8001f78: af00 add r7, sp, #0 + 8001f7a: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the user file */ } - 800124c: bf00 nop - 800124e: 370c adds r7, #12 - 8001250: 46bd mov sp, r7 - 8001252: f85d 7b04 ldr.w r7, [sp], #4 - 8001256: 4770 bx lr + 8001f7c: bf00 nop + 8001f7e: 370c adds r7, #12 + 8001f80: 46bd mov sp, r7 + 8001f82: f85d 7b04 ldr.w r7, [sp], #4 + 8001f86: 4770 bx lr -08001258 : +08001f88 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) { - 8001258: b480 push {r7} - 800125a: b083 sub sp, #12 - 800125c: af00 add r7, sp, #0 - 800125e: 6078 str r0, [r7, #4] + 8001f88: b480 push {r7} + 8001f8a: b083 sub sp, #12 + 8001f8c: af00 add r7, sp, #0 + 8001f8e: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0AbortCallback could be implemented in the user file */ } - 8001260: bf00 nop - 8001262: 370c adds r7, #12 - 8001264: 46bd mov sp, r7 - 8001266: f85d 7b04 ldr.w r7, [sp], #4 - 800126a: 4770 bx lr + 8001f90: bf00 nop + 8001f92: 370c adds r7, #12 + 8001f94: 46bd mov sp, r7 + 8001f96: f85d 7b04 ldr.w r7, [sp], #4 + 8001f9a: 4770 bx lr -0800126c : +08001f9c : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) { - 800126c: b480 push {r7} - 800126e: b083 sub sp, #12 - 8001270: af00 add r7, sp, #0 - 8001272: 6078 str r0, [r7, #4] + 8001f9c: b480 push {r7} + 8001f9e: b083 sub sp, #12 + 8001fa0: af00 add r7, sp, #0 + 8001fa2: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1AbortCallback could be implemented in the user file */ } - 8001274: bf00 nop - 8001276: 370c adds r7, #12 - 8001278: 46bd mov sp, r7 - 800127a: f85d 7b04 ldr.w r7, [sp], #4 - 800127e: 4770 bx lr + 8001fa4: bf00 nop + 8001fa6: 370c adds r7, #12 + 8001fa8: 46bd mov sp, r7 + 8001faa: f85d 7b04 ldr.w r7, [sp], #4 + 8001fae: 4770 bx lr -08001280 : +08001fb0 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) { - 8001280: b480 push {r7} - 8001282: b083 sub sp, #12 - 8001284: af00 add r7, sp, #0 - 8001286: 6078 str r0, [r7, #4] + 8001fb0: b480 push {r7} + 8001fb2: b083 sub sp, #12 + 8001fb4: af00 add r7, sp, #0 + 8001fb6: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2AbortCallback could be implemented in the user file */ } - 8001288: bf00 nop - 800128a: 370c adds r7, #12 - 800128c: 46bd mov sp, r7 - 800128e: f85d 7b04 ldr.w r7, [sp], #4 - 8001292: 4770 bx lr + 8001fb8: bf00 nop + 8001fba: 370c adds r7, #12 + 8001fbc: 46bd mov sp, r7 + 8001fbe: f85d 7b04 ldr.w r7, [sp], #4 + 8001fc2: 4770 bx lr -08001294 : - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) -{ - 8001294: b480 push {r7} - 8001296: b083 sub sp, #12 - 8001298: af00 add r7, sp, #0 - 800129a: 6078 str r0, [r7, #4] - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the - user file - */ -} - 800129c: bf00 nop - 800129e: 370c adds r7, #12 - 80012a0: 46bd mov sp, r7 - 80012a2: f85d 7b04 ldr.w r7, [sp], #4 - 80012a6: 4770 bx lr - -080012a8 : +08001fc4 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) { - 80012a8: b480 push {r7} - 80012aa: b083 sub sp, #12 - 80012ac: af00 add r7, sp, #0 - 80012ae: 6078 str r0, [r7, #4] + 8001fc4: b480 push {r7} + 8001fc6: b083 sub sp, #12 + 8001fc8: af00 add r7, sp, #0 + 8001fca: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo0FullCallback could be implemented in the user file */ } - 80012b0: bf00 nop - 80012b2: 370c adds r7, #12 - 80012b4: 46bd mov sp, r7 - 80012b6: f85d 7b04 ldr.w r7, [sp], #4 - 80012ba: 4770 bx lr + 8001fcc: bf00 nop + 8001fce: 370c adds r7, #12 + 8001fd0: 46bd mov sp, r7 + 8001fd2: f85d 7b04 ldr.w r7, [sp], #4 + 8001fd6: 4770 bx lr -080012bc : +08001fd8 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan) { - 80012bc: b480 push {r7} - 80012be: b083 sub sp, #12 - 80012c0: af00 add r7, sp, #0 - 80012c2: 6078 str r0, [r7, #4] + 8001fd8: b480 push {r7} + 8001fda: b083 sub sp, #12 + 8001fdc: af00 add r7, sp, #0 + 8001fde: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the user file */ } - 80012c4: bf00 nop - 80012c6: 370c adds r7, #12 - 80012c8: 46bd mov sp, r7 - 80012ca: f85d 7b04 ldr.w r7, [sp], #4 - 80012ce: 4770 bx lr + 8001fe0: bf00 nop + 8001fe2: 370c adds r7, #12 + 8001fe4: 46bd mov sp, r7 + 8001fe6: f85d 7b04 ldr.w r7, [sp], #4 + 8001fea: 4770 bx lr -080012d0 : +08001fec : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) { - 80012d0: b480 push {r7} - 80012d2: b083 sub sp, #12 - 80012d4: af00 add r7, sp, #0 - 80012d6: 6078 str r0, [r7, #4] + 8001fec: b480 push {r7} + 8001fee: b083 sub sp, #12 + 8001ff0: af00 add r7, sp, #0 + 8001ff2: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo1FullCallback could be implemented in the user file */ } - 80012d8: bf00 nop - 80012da: 370c adds r7, #12 - 80012dc: 46bd mov sp, r7 - 80012de: f85d 7b04 ldr.w r7, [sp], #4 - 80012e2: 4770 bx lr + 8001ff4: bf00 nop + 8001ff6: 370c adds r7, #12 + 8001ff8: 46bd mov sp, r7 + 8001ffa: f85d 7b04 ldr.w r7, [sp], #4 + 8001ffe: 4770 bx lr -080012e4 : +08002000 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) { - 80012e4: b480 push {r7} - 80012e6: b083 sub sp, #12 - 80012e8: af00 add r7, sp, #0 - 80012ea: 6078 str r0, [r7, #4] + 8002000: b480 push {r7} + 8002002: b083 sub sp, #12 + 8002004: af00 add r7, sp, #0 + 8002006: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_SleepCallback could be implemented in the user file */ } - 80012ec: bf00 nop - 80012ee: 370c adds r7, #12 - 80012f0: 46bd mov sp, r7 - 80012f2: f85d 7b04 ldr.w r7, [sp], #4 - 80012f6: 4770 bx lr + 8002008: bf00 nop + 800200a: 370c adds r7, #12 + 800200c: 46bd mov sp, r7 + 800200e: f85d 7b04 ldr.w r7, [sp], #4 + 8002012: 4770 bx lr -080012f8 : +08002014 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) { - 80012f8: b480 push {r7} - 80012fa: b083 sub sp, #12 - 80012fc: af00 add r7, sp, #0 - 80012fe: 6078 str r0, [r7, #4] + 8002014: b480 push {r7} + 8002016: b083 sub sp, #12 + 8002018: af00 add r7, sp, #0 + 800201a: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the user file */ } - 8001300: bf00 nop - 8001302: 370c adds r7, #12 - 8001304: 46bd mov sp, r7 - 8001306: f85d 7b04 ldr.w r7, [sp], #4 - 800130a: 4770 bx lr + 800201c: bf00 nop + 800201e: 370c adds r7, #12 + 8002020: 46bd mov sp, r7 + 8002022: f85d 7b04 ldr.w r7, [sp], #4 + 8002026: 4770 bx lr -0800130c : +08002028 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) { - 800130c: b480 push {r7} - 800130e: b083 sub sp, #12 - 8001310: af00 add r7, sp, #0 - 8001312: 6078 str r0, [r7, #4] + 8002028: b480 push {r7} + 800202a: b083 sub sp, #12 + 800202c: af00 add r7, sp, #0 + 800202e: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_ErrorCallback could be implemented in the user file */ } - 8001314: bf00 nop - 8001316: 370c adds r7, #12 - 8001318: 46bd mov sp, r7 - 800131a: f85d 7b04 ldr.w r7, [sp], #4 - 800131e: 4770 bx lr + 8002030: bf00 nop + 8002032: 370c adds r7, #12 + 8002034: 46bd mov sp, r7 + 8002036: f85d 7b04 ldr.w r7, [sp], #4 + 800203a: 4770 bx lr -08001320 <__NVIC_SetPriorityGrouping>: +0800203c : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL state + */ +HAL_CAN_StateTypeDef HAL_CAN_GetState(const CAN_HandleTypeDef *hcan) +{ + 800203c: b480 push {r7} + 800203e: b085 sub sp, #20 + 8002040: af00 add r7, sp, #0 + 8002042: 6078 str r0, [r7, #4] + HAL_CAN_StateTypeDef state = hcan->State; + 8002044: 687b ldr r3, [r7, #4] + 8002046: f893 3020 ldrb.w r3, [r3, #32] + 800204a: 73fb strb r3, [r7, #15] + + if ((state == HAL_CAN_STATE_READY) || + 800204c: 7bfb ldrb r3, [r7, #15] + 800204e: 2b01 cmp r3, #1 + 8002050: d002 beq.n 8002058 + 8002052: 7bfb ldrb r3, [r7, #15] + 8002054: 2b02 cmp r3, #2 + 8002056: d112 bne.n 800207e + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check sleep mode acknowledge flag */ + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + 8002058: 687b ldr r3, [r7, #4] + 800205a: 681b ldr r3, [r3, #0] + 800205c: 685b ldr r3, [r3, #4] + 800205e: f003 0302 and.w r3, r3, #2 + 8002062: 2b00 cmp r3, #0 + 8002064: d002 beq.n 800206c + { + /* Sleep mode is active */ + state = HAL_CAN_STATE_SLEEP_ACTIVE; + 8002066: 2304 movs r3, #4 + 8002068: 73fb strb r3, [r7, #15] + 800206a: e008 b.n 800207e + } + /* Check sleep mode request flag */ + else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != 0U) + 800206c: 687b ldr r3, [r7, #4] + 800206e: 681b ldr r3, [r3, #0] + 8002070: 681b ldr r3, [r3, #0] + 8002072: f003 0302 and.w r3, r3, #2 + 8002076: 2b00 cmp r3, #0 + 8002078: d001 beq.n 800207e + { + /* Sleep mode request is pending */ + state = HAL_CAN_STATE_SLEEP_PENDING; + 800207a: 2303 movs r3, #3 + 800207c: 73fb strb r3, [r7, #15] + /* Neither sleep mode request nor sleep mode acknowledge */ + } + } + + /* Return CAN state */ + return state; + 800207e: 7bfb ldrb r3, [r7, #15] +} + 8002080: 4618 mov r0, r3 + 8002082: 3714 adds r7, #20 + 8002084: 46bd mov sp, r7 + 8002086: f85d 7b04 ldr.w r7, [sp], #4 + 800208a: 4770 bx lr + +0800208c : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval CAN Error Code + */ +uint32_t HAL_CAN_GetError(const CAN_HandleTypeDef *hcan) +{ + 800208c: b480 push {r7} + 800208e: b083 sub sp, #12 + 8002090: af00 add r7, sp, #0 + 8002092: 6078 str r0, [r7, #4] + /* Return CAN error code */ + return hcan->ErrorCode; + 8002094: 687b ldr r3, [r7, #4] + 8002096: 6a5b ldr r3, [r3, #36] @ 0x24 +} + 8002098: 4618 mov r0, r3 + 800209a: 370c adds r7, #12 + 800209c: 46bd mov sp, r7 + 800209e: f85d 7b04 ldr.w r7, [sp], #4 + 80020a2: 4770 bx lr + +080020a4 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { - 8001320: b480 push {r7} - 8001322: b085 sub sp, #20 - 8001324: af00 add r7, sp, #0 - 8001326: 6078 str r0, [r7, #4] + 80020a4: b480 push {r7} + 80020a6: b085 sub sp, #20 + 80020a8: af00 add r7, sp, #0 + 80020aa: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - 8001328: 687b ldr r3, [r7, #4] - 800132a: f003 0307 and.w r3, r3, #7 - 800132e: 60fb str r3, [r7, #12] + 80020ac: 687b ldr r3, [r7, #4] + 80020ae: f003 0307 and.w r3, r3, #7 + 80020b2: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ - 8001330: 4b0c ldr r3, [pc, #48] @ (8001364 <__NVIC_SetPriorityGrouping+0x44>) - 8001332: 68db ldr r3, [r3, #12] - 8001334: 60bb str r3, [r7, #8] + 80020b4: 4b0c ldr r3, [pc, #48] @ (80020e8 <__NVIC_SetPriorityGrouping+0x44>) + 80020b6: 68db ldr r3, [r3, #12] + 80020b8: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - 8001336: 68ba ldr r2, [r7, #8] - 8001338: f64f 03ff movw r3, #63743 @ 0xf8ff - 800133c: 4013 ands r3, r2 - 800133e: 60bb str r3, [r7, #8] + 80020ba: 68ba ldr r2, [r7, #8] + 80020bc: f64f 03ff movw r3, #63743 @ 0xf8ff + 80020c0: 4013 ands r3, r2 + 80020c2: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - 8001340: 68fb ldr r3, [r7, #12] - 8001342: 021a lsls r2, r3, #8 + 80020c4: 68fb ldr r3, [r7, #12] + 80020c6: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - 8001344: 68bb ldr r3, [r7, #8] - 8001346: 4313 orrs r3, r2 + 80020c8: 68bb ldr r3, [r7, #8] + 80020ca: 4313 orrs r3, r2 reg_value = (reg_value | - 8001348: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 - 800134c: f443 3300 orr.w r3, r3, #131072 @ 0x20000 - 8001350: 60bb str r3, [r7, #8] + 80020cc: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 + 80020d0: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 80020d4: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; - 8001352: 4a04 ldr r2, [pc, #16] @ (8001364 <__NVIC_SetPriorityGrouping+0x44>) - 8001354: 68bb ldr r3, [r7, #8] - 8001356: 60d3 str r3, [r2, #12] + 80020d6: 4a04 ldr r2, [pc, #16] @ (80020e8 <__NVIC_SetPriorityGrouping+0x44>) + 80020d8: 68bb ldr r3, [r7, #8] + 80020da: 60d3 str r3, [r2, #12] } - 8001358: bf00 nop - 800135a: 3714 adds r7, #20 - 800135c: 46bd mov sp, r7 - 800135e: f85d 7b04 ldr.w r7, [sp], #4 - 8001362: 4770 bx lr - 8001364: e000ed00 .word 0xe000ed00 + 80020dc: bf00 nop + 80020de: 3714 adds r7, #20 + 80020e0: 46bd mov sp, r7 + 80020e2: f85d 7b04 ldr.w r7, [sp], #4 + 80020e6: 4770 bx lr + 80020e8: e000ed00 .word 0xe000ed00 -08001368 <__NVIC_GetPriorityGrouping>: +080020ec <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { - 8001368: b480 push {r7} - 800136a: af00 add r7, sp, #0 + 80020ec: b480 push {r7} + 80020ee: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); - 800136c: 4b04 ldr r3, [pc, #16] @ (8001380 <__NVIC_GetPriorityGrouping+0x18>) - 800136e: 68db ldr r3, [r3, #12] - 8001370: 0a1b lsrs r3, r3, #8 - 8001372: f003 0307 and.w r3, r3, #7 + 80020f0: 4b04 ldr r3, [pc, #16] @ (8002104 <__NVIC_GetPriorityGrouping+0x18>) + 80020f2: 68db ldr r3, [r3, #12] + 80020f4: 0a1b lsrs r3, r3, #8 + 80020f6: f003 0307 and.w r3, r3, #7 } - 8001376: 4618 mov r0, r3 - 8001378: 46bd mov sp, r7 - 800137a: f85d 7b04 ldr.w r7, [sp], #4 - 800137e: 4770 bx lr - 8001380: e000ed00 .word 0xe000ed00 + 80020fa: 4618 mov r0, r3 + 80020fc: 46bd mov sp, r7 + 80020fe: f85d 7b04 ldr.w r7, [sp], #4 + 8002102: 4770 bx lr + 8002104: e000ed00 .word 0xe000ed00 -08001384 <__NVIC_EnableIRQ>: +08002108 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { - 8001384: b480 push {r7} - 8001386: b083 sub sp, #12 - 8001388: af00 add r7, sp, #0 - 800138a: 4603 mov r3, r0 - 800138c: 71fb strb r3, [r7, #7] + 8002108: b480 push {r7} + 800210a: b083 sub sp, #12 + 800210c: af00 add r7, sp, #0 + 800210e: 4603 mov r3, r0 + 8002110: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) - 800138e: f997 3007 ldrsb.w r3, [r7, #7] - 8001392: 2b00 cmp r3, #0 - 8001394: db0b blt.n 80013ae <__NVIC_EnableIRQ+0x2a> + 8002112: f997 3007 ldrsb.w r3, [r7, #7] + 8002116: 2b00 cmp r3, #0 + 8002118: db0b blt.n 8002132 <__NVIC_EnableIRQ+0x2a> { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - 8001396: 79fb ldrb r3, [r7, #7] - 8001398: f003 021f and.w r2, r3, #31 - 800139c: 4907 ldr r1, [pc, #28] @ (80013bc <__NVIC_EnableIRQ+0x38>) - 800139e: f997 3007 ldrsb.w r3, [r7, #7] - 80013a2: 095b lsrs r3, r3, #5 - 80013a4: 2001 movs r0, #1 - 80013a6: fa00 f202 lsl.w r2, r0, r2 - 80013aa: f841 2023 str.w r2, [r1, r3, lsl #2] + 800211a: 79fb ldrb r3, [r7, #7] + 800211c: f003 021f and.w r2, r3, #31 + 8002120: 4907 ldr r1, [pc, #28] @ (8002140 <__NVIC_EnableIRQ+0x38>) + 8002122: f997 3007 ldrsb.w r3, [r7, #7] + 8002126: 095b lsrs r3, r3, #5 + 8002128: 2001 movs r0, #1 + 800212a: fa00 f202 lsl.w r2, r0, r2 + 800212e: f841 2023 str.w r2, [r1, r3, lsl #2] __COMPILER_BARRIER(); } } - 80013ae: bf00 nop - 80013b0: 370c adds r7, #12 - 80013b2: 46bd mov sp, r7 - 80013b4: f85d 7b04 ldr.w r7, [sp], #4 - 80013b8: 4770 bx lr - 80013ba: bf00 nop - 80013bc: e000e100 .word 0xe000e100 + 8002132: bf00 nop + 8002134: 370c adds r7, #12 + 8002136: 46bd mov sp, r7 + 8002138: f85d 7b04 ldr.w r7, [sp], #4 + 800213c: 4770 bx lr + 800213e: bf00 nop + 8002140: e000e100 .word 0xe000e100 -080013c0 <__NVIC_SetPriority>: +08002144 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - 80013c0: b480 push {r7} - 80013c2: b083 sub sp, #12 - 80013c4: af00 add r7, sp, #0 - 80013c6: 4603 mov r3, r0 - 80013c8: 6039 str r1, [r7, #0] - 80013ca: 71fb strb r3, [r7, #7] + 8002144: b480 push {r7} + 8002146: b083 sub sp, #12 + 8002148: af00 add r7, sp, #0 + 800214a: 4603 mov r3, r0 + 800214c: 6039 str r1, [r7, #0] + 800214e: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) - 80013cc: f997 3007 ldrsb.w r3, [r7, #7] - 80013d0: 2b00 cmp r3, #0 - 80013d2: db0a blt.n 80013ea <__NVIC_SetPriority+0x2a> + 8002150: f997 3007 ldrsb.w r3, [r7, #7] + 8002154: 2b00 cmp r3, #0 + 8002156: db0a blt.n 800216e <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 80013d4: 683b ldr r3, [r7, #0] - 80013d6: b2da uxtb r2, r3 - 80013d8: 490c ldr r1, [pc, #48] @ (800140c <__NVIC_SetPriority+0x4c>) - 80013da: f997 3007 ldrsb.w r3, [r7, #7] - 80013de: 0112 lsls r2, r2, #4 - 80013e0: b2d2 uxtb r2, r2 - 80013e2: 440b add r3, r1 - 80013e4: f883 2300 strb.w r2, [r3, #768] @ 0x300 + 8002158: 683b ldr r3, [r7, #0] + 800215a: b2da uxtb r2, r3 + 800215c: 490c ldr r1, [pc, #48] @ (8002190 <__NVIC_SetPriority+0x4c>) + 800215e: f997 3007 ldrsb.w r3, [r7, #7] + 8002162: 0112 lsls r2, r2, #4 + 8002164: b2d2 uxtb r2, r2 + 8002166: 440b add r3, r1 + 8002168: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } - 80013e8: e00a b.n 8001400 <__NVIC_SetPriority+0x40> + 800216c: e00a b.n 8002184 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 80013ea: 683b ldr r3, [r7, #0] - 80013ec: b2da uxtb r2, r3 - 80013ee: 4908 ldr r1, [pc, #32] @ (8001410 <__NVIC_SetPriority+0x50>) - 80013f0: 79fb ldrb r3, [r7, #7] - 80013f2: f003 030f and.w r3, r3, #15 - 80013f6: 3b04 subs r3, #4 - 80013f8: 0112 lsls r2, r2, #4 - 80013fa: b2d2 uxtb r2, r2 - 80013fc: 440b add r3, r1 - 80013fe: 761a strb r2, [r3, #24] + 800216e: 683b ldr r3, [r7, #0] + 8002170: b2da uxtb r2, r3 + 8002172: 4908 ldr r1, [pc, #32] @ (8002194 <__NVIC_SetPriority+0x50>) + 8002174: 79fb ldrb r3, [r7, #7] + 8002176: f003 030f and.w r3, r3, #15 + 800217a: 3b04 subs r3, #4 + 800217c: 0112 lsls r2, r2, #4 + 800217e: b2d2 uxtb r2, r2 + 8002180: 440b add r3, r1 + 8002182: 761a strb r2, [r3, #24] } - 8001400: bf00 nop - 8001402: 370c adds r7, #12 - 8001404: 46bd mov sp, r7 - 8001406: f85d 7b04 ldr.w r7, [sp], #4 - 800140a: 4770 bx lr - 800140c: e000e100 .word 0xe000e100 - 8001410: e000ed00 .word 0xe000ed00 + 8002184: bf00 nop + 8002186: 370c adds r7, #12 + 8002188: 46bd mov sp, r7 + 800218a: f85d 7b04 ldr.w r7, [sp], #4 + 800218e: 4770 bx lr + 8002190: e000e100 .word 0xe000e100 + 8002194: e000ed00 .word 0xe000ed00 -08001414 : +08002198 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { - 8001414: b480 push {r7} - 8001416: b089 sub sp, #36 @ 0x24 - 8001418: af00 add r7, sp, #0 - 800141a: 60f8 str r0, [r7, #12] - 800141c: 60b9 str r1, [r7, #8] - 800141e: 607a str r2, [r7, #4] + 8002198: b480 push {r7} + 800219a: b089 sub sp, #36 @ 0x24 + 800219c: af00 add r7, sp, #0 + 800219e: 60f8 str r0, [r7, #12] + 80021a0: 60b9 str r1, [r7, #8] + 80021a2: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - 8001420: 68fb ldr r3, [r7, #12] - 8001422: f003 0307 and.w r3, r3, #7 - 8001426: 61fb str r3, [r7, #28] + 80021a4: 68fb ldr r3, [r7, #12] + 80021a6: f003 0307 and.w r3, r3, #7 + 80021aa: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - 8001428: 69fb ldr r3, [r7, #28] - 800142a: f1c3 0307 rsb r3, r3, #7 - 800142e: 2b04 cmp r3, #4 - 8001430: bf28 it cs - 8001432: 2304 movcs r3, #4 - 8001434: 61bb str r3, [r7, #24] + 80021ac: 69fb ldr r3, [r7, #28] + 80021ae: f1c3 0307 rsb r3, r3, #7 + 80021b2: 2b04 cmp r3, #4 + 80021b4: bf28 it cs + 80021b6: 2304 movcs r3, #4 + 80021b8: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - 8001436: 69fb ldr r3, [r7, #28] - 8001438: 3304 adds r3, #4 - 800143a: 2b06 cmp r3, #6 - 800143c: d902 bls.n 8001444 - 800143e: 69fb ldr r3, [r7, #28] - 8001440: 3b03 subs r3, #3 - 8001442: e000 b.n 8001446 - 8001444: 2300 movs r3, #0 - 8001446: 617b str r3, [r7, #20] + 80021ba: 69fb ldr r3, [r7, #28] + 80021bc: 3304 adds r3, #4 + 80021be: 2b06 cmp r3, #6 + 80021c0: d902 bls.n 80021c8 + 80021c2: 69fb ldr r3, [r7, #28] + 80021c4: 3b03 subs r3, #3 + 80021c6: e000 b.n 80021ca + 80021c8: 2300 movs r3, #0 + 80021ca: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - 8001448: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff - 800144c: 69bb ldr r3, [r7, #24] - 800144e: fa02 f303 lsl.w r3, r2, r3 - 8001452: 43da mvns r2, r3 - 8001454: 68bb ldr r3, [r7, #8] - 8001456: 401a ands r2, r3 - 8001458: 697b ldr r3, [r7, #20] - 800145a: 409a lsls r2, r3 + 80021cc: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 80021d0: 69bb ldr r3, [r7, #24] + 80021d2: fa02 f303 lsl.w r3, r2, r3 + 80021d6: 43da mvns r2, r3 + 80021d8: 68bb ldr r3, [r7, #8] + 80021da: 401a ands r2, r3 + 80021dc: 697b ldr r3, [r7, #20] + 80021de: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - 800145c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff - 8001460: 697b ldr r3, [r7, #20] - 8001462: fa01 f303 lsl.w r3, r1, r3 - 8001466: 43d9 mvns r1, r3 - 8001468: 687b ldr r3, [r7, #4] - 800146a: 400b ands r3, r1 + 80021e0: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff + 80021e4: 697b ldr r3, [r7, #20] + 80021e6: fa01 f303 lsl.w r3, r1, r3 + 80021ea: 43d9 mvns r1, r3 + 80021ec: 687b ldr r3, [r7, #4] + 80021ee: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - 800146c: 4313 orrs r3, r2 + 80021f0: 4313 orrs r3, r2 ); } - 800146e: 4618 mov r0, r3 - 8001470: 3724 adds r7, #36 @ 0x24 - 8001472: 46bd mov sp, r7 - 8001474: f85d 7b04 ldr.w r7, [sp], #4 - 8001478: 4770 bx lr + 80021f2: 4618 mov r0, r3 + 80021f4: 3724 adds r7, #36 @ 0x24 + 80021f6: 46bd mov sp, r7 + 80021f8: f85d 7b04 ldr.w r7, [sp], #4 + 80021fc: 4770 bx lr ... -0800147c : +08002200 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { - 800147c: b580 push {r7, lr} - 800147e: b082 sub sp, #8 - 8001480: af00 add r7, sp, #0 - 8001482: 6078 str r0, [r7, #4] + 8002200: b580 push {r7, lr} + 8002202: b082 sub sp, #8 + 8002204: af00 add r7, sp, #0 + 8002206: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); - 8001484: 687b ldr r3, [r7, #4] - 8001486: 2b07 cmp r3, #7 - 8001488: d00f beq.n 80014aa - 800148a: 687b ldr r3, [r7, #4] - 800148c: 2b06 cmp r3, #6 - 800148e: d00c beq.n 80014aa - 8001490: 687b ldr r3, [r7, #4] - 8001492: 2b05 cmp r3, #5 - 8001494: d009 beq.n 80014aa - 8001496: 687b ldr r3, [r7, #4] - 8001498: 2b04 cmp r3, #4 - 800149a: d006 beq.n 80014aa - 800149c: 687b ldr r3, [r7, #4] - 800149e: 2b03 cmp r3, #3 - 80014a0: d003 beq.n 80014aa - 80014a2: 2190 movs r1, #144 @ 0x90 - 80014a4: 4804 ldr r0, [pc, #16] @ (80014b8 ) - 80014a6: f7ff f9cf bl 8000848 + 8002208: 687b ldr r3, [r7, #4] + 800220a: 2b07 cmp r3, #7 + 800220c: d00f beq.n 800222e + 800220e: 687b ldr r3, [r7, #4] + 8002210: 2b06 cmp r3, #6 + 8002212: d00c beq.n 800222e + 8002214: 687b ldr r3, [r7, #4] + 8002216: 2b05 cmp r3, #5 + 8002218: d009 beq.n 800222e + 800221a: 687b ldr r3, [r7, #4] + 800221c: 2b04 cmp r3, #4 + 800221e: d006 beq.n 800222e + 8002220: 687b ldr r3, [r7, #4] + 8002222: 2b03 cmp r3, #3 + 8002224: d003 beq.n 800222e + 8002226: 2190 movs r1, #144 @ 0x90 + 8002228: 4804 ldr r0, [pc, #16] @ (800223c ) + 800222a: f7fe fd83 bl 8000d34 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); - 80014aa: 6878 ldr r0, [r7, #4] - 80014ac: f7ff ff38 bl 8001320 <__NVIC_SetPriorityGrouping> + 800222e: 6878 ldr r0, [r7, #4] + 8002230: f7ff ff38 bl 80020a4 <__NVIC_SetPriorityGrouping> } - 80014b0: bf00 nop - 80014b2: 3708 adds r7, #8 - 80014b4: 46bd mov sp, r7 - 80014b6: bd80 pop {r7, pc} - 80014b8: 08005c20 .word 0x08005c20 + 8002234: bf00 nop + 8002236: 3708 adds r7, #8 + 8002238: 46bd mov sp, r7 + 800223a: bd80 pop {r7, pc} + 800223c: 0800a0f4 .word 0x0800a0f4 -080014bc : +08002240 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { - 80014bc: b580 push {r7, lr} - 80014be: b086 sub sp, #24 - 80014c0: af00 add r7, sp, #0 - 80014c2: 4603 mov r3, r0 - 80014c4: 60b9 str r1, [r7, #8] - 80014c6: 607a str r2, [r7, #4] - 80014c8: 73fb strb r3, [r7, #15] + 8002240: b580 push {r7, lr} + 8002242: b086 sub sp, #24 + 8002244: af00 add r7, sp, #0 + 8002246: 4603 mov r3, r0 + 8002248: 60b9 str r1, [r7, #8] + 800224a: 607a str r2, [r7, #4] + 800224c: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; - 80014ca: 2300 movs r3, #0 - 80014cc: 617b str r3, [r7, #20] + 800224e: 2300 movs r3, #0 + 8002250: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); - 80014ce: 687b ldr r3, [r7, #4] - 80014d0: 2b0f cmp r3, #15 - 80014d2: d903 bls.n 80014dc - 80014d4: 21a8 movs r1, #168 @ 0xa8 - 80014d6: 480e ldr r0, [pc, #56] @ (8001510 ) - 80014d8: f7ff f9b6 bl 8000848 + 8002252: 687b ldr r3, [r7, #4] + 8002254: 2b0f cmp r3, #15 + 8002256: d903 bls.n 8002260 + 8002258: 21a8 movs r1, #168 @ 0xa8 + 800225a: 480e ldr r0, [pc, #56] @ (8002294 ) + 800225c: f7fe fd6a bl 8000d34 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); - 80014dc: 68bb ldr r3, [r7, #8] - 80014de: 2b0f cmp r3, #15 - 80014e0: d903 bls.n 80014ea - 80014e2: 21a9 movs r1, #169 @ 0xa9 - 80014e4: 480a ldr r0, [pc, #40] @ (8001510 ) - 80014e6: f7ff f9af bl 8000848 + 8002260: 68bb ldr r3, [r7, #8] + 8002262: 2b0f cmp r3, #15 + 8002264: d903 bls.n 800226e + 8002266: 21a9 movs r1, #169 @ 0xa9 + 8002268: 480a ldr r0, [pc, #40] @ (8002294 ) + 800226a: f7fe fd63 bl 8000d34 prioritygroup = NVIC_GetPriorityGrouping(); - 80014ea: f7ff ff3d bl 8001368 <__NVIC_GetPriorityGrouping> - 80014ee: 6178 str r0, [r7, #20] + 800226e: f7ff ff3d bl 80020ec <__NVIC_GetPriorityGrouping> + 8002272: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); - 80014f0: 687a ldr r2, [r7, #4] - 80014f2: 68b9 ldr r1, [r7, #8] - 80014f4: 6978 ldr r0, [r7, #20] - 80014f6: f7ff ff8d bl 8001414 - 80014fa: 4602 mov r2, r0 - 80014fc: f997 300f ldrsb.w r3, [r7, #15] - 8001500: 4611 mov r1, r2 - 8001502: 4618 mov r0, r3 - 8001504: f7ff ff5c bl 80013c0 <__NVIC_SetPriority> + 8002274: 687a ldr r2, [r7, #4] + 8002276: 68b9 ldr r1, [r7, #8] + 8002278: 6978 ldr r0, [r7, #20] + 800227a: f7ff ff8d bl 8002198 + 800227e: 4602 mov r2, r0 + 8002280: f997 300f ldrsb.w r3, [r7, #15] + 8002284: 4611 mov r1, r2 + 8002286: 4618 mov r0, r3 + 8002288: f7ff ff5c bl 8002144 <__NVIC_SetPriority> } - 8001508: bf00 nop - 800150a: 3718 adds r7, #24 - 800150c: 46bd mov sp, r7 - 800150e: bd80 pop {r7, pc} - 8001510: 08005c20 .word 0x08005c20 + 800228c: bf00 nop + 800228e: 3718 adds r7, #24 + 8002290: 46bd mov sp, r7 + 8002292: bd80 pop {r7, pc} + 8002294: 0800a0f4 .word 0x0800a0f4 -08001514 : +08002298 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { - 8001514: b580 push {r7, lr} - 8001516: b082 sub sp, #8 - 8001518: af00 add r7, sp, #0 - 800151a: 4603 mov r3, r0 - 800151c: 71fb strb r3, [r7, #7] + 8002298: b580 push {r7, lr} + 800229a: b082 sub sp, #8 + 800229c: af00 add r7, sp, #0 + 800229e: 4603 mov r3, r0 + 80022a0: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - 800151e: f997 3007 ldrsb.w r3, [r7, #7] - 8001522: 2b00 cmp r3, #0 - 8001524: da03 bge.n 800152e - 8001526: 21bc movs r1, #188 @ 0xbc - 8001528: 4805 ldr r0, [pc, #20] @ (8001540 ) - 800152a: f7ff f98d bl 8000848 + 80022a2: f997 3007 ldrsb.w r3, [r7, #7] + 80022a6: 2b00 cmp r3, #0 + 80022a8: da03 bge.n 80022b2 + 80022aa: 21bc movs r1, #188 @ 0xbc + 80022ac: 4805 ldr r0, [pc, #20] @ (80022c4 ) + 80022ae: f7fe fd41 bl 8000d34 /* Enable interrupt */ NVIC_EnableIRQ(IRQn); - 800152e: f997 3007 ldrsb.w r3, [r7, #7] - 8001532: 4618 mov r0, r3 - 8001534: f7ff ff26 bl 8001384 <__NVIC_EnableIRQ> + 80022b2: f997 3007 ldrsb.w r3, [r7, #7] + 80022b6: 4618 mov r0, r3 + 80022b8: f7ff ff26 bl 8002108 <__NVIC_EnableIRQ> } - 8001538: bf00 nop - 800153a: 3708 adds r7, #8 - 800153c: 46bd mov sp, r7 - 800153e: bd80 pop {r7, pc} - 8001540: 08005c20 .word 0x08005c20 + 80022bc: bf00 nop + 80022be: 3708 adds r7, #8 + 80022c0: 46bd mov sp, r7 + 80022c2: bd80 pop {r7, pc} + 80022c4: 0800a0f4 .word 0x0800a0f4 -08001544 : +080022c8 : + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + 80022c8: b580 push {r7, lr} + 80022ca: b086 sub sp, #24 + 80022cc: af00 add r7, sp, #0 + 80022ce: 6078 str r0, [r7, #4] + uint32_t tmp = 0U; + 80022d0: 2300 movs r3, #0 + 80022d2: 617b str r3, [r7, #20] + uint32_t tickstart = HAL_GetTick(); + 80022d4: f7ff f8b0 bl 8001438 + 80022d8: 6138 str r0, [r7, #16] + DMA_Base_Registers *regs; + + /* Check the DMA peripheral state */ + if(hdma == NULL) + 80022da: 687b ldr r3, [r7, #4] + 80022dc: 2b00 cmp r3, #0 + 80022de: d101 bne.n 80022e4 + { + return HAL_ERROR; + 80022e0: 2301 movs r3, #1 + 80022e2: e203 b.n 80026ec + } + + /* Check the parameters */ + assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); + 80022e4: 687b ldr r3, [r7, #4] + 80022e6: 681b ldr r3, [r3, #0] + 80022e8: 4a8b ldr r2, [pc, #556] @ (8002518 ) + 80022ea: 4293 cmp r3, r2 + 80022ec: d04e beq.n 800238c + 80022ee: 687b ldr r3, [r7, #4] + 80022f0: 681b ldr r3, [r3, #0] + 80022f2: 4a8a ldr r2, [pc, #552] @ (800251c ) + 80022f4: 4293 cmp r3, r2 + 80022f6: d049 beq.n 800238c + 80022f8: 687b ldr r3, [r7, #4] + 80022fa: 681b ldr r3, [r3, #0] + 80022fc: 4a88 ldr r2, [pc, #544] @ (8002520 ) + 80022fe: 4293 cmp r3, r2 + 8002300: d044 beq.n 800238c + 8002302: 687b ldr r3, [r7, #4] + 8002304: 681b ldr r3, [r3, #0] + 8002306: 4a87 ldr r2, [pc, #540] @ (8002524 ) + 8002308: 4293 cmp r3, r2 + 800230a: d03f beq.n 800238c + 800230c: 687b ldr r3, [r7, #4] + 800230e: 681b ldr r3, [r3, #0] + 8002310: 4a85 ldr r2, [pc, #532] @ (8002528 ) + 8002312: 4293 cmp r3, r2 + 8002314: d03a beq.n 800238c + 8002316: 687b ldr r3, [r7, #4] + 8002318: 681b ldr r3, [r3, #0] + 800231a: 4a84 ldr r2, [pc, #528] @ (800252c ) + 800231c: 4293 cmp r3, r2 + 800231e: d035 beq.n 800238c + 8002320: 687b ldr r3, [r7, #4] + 8002322: 681b ldr r3, [r3, #0] + 8002324: 4a82 ldr r2, [pc, #520] @ (8002530 ) + 8002326: 4293 cmp r3, r2 + 8002328: d030 beq.n 800238c + 800232a: 687b ldr r3, [r7, #4] + 800232c: 681b ldr r3, [r3, #0] + 800232e: 4a81 ldr r2, [pc, #516] @ (8002534 ) + 8002330: 4293 cmp r3, r2 + 8002332: d02b beq.n 800238c + 8002334: 687b ldr r3, [r7, #4] + 8002336: 681b ldr r3, [r3, #0] + 8002338: 4a7f ldr r2, [pc, #508] @ (8002538 ) + 800233a: 4293 cmp r3, r2 + 800233c: d026 beq.n 800238c + 800233e: 687b ldr r3, [r7, #4] + 8002340: 681b ldr r3, [r3, #0] + 8002342: 4a7e ldr r2, [pc, #504] @ (800253c ) + 8002344: 4293 cmp r3, r2 + 8002346: d021 beq.n 800238c + 8002348: 687b ldr r3, [r7, #4] + 800234a: 681b ldr r3, [r3, #0] + 800234c: 4a7c ldr r2, [pc, #496] @ (8002540 ) + 800234e: 4293 cmp r3, r2 + 8002350: d01c beq.n 800238c + 8002352: 687b ldr r3, [r7, #4] + 8002354: 681b ldr r3, [r3, #0] + 8002356: 4a7b ldr r2, [pc, #492] @ (8002544 ) + 8002358: 4293 cmp r3, r2 + 800235a: d017 beq.n 800238c + 800235c: 687b ldr r3, [r7, #4] + 800235e: 681b ldr r3, [r3, #0] + 8002360: 4a79 ldr r2, [pc, #484] @ (8002548 ) + 8002362: 4293 cmp r3, r2 + 8002364: d012 beq.n 800238c + 8002366: 687b ldr r3, [r7, #4] + 8002368: 681b ldr r3, [r3, #0] + 800236a: 4a78 ldr r2, [pc, #480] @ (800254c ) + 800236c: 4293 cmp r3, r2 + 800236e: d00d beq.n 800238c + 8002370: 687b ldr r3, [r7, #4] + 8002372: 681b ldr r3, [r3, #0] + 8002374: 4a76 ldr r2, [pc, #472] @ (8002550 ) + 8002376: 4293 cmp r3, r2 + 8002378: d008 beq.n 800238c + 800237a: 687b ldr r3, [r7, #4] + 800237c: 681b ldr r3, [r3, #0] + 800237e: 4a75 ldr r2, [pc, #468] @ (8002554 ) + 8002380: 4293 cmp r3, r2 + 8002382: d003 beq.n 800238c + 8002384: 21b7 movs r1, #183 @ 0xb7 + 8002386: 4874 ldr r0, [pc, #464] @ (8002558 ) + 8002388: f7fe fcd4 bl 8000d34 + assert_param(IS_DMA_CHANNEL(hdma->Init.Channel)); + 800238c: 687b ldr r3, [r7, #4] + 800238e: 685b ldr r3, [r3, #4] + 8002390: 2b00 cmp r3, #0 + 8002392: d026 beq.n 80023e2 + 8002394: 687b ldr r3, [r7, #4] + 8002396: 685b ldr r3, [r3, #4] + 8002398: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 + 800239c: d021 beq.n 80023e2 + 800239e: 687b ldr r3, [r7, #4] + 80023a0: 685b ldr r3, [r3, #4] + 80023a2: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 + 80023a6: d01c beq.n 80023e2 + 80023a8: 687b ldr r3, [r7, #4] + 80023aa: 685b ldr r3, [r3, #4] + 80023ac: f1b3 6fc0 cmp.w r3, #100663296 @ 0x6000000 + 80023b0: d017 beq.n 80023e2 + 80023b2: 687b ldr r3, [r7, #4] + 80023b4: 685b ldr r3, [r3, #4] + 80023b6: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 + 80023ba: d012 beq.n 80023e2 + 80023bc: 687b ldr r3, [r7, #4] + 80023be: 685b ldr r3, [r3, #4] + 80023c0: f1b3 6f20 cmp.w r3, #167772160 @ 0xa000000 + 80023c4: d00d beq.n 80023e2 + 80023c6: 687b ldr r3, [r7, #4] + 80023c8: 685b ldr r3, [r3, #4] + 80023ca: f1b3 6f40 cmp.w r3, #201326592 @ 0xc000000 + 80023ce: d008 beq.n 80023e2 + 80023d0: 687b ldr r3, [r7, #4] + 80023d2: 685b ldr r3, [r3, #4] + 80023d4: f1b3 6f60 cmp.w r3, #234881024 @ 0xe000000 + 80023d8: d003 beq.n 80023e2 + 80023da: 21b8 movs r1, #184 @ 0xb8 + 80023dc: 485e ldr r0, [pc, #376] @ (8002558 ) + 80023de: f7fe fca9 bl 8000d34 + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + 80023e2: 687b ldr r3, [r7, #4] + 80023e4: 689b ldr r3, [r3, #8] + 80023e6: 2b00 cmp r3, #0 + 80023e8: d00b beq.n 8002402 + 80023ea: 687b ldr r3, [r7, #4] + 80023ec: 689b ldr r3, [r3, #8] + 80023ee: 2b40 cmp r3, #64 @ 0x40 + 80023f0: d007 beq.n 8002402 + 80023f2: 687b ldr r3, [r7, #4] + 80023f4: 689b ldr r3, [r3, #8] + 80023f6: 2b80 cmp r3, #128 @ 0x80 + 80023f8: d003 beq.n 8002402 + 80023fa: 21b9 movs r1, #185 @ 0xb9 + 80023fc: 4856 ldr r0, [pc, #344] @ (8002558 ) + 80023fe: f7fe fc99 bl 8000d34 + assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + 8002402: 687b ldr r3, [r7, #4] + 8002404: 68db ldr r3, [r3, #12] + 8002406: f5b3 7f00 cmp.w r3, #512 @ 0x200 + 800240a: d007 beq.n 800241c + 800240c: 687b ldr r3, [r7, #4] + 800240e: 68db ldr r3, [r3, #12] + 8002410: 2b00 cmp r3, #0 + 8002412: d003 beq.n 800241c + 8002414: 21ba movs r1, #186 @ 0xba + 8002416: 4850 ldr r0, [pc, #320] @ (8002558 ) + 8002418: f7fe fc8c bl 8000d34 + assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + 800241c: 687b ldr r3, [r7, #4] + 800241e: 691b ldr r3, [r3, #16] + 8002420: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 8002424: d007 beq.n 8002436 + 8002426: 687b ldr r3, [r7, #4] + 8002428: 691b ldr r3, [r3, #16] + 800242a: 2b00 cmp r3, #0 + 800242c: d003 beq.n 8002436 + 800242e: 21bb movs r1, #187 @ 0xbb + 8002430: 4849 ldr r0, [pc, #292] @ (8002558 ) + 8002432: f7fe fc7f bl 8000d34 + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + 8002436: 687b ldr r3, [r7, #4] + 8002438: 695b ldr r3, [r3, #20] + 800243a: 2b00 cmp r3, #0 + 800243c: d00d beq.n 800245a + 800243e: 687b ldr r3, [r7, #4] + 8002440: 695b ldr r3, [r3, #20] + 8002442: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 8002446: d008 beq.n 800245a + 8002448: 687b ldr r3, [r7, #4] + 800244a: 695b ldr r3, [r3, #20] + 800244c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 8002450: d003 beq.n 800245a + 8002452: 21bc movs r1, #188 @ 0xbc + 8002454: 4840 ldr r0, [pc, #256] @ (8002558 ) + 8002456: f7fe fc6d bl 8000d34 + assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + 800245a: 687b ldr r3, [r7, #4] + 800245c: 699b ldr r3, [r3, #24] + 800245e: 2b00 cmp r3, #0 + 8002460: d00d beq.n 800247e + 8002462: 687b ldr r3, [r7, #4] + 8002464: 699b ldr r3, [r3, #24] + 8002466: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 800246a: d008 beq.n 800247e + 800246c: 687b ldr r3, [r7, #4] + 800246e: 699b ldr r3, [r3, #24] + 8002470: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 + 8002474: d003 beq.n 800247e + 8002476: 21bd movs r1, #189 @ 0xbd + 8002478: 4837 ldr r0, [pc, #220] @ (8002558 ) + 800247a: f7fe fc5b bl 8000d34 + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + 800247e: 687b ldr r3, [r7, #4] + 8002480: 69db ldr r3, [r3, #28] + 8002482: 2b00 cmp r3, #0 + 8002484: d00c beq.n 80024a0 + 8002486: 687b ldr r3, [r7, #4] + 8002488: 69db ldr r3, [r3, #28] + 800248a: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 800248e: d007 beq.n 80024a0 + 8002490: 687b ldr r3, [r7, #4] + 8002492: 69db ldr r3, [r3, #28] + 8002494: 2b20 cmp r3, #32 + 8002496: d003 beq.n 80024a0 + 8002498: 21be movs r1, #190 @ 0xbe + 800249a: 482f ldr r0, [pc, #188] @ (8002558 ) + 800249c: f7fe fc4a bl 8000d34 + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + 80024a0: 687b ldr r3, [r7, #4] + 80024a2: 6a1b ldr r3, [r3, #32] + 80024a4: 2b00 cmp r3, #0 + 80024a6: d012 beq.n 80024ce + 80024a8: 687b ldr r3, [r7, #4] + 80024aa: 6a1b ldr r3, [r3, #32] + 80024ac: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 80024b0: d00d beq.n 80024ce + 80024b2: 687b ldr r3, [r7, #4] + 80024b4: 6a1b ldr r3, [r3, #32] + 80024b6: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 + 80024ba: d008 beq.n 80024ce + 80024bc: 687b ldr r3, [r7, #4] + 80024be: 6a1b ldr r3, [r3, #32] + 80024c0: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 + 80024c4: d003 beq.n 80024ce + 80024c6: 21bf movs r1, #191 @ 0xbf + 80024c8: 4823 ldr r0, [pc, #140] @ (8002558 ) + 80024ca: f7fe fc33 bl 8000d34 + assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode)); + 80024ce: 687b ldr r3, [r7, #4] + 80024d0: 6a5b ldr r3, [r3, #36] @ 0x24 + 80024d2: 2b00 cmp r3, #0 + 80024d4: d007 beq.n 80024e6 + 80024d6: 687b ldr r3, [r7, #4] + 80024d8: 6a5b ldr r3, [r3, #36] @ 0x24 + 80024da: 2b04 cmp r3, #4 + 80024dc: d003 beq.n 80024e6 + 80024de: 21c0 movs r1, #192 @ 0xc0 + 80024e0: 481d ldr r0, [pc, #116] @ (8002558 ) + 80024e2: f7fe fc27 bl 8000d34 + /* Check the memory burst, peripheral burst and FIFO threshold parameters only + when FIFO mode is enabled */ + if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE) + 80024e6: 687b ldr r3, [r7, #4] + 80024e8: 6a5b ldr r3, [r3, #36] @ 0x24 + 80024ea: 2b00 cmp r3, #0 + 80024ec: d064 beq.n 80025b8 + { + assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold)); + 80024ee: 687b ldr r3, [r7, #4] + 80024f0: 6a9b ldr r3, [r3, #40] @ 0x28 + 80024f2: 2b00 cmp r3, #0 + 80024f4: d032 beq.n 800255c + 80024f6: 687b ldr r3, [r7, #4] + 80024f8: 6a9b ldr r3, [r3, #40] @ 0x28 + 80024fa: 2b01 cmp r3, #1 + 80024fc: d02e beq.n 800255c + 80024fe: 687b ldr r3, [r7, #4] + 8002500: 6a9b ldr r3, [r3, #40] @ 0x28 + 8002502: 2b02 cmp r3, #2 + 8002504: d02a beq.n 800255c + 8002506: 687b ldr r3, [r7, #4] + 8002508: 6a9b ldr r3, [r3, #40] @ 0x28 + 800250a: 2b03 cmp r3, #3 + 800250c: d026 beq.n 800255c + 800250e: 21c5 movs r1, #197 @ 0xc5 + 8002510: 4811 ldr r0, [pc, #68] @ (8002558 ) + 8002512: f7fe fc0f bl 8000d34 + 8002516: e021 b.n 800255c + 8002518: 40026010 .word 0x40026010 + 800251c: 40026028 .word 0x40026028 + 8002520: 40026040 .word 0x40026040 + 8002524: 40026058 .word 0x40026058 + 8002528: 40026070 .word 0x40026070 + 800252c: 40026088 .word 0x40026088 + 8002530: 400260a0 .word 0x400260a0 + 8002534: 400260b8 .word 0x400260b8 + 8002538: 40026410 .word 0x40026410 + 800253c: 40026428 .word 0x40026428 + 8002540: 40026440 .word 0x40026440 + 8002544: 40026458 .word 0x40026458 + 8002548: 40026470 .word 0x40026470 + 800254c: 40026488 .word 0x40026488 + 8002550: 400264a0 .word 0x400264a0 + 8002554: 400264b8 .word 0x400264b8 + 8002558: 0800a130 .word 0x0800a130 + assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); + 800255c: 687b ldr r3, [r7, #4] + 800255e: 6adb ldr r3, [r3, #44] @ 0x2c + 8002560: 2b00 cmp r3, #0 + 8002562: d012 beq.n 800258a + 8002564: 687b ldr r3, [r7, #4] + 8002566: 6adb ldr r3, [r3, #44] @ 0x2c + 8002568: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 + 800256c: d00d beq.n 800258a + 800256e: 687b ldr r3, [r7, #4] + 8002570: 6adb ldr r3, [r3, #44] @ 0x2c + 8002572: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 + 8002576: d008 beq.n 800258a + 8002578: 687b ldr r3, [r7, #4] + 800257a: 6adb ldr r3, [r3, #44] @ 0x2c + 800257c: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 + 8002580: d003 beq.n 800258a + 8002582: 21c6 movs r1, #198 @ 0xc6 + 8002584: 485b ldr r0, [pc, #364] @ (80026f4 ) + 8002586: f7fe fbd5 bl 8000d34 + assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); + 800258a: 687b ldr r3, [r7, #4] + 800258c: 6b1b ldr r3, [r3, #48] @ 0x30 + 800258e: 2b00 cmp r3, #0 + 8002590: d012 beq.n 80025b8 + 8002592: 687b ldr r3, [r7, #4] + 8002594: 6b1b ldr r3, [r3, #48] @ 0x30 + 8002596: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 + 800259a: d00d beq.n 80025b8 + 800259c: 687b ldr r3, [r7, #4] + 800259e: 6b1b ldr r3, [r3, #48] @ 0x30 + 80025a0: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 + 80025a4: d008 beq.n 80025b8 + 80025a6: 687b ldr r3, [r7, #4] + 80025a8: 6b1b ldr r3, [r3, #48] @ 0x30 + 80025aa: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 + 80025ae: d003 beq.n 80025b8 + 80025b0: 21c7 movs r1, #199 @ 0xc7 + 80025b2: 4850 ldr r0, [pc, #320] @ (80026f4 ) + 80025b4: f7fe fbbe bl 8000d34 + } + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + 80025b8: 687b ldr r3, [r7, #4] + 80025ba: 2202 movs r2, #2 + 80025bc: f883 2035 strb.w r2, [r3, #53] @ 0x35 + + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + 80025c0: 687b ldr r3, [r7, #4] + 80025c2: 2200 movs r2, #0 + 80025c4: f883 2034 strb.w r2, [r3, #52] @ 0x34 + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + 80025c8: 687b ldr r3, [r7, #4] + 80025ca: 681b ldr r3, [r3, #0] + 80025cc: 681a ldr r2, [r3, #0] + 80025ce: 687b ldr r3, [r7, #4] + 80025d0: 681b ldr r3, [r3, #0] + 80025d2: f022 0201 bic.w r2, r2, #1 + 80025d6: 601a str r2, [r3, #0] + + /* Check if the DMA Stream is effectively disabled */ + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) + 80025d8: e00f b.n 80025fa + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + 80025da: f7fe ff2d bl 8001438 + 80025de: 4602 mov r2, r0 + 80025e0: 693b ldr r3, [r7, #16] + 80025e2: 1ad3 subs r3, r2, r3 + 80025e4: 2b05 cmp r3, #5 + 80025e6: d908 bls.n 80025fa + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + 80025e8: 687b ldr r3, [r7, #4] + 80025ea: 2220 movs r2, #32 + 80025ec: 655a str r2, [r3, #84] @ 0x54 + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_TIMEOUT; + 80025ee: 687b ldr r3, [r7, #4] + 80025f0: 2203 movs r2, #3 + 80025f2: f883 2035 strb.w r2, [r3, #53] @ 0x35 + + return HAL_TIMEOUT; + 80025f6: 2303 movs r3, #3 + 80025f8: e078 b.n 80026ec + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) + 80025fa: 687b ldr r3, [r7, #4] + 80025fc: 681b ldr r3, [r3, #0] + 80025fe: 681b ldr r3, [r3, #0] + 8002600: f003 0301 and.w r3, r3, #1 + 8002604: 2b00 cmp r3, #0 + 8002606: d1e8 bne.n 80025da + } + } + + /* Get the CR register value */ + tmp = hdma->Instance->CR; + 8002608: 687b ldr r3, [r7, #4] + 800260a: 681b ldr r3, [r3, #0] + 800260c: 681b ldr r3, [r3, #0] + 800260e: 617b str r3, [r7, #20] + + /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ + tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ + 8002610: 697a ldr r2, [r7, #20] + 8002612: 4b39 ldr r3, [pc, #228] @ (80026f8 ) + 8002614: 4013 ands r3, r2 + 8002616: 617b str r3, [r7, #20] + DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ + DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ + DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); + + /* Prepare the DMA Stream configuration */ + tmp |= hdma->Init.Channel | hdma->Init.Direction | + 8002618: 687b ldr r3, [r7, #4] + 800261a: 685a ldr r2, [r3, #4] + 800261c: 687b ldr r3, [r7, #4] + 800261e: 689b ldr r3, [r3, #8] + 8002620: 431a orrs r2, r3 + hdma->Init.PeriphInc | hdma->Init.MemInc | + 8002622: 687b ldr r3, [r7, #4] + 8002624: 68db ldr r3, [r3, #12] + tmp |= hdma->Init.Channel | hdma->Init.Direction | + 8002626: 431a orrs r2, r3 + hdma->Init.PeriphInc | hdma->Init.MemInc | + 8002628: 687b ldr r3, [r7, #4] + 800262a: 691b ldr r3, [r3, #16] + 800262c: 431a orrs r2, r3 + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 800262e: 687b ldr r3, [r7, #4] + 8002630: 695b ldr r3, [r3, #20] + hdma->Init.PeriphInc | hdma->Init.MemInc | + 8002632: 431a orrs r2, r3 + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 8002634: 687b ldr r3, [r7, #4] + 8002636: 699b ldr r3, [r3, #24] + 8002638: 431a orrs r2, r3 + hdma->Init.Mode | hdma->Init.Priority; + 800263a: 687b ldr r3, [r7, #4] + 800263c: 69db ldr r3, [r3, #28] + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 800263e: 431a orrs r2, r3 + hdma->Init.Mode | hdma->Init.Priority; + 8002640: 687b ldr r3, [r7, #4] + 8002642: 6a1b ldr r3, [r3, #32] + 8002644: 4313 orrs r3, r2 + tmp |= hdma->Init.Channel | hdma->Init.Direction | + 8002646: 697a ldr r2, [r7, #20] + 8002648: 4313 orrs r3, r2 + 800264a: 617b str r3, [r7, #20] + + /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + 800264c: 687b ldr r3, [r7, #4] + 800264e: 6a5b ldr r3, [r3, #36] @ 0x24 + 8002650: 2b04 cmp r3, #4 + 8002652: d107 bne.n 8002664 + { + /* Get memory burst and peripheral burst */ + tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; + 8002654: 687b ldr r3, [r7, #4] + 8002656: 6ada ldr r2, [r3, #44] @ 0x2c + 8002658: 687b ldr r3, [r7, #4] + 800265a: 6b1b ldr r3, [r3, #48] @ 0x30 + 800265c: 4313 orrs r3, r2 + 800265e: 697a ldr r2, [r7, #20] + 8002660: 4313 orrs r3, r2 + 8002662: 617b str r3, [r7, #20] + } + + /* Write to DMA Stream CR register */ + hdma->Instance->CR = tmp; + 8002664: 687b ldr r3, [r7, #4] + 8002666: 681b ldr r3, [r3, #0] + 8002668: 697a ldr r2, [r7, #20] + 800266a: 601a str r2, [r3, #0] + + /* Get the FCR register value */ + tmp = hdma->Instance->FCR; + 800266c: 687b ldr r3, [r7, #4] + 800266e: 681b ldr r3, [r3, #0] + 8002670: 695b ldr r3, [r3, #20] + 8002672: 617b str r3, [r7, #20] + + /* Clear Direct mode and FIFO threshold bits */ + tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); + 8002674: 697b ldr r3, [r7, #20] + 8002676: f023 0307 bic.w r3, r3, #7 + 800267a: 617b str r3, [r7, #20] + + /* Prepare the DMA Stream FIFO configuration */ + tmp |= hdma->Init.FIFOMode; + 800267c: 687b ldr r3, [r7, #4] + 800267e: 6a5b ldr r3, [r3, #36] @ 0x24 + 8002680: 697a ldr r2, [r7, #20] + 8002682: 4313 orrs r3, r2 + 8002684: 617b str r3, [r7, #20] + + /* The FIFO threshold is not used when the FIFO mode is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + 8002686: 687b ldr r3, [r7, #4] + 8002688: 6a5b ldr r3, [r3, #36] @ 0x24 + 800268a: 2b04 cmp r3, #4 + 800268c: d117 bne.n 80026be + { + /* Get the FIFO threshold */ + tmp |= hdma->Init.FIFOThreshold; + 800268e: 687b ldr r3, [r7, #4] + 8002690: 6a9b ldr r3, [r3, #40] @ 0x28 + 8002692: 697a ldr r2, [r7, #20] + 8002694: 4313 orrs r3, r2 + 8002696: 617b str r3, [r7, #20] + + /* Check compatibility between FIFO threshold level and size of the memory burst */ + /* for INCR4, INCR8, INCR16 bursts */ + if (hdma->Init.MemBurst != DMA_MBURST_SINGLE) + 8002698: 687b ldr r3, [r7, #4] + 800269a: 6adb ldr r3, [r3, #44] @ 0x2c + 800269c: 2b00 cmp r3, #0 + 800269e: d00e beq.n 80026be + { + if (DMA_CheckFifoParam(hdma) != HAL_OK) + 80026a0: 6878 ldr r0, [r7, #4] + 80026a2: f000 fa0d bl 8002ac0 + 80026a6: 4603 mov r3, r0 + 80026a8: 2b00 cmp r3, #0 + 80026aa: d008 beq.n 80026be + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + 80026ac: 687b ldr r3, [r7, #4] + 80026ae: 2240 movs r2, #64 @ 0x40 + 80026b0: 655a str r2, [r3, #84] @ 0x54 + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + 80026b2: 687b ldr r3, [r7, #4] + 80026b4: 2201 movs r2, #1 + 80026b6: f883 2035 strb.w r2, [r3, #53] @ 0x35 + + return HAL_ERROR; + 80026ba: 2301 movs r3, #1 + 80026bc: e016 b.n 80026ec + } + } + } + + /* Write to DMA Stream FCR */ + hdma->Instance->FCR = tmp; + 80026be: 687b ldr r3, [r7, #4] + 80026c0: 681b ldr r3, [r3, #0] + 80026c2: 697a ldr r2, [r7, #20] + 80026c4: 615a str r2, [r3, #20] + + /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate + DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ + regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + 80026c6: 6878 ldr r0, [r7, #4] + 80026c8: f000 f9c4 bl 8002a54 + 80026cc: 4603 mov r3, r0 + 80026ce: 60fb str r3, [r7, #12] + + /* Clear all interrupt flags */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + 80026d0: 687b ldr r3, [r7, #4] + 80026d2: 6ddb ldr r3, [r3, #92] @ 0x5c + 80026d4: 223f movs r2, #63 @ 0x3f + 80026d6: 409a lsls r2, r3 + 80026d8: 68fb ldr r3, [r7, #12] + 80026da: 609a str r2, [r3, #8] + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 80026dc: 687b ldr r3, [r7, #4] + 80026de: 2200 movs r2, #0 + 80026e0: 655a str r2, [r3, #84] @ 0x54 + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + 80026e2: 687b ldr r3, [r7, #4] + 80026e4: 2201 movs r2, #1 + 80026e6: f883 2035 strb.w r2, [r3, #53] @ 0x35 + + return HAL_OK; + 80026ea: 2300 movs r3, #0 +} + 80026ec: 4618 mov r0, r3 + 80026ee: 3718 adds r7, #24 + 80026f0: 46bd mov sp, r7 + 80026f2: bd80 pop {r7, pc} + 80026f4: 0800a130 .word 0x0800a130 + 80026f8: f010803f .word 0xf010803f + +080026fc : + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + 80026fc: b480 push {r7} + 80026fe: b083 sub sp, #12 + 8002700: af00 add r7, sp, #0 + 8002702: 6078 str r0, [r7, #4] + if(hdma->State != HAL_DMA_STATE_BUSY) + 8002704: 687b ldr r3, [r7, #4] + 8002706: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 + 800270a: b2db uxtb r3, r3 + 800270c: 2b02 cmp r3, #2 + 800270e: d004 beq.n 800271a + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 8002710: 687b ldr r3, [r7, #4] + 8002712: 2280 movs r2, #128 @ 0x80 + 8002714: 655a str r2, [r3, #84] @ 0x54 + return HAL_ERROR; + 8002716: 2301 movs r3, #1 + 8002718: e00c b.n 8002734 + } + else + { + /* Set Abort State */ + hdma->State = HAL_DMA_STATE_ABORT; + 800271a: 687b ldr r3, [r7, #4] + 800271c: 2205 movs r2, #5 + 800271e: f883 2035 strb.w r2, [r3, #53] @ 0x35 + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + 8002722: 687b ldr r3, [r7, #4] + 8002724: 681b ldr r3, [r3, #0] + 8002726: 681a ldr r2, [r3, #0] + 8002728: 687b ldr r3, [r7, #4] + 800272a: 681b ldr r3, [r3, #0] + 800272c: f022 0201 bic.w r2, r2, #1 + 8002730: 601a str r2, [r3, #0] + } + + return HAL_OK; + 8002732: 2300 movs r3, #0 +} + 8002734: 4618 mov r0, r3 + 8002736: 370c adds r7, #12 + 8002738: 46bd mov sp, r7 + 800273a: f85d 7b04 ldr.w r7, [sp], #4 + 800273e: 4770 bx lr + +08002740 : + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + 8002740: b580 push {r7, lr} + 8002742: b086 sub sp, #24 + 8002744: af00 add r7, sp, #0 + 8002746: 6078 str r0, [r7, #4] + uint32_t tmpisr; + __IO uint32_t count = 0U; + 8002748: 2300 movs r3, #0 + 800274a: 60bb str r3, [r7, #8] + uint32_t timeout = SystemCoreClock / 9600U; + 800274c: 4b8e ldr r3, [pc, #568] @ (8002988 ) + 800274e: 681b ldr r3, [r3, #0] + 8002750: 4a8e ldr r2, [pc, #568] @ (800298c ) + 8002752: fba2 2303 umull r2, r3, r2, r3 + 8002756: 0a9b lsrs r3, r3, #10 + 8002758: 617b str r3, [r7, #20] + + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + 800275a: 687b ldr r3, [r7, #4] + 800275c: 6d9b ldr r3, [r3, #88] @ 0x58 + 800275e: 613b str r3, [r7, #16] + + tmpisr = regs->ISR; + 8002760: 693b ldr r3, [r7, #16] + 8002762: 681b ldr r3, [r3, #0] + 8002764: 60fb str r3, [r7, #12] + + /* Transfer Error Interrupt management ***************************************/ + if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) + 8002766: 687b ldr r3, [r7, #4] + 8002768: 6ddb ldr r3, [r3, #92] @ 0x5c + 800276a: 2208 movs r2, #8 + 800276c: 409a lsls r2, r3 + 800276e: 68fb ldr r3, [r7, #12] + 8002770: 4013 ands r3, r2 + 8002772: 2b00 cmp r3, #0 + 8002774: d01a beq.n 80027ac + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) + 8002776: 687b ldr r3, [r7, #4] + 8002778: 681b ldr r3, [r3, #0] + 800277a: 681b ldr r3, [r3, #0] + 800277c: f003 0304 and.w r3, r3, #4 + 8002780: 2b00 cmp r3, #0 + 8002782: d013 beq.n 80027ac + { + /* Disable the transfer error interrupt */ + hdma->Instance->CR &= ~(DMA_IT_TE); + 8002784: 687b ldr r3, [r7, #4] + 8002786: 681b ldr r3, [r3, #0] + 8002788: 681a ldr r2, [r3, #0] + 800278a: 687b ldr r3, [r7, #4] + 800278c: 681b ldr r3, [r3, #0] + 800278e: f022 0204 bic.w r2, r2, #4 + 8002792: 601a str r2, [r3, #0] + + /* Clear the transfer error flag */ + regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; + 8002794: 687b ldr r3, [r7, #4] + 8002796: 6ddb ldr r3, [r3, #92] @ 0x5c + 8002798: 2208 movs r2, #8 + 800279a: 409a lsls r2, r3 + 800279c: 693b ldr r3, [r7, #16] + 800279e: 609a str r2, [r3, #8] + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TE; + 80027a0: 687b ldr r3, [r7, #4] + 80027a2: 6d5b ldr r3, [r3, #84] @ 0x54 + 80027a4: f043 0201 orr.w r2, r3, #1 + 80027a8: 687b ldr r3, [r7, #4] + 80027aa: 655a str r2, [r3, #84] @ 0x54 + } + } + /* FIFO Error Interrupt management ******************************************/ + if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) + 80027ac: 687b ldr r3, [r7, #4] + 80027ae: 6ddb ldr r3, [r3, #92] @ 0x5c + 80027b0: 2201 movs r2, #1 + 80027b2: 409a lsls r2, r3 + 80027b4: 68fb ldr r3, [r7, #12] + 80027b6: 4013 ands r3, r2 + 80027b8: 2b00 cmp r3, #0 + 80027ba: d012 beq.n 80027e2 + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) + 80027bc: 687b ldr r3, [r7, #4] + 80027be: 681b ldr r3, [r3, #0] + 80027c0: 695b ldr r3, [r3, #20] + 80027c2: f003 0380 and.w r3, r3, #128 @ 0x80 + 80027c6: 2b00 cmp r3, #0 + 80027c8: d00b beq.n 80027e2 + { + /* Clear the FIFO error flag */ + regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; + 80027ca: 687b ldr r3, [r7, #4] + 80027cc: 6ddb ldr r3, [r3, #92] @ 0x5c + 80027ce: 2201 movs r2, #1 + 80027d0: 409a lsls r2, r3 + 80027d2: 693b ldr r3, [r7, #16] + 80027d4: 609a str r2, [r3, #8] + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_FE; + 80027d6: 687b ldr r3, [r7, #4] + 80027d8: 6d5b ldr r3, [r3, #84] @ 0x54 + 80027da: f043 0202 orr.w r2, r3, #2 + 80027de: 687b ldr r3, [r7, #4] + 80027e0: 655a str r2, [r3, #84] @ 0x54 + } + } + /* Direct Mode Error Interrupt management ***********************************/ + if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) + 80027e2: 687b ldr r3, [r7, #4] + 80027e4: 6ddb ldr r3, [r3, #92] @ 0x5c + 80027e6: 2204 movs r2, #4 + 80027e8: 409a lsls r2, r3 + 80027ea: 68fb ldr r3, [r7, #12] + 80027ec: 4013 ands r3, r2 + 80027ee: 2b00 cmp r3, #0 + 80027f0: d012 beq.n 8002818 + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) + 80027f2: 687b ldr r3, [r7, #4] + 80027f4: 681b ldr r3, [r3, #0] + 80027f6: 681b ldr r3, [r3, #0] + 80027f8: f003 0302 and.w r3, r3, #2 + 80027fc: 2b00 cmp r3, #0 + 80027fe: d00b beq.n 8002818 + { + /* Clear the direct mode error flag */ + regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; + 8002800: 687b ldr r3, [r7, #4] + 8002802: 6ddb ldr r3, [r3, #92] @ 0x5c + 8002804: 2204 movs r2, #4 + 8002806: 409a lsls r2, r3 + 8002808: 693b ldr r3, [r7, #16] + 800280a: 609a str r2, [r3, #8] + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DME; + 800280c: 687b ldr r3, [r7, #4] + 800280e: 6d5b ldr r3, [r3, #84] @ 0x54 + 8002810: f043 0204 orr.w r2, r3, #4 + 8002814: 687b ldr r3, [r7, #4] + 8002816: 655a str r2, [r3, #84] @ 0x54 + } + } + /* Half Transfer Complete Interrupt management ******************************/ + if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET) + 8002818: 687b ldr r3, [r7, #4] + 800281a: 6ddb ldr r3, [r3, #92] @ 0x5c + 800281c: 2210 movs r2, #16 + 800281e: 409a lsls r2, r3 + 8002820: 68fb ldr r3, [r7, #12] + 8002822: 4013 ands r3, r2 + 8002824: 2b00 cmp r3, #0 + 8002826: d043 beq.n 80028b0 + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) + 8002828: 687b ldr r3, [r7, #4] + 800282a: 681b ldr r3, [r3, #0] + 800282c: 681b ldr r3, [r3, #0] + 800282e: f003 0308 and.w r3, r3, #8 + 8002832: 2b00 cmp r3, #0 + 8002834: d03c beq.n 80028b0 + { + /* Clear the half transfer complete flag */ + regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; + 8002836: 687b ldr r3, [r7, #4] + 8002838: 6ddb ldr r3, [r3, #92] @ 0x5c + 800283a: 2210 movs r2, #16 + 800283c: 409a lsls r2, r3 + 800283e: 693b ldr r3, [r7, #16] + 8002840: 609a str r2, [r3, #8] + + /* Multi_Buffering mode enabled */ + if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) + 8002842: 687b ldr r3, [r7, #4] + 8002844: 681b ldr r3, [r3, #0] + 8002846: 681b ldr r3, [r3, #0] + 8002848: f403 2380 and.w r3, r3, #262144 @ 0x40000 + 800284c: 2b00 cmp r3, #0 + 800284e: d018 beq.n 8002882 + { + /* Current memory buffer used is Memory 0 */ + if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) + 8002850: 687b ldr r3, [r7, #4] + 8002852: 681b ldr r3, [r3, #0] + 8002854: 681b ldr r3, [r3, #0] + 8002856: f403 2300 and.w r3, r3, #524288 @ 0x80000 + 800285a: 2b00 cmp r3, #0 + 800285c: d108 bne.n 8002870 + { + if(hdma->XferHalfCpltCallback != NULL) + 800285e: 687b ldr r3, [r7, #4] + 8002860: 6c1b ldr r3, [r3, #64] @ 0x40 + 8002862: 2b00 cmp r3, #0 + 8002864: d024 beq.n 80028b0 + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + 8002866: 687b ldr r3, [r7, #4] + 8002868: 6c1b ldr r3, [r3, #64] @ 0x40 + 800286a: 6878 ldr r0, [r7, #4] + 800286c: 4798 blx r3 + 800286e: e01f b.n 80028b0 + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferM1HalfCpltCallback != NULL) + 8002870: 687b ldr r3, [r7, #4] + 8002872: 6c9b ldr r3, [r3, #72] @ 0x48 + 8002874: 2b00 cmp r3, #0 + 8002876: d01b beq.n 80028b0 + { + /* Half transfer callback */ + hdma->XferM1HalfCpltCallback(hdma); + 8002878: 687b ldr r3, [r7, #4] + 800287a: 6c9b ldr r3, [r3, #72] @ 0x48 + 800287c: 6878 ldr r0, [r7, #4] + 800287e: 4798 blx r3 + 8002880: e016 b.n 80028b0 + } + } + else + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) + 8002882: 687b ldr r3, [r7, #4] + 8002884: 681b ldr r3, [r3, #0] + 8002886: 681b ldr r3, [r3, #0] + 8002888: f403 7380 and.w r3, r3, #256 @ 0x100 + 800288c: 2b00 cmp r3, #0 + 800288e: d107 bne.n 80028a0 + { + /* Disable the half transfer interrupt */ + hdma->Instance->CR &= ~(DMA_IT_HT); + 8002890: 687b ldr r3, [r7, #4] + 8002892: 681b ldr r3, [r3, #0] + 8002894: 681a ldr r2, [r3, #0] + 8002896: 687b ldr r3, [r7, #4] + 8002898: 681b ldr r3, [r3, #0] + 800289a: f022 0208 bic.w r2, r2, #8 + 800289e: 601a str r2, [r3, #0] + } + + if(hdma->XferHalfCpltCallback != NULL) + 80028a0: 687b ldr r3, [r7, #4] + 80028a2: 6c1b ldr r3, [r3, #64] @ 0x40 + 80028a4: 2b00 cmp r3, #0 + 80028a6: d003 beq.n 80028b0 + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + 80028a8: 687b ldr r3, [r7, #4] + 80028aa: 6c1b ldr r3, [r3, #64] @ 0x40 + 80028ac: 6878 ldr r0, [r7, #4] + 80028ae: 4798 blx r3 + } + } + } + } + /* Transfer Complete Interrupt management ***********************************/ + if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET) + 80028b0: 687b ldr r3, [r7, #4] + 80028b2: 6ddb ldr r3, [r3, #92] @ 0x5c + 80028b4: 2220 movs r2, #32 + 80028b6: 409a lsls r2, r3 + 80028b8: 68fb ldr r3, [r7, #12] + 80028ba: 4013 ands r3, r2 + 80028bc: 2b00 cmp r3, #0 + 80028be: f000 808f beq.w 80029e0 + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) + 80028c2: 687b ldr r3, [r7, #4] + 80028c4: 681b ldr r3, [r3, #0] + 80028c6: 681b ldr r3, [r3, #0] + 80028c8: f003 0310 and.w r3, r3, #16 + 80028cc: 2b00 cmp r3, #0 + 80028ce: f000 8087 beq.w 80029e0 + { + /* Clear the transfer complete flag */ + regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; + 80028d2: 687b ldr r3, [r7, #4] + 80028d4: 6ddb ldr r3, [r3, #92] @ 0x5c + 80028d6: 2220 movs r2, #32 + 80028d8: 409a lsls r2, r3 + 80028da: 693b ldr r3, [r7, #16] + 80028dc: 609a str r2, [r3, #8] + + if(HAL_DMA_STATE_ABORT == hdma->State) + 80028de: 687b ldr r3, [r7, #4] + 80028e0: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 + 80028e4: b2db uxtb r3, r3 + 80028e6: 2b05 cmp r3, #5 + 80028e8: d136 bne.n 8002958 + { + /* Disable all the transfer interrupts */ + hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); + 80028ea: 687b ldr r3, [r7, #4] + 80028ec: 681b ldr r3, [r3, #0] + 80028ee: 681a ldr r2, [r3, #0] + 80028f0: 687b ldr r3, [r7, #4] + 80028f2: 681b ldr r3, [r3, #0] + 80028f4: f022 0216 bic.w r2, r2, #22 + 80028f8: 601a str r2, [r3, #0] + hdma->Instance->FCR &= ~(DMA_IT_FE); + 80028fa: 687b ldr r3, [r7, #4] + 80028fc: 681b ldr r3, [r3, #0] + 80028fe: 695a ldr r2, [r3, #20] + 8002900: 687b ldr r3, [r7, #4] + 8002902: 681b ldr r3, [r3, #0] + 8002904: f022 0280 bic.w r2, r2, #128 @ 0x80 + 8002908: 615a str r2, [r3, #20] + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + 800290a: 687b ldr r3, [r7, #4] + 800290c: 6c1b ldr r3, [r3, #64] @ 0x40 + 800290e: 2b00 cmp r3, #0 + 8002910: d103 bne.n 800291a + 8002912: 687b ldr r3, [r7, #4] + 8002914: 6c9b ldr r3, [r3, #72] @ 0x48 + 8002916: 2b00 cmp r3, #0 + 8002918: d007 beq.n 800292a + { + hdma->Instance->CR &= ~(DMA_IT_HT); + 800291a: 687b ldr r3, [r7, #4] + 800291c: 681b ldr r3, [r3, #0] + 800291e: 681a ldr r2, [r3, #0] + 8002920: 687b ldr r3, [r7, #4] + 8002922: 681b ldr r3, [r3, #0] + 8002924: f022 0208 bic.w r2, r2, #8 + 8002928: 601a str r2, [r3, #0] + } + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + 800292a: 687b ldr r3, [r7, #4] + 800292c: 6ddb ldr r3, [r3, #92] @ 0x5c + 800292e: 223f movs r2, #63 @ 0x3f + 8002930: 409a lsls r2, r3 + 8002932: 693b ldr r3, [r7, #16] + 8002934: 609a str r2, [r3, #8] + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + 8002936: 687b ldr r3, [r7, #4] + 8002938: 2201 movs r2, #1 + 800293a: f883 2035 strb.w r2, [r3, #53] @ 0x35 + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 800293e: 687b ldr r3, [r7, #4] + 8002940: 2200 movs r2, #0 + 8002942: f883 2034 strb.w r2, [r3, #52] @ 0x34 + + if(hdma->XferAbortCallback != NULL) + 8002946: 687b ldr r3, [r7, #4] + 8002948: 6d1b ldr r3, [r3, #80] @ 0x50 + 800294a: 2b00 cmp r3, #0 + 800294c: d07e beq.n 8002a4c + { + hdma->XferAbortCallback(hdma); + 800294e: 687b ldr r3, [r7, #4] + 8002950: 6d1b ldr r3, [r3, #80] @ 0x50 + 8002952: 6878 ldr r0, [r7, #4] + 8002954: 4798 blx r3 + } + return; + 8002956: e079 b.n 8002a4c + } + + if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) + 8002958: 687b ldr r3, [r7, #4] + 800295a: 681b ldr r3, [r3, #0] + 800295c: 681b ldr r3, [r3, #0] + 800295e: f403 2380 and.w r3, r3, #262144 @ 0x40000 + 8002962: 2b00 cmp r3, #0 + 8002964: d01d beq.n 80029a2 + { + /* Current memory buffer used is Memory 0 */ + if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) + 8002966: 687b ldr r3, [r7, #4] + 8002968: 681b ldr r3, [r3, #0] + 800296a: 681b ldr r3, [r3, #0] + 800296c: f403 2300 and.w r3, r3, #524288 @ 0x80000 + 8002970: 2b00 cmp r3, #0 + 8002972: d10d bne.n 8002990 + { + if(hdma->XferM1CpltCallback != NULL) + 8002974: 687b ldr r3, [r7, #4] + 8002976: 6c5b ldr r3, [r3, #68] @ 0x44 + 8002978: 2b00 cmp r3, #0 + 800297a: d031 beq.n 80029e0 + { + /* Transfer complete Callback for memory1 */ + hdma->XferM1CpltCallback(hdma); + 800297c: 687b ldr r3, [r7, #4] + 800297e: 6c5b ldr r3, [r3, #68] @ 0x44 + 8002980: 6878 ldr r0, [r7, #4] + 8002982: 4798 blx r3 + 8002984: e02c b.n 80029e0 + 8002986: bf00 nop + 8002988: 20000018 .word 0x20000018 + 800298c: 1b4e81b5 .word 0x1b4e81b5 + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferCpltCallback != NULL) + 8002990: 687b ldr r3, [r7, #4] + 8002992: 6bdb ldr r3, [r3, #60] @ 0x3c + 8002994: 2b00 cmp r3, #0 + 8002996: d023 beq.n 80029e0 + { + /* Transfer complete Callback for memory0 */ + hdma->XferCpltCallback(hdma); + 8002998: 687b ldr r3, [r7, #4] + 800299a: 6bdb ldr r3, [r3, #60] @ 0x3c + 800299c: 6878 ldr r0, [r7, #4] + 800299e: 4798 blx r3 + 80029a0: e01e b.n 80029e0 + } + } + /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ + else + { + if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) + 80029a2: 687b ldr r3, [r7, #4] + 80029a4: 681b ldr r3, [r3, #0] + 80029a6: 681b ldr r3, [r3, #0] + 80029a8: f403 7380 and.w r3, r3, #256 @ 0x100 + 80029ac: 2b00 cmp r3, #0 + 80029ae: d10f bne.n 80029d0 + { + /* Disable the transfer complete interrupt */ + hdma->Instance->CR &= ~(DMA_IT_TC); + 80029b0: 687b ldr r3, [r7, #4] + 80029b2: 681b ldr r3, [r3, #0] + 80029b4: 681a ldr r2, [r3, #0] + 80029b6: 687b ldr r3, [r7, #4] + 80029b8: 681b ldr r3, [r3, #0] + 80029ba: f022 0210 bic.w r2, r2, #16 + 80029be: 601a str r2, [r3, #0] + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + 80029c0: 687b ldr r3, [r7, #4] + 80029c2: 2201 movs r2, #1 + 80029c4: f883 2035 strb.w r2, [r3, #53] @ 0x35 + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 80029c8: 687b ldr r3, [r7, #4] + 80029ca: 2200 movs r2, #0 + 80029cc: f883 2034 strb.w r2, [r3, #52] @ 0x34 + } + + if(hdma->XferCpltCallback != NULL) + 80029d0: 687b ldr r3, [r7, #4] + 80029d2: 6bdb ldr r3, [r3, #60] @ 0x3c + 80029d4: 2b00 cmp r3, #0 + 80029d6: d003 beq.n 80029e0 + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + 80029d8: 687b ldr r3, [r7, #4] + 80029da: 6bdb ldr r3, [r3, #60] @ 0x3c + 80029dc: 6878 ldr r0, [r7, #4] + 80029de: 4798 blx r3 + } + } + } + + /* manage error case */ + if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) + 80029e0: 687b ldr r3, [r7, #4] + 80029e2: 6d5b ldr r3, [r3, #84] @ 0x54 + 80029e4: 2b00 cmp r3, #0 + 80029e6: d032 beq.n 8002a4e + { + if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) + 80029e8: 687b ldr r3, [r7, #4] + 80029ea: 6d5b ldr r3, [r3, #84] @ 0x54 + 80029ec: f003 0301 and.w r3, r3, #1 + 80029f0: 2b00 cmp r3, #0 + 80029f2: d022 beq.n 8002a3a + { + hdma->State = HAL_DMA_STATE_ABORT; + 80029f4: 687b ldr r3, [r7, #4] + 80029f6: 2205 movs r2, #5 + 80029f8: f883 2035 strb.w r2, [r3, #53] @ 0x35 + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + 80029fc: 687b ldr r3, [r7, #4] + 80029fe: 681b ldr r3, [r3, #0] + 8002a00: 681a ldr r2, [r3, #0] + 8002a02: 687b ldr r3, [r7, #4] + 8002a04: 681b ldr r3, [r3, #0] + 8002a06: f022 0201 bic.w r2, r2, #1 + 8002a0a: 601a str r2, [r3, #0] + + do + { + if (++count > timeout) + 8002a0c: 68bb ldr r3, [r7, #8] + 8002a0e: 3301 adds r3, #1 + 8002a10: 60bb str r3, [r7, #8] + 8002a12: 697a ldr r2, [r7, #20] + 8002a14: 429a cmp r2, r3 + 8002a16: d307 bcc.n 8002a28 + { + break; + } + } + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); + 8002a18: 687b ldr r3, [r7, #4] + 8002a1a: 681b ldr r3, [r3, #0] + 8002a1c: 681b ldr r3, [r3, #0] + 8002a1e: f003 0301 and.w r3, r3, #1 + 8002a22: 2b00 cmp r3, #0 + 8002a24: d1f2 bne.n 8002a0c + 8002a26: e000 b.n 8002a2a + break; + 8002a28: bf00 nop + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + 8002a2a: 687b ldr r3, [r7, #4] + 8002a2c: 2201 movs r2, #1 + 8002a2e: f883 2035 strb.w r2, [r3, #53] @ 0x35 + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 8002a32: 687b ldr r3, [r7, #4] + 8002a34: 2200 movs r2, #0 + 8002a36: f883 2034 strb.w r2, [r3, #52] @ 0x34 + } + + if(hdma->XferErrorCallback != NULL) + 8002a3a: 687b ldr r3, [r7, #4] + 8002a3c: 6cdb ldr r3, [r3, #76] @ 0x4c + 8002a3e: 2b00 cmp r3, #0 + 8002a40: d005 beq.n 8002a4e + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + 8002a42: 687b ldr r3, [r7, #4] + 8002a44: 6cdb ldr r3, [r3, #76] @ 0x4c + 8002a46: 6878 ldr r0, [r7, #4] + 8002a48: 4798 blx r3 + 8002a4a: e000 b.n 8002a4e + return; + 8002a4c: bf00 nop + } + } +} + 8002a4e: 3718 adds r7, #24 + 8002a50: 46bd mov sp, r7 + 8002a52: bd80 pop {r7, pc} + +08002a54 : + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval Stream base address + */ +static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) +{ + 8002a54: b480 push {r7} + 8002a56: b085 sub sp, #20 + 8002a58: af00 add r7, sp, #0 + 8002a5a: 6078 str r0, [r7, #4] + uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U; + 8002a5c: 687b ldr r3, [r7, #4] + 8002a5e: 681b ldr r3, [r3, #0] + 8002a60: b2db uxtb r3, r3 + 8002a62: 3b10 subs r3, #16 + 8002a64: 4a14 ldr r2, [pc, #80] @ (8002ab8 ) + 8002a66: fba2 2303 umull r2, r3, r2, r3 + 8002a6a: 091b lsrs r3, r3, #4 + 8002a6c: 60fb str r3, [r7, #12] + + /* lookup table for necessary bitshift of flags within status registers */ + static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; + hdma->StreamIndex = flagBitshiftOffset[stream_number]; + 8002a6e: 4a13 ldr r2, [pc, #76] @ (8002abc ) + 8002a70: 68fb ldr r3, [r7, #12] + 8002a72: 4413 add r3, r2 + 8002a74: 781b ldrb r3, [r3, #0] + 8002a76: 461a mov r2, r3 + 8002a78: 687b ldr r3, [r7, #4] + 8002a7a: 65da str r2, [r3, #92] @ 0x5c + + if (stream_number > 3U) + 8002a7c: 68fb ldr r3, [r7, #12] + 8002a7e: 2b03 cmp r3, #3 + 8002a80: d909 bls.n 8002a96 + { + /* return pointer to HISR and HIFCR */ + hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U); + 8002a82: 687b ldr r3, [r7, #4] + 8002a84: 681b ldr r3, [r3, #0] + 8002a86: f423 737f bic.w r3, r3, #1020 @ 0x3fc + 8002a8a: f023 0303 bic.w r3, r3, #3 + 8002a8e: 1d1a adds r2, r3, #4 + 8002a90: 687b ldr r3, [r7, #4] + 8002a92: 659a str r2, [r3, #88] @ 0x58 + 8002a94: e007 b.n 8002aa6 + } + else + { + /* return pointer to LISR and LIFCR */ + hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)); + 8002a96: 687b ldr r3, [r7, #4] + 8002a98: 681b ldr r3, [r3, #0] + 8002a9a: f423 737f bic.w r3, r3, #1020 @ 0x3fc + 8002a9e: f023 0303 bic.w r3, r3, #3 + 8002aa2: 687a ldr r2, [r7, #4] + 8002aa4: 6593 str r3, [r2, #88] @ 0x58 + } + + return hdma->StreamBaseAddress; + 8002aa6: 687b ldr r3, [r7, #4] + 8002aa8: 6d9b ldr r3, [r3, #88] @ 0x58 +} + 8002aaa: 4618 mov r0, r3 + 8002aac: 3714 adds r7, #20 + 8002aae: 46bd mov sp, r7 + 8002ab0: f85d 7b04 ldr.w r7, [sp], #4 + 8002ab4: 4770 bx lr + 8002ab6: bf00 nop + 8002ab8: aaaaaaab .word 0xaaaaaaab + 8002abc: 0800a2b8 .word 0x0800a2b8 + +08002ac0 : + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) +{ + 8002ac0: b480 push {r7} + 8002ac2: b085 sub sp, #20 + 8002ac4: af00 add r7, sp, #0 + 8002ac6: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 8002ac8: 2300 movs r3, #0 + 8002aca: 73fb strb r3, [r7, #15] + uint32_t tmp = hdma->Init.FIFOThreshold; + 8002acc: 687b ldr r3, [r7, #4] + 8002ace: 6a9b ldr r3, [r3, #40] @ 0x28 + 8002ad0: 60bb str r3, [r7, #8] + + /* Memory Data size equal to Byte */ + if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) + 8002ad2: 687b ldr r3, [r7, #4] + 8002ad4: 699b ldr r3, [r3, #24] + 8002ad6: 2b00 cmp r3, #0 + 8002ad8: d11f bne.n 8002b1a + { + switch (tmp) + 8002ada: 68bb ldr r3, [r7, #8] + 8002adc: 2b03 cmp r3, #3 + 8002ade: d856 bhi.n 8002b8e + 8002ae0: a201 add r2, pc, #4 @ (adr r2, 8002ae8 ) + 8002ae2: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8002ae6: bf00 nop + 8002ae8: 08002af9 .word 0x08002af9 + 8002aec: 08002b0b .word 0x08002b0b + 8002af0: 08002af9 .word 0x08002af9 + 8002af4: 08002b8f .word 0x08002b8f + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + 8002af8: 687b ldr r3, [r7, #4] + 8002afa: 6adb ldr r3, [r3, #44] @ 0x2c + 8002afc: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 + 8002b00: 2b00 cmp r3, #0 + 8002b02: d046 beq.n 8002b92 + { + status = HAL_ERROR; + 8002b04: 2301 movs r3, #1 + 8002b06: 73fb strb r3, [r7, #15] + } + break; + 8002b08: e043 b.n 8002b92 + case DMA_FIFO_THRESHOLD_HALFFULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + 8002b0a: 687b ldr r3, [r7, #4] + 8002b0c: 6adb ldr r3, [r3, #44] @ 0x2c + 8002b0e: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 + 8002b12: d140 bne.n 8002b96 + { + status = HAL_ERROR; + 8002b14: 2301 movs r3, #1 + 8002b16: 73fb strb r3, [r7, #15] + } + break; + 8002b18: e03d b.n 8002b96 + break; + } + } + + /* Memory Data size equal to Half-Word */ + else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + 8002b1a: 687b ldr r3, [r7, #4] + 8002b1c: 699b ldr r3, [r3, #24] + 8002b1e: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 8002b22: d121 bne.n 8002b68 + { + switch (tmp) + 8002b24: 68bb ldr r3, [r7, #8] + 8002b26: 2b03 cmp r3, #3 + 8002b28: d837 bhi.n 8002b9a + 8002b2a: a201 add r2, pc, #4 @ (adr r2, 8002b30 ) + 8002b2c: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8002b30: 08002b41 .word 0x08002b41 + 8002b34: 08002b47 .word 0x08002b47 + 8002b38: 08002b41 .word 0x08002b41 + 8002b3c: 08002b59 .word 0x08002b59 + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + status = HAL_ERROR; + 8002b40: 2301 movs r3, #1 + 8002b42: 73fb strb r3, [r7, #15] + break; + 8002b44: e030 b.n 8002ba8 + case DMA_FIFO_THRESHOLD_HALFFULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + 8002b46: 687b ldr r3, [r7, #4] + 8002b48: 6adb ldr r3, [r3, #44] @ 0x2c + 8002b4a: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 + 8002b4e: 2b00 cmp r3, #0 + 8002b50: d025 beq.n 8002b9e + { + status = HAL_ERROR; + 8002b52: 2301 movs r3, #1 + 8002b54: 73fb strb r3, [r7, #15] + } + break; + 8002b56: e022 b.n 8002b9e + case DMA_FIFO_THRESHOLD_FULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + 8002b58: 687b ldr r3, [r7, #4] + 8002b5a: 6adb ldr r3, [r3, #44] @ 0x2c + 8002b5c: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 + 8002b60: d11f bne.n 8002ba2 + { + status = HAL_ERROR; + 8002b62: 2301 movs r3, #1 + 8002b64: 73fb strb r3, [r7, #15] + } + break; + 8002b66: e01c b.n 8002ba2 + } + + /* Memory Data size equal to Word */ + else + { + switch (tmp) + 8002b68: 68bb ldr r3, [r7, #8] + 8002b6a: 2b02 cmp r3, #2 + 8002b6c: d903 bls.n 8002b76 + 8002b6e: 68bb ldr r3, [r7, #8] + 8002b70: 2b03 cmp r3, #3 + 8002b72: d003 beq.n 8002b7c + { + status = HAL_ERROR; + } + break; + default: + break; + 8002b74: e018 b.n 8002ba8 + status = HAL_ERROR; + 8002b76: 2301 movs r3, #1 + 8002b78: 73fb strb r3, [r7, #15] + break; + 8002b7a: e015 b.n 8002ba8 + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + 8002b7c: 687b ldr r3, [r7, #4] + 8002b7e: 6adb ldr r3, [r3, #44] @ 0x2c + 8002b80: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 + 8002b84: 2b00 cmp r3, #0 + 8002b86: d00e beq.n 8002ba6 + status = HAL_ERROR; + 8002b88: 2301 movs r3, #1 + 8002b8a: 73fb strb r3, [r7, #15] + break; + 8002b8c: e00b b.n 8002ba6 + break; + 8002b8e: bf00 nop + 8002b90: e00a b.n 8002ba8 + break; + 8002b92: bf00 nop + 8002b94: e008 b.n 8002ba8 + break; + 8002b96: bf00 nop + 8002b98: e006 b.n 8002ba8 + break; + 8002b9a: bf00 nop + 8002b9c: e004 b.n 8002ba8 + break; + 8002b9e: bf00 nop + 8002ba0: e002 b.n 8002ba8 + break; + 8002ba2: bf00 nop + 8002ba4: e000 b.n 8002ba8 + break; + 8002ba6: bf00 nop + } + } + + return status; + 8002ba8: 7bfb ldrb r3, [r7, #15] +} + 8002baa: 4618 mov r0, r3 + 8002bac: 3714 adds r7, #20 + 8002bae: 46bd mov sp, r7 + 8002bb0: f85d 7b04 ldr.w r7, [sp], #4 + 8002bb4: 4770 bx lr + 8002bb6: bf00 nop + +08002bb8 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { - 8001544: b580 push {r7, lr} - 8001546: b088 sub sp, #32 - 8001548: af00 add r7, sp, #0 - 800154a: 6078 str r0, [r7, #4] - 800154c: 6039 str r1, [r7, #0] + 8002bb8: b580 push {r7, lr} + 8002bba: b088 sub sp, #32 + 8002bbc: af00 add r7, sp, #0 + 8002bbe: 6078 str r0, [r7, #4] + 8002bc0: 6039 str r1, [r7, #0] uint32_t position; uint32_t ioposition = 0x00U; - 800154e: 2300 movs r3, #0 - 8001550: 617b str r3, [r7, #20] + 8002bc2: 2300 movs r3, #0 + 8002bc4: 617b str r3, [r7, #20] uint32_t iocurrent = 0x00U; - 8001552: 2300 movs r3, #0 - 8001554: 613b str r3, [r7, #16] + 8002bc6: 2300 movs r3, #0 + 8002bc8: 613b str r3, [r7, #16] uint32_t temp = 0x00U; - 8001556: 2300 movs r3, #0 - 8001558: 61bb str r3, [r7, #24] + 8002bca: 2300 movs r3, #0 + 8002bcc: 61bb str r3, [r7, #24] /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - 800155a: 687b ldr r3, [r7, #4] - 800155c: 4a38 ldr r2, [pc, #224] @ (8001640 ) - 800155e: 4293 cmp r3, r2 - 8001560: d023 beq.n 80015aa - 8001562: 687b ldr r3, [r7, #4] - 8001564: 4a37 ldr r2, [pc, #220] @ (8001644 ) - 8001566: 4293 cmp r3, r2 - 8001568: d01f beq.n 80015aa - 800156a: 687b ldr r3, [r7, #4] - 800156c: 4a36 ldr r2, [pc, #216] @ (8001648 ) - 800156e: 4293 cmp r3, r2 - 8001570: d01b beq.n 80015aa - 8001572: 687b ldr r3, [r7, #4] - 8001574: 4a35 ldr r2, [pc, #212] @ (800164c ) - 8001576: 4293 cmp r3, r2 - 8001578: d017 beq.n 80015aa - 800157a: 687b ldr r3, [r7, #4] - 800157c: 4a34 ldr r2, [pc, #208] @ (8001650 ) - 800157e: 4293 cmp r3, r2 - 8001580: d013 beq.n 80015aa - 8001582: 687b ldr r3, [r7, #4] - 8001584: 4a33 ldr r2, [pc, #204] @ (8001654 ) - 8001586: 4293 cmp r3, r2 - 8001588: d00f beq.n 80015aa - 800158a: 687b ldr r3, [r7, #4] - 800158c: 4a32 ldr r2, [pc, #200] @ (8001658 ) - 800158e: 4293 cmp r3, r2 - 8001590: d00b beq.n 80015aa - 8001592: 687b ldr r3, [r7, #4] - 8001594: 4a31 ldr r2, [pc, #196] @ (800165c ) - 8001596: 4293 cmp r3, r2 - 8001598: d007 beq.n 80015aa - 800159a: 687b ldr r3, [r7, #4] - 800159c: 4a30 ldr r2, [pc, #192] @ (8001660 ) - 800159e: 4293 cmp r3, r2 - 80015a0: d003 beq.n 80015aa - 80015a2: 21ac movs r1, #172 @ 0xac - 80015a4: 482f ldr r0, [pc, #188] @ (8001664 ) - 80015a6: f7ff f94f bl 8000848 + 8002bce: 687b ldr r3, [r7, #4] + 8002bd0: 4a38 ldr r2, [pc, #224] @ (8002cb4 ) + 8002bd2: 4293 cmp r3, r2 + 8002bd4: d023 beq.n 8002c1e + 8002bd6: 687b ldr r3, [r7, #4] + 8002bd8: 4a37 ldr r2, [pc, #220] @ (8002cb8 ) + 8002bda: 4293 cmp r3, r2 + 8002bdc: d01f beq.n 8002c1e + 8002bde: 687b ldr r3, [r7, #4] + 8002be0: 4a36 ldr r2, [pc, #216] @ (8002cbc ) + 8002be2: 4293 cmp r3, r2 + 8002be4: d01b beq.n 8002c1e + 8002be6: 687b ldr r3, [r7, #4] + 8002be8: 4a35 ldr r2, [pc, #212] @ (8002cc0 ) + 8002bea: 4293 cmp r3, r2 + 8002bec: d017 beq.n 8002c1e + 8002bee: 687b ldr r3, [r7, #4] + 8002bf0: 4a34 ldr r2, [pc, #208] @ (8002cc4 ) + 8002bf2: 4293 cmp r3, r2 + 8002bf4: d013 beq.n 8002c1e + 8002bf6: 687b ldr r3, [r7, #4] + 8002bf8: 4a33 ldr r2, [pc, #204] @ (8002cc8 ) + 8002bfa: 4293 cmp r3, r2 + 8002bfc: d00f beq.n 8002c1e + 8002bfe: 687b ldr r3, [r7, #4] + 8002c00: 4a32 ldr r2, [pc, #200] @ (8002ccc ) + 8002c02: 4293 cmp r3, r2 + 8002c04: d00b beq.n 8002c1e + 8002c06: 687b ldr r3, [r7, #4] + 8002c08: 4a31 ldr r2, [pc, #196] @ (8002cd0 ) + 8002c0a: 4293 cmp r3, r2 + 8002c0c: d007 beq.n 8002c1e + 8002c0e: 687b ldr r3, [r7, #4] + 8002c10: 4a30 ldr r2, [pc, #192] @ (8002cd4 ) + 8002c12: 4293 cmp r3, r2 + 8002c14: d003 beq.n 8002c1e + 8002c16: 21ac movs r1, #172 @ 0xac + 8002c18: 482f ldr r0, [pc, #188] @ (8002cd8 ) + 8002c1a: f7fe f88b bl 8000d34 assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); - 80015aa: 683b ldr r3, [r7, #0] - 80015ac: 681b ldr r3, [r3, #0] - 80015ae: b29b uxth r3, r3 - 80015b0: 2b00 cmp r3, #0 - 80015b2: d004 beq.n 80015be - 80015b4: 683b ldr r3, [r7, #0] - 80015b6: 681b ldr r3, [r3, #0] - 80015b8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 - 80015bc: d303 bcc.n 80015c6 - 80015be: 21ad movs r1, #173 @ 0xad - 80015c0: 4828 ldr r0, [pc, #160] @ (8001664 ) - 80015c2: f7ff f941 bl 8000848 + 8002c1e: 683b ldr r3, [r7, #0] + 8002c20: 681b ldr r3, [r3, #0] + 8002c22: b29b uxth r3, r3 + 8002c24: 2b00 cmp r3, #0 + 8002c26: d004 beq.n 8002c32 + 8002c28: 683b ldr r3, [r7, #0] + 8002c2a: 681b ldr r3, [r3, #0] + 8002c2c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8002c30: d303 bcc.n 8002c3a + 8002c32: 21ad movs r1, #173 @ 0xad + 8002c34: 4828 ldr r0, [pc, #160] @ (8002cd8 ) + 8002c36: f7fe f87d bl 8000d34 assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); - 80015c6: 683b ldr r3, [r7, #0] - 80015c8: 685b ldr r3, [r3, #4] - 80015ca: 2b00 cmp r3, #0 - 80015cc: d035 beq.n 800163a - 80015ce: 683b ldr r3, [r7, #0] - 80015d0: 685b ldr r3, [r3, #4] - 80015d2: 2b01 cmp r3, #1 - 80015d4: d031 beq.n 800163a - 80015d6: 683b ldr r3, [r7, #0] - 80015d8: 685b ldr r3, [r3, #4] - 80015da: 2b11 cmp r3, #17 - 80015dc: d02d beq.n 800163a - 80015de: 683b ldr r3, [r7, #0] - 80015e0: 685b ldr r3, [r3, #4] - 80015e2: 2b02 cmp r3, #2 - 80015e4: d029 beq.n 800163a - 80015e6: 683b ldr r3, [r7, #0] - 80015e8: 685b ldr r3, [r3, #4] - 80015ea: 2b12 cmp r3, #18 - 80015ec: d025 beq.n 800163a - 80015ee: 683b ldr r3, [r7, #0] - 80015f0: 685b ldr r3, [r3, #4] - 80015f2: f5b3 1f88 cmp.w r3, #1114112 @ 0x110000 - 80015f6: d020 beq.n 800163a - 80015f8: 683b ldr r3, [r7, #0] - 80015fa: 685b ldr r3, [r3, #4] - 80015fc: f5b3 1f04 cmp.w r3, #2162688 @ 0x210000 - 8001600: d01b beq.n 800163a - 8001602: 683b ldr r3, [r7, #0] - 8001604: 685b ldr r3, [r3, #4] - 8001606: f5b3 1f44 cmp.w r3, #3211264 @ 0x310000 - 800160a: d016 beq.n 800163a - 800160c: 683b ldr r3, [r7, #0] - 800160e: 685b ldr r3, [r3, #4] - 8001610: f5b3 1f90 cmp.w r3, #1179648 @ 0x120000 - 8001614: d011 beq.n 800163a - 8001616: 683b ldr r3, [r7, #0] - 8001618: 685b ldr r3, [r3, #4] - 800161a: f5b3 1f08 cmp.w r3, #2228224 @ 0x220000 - 800161e: d00c beq.n 800163a - 8001620: 683b ldr r3, [r7, #0] - 8001622: 685b ldr r3, [r3, #4] - 8001624: f5b3 1f48 cmp.w r3, #3276800 @ 0x320000 - 8001628: d007 beq.n 800163a - 800162a: 683b ldr r3, [r7, #0] - 800162c: 685b ldr r3, [r3, #4] - 800162e: 2b03 cmp r3, #3 - 8001630: d003 beq.n 800163a - 8001632: 21ae movs r1, #174 @ 0xae - 8001634: 480b ldr r0, [pc, #44] @ (8001664 ) - 8001636: f7ff f907 bl 8000848 + 8002c3a: 683b ldr r3, [r7, #0] + 8002c3c: 685b ldr r3, [r3, #4] + 8002c3e: 2b00 cmp r3, #0 + 8002c40: d035 beq.n 8002cae + 8002c42: 683b ldr r3, [r7, #0] + 8002c44: 685b ldr r3, [r3, #4] + 8002c46: 2b01 cmp r3, #1 + 8002c48: d031 beq.n 8002cae + 8002c4a: 683b ldr r3, [r7, #0] + 8002c4c: 685b ldr r3, [r3, #4] + 8002c4e: 2b11 cmp r3, #17 + 8002c50: d02d beq.n 8002cae + 8002c52: 683b ldr r3, [r7, #0] + 8002c54: 685b ldr r3, [r3, #4] + 8002c56: 2b02 cmp r3, #2 + 8002c58: d029 beq.n 8002cae + 8002c5a: 683b ldr r3, [r7, #0] + 8002c5c: 685b ldr r3, [r3, #4] + 8002c5e: 2b12 cmp r3, #18 + 8002c60: d025 beq.n 8002cae + 8002c62: 683b ldr r3, [r7, #0] + 8002c64: 685b ldr r3, [r3, #4] + 8002c66: f5b3 1f88 cmp.w r3, #1114112 @ 0x110000 + 8002c6a: d020 beq.n 8002cae + 8002c6c: 683b ldr r3, [r7, #0] + 8002c6e: 685b ldr r3, [r3, #4] + 8002c70: f5b3 1f04 cmp.w r3, #2162688 @ 0x210000 + 8002c74: d01b beq.n 8002cae + 8002c76: 683b ldr r3, [r7, #0] + 8002c78: 685b ldr r3, [r3, #4] + 8002c7a: f5b3 1f44 cmp.w r3, #3211264 @ 0x310000 + 8002c7e: d016 beq.n 8002cae + 8002c80: 683b ldr r3, [r7, #0] + 8002c82: 685b ldr r3, [r3, #4] + 8002c84: f5b3 1f90 cmp.w r3, #1179648 @ 0x120000 + 8002c88: d011 beq.n 8002cae + 8002c8a: 683b ldr r3, [r7, #0] + 8002c8c: 685b ldr r3, [r3, #4] + 8002c8e: f5b3 1f08 cmp.w r3, #2228224 @ 0x220000 + 8002c92: d00c beq.n 8002cae + 8002c94: 683b ldr r3, [r7, #0] + 8002c96: 685b ldr r3, [r3, #4] + 8002c98: f5b3 1f48 cmp.w r3, #3276800 @ 0x320000 + 8002c9c: d007 beq.n 8002cae + 8002c9e: 683b ldr r3, [r7, #0] + 8002ca0: 685b ldr r3, [r3, #4] + 8002ca2: 2b03 cmp r3, #3 + 8002ca4: d003 beq.n 8002cae + 8002ca6: 21ae movs r1, #174 @ 0xae + 8002ca8: 480b ldr r0, [pc, #44] @ (8002cd8 ) + 8002caa: f7fe f843 bl 8000d34 /* Configure the port pins */ for(position = 0U; position < GPIO_NUMBER; position++) - 800163a: 2300 movs r3, #0 - 800163c: 61fb str r3, [r7, #28] - 800163e: e235 b.n 8001aac - 8001640: 40020000 .word 0x40020000 - 8001644: 40020400 .word 0x40020400 - 8001648: 40020800 .word 0x40020800 - 800164c: 40020c00 .word 0x40020c00 - 8001650: 40021000 .word 0x40021000 - 8001654: 40021400 .word 0x40021400 - 8001658: 40021800 .word 0x40021800 - 800165c: 40021c00 .word 0x40021c00 - 8001660: 40022000 .word 0x40022000 - 8001664: 08005c5c .word 0x08005c5c + 8002cae: 2300 movs r3, #0 + 8002cb0: 61fb str r3, [r7, #28] + 8002cb2: e235 b.n 8003120 + 8002cb4: 40020000 .word 0x40020000 + 8002cb8: 40020400 .word 0x40020400 + 8002cbc: 40020800 .word 0x40020800 + 8002cc0: 40020c00 .word 0x40020c00 + 8002cc4: 40021000 .word 0x40021000 + 8002cc8: 40021400 .word 0x40021400 + 8002ccc: 40021800 .word 0x40021800 + 8002cd0: 40021c00 .word 0x40021c00 + 8002cd4: 40022000 .word 0x40022000 + 8002cd8: 0800a168 .word 0x0800a168 { /* Get the IO position */ ioposition = 0x01U << position; - 8001668: 2201 movs r2, #1 - 800166a: 69fb ldr r3, [r7, #28] - 800166c: fa02 f303 lsl.w r3, r2, r3 - 8001670: 617b str r3, [r7, #20] + 8002cdc: 2201 movs r2, #1 + 8002cde: 69fb ldr r3, [r7, #28] + 8002ce0: fa02 f303 lsl.w r3, r2, r3 + 8002ce4: 617b str r3, [r7, #20] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; - 8001672: 683b ldr r3, [r7, #0] - 8001674: 681b ldr r3, [r3, #0] - 8001676: 697a ldr r2, [r7, #20] - 8001678: 4013 ands r3, r2 - 800167a: 613b str r3, [r7, #16] + 8002ce6: 683b ldr r3, [r7, #0] + 8002ce8: 681b ldr r3, [r3, #0] + 8002cea: 697a ldr r2, [r7, #20] + 8002cec: 4013 ands r3, r2 + 8002cee: 613b str r3, [r7, #16] if(iocurrent == ioposition) - 800167c: 693a ldr r2, [r7, #16] - 800167e: 697b ldr r3, [r7, #20] - 8001680: 429a cmp r2, r3 - 8001682: f040 8210 bne.w 8001aa6 + 8002cf0: 693a ldr r2, [r7, #16] + 8002cf2: 697b ldr r3, [r7, #20] + 8002cf4: 429a cmp r2, r3 + 8002cf6: f040 8210 bne.w 800311a { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ - 8001686: 683b ldr r3, [r7, #0] - 8001688: 685b ldr r3, [r3, #4] - 800168a: f003 0303 and.w r3, r3, #3 - 800168e: 2b01 cmp r3, #1 - 8001690: d005 beq.n 800169e + 8002cfa: 683b ldr r3, [r7, #0] + 8002cfc: 685b ldr r3, [r3, #4] + 8002cfe: f003 0303 and.w r3, r3, #3 + 8002d02: 2b01 cmp r3, #1 + 8002d04: d005 beq.n 8002d12 (GPIO_Init->Mode & GPIO_MODE) == MODE_AF) - 8001692: 683b ldr r3, [r7, #0] - 8001694: 685b ldr r3, [r3, #4] - 8001696: f003 0303 and.w r3, r3, #3 + 8002d06: 683b ldr r3, [r7, #0] + 8002d08: 685b ldr r3, [r3, #4] + 8002d0a: f003 0303 and.w r3, r3, #3 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ - 800169a: 2b02 cmp r3, #2 - 800169c: d144 bne.n 8001728 + 8002d0e: 2b02 cmp r3, #2 + 8002d10: d144 bne.n 8002d9c { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); - 800169e: 683b ldr r3, [r7, #0] - 80016a0: 68db ldr r3, [r3, #12] - 80016a2: 2b00 cmp r3, #0 - 80016a4: d00f beq.n 80016c6 - 80016a6: 683b ldr r3, [r7, #0] - 80016a8: 68db ldr r3, [r3, #12] - 80016aa: 2b01 cmp r3, #1 - 80016ac: d00b beq.n 80016c6 - 80016ae: 683b ldr r3, [r7, #0] - 80016b0: 68db ldr r3, [r3, #12] - 80016b2: 2b02 cmp r3, #2 - 80016b4: d007 beq.n 80016c6 - 80016b6: 683b ldr r3, [r7, #0] - 80016b8: 68db ldr r3, [r3, #12] - 80016ba: 2b03 cmp r3, #3 - 80016bc: d003 beq.n 80016c6 - 80016be: 21c0 movs r1, #192 @ 0xc0 - 80016c0: 488d ldr r0, [pc, #564] @ (80018f8 ) - 80016c2: f7ff f8c1 bl 8000848 + 8002d12: 683b ldr r3, [r7, #0] + 8002d14: 68db ldr r3, [r3, #12] + 8002d16: 2b00 cmp r3, #0 + 8002d18: d00f beq.n 8002d3a + 8002d1a: 683b ldr r3, [r7, #0] + 8002d1c: 68db ldr r3, [r3, #12] + 8002d1e: 2b01 cmp r3, #1 + 8002d20: d00b beq.n 8002d3a + 8002d22: 683b ldr r3, [r7, #0] + 8002d24: 68db ldr r3, [r3, #12] + 8002d26: 2b02 cmp r3, #2 + 8002d28: d007 beq.n 8002d3a + 8002d2a: 683b ldr r3, [r7, #0] + 8002d2c: 68db ldr r3, [r3, #12] + 8002d2e: 2b03 cmp r3, #3 + 8002d30: d003 beq.n 8002d3a + 8002d32: 21c0 movs r1, #192 @ 0xc0 + 8002d34: 488d ldr r0, [pc, #564] @ (8002f6c ) + 8002d36: f7fd fffd bl 8000d34 /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; - 80016c6: 687b ldr r3, [r7, #4] - 80016c8: 689b ldr r3, [r3, #8] - 80016ca: 61bb str r3, [r7, #24] + 8002d3a: 687b ldr r3, [r7, #4] + 8002d3c: 689b ldr r3, [r3, #8] + 8002d3e: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); - 80016cc: 69fb ldr r3, [r7, #28] - 80016ce: 005b lsls r3, r3, #1 - 80016d0: 2203 movs r2, #3 - 80016d2: fa02 f303 lsl.w r3, r2, r3 - 80016d6: 43db mvns r3, r3 - 80016d8: 69ba ldr r2, [r7, #24] - 80016da: 4013 ands r3, r2 - 80016dc: 61bb str r3, [r7, #24] + 8002d40: 69fb ldr r3, [r7, #28] + 8002d42: 005b lsls r3, r3, #1 + 8002d44: 2203 movs r2, #3 + 8002d46: fa02 f303 lsl.w r3, r2, r3 + 8002d4a: 43db mvns r3, r3 + 8002d4c: 69ba ldr r2, [r7, #24] + 8002d4e: 4013 ands r3, r2 + 8002d50: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); - 80016de: 683b ldr r3, [r7, #0] - 80016e0: 68da ldr r2, [r3, #12] - 80016e2: 69fb ldr r3, [r7, #28] - 80016e4: 005b lsls r3, r3, #1 - 80016e6: fa02 f303 lsl.w r3, r2, r3 - 80016ea: 69ba ldr r2, [r7, #24] - 80016ec: 4313 orrs r3, r2 - 80016ee: 61bb str r3, [r7, #24] + 8002d52: 683b ldr r3, [r7, #0] + 8002d54: 68da ldr r2, [r3, #12] + 8002d56: 69fb ldr r3, [r7, #28] + 8002d58: 005b lsls r3, r3, #1 + 8002d5a: fa02 f303 lsl.w r3, r2, r3 + 8002d5e: 69ba ldr r2, [r7, #24] + 8002d60: 4313 orrs r3, r2 + 8002d62: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; - 80016f0: 687b ldr r3, [r7, #4] - 80016f2: 69ba ldr r2, [r7, #24] - 80016f4: 609a str r2, [r3, #8] + 8002d64: 687b ldr r3, [r7, #4] + 8002d66: 69ba ldr r2, [r7, #24] + 8002d68: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; - 80016f6: 687b ldr r3, [r7, #4] - 80016f8: 685b ldr r3, [r3, #4] - 80016fa: 61bb str r3, [r7, #24] + 8002d6a: 687b ldr r3, [r7, #4] + 8002d6c: 685b ldr r3, [r3, #4] + 8002d6e: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT_0 << position) ; - 80016fc: 2201 movs r2, #1 - 80016fe: 69fb ldr r3, [r7, #28] - 8001700: fa02 f303 lsl.w r3, r2, r3 - 8001704: 43db mvns r3, r3 - 8001706: 69ba ldr r2, [r7, #24] - 8001708: 4013 ands r3, r2 - 800170a: 61bb str r3, [r7, #24] + 8002d70: 2201 movs r2, #1 + 8002d72: 69fb ldr r3, [r7, #28] + 8002d74: fa02 f303 lsl.w r3, r2, r3 + 8002d78: 43db mvns r3, r3 + 8002d7a: 69ba ldr r2, [r7, #24] + 8002d7c: 4013 ands r3, r2 + 8002d7e: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); - 800170c: 683b ldr r3, [r7, #0] - 800170e: 685b ldr r3, [r3, #4] - 8001710: 091b lsrs r3, r3, #4 - 8001712: f003 0201 and.w r2, r3, #1 - 8001716: 69fb ldr r3, [r7, #28] - 8001718: fa02 f303 lsl.w r3, r2, r3 - 800171c: 69ba ldr r2, [r7, #24] - 800171e: 4313 orrs r3, r2 - 8001720: 61bb str r3, [r7, #24] + 8002d80: 683b ldr r3, [r7, #0] + 8002d82: 685b ldr r3, [r3, #4] + 8002d84: 091b lsrs r3, r3, #4 + 8002d86: f003 0201 and.w r2, r3, #1 + 8002d8a: 69fb ldr r3, [r7, #28] + 8002d8c: fa02 f303 lsl.w r3, r2, r3 + 8002d90: 69ba ldr r2, [r7, #24] + 8002d92: 4313 orrs r3, r2 + 8002d94: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; - 8001722: 687b ldr r3, [r7, #4] - 8001724: 69ba ldr r2, [r7, #24] - 8001726: 605a str r2, [r3, #4] + 8002d96: 687b ldr r3, [r7, #4] + 8002d98: 69ba ldr r2, [r7, #24] + 8002d9a: 605a str r2, [r3, #4] } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) - 8001728: 683b ldr r3, [r7, #0] - 800172a: 685b ldr r3, [r3, #4] - 800172c: f003 0303 and.w r3, r3, #3 - 8001730: 2b03 cmp r3, #3 - 8001732: d027 beq.n 8001784 + 8002d9c: 683b ldr r3, [r7, #0] + 8002d9e: 685b ldr r3, [r3, #4] + 8002da0: f003 0303 and.w r3, r3, #3 + 8002da4: 2b03 cmp r3, #3 + 8002da6: d027 beq.n 8002df8 { /* Check the parameters */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); - 8001734: 683b ldr r3, [r7, #0] - 8001736: 689b ldr r3, [r3, #8] - 8001738: 2b00 cmp r3, #0 - 800173a: d00b beq.n 8001754 - 800173c: 683b ldr r3, [r7, #0] - 800173e: 689b ldr r3, [r3, #8] - 8001740: 2b01 cmp r3, #1 - 8001742: d007 beq.n 8001754 - 8001744: 683b ldr r3, [r7, #0] - 8001746: 689b ldr r3, [r3, #8] - 8001748: 2b02 cmp r3, #2 - 800174a: d003 beq.n 8001754 - 800174c: 21d1 movs r1, #209 @ 0xd1 - 800174e: 486a ldr r0, [pc, #424] @ (80018f8 ) - 8001750: f7ff f87a bl 8000848 + 8002da8: 683b ldr r3, [r7, #0] + 8002daa: 689b ldr r3, [r3, #8] + 8002dac: 2b00 cmp r3, #0 + 8002dae: d00b beq.n 8002dc8 + 8002db0: 683b ldr r3, [r7, #0] + 8002db2: 689b ldr r3, [r3, #8] + 8002db4: 2b01 cmp r3, #1 + 8002db6: d007 beq.n 8002dc8 + 8002db8: 683b ldr r3, [r7, #0] + 8002dba: 689b ldr r3, [r3, #8] + 8002dbc: 2b02 cmp r3, #2 + 8002dbe: d003 beq.n 8002dc8 + 8002dc0: 21d1 movs r1, #209 @ 0xd1 + 8002dc2: 486a ldr r0, [pc, #424] @ (8002f6c ) + 8002dc4: f7fd ffb6 bl 8000d34 /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; - 8001754: 687b ldr r3, [r7, #4] - 8001756: 68db ldr r3, [r3, #12] - 8001758: 61bb str r3, [r7, #24] + 8002dc8: 687b ldr r3, [r7, #4] + 8002dca: 68db ldr r3, [r3, #12] + 8002dcc: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); - 800175a: 69fb ldr r3, [r7, #28] - 800175c: 005b lsls r3, r3, #1 - 800175e: 2203 movs r2, #3 - 8001760: fa02 f303 lsl.w r3, r2, r3 - 8001764: 43db mvns r3, r3 - 8001766: 69ba ldr r2, [r7, #24] - 8001768: 4013 ands r3, r2 - 800176a: 61bb str r3, [r7, #24] + 8002dce: 69fb ldr r3, [r7, #28] + 8002dd0: 005b lsls r3, r3, #1 + 8002dd2: 2203 movs r2, #3 + 8002dd4: fa02 f303 lsl.w r3, r2, r3 + 8002dd8: 43db mvns r3, r3 + 8002dda: 69ba ldr r2, [r7, #24] + 8002ddc: 4013 ands r3, r2 + 8002dde: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); - 800176c: 683b ldr r3, [r7, #0] - 800176e: 689a ldr r2, [r3, #8] - 8001770: 69fb ldr r3, [r7, #28] - 8001772: 005b lsls r3, r3, #1 - 8001774: fa02 f303 lsl.w r3, r2, r3 - 8001778: 69ba ldr r2, [r7, #24] - 800177a: 4313 orrs r3, r2 - 800177c: 61bb str r3, [r7, #24] + 8002de0: 683b ldr r3, [r7, #0] + 8002de2: 689a ldr r2, [r3, #8] + 8002de4: 69fb ldr r3, [r7, #28] + 8002de6: 005b lsls r3, r3, #1 + 8002de8: fa02 f303 lsl.w r3, r2, r3 + 8002dec: 69ba ldr r2, [r7, #24] + 8002dee: 4313 orrs r3, r2 + 8002df0: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; - 800177e: 687b ldr r3, [r7, #4] - 8001780: 69ba ldr r2, [r7, #24] - 8001782: 60da str r2, [r3, #12] + 8002df2: 687b ldr r3, [r7, #4] + 8002df4: 69ba ldr r2, [r7, #24] + 8002df6: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) - 8001784: 683b ldr r3, [r7, #0] - 8001786: 685b ldr r3, [r3, #4] - 8001788: f003 0303 and.w r3, r3, #3 - 800178c: 2b02 cmp r3, #2 - 800178e: f040 80b5 bne.w 80018fc + 8002df8: 683b ldr r3, [r7, #0] + 8002dfa: 685b ldr r3, [r3, #4] + 8002dfc: f003 0303 and.w r3, r3, #3 + 8002e00: 2b02 cmp r3, #2 + 8002e02: f040 80b5 bne.w 8002f70 { /* Check the Alternate function parameter */ assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); - 8001792: 683b ldr r3, [r7, #0] - 8001794: 691b ldr r3, [r3, #16] - 8001796: 2b00 cmp r3, #0 - 8001798: f000 8089 beq.w 80018ae - 800179c: 683b ldr r3, [r7, #0] - 800179e: 691b ldr r3, [r3, #16] - 80017a0: 2b09 cmp r3, #9 - 80017a2: f000 8084 beq.w 80018ae - 80017a6: 683b ldr r3, [r7, #0] - 80017a8: 691b ldr r3, [r3, #16] - 80017aa: 2b00 cmp r3, #0 - 80017ac: d07f beq.n 80018ae - 80017ae: 683b ldr r3, [r7, #0] - 80017b0: 691b ldr r3, [r3, #16] - 80017b2: 2b00 cmp r3, #0 - 80017b4: d07b beq.n 80018ae - 80017b6: 683b ldr r3, [r7, #0] - 80017b8: 691b ldr r3, [r3, #16] - 80017ba: 2b00 cmp r3, #0 - 80017bc: d077 beq.n 80018ae - 80017be: 683b ldr r3, [r7, #0] - 80017c0: 691b ldr r3, [r3, #16] - 80017c2: 2b00 cmp r3, #0 - 80017c4: d073 beq.n 80018ae - 80017c6: 683b ldr r3, [r7, #0] - 80017c8: 691b ldr r3, [r3, #16] - 80017ca: 2b01 cmp r3, #1 - 80017cc: d06f beq.n 80018ae - 80017ce: 683b ldr r3, [r7, #0] - 80017d0: 691b ldr r3, [r3, #16] - 80017d2: 2b01 cmp r3, #1 - 80017d4: d06b beq.n 80018ae - 80017d6: 683b ldr r3, [r7, #0] - 80017d8: 691b ldr r3, [r3, #16] - 80017da: 2b02 cmp r3, #2 - 80017dc: d067 beq.n 80018ae - 80017de: 683b ldr r3, [r7, #0] - 80017e0: 691b ldr r3, [r3, #16] - 80017e2: 2b02 cmp r3, #2 - 80017e4: d063 beq.n 80018ae - 80017e6: 683b ldr r3, [r7, #0] - 80017e8: 691b ldr r3, [r3, #16] - 80017ea: 2b02 cmp r3, #2 - 80017ec: d05f beq.n 80018ae - 80017ee: 683b ldr r3, [r7, #0] - 80017f0: 691b ldr r3, [r3, #16] - 80017f2: 2b03 cmp r3, #3 - 80017f4: d05b beq.n 80018ae - 80017f6: 683b ldr r3, [r7, #0] - 80017f8: 691b ldr r3, [r3, #16] - 80017fa: 2b04 cmp r3, #4 - 80017fc: d057 beq.n 80018ae - 80017fe: 683b ldr r3, [r7, #0] - 8001800: 691b ldr r3, [r3, #16] - 8001802: 2b04 cmp r3, #4 - 8001804: d053 beq.n 80018ae - 8001806: 683b ldr r3, [r7, #0] - 8001808: 691b ldr r3, [r3, #16] - 800180a: 2b04 cmp r3, #4 - 800180c: d04f beq.n 80018ae - 800180e: 683b ldr r3, [r7, #0] - 8001810: 691b ldr r3, [r3, #16] - 8001812: 2b05 cmp r3, #5 - 8001814: d04b beq.n 80018ae - 8001816: 683b ldr r3, [r7, #0] - 8001818: 691b ldr r3, [r3, #16] - 800181a: 2b05 cmp r3, #5 - 800181c: d047 beq.n 80018ae - 800181e: 683b ldr r3, [r7, #0] - 8001820: 691b ldr r3, [r3, #16] - 8001822: 2b09 cmp r3, #9 - 8001824: d043 beq.n 80018ae - 8001826: 683b ldr r3, [r7, #0] - 8001828: 691b ldr r3, [r3, #16] - 800182a: 2b06 cmp r3, #6 - 800182c: d03f beq.n 80018ae - 800182e: 683b ldr r3, [r7, #0] - 8001830: 691b ldr r3, [r3, #16] - 8001832: 2b09 cmp r3, #9 - 8001834: d03b beq.n 80018ae - 8001836: 683b ldr r3, [r7, #0] - 8001838: 691b ldr r3, [r3, #16] - 800183a: 2b07 cmp r3, #7 - 800183c: d037 beq.n 80018ae - 800183e: 683b ldr r3, [r7, #0] - 8001840: 691b ldr r3, [r3, #16] - 8001842: 2b07 cmp r3, #7 - 8001844: d033 beq.n 80018ae - 8001846: 683b ldr r3, [r7, #0] - 8001848: 691b ldr r3, [r3, #16] - 800184a: 2b07 cmp r3, #7 - 800184c: d02f beq.n 80018ae - 800184e: 683b ldr r3, [r7, #0] - 8001850: 691b ldr r3, [r3, #16] - 8001852: 2b08 cmp r3, #8 - 8001854: d02b beq.n 80018ae - 8001856: 683b ldr r3, [r7, #0] - 8001858: 691b ldr r3, [r3, #16] - 800185a: 2b08 cmp r3, #8 - 800185c: d027 beq.n 80018ae - 800185e: 683b ldr r3, [r7, #0] - 8001860: 691b ldr r3, [r3, #16] - 8001862: 2b08 cmp r3, #8 - 8001864: d023 beq.n 80018ae - 8001866: 683b ldr r3, [r7, #0] - 8001868: 691b ldr r3, [r3, #16] - 800186a: 2b09 cmp r3, #9 - 800186c: d01f beq.n 80018ae - 800186e: 683b ldr r3, [r7, #0] - 8001870: 691b ldr r3, [r3, #16] - 8001872: 2b09 cmp r3, #9 - 8001874: d01b beq.n 80018ae - 8001876: 683b ldr r3, [r7, #0] - 8001878: 691b ldr r3, [r3, #16] - 800187a: 2b0a cmp r3, #10 - 800187c: d017 beq.n 80018ae - 800187e: 683b ldr r3, [r7, #0] - 8001880: 691b ldr r3, [r3, #16] - 8001882: 2b0a cmp r3, #10 - 8001884: d013 beq.n 80018ae - 8001886: 683b ldr r3, [r7, #0] - 8001888: 691b ldr r3, [r3, #16] - 800188a: 2b0c cmp r3, #12 - 800188c: d00f beq.n 80018ae - 800188e: 683b ldr r3, [r7, #0] - 8001890: 691b ldr r3, [r3, #16] - 8001892: 2b0c cmp r3, #12 - 8001894: d00b beq.n 80018ae - 8001896: 683b ldr r3, [r7, #0] - 8001898: 691b ldr r3, [r3, #16] - 800189a: 2b0c cmp r3, #12 - 800189c: d007 beq.n 80018ae - 800189e: 683b ldr r3, [r7, #0] - 80018a0: 691b ldr r3, [r3, #16] - 80018a2: 2b0f cmp r3, #15 - 80018a4: d003 beq.n 80018ae - 80018a6: 21de movs r1, #222 @ 0xde - 80018a8: 4813 ldr r0, [pc, #76] @ (80018f8 ) - 80018aa: f7fe ffcd bl 8000848 + 8002e06: 683b ldr r3, [r7, #0] + 8002e08: 691b ldr r3, [r3, #16] + 8002e0a: 2b00 cmp r3, #0 + 8002e0c: f000 8089 beq.w 8002f22 + 8002e10: 683b ldr r3, [r7, #0] + 8002e12: 691b ldr r3, [r3, #16] + 8002e14: 2b09 cmp r3, #9 + 8002e16: f000 8084 beq.w 8002f22 + 8002e1a: 683b ldr r3, [r7, #0] + 8002e1c: 691b ldr r3, [r3, #16] + 8002e1e: 2b00 cmp r3, #0 + 8002e20: d07f beq.n 8002f22 + 8002e22: 683b ldr r3, [r7, #0] + 8002e24: 691b ldr r3, [r3, #16] + 8002e26: 2b00 cmp r3, #0 + 8002e28: d07b beq.n 8002f22 + 8002e2a: 683b ldr r3, [r7, #0] + 8002e2c: 691b ldr r3, [r3, #16] + 8002e2e: 2b00 cmp r3, #0 + 8002e30: d077 beq.n 8002f22 + 8002e32: 683b ldr r3, [r7, #0] + 8002e34: 691b ldr r3, [r3, #16] + 8002e36: 2b00 cmp r3, #0 + 8002e38: d073 beq.n 8002f22 + 8002e3a: 683b ldr r3, [r7, #0] + 8002e3c: 691b ldr r3, [r3, #16] + 8002e3e: 2b01 cmp r3, #1 + 8002e40: d06f beq.n 8002f22 + 8002e42: 683b ldr r3, [r7, #0] + 8002e44: 691b ldr r3, [r3, #16] + 8002e46: 2b01 cmp r3, #1 + 8002e48: d06b beq.n 8002f22 + 8002e4a: 683b ldr r3, [r7, #0] + 8002e4c: 691b ldr r3, [r3, #16] + 8002e4e: 2b02 cmp r3, #2 + 8002e50: d067 beq.n 8002f22 + 8002e52: 683b ldr r3, [r7, #0] + 8002e54: 691b ldr r3, [r3, #16] + 8002e56: 2b02 cmp r3, #2 + 8002e58: d063 beq.n 8002f22 + 8002e5a: 683b ldr r3, [r7, #0] + 8002e5c: 691b ldr r3, [r3, #16] + 8002e5e: 2b02 cmp r3, #2 + 8002e60: d05f beq.n 8002f22 + 8002e62: 683b ldr r3, [r7, #0] + 8002e64: 691b ldr r3, [r3, #16] + 8002e66: 2b03 cmp r3, #3 + 8002e68: d05b beq.n 8002f22 + 8002e6a: 683b ldr r3, [r7, #0] + 8002e6c: 691b ldr r3, [r3, #16] + 8002e6e: 2b04 cmp r3, #4 + 8002e70: d057 beq.n 8002f22 + 8002e72: 683b ldr r3, [r7, #0] + 8002e74: 691b ldr r3, [r3, #16] + 8002e76: 2b04 cmp r3, #4 + 8002e78: d053 beq.n 8002f22 + 8002e7a: 683b ldr r3, [r7, #0] + 8002e7c: 691b ldr r3, [r3, #16] + 8002e7e: 2b04 cmp r3, #4 + 8002e80: d04f beq.n 8002f22 + 8002e82: 683b ldr r3, [r7, #0] + 8002e84: 691b ldr r3, [r3, #16] + 8002e86: 2b05 cmp r3, #5 + 8002e88: d04b beq.n 8002f22 + 8002e8a: 683b ldr r3, [r7, #0] + 8002e8c: 691b ldr r3, [r3, #16] + 8002e8e: 2b05 cmp r3, #5 + 8002e90: d047 beq.n 8002f22 + 8002e92: 683b ldr r3, [r7, #0] + 8002e94: 691b ldr r3, [r3, #16] + 8002e96: 2b09 cmp r3, #9 + 8002e98: d043 beq.n 8002f22 + 8002e9a: 683b ldr r3, [r7, #0] + 8002e9c: 691b ldr r3, [r3, #16] + 8002e9e: 2b06 cmp r3, #6 + 8002ea0: d03f beq.n 8002f22 + 8002ea2: 683b ldr r3, [r7, #0] + 8002ea4: 691b ldr r3, [r3, #16] + 8002ea6: 2b09 cmp r3, #9 + 8002ea8: d03b beq.n 8002f22 + 8002eaa: 683b ldr r3, [r7, #0] + 8002eac: 691b ldr r3, [r3, #16] + 8002eae: 2b07 cmp r3, #7 + 8002eb0: d037 beq.n 8002f22 + 8002eb2: 683b ldr r3, [r7, #0] + 8002eb4: 691b ldr r3, [r3, #16] + 8002eb6: 2b07 cmp r3, #7 + 8002eb8: d033 beq.n 8002f22 + 8002eba: 683b ldr r3, [r7, #0] + 8002ebc: 691b ldr r3, [r3, #16] + 8002ebe: 2b07 cmp r3, #7 + 8002ec0: d02f beq.n 8002f22 + 8002ec2: 683b ldr r3, [r7, #0] + 8002ec4: 691b ldr r3, [r3, #16] + 8002ec6: 2b08 cmp r3, #8 + 8002ec8: d02b beq.n 8002f22 + 8002eca: 683b ldr r3, [r7, #0] + 8002ecc: 691b ldr r3, [r3, #16] + 8002ece: 2b08 cmp r3, #8 + 8002ed0: d027 beq.n 8002f22 + 8002ed2: 683b ldr r3, [r7, #0] + 8002ed4: 691b ldr r3, [r3, #16] + 8002ed6: 2b08 cmp r3, #8 + 8002ed8: d023 beq.n 8002f22 + 8002eda: 683b ldr r3, [r7, #0] + 8002edc: 691b ldr r3, [r3, #16] + 8002ede: 2b09 cmp r3, #9 + 8002ee0: d01f beq.n 8002f22 + 8002ee2: 683b ldr r3, [r7, #0] + 8002ee4: 691b ldr r3, [r3, #16] + 8002ee6: 2b09 cmp r3, #9 + 8002ee8: d01b beq.n 8002f22 + 8002eea: 683b ldr r3, [r7, #0] + 8002eec: 691b ldr r3, [r3, #16] + 8002eee: 2b0a cmp r3, #10 + 8002ef0: d017 beq.n 8002f22 + 8002ef2: 683b ldr r3, [r7, #0] + 8002ef4: 691b ldr r3, [r3, #16] + 8002ef6: 2b0a cmp r3, #10 + 8002ef8: d013 beq.n 8002f22 + 8002efa: 683b ldr r3, [r7, #0] + 8002efc: 691b ldr r3, [r3, #16] + 8002efe: 2b0c cmp r3, #12 + 8002f00: d00f beq.n 8002f22 + 8002f02: 683b ldr r3, [r7, #0] + 8002f04: 691b ldr r3, [r3, #16] + 8002f06: 2b0c cmp r3, #12 + 8002f08: d00b beq.n 8002f22 + 8002f0a: 683b ldr r3, [r7, #0] + 8002f0c: 691b ldr r3, [r3, #16] + 8002f0e: 2b0c cmp r3, #12 + 8002f10: d007 beq.n 8002f22 + 8002f12: 683b ldr r3, [r7, #0] + 8002f14: 691b ldr r3, [r3, #16] + 8002f16: 2b0f cmp r3, #15 + 8002f18: d003 beq.n 8002f22 + 8002f1a: 21de movs r1, #222 @ 0xde + 8002f1c: 4813 ldr r0, [pc, #76] @ (8002f6c ) + 8002f1e: f7fd ff09 bl 8000d34 /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; - 80018ae: 69fb ldr r3, [r7, #28] - 80018b0: 08da lsrs r2, r3, #3 - 80018b2: 687b ldr r3, [r7, #4] - 80018b4: 3208 adds r2, #8 - 80018b6: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 80018ba: 61bb str r3, [r7, #24] + 8002f22: 69fb ldr r3, [r7, #28] + 8002f24: 08da lsrs r2, r3, #3 + 8002f26: 687b ldr r3, [r7, #4] + 8002f28: 3208 adds r2, #8 + 8002f2a: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8002f2e: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; - 80018bc: 69fb ldr r3, [r7, #28] - 80018be: f003 0307 and.w r3, r3, #7 - 80018c2: 009b lsls r3, r3, #2 - 80018c4: 220f movs r2, #15 - 80018c6: fa02 f303 lsl.w r3, r2, r3 - 80018ca: 43db mvns r3, r3 - 80018cc: 69ba ldr r2, [r7, #24] - 80018ce: 4013 ands r3, r2 - 80018d0: 61bb str r3, [r7, #24] + 8002f30: 69fb ldr r3, [r7, #28] + 8002f32: f003 0307 and.w r3, r3, #7 + 8002f36: 009b lsls r3, r3, #2 + 8002f38: 220f movs r2, #15 + 8002f3a: fa02 f303 lsl.w r3, r2, r3 + 8002f3e: 43db mvns r3, r3 + 8002f40: 69ba ldr r2, [r7, #24] + 8002f42: 4013 ands r3, r2 + 8002f44: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); - 80018d2: 683b ldr r3, [r7, #0] - 80018d4: 691a ldr r2, [r3, #16] - 80018d6: 69fb ldr r3, [r7, #28] - 80018d8: f003 0307 and.w r3, r3, #7 - 80018dc: 009b lsls r3, r3, #2 - 80018de: fa02 f303 lsl.w r3, r2, r3 - 80018e2: 69ba ldr r2, [r7, #24] - 80018e4: 4313 orrs r3, r2 - 80018e6: 61bb str r3, [r7, #24] + 8002f46: 683b ldr r3, [r7, #0] + 8002f48: 691a ldr r2, [r3, #16] + 8002f4a: 69fb ldr r3, [r7, #28] + 8002f4c: f003 0307 and.w r3, r3, #7 + 8002f50: 009b lsls r3, r3, #2 + 8002f52: fa02 f303 lsl.w r3, r2, r3 + 8002f56: 69ba ldr r2, [r7, #24] + 8002f58: 4313 orrs r3, r2 + 8002f5a: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; - 80018e8: 69fb ldr r3, [r7, #28] - 80018ea: 08da lsrs r2, r3, #3 - 80018ec: 687b ldr r3, [r7, #4] - 80018ee: 3208 adds r2, #8 - 80018f0: 69b9 ldr r1, [r7, #24] - 80018f2: f843 1022 str.w r1, [r3, r2, lsl #2] - 80018f6: e001 b.n 80018fc - 80018f8: 08005c5c .word 0x08005c5c + 8002f5c: 69fb ldr r3, [r7, #28] + 8002f5e: 08da lsrs r2, r3, #3 + 8002f60: 687b ldr r3, [r7, #4] + 8002f62: 3208 adds r2, #8 + 8002f64: 69b9 ldr r1, [r7, #24] + 8002f66: f843 1022 str.w r1, [r3, r2, lsl #2] + 8002f6a: e001 b.n 8002f70 + 8002f6c: 0800a168 .word 0x0800a168 } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; - 80018fc: 687b ldr r3, [r7, #4] - 80018fe: 681b ldr r3, [r3, #0] - 8001900: 61bb str r3, [r7, #24] + 8002f70: 687b ldr r3, [r7, #4] + 8002f72: 681b ldr r3, [r3, #0] + 8002f74: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); - 8001902: 69fb ldr r3, [r7, #28] - 8001904: 005b lsls r3, r3, #1 - 8001906: 2203 movs r2, #3 - 8001908: fa02 f303 lsl.w r3, r2, r3 - 800190c: 43db mvns r3, r3 - 800190e: 69ba ldr r2, [r7, #24] - 8001910: 4013 ands r3, r2 - 8001912: 61bb str r3, [r7, #24] + 8002f76: 69fb ldr r3, [r7, #28] + 8002f78: 005b lsls r3, r3, #1 + 8002f7a: 2203 movs r2, #3 + 8002f7c: fa02 f303 lsl.w r3, r2, r3 + 8002f80: 43db mvns r3, r3 + 8002f82: 69ba ldr r2, [r7, #24] + 8002f84: 4013 ands r3, r2 + 8002f86: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); - 8001914: 683b ldr r3, [r7, #0] - 8001916: 685b ldr r3, [r3, #4] - 8001918: f003 0203 and.w r2, r3, #3 - 800191c: 69fb ldr r3, [r7, #28] - 800191e: 005b lsls r3, r3, #1 - 8001920: fa02 f303 lsl.w r3, r2, r3 - 8001924: 69ba ldr r2, [r7, #24] - 8001926: 4313 orrs r3, r2 - 8001928: 61bb str r3, [r7, #24] + 8002f88: 683b ldr r3, [r7, #0] + 8002f8a: 685b ldr r3, [r3, #4] + 8002f8c: f003 0203 and.w r2, r3, #3 + 8002f90: 69fb ldr r3, [r7, #28] + 8002f92: 005b lsls r3, r3, #1 + 8002f94: fa02 f303 lsl.w r3, r2, r3 + 8002f98: 69ba ldr r2, [r7, #24] + 8002f9a: 4313 orrs r3, r2 + 8002f9c: 61bb str r3, [r7, #24] GPIOx->MODER = temp; - 800192a: 687b ldr r3, [r7, #4] - 800192c: 69ba ldr r2, [r7, #24] - 800192e: 601a str r2, [r3, #0] + 8002f9e: 687b ldr r3, [r7, #4] + 8002fa0: 69ba ldr r2, [r7, #24] + 8002fa2: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) != 0x00U) - 8001930: 683b ldr r3, [r7, #0] - 8001932: 685b ldr r3, [r3, #4] - 8001934: f403 3340 and.w r3, r3, #196608 @ 0x30000 - 8001938: 2b00 cmp r3, #0 - 800193a: f000 80b4 beq.w 8001aa6 + 8002fa4: 683b ldr r3, [r7, #0] + 8002fa6: 685b ldr r3, [r3, #4] + 8002fa8: f403 3340 and.w r3, r3, #196608 @ 0x30000 + 8002fac: 2b00 cmp r3, #0 + 8002fae: f000 80b4 beq.w 800311a { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); - 800193e: 2300 movs r3, #0 - 8001940: 60fb str r3, [r7, #12] - 8001942: 4b5f ldr r3, [pc, #380] @ (8001ac0 ) - 8001944: 6c5b ldr r3, [r3, #68] @ 0x44 - 8001946: 4a5e ldr r2, [pc, #376] @ (8001ac0 ) - 8001948: f443 4380 orr.w r3, r3, #16384 @ 0x4000 - 800194c: 6453 str r3, [r2, #68] @ 0x44 - 800194e: 4b5c ldr r3, [pc, #368] @ (8001ac0 ) - 8001950: 6c5b ldr r3, [r3, #68] @ 0x44 - 8001952: f403 4380 and.w r3, r3, #16384 @ 0x4000 - 8001956: 60fb str r3, [r7, #12] - 8001958: 68fb ldr r3, [r7, #12] + 8002fb2: 2300 movs r3, #0 + 8002fb4: 60fb str r3, [r7, #12] + 8002fb6: 4b5f ldr r3, [pc, #380] @ (8003134 ) + 8002fb8: 6c5b ldr r3, [r3, #68] @ 0x44 + 8002fba: 4a5e ldr r2, [pc, #376] @ (8003134 ) + 8002fbc: f443 4380 orr.w r3, r3, #16384 @ 0x4000 + 8002fc0: 6453 str r3, [r2, #68] @ 0x44 + 8002fc2: 4b5c ldr r3, [pc, #368] @ (8003134 ) + 8002fc4: 6c5b ldr r3, [r3, #68] @ 0x44 + 8002fc6: f403 4380 and.w r3, r3, #16384 @ 0x4000 + 8002fca: 60fb str r3, [r7, #12] + 8002fcc: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; - 800195a: 4a5a ldr r2, [pc, #360] @ (8001ac4 ) - 800195c: 69fb ldr r3, [r7, #28] - 800195e: 089b lsrs r3, r3, #2 - 8001960: 3302 adds r3, #2 - 8001962: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 8001966: 61bb str r3, [r7, #24] + 8002fce: 4a5a ldr r2, [pc, #360] @ (8003138 ) + 8002fd0: 69fb ldr r3, [r7, #28] + 8002fd2: 089b lsrs r3, r3, #2 + 8002fd4: 3302 adds r3, #2 + 8002fd6: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8002fda: 61bb str r3, [r7, #24] temp &= ~(0x0FU << (4U * (position & 0x03U))); - 8001968: 69fb ldr r3, [r7, #28] - 800196a: f003 0303 and.w r3, r3, #3 - 800196e: 009b lsls r3, r3, #2 - 8001970: 220f movs r2, #15 - 8001972: fa02 f303 lsl.w r3, r2, r3 - 8001976: 43db mvns r3, r3 - 8001978: 69ba ldr r2, [r7, #24] - 800197a: 4013 ands r3, r2 - 800197c: 61bb str r3, [r7, #24] + 8002fdc: 69fb ldr r3, [r7, #28] + 8002fde: f003 0303 and.w r3, r3, #3 + 8002fe2: 009b lsls r3, r3, #2 + 8002fe4: 220f movs r2, #15 + 8002fe6: fa02 f303 lsl.w r3, r2, r3 + 8002fea: 43db mvns r3, r3 + 8002fec: 69ba ldr r2, [r7, #24] + 8002fee: 4013 ands r3, r2 + 8002ff0: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); - 800197e: 687b ldr r3, [r7, #4] - 8001980: 4a51 ldr r2, [pc, #324] @ (8001ac8 ) - 8001982: 4293 cmp r3, r2 - 8001984: d02b beq.n 80019de - 8001986: 687b ldr r3, [r7, #4] - 8001988: 4a50 ldr r2, [pc, #320] @ (8001acc ) - 800198a: 4293 cmp r3, r2 - 800198c: d025 beq.n 80019da - 800198e: 687b ldr r3, [r7, #4] - 8001990: 4a4f ldr r2, [pc, #316] @ (8001ad0 ) - 8001992: 4293 cmp r3, r2 - 8001994: d01f beq.n 80019d6 - 8001996: 687b ldr r3, [r7, #4] - 8001998: 4a4e ldr r2, [pc, #312] @ (8001ad4 ) - 800199a: 4293 cmp r3, r2 - 800199c: d019 beq.n 80019d2 - 800199e: 687b ldr r3, [r7, #4] - 80019a0: 4a4d ldr r2, [pc, #308] @ (8001ad8 ) - 80019a2: 4293 cmp r3, r2 - 80019a4: d013 beq.n 80019ce - 80019a6: 687b ldr r3, [r7, #4] - 80019a8: 4a4c ldr r2, [pc, #304] @ (8001adc ) - 80019aa: 4293 cmp r3, r2 - 80019ac: d00d beq.n 80019ca - 80019ae: 687b ldr r3, [r7, #4] - 80019b0: 4a4b ldr r2, [pc, #300] @ (8001ae0 ) - 80019b2: 4293 cmp r3, r2 - 80019b4: d007 beq.n 80019c6 - 80019b6: 687b ldr r3, [r7, #4] - 80019b8: 4a4a ldr r2, [pc, #296] @ (8001ae4 ) - 80019ba: 4293 cmp r3, r2 - 80019bc: d101 bne.n 80019c2 - 80019be: 2307 movs r3, #7 - 80019c0: e00e b.n 80019e0 - 80019c2: 2308 movs r3, #8 - 80019c4: e00c b.n 80019e0 - 80019c6: 2306 movs r3, #6 - 80019c8: e00a b.n 80019e0 - 80019ca: 2305 movs r3, #5 - 80019cc: e008 b.n 80019e0 - 80019ce: 2304 movs r3, #4 - 80019d0: e006 b.n 80019e0 - 80019d2: 2303 movs r3, #3 - 80019d4: e004 b.n 80019e0 - 80019d6: 2302 movs r3, #2 - 80019d8: e002 b.n 80019e0 - 80019da: 2301 movs r3, #1 - 80019dc: e000 b.n 80019e0 - 80019de: 2300 movs r3, #0 - 80019e0: 69fa ldr r2, [r7, #28] - 80019e2: f002 0203 and.w r2, r2, #3 - 80019e6: 0092 lsls r2, r2, #2 - 80019e8: 4093 lsls r3, r2 - 80019ea: 69ba ldr r2, [r7, #24] - 80019ec: 4313 orrs r3, r2 - 80019ee: 61bb str r3, [r7, #24] + 8002ff2: 687b ldr r3, [r7, #4] + 8002ff4: 4a51 ldr r2, [pc, #324] @ (800313c ) + 8002ff6: 4293 cmp r3, r2 + 8002ff8: d02b beq.n 8003052 + 8002ffa: 687b ldr r3, [r7, #4] + 8002ffc: 4a50 ldr r2, [pc, #320] @ (8003140 ) + 8002ffe: 4293 cmp r3, r2 + 8003000: d025 beq.n 800304e + 8003002: 687b ldr r3, [r7, #4] + 8003004: 4a4f ldr r2, [pc, #316] @ (8003144 ) + 8003006: 4293 cmp r3, r2 + 8003008: d01f beq.n 800304a + 800300a: 687b ldr r3, [r7, #4] + 800300c: 4a4e ldr r2, [pc, #312] @ (8003148 ) + 800300e: 4293 cmp r3, r2 + 8003010: d019 beq.n 8003046 + 8003012: 687b ldr r3, [r7, #4] + 8003014: 4a4d ldr r2, [pc, #308] @ (800314c ) + 8003016: 4293 cmp r3, r2 + 8003018: d013 beq.n 8003042 + 800301a: 687b ldr r3, [r7, #4] + 800301c: 4a4c ldr r2, [pc, #304] @ (8003150 ) + 800301e: 4293 cmp r3, r2 + 8003020: d00d beq.n 800303e + 8003022: 687b ldr r3, [r7, #4] + 8003024: 4a4b ldr r2, [pc, #300] @ (8003154 ) + 8003026: 4293 cmp r3, r2 + 8003028: d007 beq.n 800303a + 800302a: 687b ldr r3, [r7, #4] + 800302c: 4a4a ldr r2, [pc, #296] @ (8003158 ) + 800302e: 4293 cmp r3, r2 + 8003030: d101 bne.n 8003036 + 8003032: 2307 movs r3, #7 + 8003034: e00e b.n 8003054 + 8003036: 2308 movs r3, #8 + 8003038: e00c b.n 8003054 + 800303a: 2306 movs r3, #6 + 800303c: e00a b.n 8003054 + 800303e: 2305 movs r3, #5 + 8003040: e008 b.n 8003054 + 8003042: 2304 movs r3, #4 + 8003044: e006 b.n 8003054 + 8003046: 2303 movs r3, #3 + 8003048: e004 b.n 8003054 + 800304a: 2302 movs r3, #2 + 800304c: e002 b.n 8003054 + 800304e: 2301 movs r3, #1 + 8003050: e000 b.n 8003054 + 8003052: 2300 movs r3, #0 + 8003054: 69fa ldr r2, [r7, #28] + 8003056: f002 0203 and.w r2, r2, #3 + 800305a: 0092 lsls r2, r2, #2 + 800305c: 4093 lsls r3, r2 + 800305e: 69ba ldr r2, [r7, #24] + 8003060: 4313 orrs r3, r2 + 8003062: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; - 80019f0: 4934 ldr r1, [pc, #208] @ (8001ac4 ) - 80019f2: 69fb ldr r3, [r7, #28] - 80019f4: 089b lsrs r3, r3, #2 - 80019f6: 3302 adds r3, #2 - 80019f8: 69ba ldr r2, [r7, #24] - 80019fa: f841 2023 str.w r2, [r1, r3, lsl #2] + 8003064: 4934 ldr r1, [pc, #208] @ (8003138 ) + 8003066: 69fb ldr r3, [r7, #28] + 8003068: 089b lsrs r3, r3, #2 + 800306a: 3302 adds r3, #2 + 800306c: 69ba ldr r2, [r7, #24] + 800306e: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; - 80019fe: 4b3a ldr r3, [pc, #232] @ (8001ae8 ) - 8001a00: 689b ldr r3, [r3, #8] - 8001a02: 61bb str r3, [r7, #24] + 8003072: 4b3a ldr r3, [pc, #232] @ (800315c ) + 8003074: 689b ldr r3, [r3, #8] + 8003076: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); - 8001a04: 693b ldr r3, [r7, #16] - 8001a06: 43db mvns r3, r3 - 8001a08: 69ba ldr r2, [r7, #24] - 8001a0a: 4013 ands r3, r2 - 8001a0c: 61bb str r3, [r7, #24] + 8003078: 693b ldr r3, [r7, #16] + 800307a: 43db mvns r3, r3 + 800307c: 69ba ldr r2, [r7, #24] + 800307e: 4013 ands r3, r2 + 8003080: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) - 8001a0e: 683b ldr r3, [r7, #0] - 8001a10: 685b ldr r3, [r3, #4] - 8001a12: f403 1380 and.w r3, r3, #1048576 @ 0x100000 - 8001a16: 2b00 cmp r3, #0 - 8001a18: d003 beq.n 8001a22 + 8003082: 683b ldr r3, [r7, #0] + 8003084: 685b ldr r3, [r3, #4] + 8003086: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 800308a: 2b00 cmp r3, #0 + 800308c: d003 beq.n 8003096 { temp |= iocurrent; - 8001a1a: 69ba ldr r2, [r7, #24] - 8001a1c: 693b ldr r3, [r7, #16] - 8001a1e: 4313 orrs r3, r2 - 8001a20: 61bb str r3, [r7, #24] + 800308e: 69ba ldr r2, [r7, #24] + 8003090: 693b ldr r3, [r7, #16] + 8003092: 4313 orrs r3, r2 + 8003094: 61bb str r3, [r7, #24] } EXTI->RTSR = temp; - 8001a22: 4a31 ldr r2, [pc, #196] @ (8001ae8 ) - 8001a24: 69bb ldr r3, [r7, #24] - 8001a26: 6093 str r3, [r2, #8] + 8003096: 4a31 ldr r2, [pc, #196] @ (800315c ) + 8003098: 69bb ldr r3, [r7, #24] + 800309a: 6093 str r3, [r2, #8] temp = EXTI->FTSR; - 8001a28: 4b2f ldr r3, [pc, #188] @ (8001ae8 ) - 8001a2a: 68db ldr r3, [r3, #12] - 8001a2c: 61bb str r3, [r7, #24] + 800309c: 4b2f ldr r3, [pc, #188] @ (800315c ) + 800309e: 68db ldr r3, [r3, #12] + 80030a0: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); - 8001a2e: 693b ldr r3, [r7, #16] - 8001a30: 43db mvns r3, r3 - 8001a32: 69ba ldr r2, [r7, #24] - 8001a34: 4013 ands r3, r2 - 8001a36: 61bb str r3, [r7, #24] + 80030a2: 693b ldr r3, [r7, #16] + 80030a4: 43db mvns r3, r3 + 80030a6: 69ba ldr r2, [r7, #24] + 80030a8: 4013 ands r3, r2 + 80030aa: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) - 8001a38: 683b ldr r3, [r7, #0] - 8001a3a: 685b ldr r3, [r3, #4] - 8001a3c: f403 1300 and.w r3, r3, #2097152 @ 0x200000 - 8001a40: 2b00 cmp r3, #0 - 8001a42: d003 beq.n 8001a4c + 80030ac: 683b ldr r3, [r7, #0] + 80030ae: 685b ldr r3, [r3, #4] + 80030b0: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 80030b4: 2b00 cmp r3, #0 + 80030b6: d003 beq.n 80030c0 { temp |= iocurrent; - 8001a44: 69ba ldr r2, [r7, #24] - 8001a46: 693b ldr r3, [r7, #16] - 8001a48: 4313 orrs r3, r2 - 8001a4a: 61bb str r3, [r7, #24] + 80030b8: 69ba ldr r2, [r7, #24] + 80030ba: 693b ldr r3, [r7, #16] + 80030bc: 4313 orrs r3, r2 + 80030be: 61bb str r3, [r7, #24] } EXTI->FTSR = temp; - 8001a4c: 4a26 ldr r2, [pc, #152] @ (8001ae8 ) - 8001a4e: 69bb ldr r3, [r7, #24] - 8001a50: 60d3 str r3, [r2, #12] + 80030c0: 4a26 ldr r2, [pc, #152] @ (800315c ) + 80030c2: 69bb ldr r3, [r7, #24] + 80030c4: 60d3 str r3, [r2, #12] temp = EXTI->EMR; - 8001a52: 4b25 ldr r3, [pc, #148] @ (8001ae8 ) - 8001a54: 685b ldr r3, [r3, #4] - 8001a56: 61bb str r3, [r7, #24] + 80030c6: 4b25 ldr r3, [pc, #148] @ (800315c ) + 80030c8: 685b ldr r3, [r3, #4] + 80030ca: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); - 8001a58: 693b ldr r3, [r7, #16] - 8001a5a: 43db mvns r3, r3 - 8001a5c: 69ba ldr r2, [r7, #24] - 8001a5e: 4013 ands r3, r2 - 8001a60: 61bb str r3, [r7, #24] + 80030cc: 693b ldr r3, [r7, #16] + 80030ce: 43db mvns r3, r3 + 80030d0: 69ba ldr r2, [r7, #24] + 80030d2: 4013 ands r3, r2 + 80030d4: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_EVT) != 0x00U) - 8001a62: 683b ldr r3, [r7, #0] - 8001a64: 685b ldr r3, [r3, #4] - 8001a66: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8001a6a: 2b00 cmp r3, #0 - 8001a6c: d003 beq.n 8001a76 + 80030d6: 683b ldr r3, [r7, #0] + 80030d8: 685b ldr r3, [r3, #4] + 80030da: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80030de: 2b00 cmp r3, #0 + 80030e0: d003 beq.n 80030ea { temp |= iocurrent; - 8001a6e: 69ba ldr r2, [r7, #24] - 8001a70: 693b ldr r3, [r7, #16] - 8001a72: 4313 orrs r3, r2 - 8001a74: 61bb str r3, [r7, #24] + 80030e2: 69ba ldr r2, [r7, #24] + 80030e4: 693b ldr r3, [r7, #16] + 80030e6: 4313 orrs r3, r2 + 80030e8: 61bb str r3, [r7, #24] } EXTI->EMR = temp; - 8001a76: 4a1c ldr r2, [pc, #112] @ (8001ae8 ) - 8001a78: 69bb ldr r3, [r7, #24] - 8001a7a: 6053 str r3, [r2, #4] + 80030ea: 4a1c ldr r2, [pc, #112] @ (800315c ) + 80030ec: 69bb ldr r3, [r7, #24] + 80030ee: 6053 str r3, [r2, #4] /* Clear EXTI line configuration */ temp = EXTI->IMR; - 8001a7c: 4b1a ldr r3, [pc, #104] @ (8001ae8 ) - 8001a7e: 681b ldr r3, [r3, #0] - 8001a80: 61bb str r3, [r7, #24] + 80030f0: 4b1a ldr r3, [pc, #104] @ (800315c ) + 80030f2: 681b ldr r3, [r3, #0] + 80030f4: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); - 8001a82: 693b ldr r3, [r7, #16] - 8001a84: 43db mvns r3, r3 - 8001a86: 69ba ldr r2, [r7, #24] - 8001a88: 4013 ands r3, r2 - 8001a8a: 61bb str r3, [r7, #24] + 80030f6: 693b ldr r3, [r7, #16] + 80030f8: 43db mvns r3, r3 + 80030fa: 69ba ldr r2, [r7, #24] + 80030fc: 4013 ands r3, r2 + 80030fe: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_IT) != 0x00U) - 8001a8c: 683b ldr r3, [r7, #0] - 8001a8e: 685b ldr r3, [r3, #4] - 8001a90: f403 3380 and.w r3, r3, #65536 @ 0x10000 - 8001a94: 2b00 cmp r3, #0 - 8001a96: d003 beq.n 8001aa0 + 8003100: 683b ldr r3, [r7, #0] + 8003102: 685b ldr r3, [r3, #4] + 8003104: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8003108: 2b00 cmp r3, #0 + 800310a: d003 beq.n 8003114 { temp |= iocurrent; - 8001a98: 69ba ldr r2, [r7, #24] - 8001a9a: 693b ldr r3, [r7, #16] - 8001a9c: 4313 orrs r3, r2 - 8001a9e: 61bb str r3, [r7, #24] + 800310c: 69ba ldr r2, [r7, #24] + 800310e: 693b ldr r3, [r7, #16] + 8003110: 4313 orrs r3, r2 + 8003112: 61bb str r3, [r7, #24] } EXTI->IMR = temp; - 8001aa0: 4a11 ldr r2, [pc, #68] @ (8001ae8 ) - 8001aa2: 69bb ldr r3, [r7, #24] - 8001aa4: 6013 str r3, [r2, #0] + 8003114: 4a11 ldr r2, [pc, #68] @ (800315c ) + 8003116: 69bb ldr r3, [r7, #24] + 8003118: 6013 str r3, [r2, #0] for(position = 0U; position < GPIO_NUMBER; position++) - 8001aa6: 69fb ldr r3, [r7, #28] - 8001aa8: 3301 adds r3, #1 - 8001aaa: 61fb str r3, [r7, #28] - 8001aac: 69fb ldr r3, [r7, #28] - 8001aae: 2b0f cmp r3, #15 - 8001ab0: f67f adda bls.w 8001668 + 800311a: 69fb ldr r3, [r7, #28] + 800311c: 3301 adds r3, #1 + 800311e: 61fb str r3, [r7, #28] + 8003120: 69fb ldr r3, [r7, #28] + 8003122: 2b0f cmp r3, #15 + 8003124: f67f adda bls.w 8002cdc } } } } - 8001ab4: bf00 nop - 8001ab6: bf00 nop - 8001ab8: 3720 adds r7, #32 - 8001aba: 46bd mov sp, r7 - 8001abc: bd80 pop {r7, pc} - 8001abe: bf00 nop - 8001ac0: 40023800 .word 0x40023800 - 8001ac4: 40013800 .word 0x40013800 - 8001ac8: 40020000 .word 0x40020000 - 8001acc: 40020400 .word 0x40020400 - 8001ad0: 40020800 .word 0x40020800 - 8001ad4: 40020c00 .word 0x40020c00 - 8001ad8: 40021000 .word 0x40021000 - 8001adc: 40021400 .word 0x40021400 - 8001ae0: 40021800 .word 0x40021800 - 8001ae4: 40021c00 .word 0x40021c00 - 8001ae8: 40013c00 .word 0x40013c00 + 8003128: bf00 nop + 800312a: bf00 nop + 800312c: 3720 adds r7, #32 + 800312e: 46bd mov sp, r7 + 8003130: bd80 pop {r7, pc} + 8003132: bf00 nop + 8003134: 40023800 .word 0x40023800 + 8003138: 40013800 .word 0x40013800 + 800313c: 40020000 .word 0x40020000 + 8003140: 40020400 .word 0x40020400 + 8003144: 40020800 .word 0x40020800 + 8003148: 40020c00 .word 0x40020c00 + 800314c: 40021000 .word 0x40021000 + 8003150: 40021400 .word 0x40021400 + 8003154: 40021800 .word 0x40021800 + 8003158: 40021c00 .word 0x40021c00 + 800315c: 40013c00 .word 0x40013c00 -08001aec : +08003160 : + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + 8003160: b580 push {r7, lr} + 8003162: b082 sub sp, #8 + 8003164: af00 add r7, sp, #0 + 8003166: 6078 str r0, [r7, #4] + 8003168: 460b mov r3, r1 + 800316a: 807b strh r3, [r7, #2] + 800316c: 4613 mov r3, r2 + 800316e: 707b strb r3, [r7, #1] + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + 8003170: 887b ldrh r3, [r7, #2] + 8003172: 2b00 cmp r3, #0 + 8003174: d104 bne.n 8003180 + 8003176: f240 119d movw r1, #413 @ 0x19d + 800317a: 480e ldr r0, [pc, #56] @ (80031b4 ) + 800317c: f7fd fdda bl 8000d34 + assert_param(IS_GPIO_PIN_ACTION(PinState)); + 8003180: 787b ldrb r3, [r7, #1] + 8003182: 2b00 cmp r3, #0 + 8003184: d007 beq.n 8003196 + 8003186: 787b ldrb r3, [r7, #1] + 8003188: 2b01 cmp r3, #1 + 800318a: d004 beq.n 8003196 + 800318c: f44f 71cf mov.w r1, #414 @ 0x19e + 8003190: 4808 ldr r0, [pc, #32] @ (80031b4 ) + 8003192: f7fd fdcf bl 8000d34 + + if(PinState != GPIO_PIN_RESET) + 8003196: 787b ldrb r3, [r7, #1] + 8003198: 2b00 cmp r3, #0 + 800319a: d003 beq.n 80031a4 + { + GPIOx->BSRR = GPIO_Pin; + 800319c: 887a ldrh r2, [r7, #2] + 800319e: 687b ldr r3, [r7, #4] + 80031a0: 619a str r2, [r3, #24] + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; + } +} + 80031a2: e003 b.n 80031ac + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; + 80031a4: 887b ldrh r3, [r7, #2] + 80031a6: 041a lsls r2, r3, #16 + 80031a8: 687b ldr r3, [r7, #4] + 80031aa: 619a str r2, [r3, #24] +} + 80031ac: bf00 nop + 80031ae: 3708 adds r7, #8 + 80031b0: 46bd mov sp, r7 + 80031b2: bd80 pop {r7, pc} + 80031b4: 0800a168 .word 0x0800a168 + +080031b8 : + * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. + * @param GPIO_Pin Specifies the pins to be toggled. + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + 80031b8: b580 push {r7, lr} + 80031ba: b084 sub sp, #16 + 80031bc: af00 add r7, sp, #0 + 80031be: 6078 str r0, [r7, #4] + 80031c0: 460b mov r3, r1 + 80031c2: 807b strh r3, [r7, #2] + uint32_t odr; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + 80031c4: 887b ldrh r3, [r7, #2] + 80031c6: 2b00 cmp r3, #0 + 80031c8: d104 bne.n 80031d4 + 80031ca: f44f 71db mov.w r1, #438 @ 0x1b6 + 80031ce: 480a ldr r0, [pc, #40] @ (80031f8 ) + 80031d0: f7fd fdb0 bl 8000d34 + + /* get current Output Data Register value */ + odr = GPIOx->ODR; + 80031d4: 687b ldr r3, [r7, #4] + 80031d6: 695b ldr r3, [r3, #20] + 80031d8: 60fb str r3, [r7, #12] + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); + 80031da: 887a ldrh r2, [r7, #2] + 80031dc: 68fb ldr r3, [r7, #12] + 80031de: 4013 ands r3, r2 + 80031e0: 041a lsls r2, r3, #16 + 80031e2: 68fb ldr r3, [r7, #12] + 80031e4: 43d9 mvns r1, r3 + 80031e6: 887b ldrh r3, [r7, #2] + 80031e8: 400b ands r3, r1 + 80031ea: 431a orrs r2, r3 + 80031ec: 687b ldr r3, [r7, #4] + 80031ee: 619a str r2, [r3, #24] +} + 80031f0: bf00 nop + 80031f2: 3710 adds r7, #16 + 80031f4: 46bd mov sp, r7 + 80031f6: bd80 pop {r7, pc} + 80031f8: 0800a168 .word 0x0800a168 + +080031fc : * supported by this API. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) { - 8001aec: b580 push {r7, lr} - 8001aee: b086 sub sp, #24 - 8001af0: af00 add r7, sp, #0 - 8001af2: 6078 str r0, [r7, #4] + 80031fc: b580 push {r7, lr} + 80031fe: b086 sub sp, #24 + 8003200: af00 add r7, sp, #0 + 8003202: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) - 8001af4: 687b ldr r3, [r7, #4] - 8001af6: 2b00 cmp r3, #0 - 8001af8: d101 bne.n 8001afe + 8003204: 687b ldr r3, [r7, #4] + 8003206: 2b00 cmp r3, #0 + 8003208: d101 bne.n 800320e { return HAL_ERROR; - 8001afa: 2301 movs r3, #1 - 8001afc: e318 b.n 8002130 + 800320a: 2301 movs r3, #1 + 800320c: e318 b.n 8003840 } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); - 8001afe: 687b ldr r3, [r7, #4] - 8001b00: 681b ldr r3, [r3, #0] - 8001b02: 2b0f cmp r3, #15 - 8001b04: d903 bls.n 8001b0e - 8001b06: 21e6 movs r1, #230 @ 0xe6 - 8001b08: 4897 ldr r0, [pc, #604] @ (8001d68 ) - 8001b0a: f7fe fe9d bl 8000848 + 800320e: 687b ldr r3, [r7, #4] + 8003210: 681b ldr r3, [r3, #0] + 8003212: 2b0f cmp r3, #15 + 8003214: d903 bls.n 800321e + 8003216: 21e6 movs r1, #230 @ 0xe6 + 8003218: 4897 ldr r0, [pc, #604] @ (8003478 ) + 800321a: f7fd fd8b bl 8000d34 /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) - 8001b0e: 687b ldr r3, [r7, #4] - 8001b10: 681b ldr r3, [r3, #0] - 8001b12: f003 0301 and.w r3, r3, #1 - 8001b16: 2b00 cmp r3, #0 - 8001b18: f000 8088 beq.w 8001c2c + 800321e: 687b ldr r3, [r7, #4] + 8003220: 681b ldr r3, [r3, #0] + 8003222: f003 0301 and.w r3, r3, #1 + 8003226: 2b00 cmp r3, #0 + 8003228: f000 8088 beq.w 800333c { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); - 8001b1c: 687b ldr r3, [r7, #4] - 8001b1e: 685b ldr r3, [r3, #4] - 8001b20: 2b00 cmp r3, #0 - 8001b22: d00d beq.n 8001b40 - 8001b24: 687b ldr r3, [r7, #4] - 8001b26: 685b ldr r3, [r3, #4] - 8001b28: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 - 8001b2c: d008 beq.n 8001b40 - 8001b2e: 687b ldr r3, [r7, #4] - 8001b30: 685b ldr r3, [r3, #4] - 8001b32: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 - 8001b36: d003 beq.n 8001b40 - 8001b38: 21eb movs r1, #235 @ 0xeb - 8001b3a: 488b ldr r0, [pc, #556] @ (8001d68 ) - 8001b3c: f7fe fe84 bl 8000848 + 800322c: 687b ldr r3, [r7, #4] + 800322e: 685b ldr r3, [r3, #4] + 8003230: 2b00 cmp r3, #0 + 8003232: d00d beq.n 8003250 + 8003234: 687b ldr r3, [r7, #4] + 8003236: 685b ldr r3, [r3, #4] + 8003238: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 800323c: d008 beq.n 8003250 + 800323e: 687b ldr r3, [r7, #4] + 8003240: 685b ldr r3, [r3, #4] + 8003242: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 + 8003246: d003 beq.n 8003250 + 8003248: 21eb movs r1, #235 @ 0xeb + 800324a: 488b ldr r0, [pc, #556] @ (8003478 ) + 800324c: f7fd fd72 bl 8000d34 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \ - 8001b40: 4b8a ldr r3, [pc, #552] @ (8001d6c ) - 8001b42: 689b ldr r3, [r3, #8] - 8001b44: f003 030c and.w r3, r3, #12 - 8001b48: 2b04 cmp r3, #4 - 8001b4a: d00c beq.n 8001b66 + 8003250: 4b8a ldr r3, [pc, #552] @ (800347c ) + 8003252: 689b ldr r3, [r3, #8] + 8003254: f003 030c and.w r3, r3, #12 + 8003258: 2b04 cmp r3, #4 + 800325a: d00c beq.n 8003276 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) - 8001b4c: 4b87 ldr r3, [pc, #540] @ (8001d6c ) - 8001b4e: 689b ldr r3, [r3, #8] - 8001b50: f003 030c and.w r3, r3, #12 + 800325c: 4b87 ldr r3, [pc, #540] @ (800347c ) + 800325e: 689b ldr r3, [r3, #8] + 8003260: f003 030c and.w r3, r3, #12 if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \ - 8001b54: 2b08 cmp r3, #8 - 8001b56: d112 bne.n 8001b7e + 8003264: 2b08 cmp r3, #8 + 8003266: d112 bne.n 800328e ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) - 8001b58: 4b84 ldr r3, [pc, #528] @ (8001d6c ) - 8001b5a: 685b ldr r3, [r3, #4] - 8001b5c: f403 0380 and.w r3, r3, #4194304 @ 0x400000 - 8001b60: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 - 8001b64: d10b bne.n 8001b7e + 8003268: 4b84 ldr r3, [pc, #528] @ (800347c ) + 800326a: 685b ldr r3, [r3, #4] + 800326c: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 8003270: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 + 8003274: d10b bne.n 800328e { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - 8001b66: 4b81 ldr r3, [pc, #516] @ (8001d6c ) - 8001b68: 681b ldr r3, [r3, #0] - 8001b6a: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8001b6e: 2b00 cmp r3, #0 - 8001b70: d05b beq.n 8001c2a - 8001b72: 687b ldr r3, [r7, #4] - 8001b74: 685b ldr r3, [r3, #4] - 8001b76: 2b00 cmp r3, #0 - 8001b78: d157 bne.n 8001c2a + 8003276: 4b81 ldr r3, [pc, #516] @ (800347c ) + 8003278: 681b ldr r3, [r3, #0] + 800327a: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 800327e: 2b00 cmp r3, #0 + 8003280: d05b beq.n 800333a + 8003282: 687b ldr r3, [r7, #4] + 8003284: 685b ldr r3, [r3, #4] + 8003286: 2b00 cmp r3, #0 + 8003288: d157 bne.n 800333a { return HAL_ERROR; - 8001b7a: 2301 movs r3, #1 - 8001b7c: e2d8 b.n 8002130 + 800328a: 2301 movs r3, #1 + 800328c: e2d8 b.n 8003840 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - 8001b7e: 687b ldr r3, [r7, #4] - 8001b80: 685b ldr r3, [r3, #4] - 8001b82: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 - 8001b86: d106 bne.n 8001b96 - 8001b88: 4b78 ldr r3, [pc, #480] @ (8001d6c ) - 8001b8a: 681b ldr r3, [r3, #0] - 8001b8c: 4a77 ldr r2, [pc, #476] @ (8001d6c ) - 8001b8e: f443 3380 orr.w r3, r3, #65536 @ 0x10000 - 8001b92: 6013 str r3, [r2, #0] - 8001b94: e01d b.n 8001bd2 - 8001b96: 687b ldr r3, [r7, #4] - 8001b98: 685b ldr r3, [r3, #4] - 8001b9a: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 - 8001b9e: d10c bne.n 8001bba - 8001ba0: 4b72 ldr r3, [pc, #456] @ (8001d6c ) - 8001ba2: 681b ldr r3, [r3, #0] - 8001ba4: 4a71 ldr r2, [pc, #452] @ (8001d6c ) - 8001ba6: f443 2380 orr.w r3, r3, #262144 @ 0x40000 - 8001baa: 6013 str r3, [r2, #0] - 8001bac: 4b6f ldr r3, [pc, #444] @ (8001d6c ) - 8001bae: 681b ldr r3, [r3, #0] - 8001bb0: 4a6e ldr r2, [pc, #440] @ (8001d6c ) - 8001bb2: f443 3380 orr.w r3, r3, #65536 @ 0x10000 - 8001bb6: 6013 str r3, [r2, #0] - 8001bb8: e00b b.n 8001bd2 - 8001bba: 4b6c ldr r3, [pc, #432] @ (8001d6c ) - 8001bbc: 681b ldr r3, [r3, #0] - 8001bbe: 4a6b ldr r2, [pc, #428] @ (8001d6c ) - 8001bc0: f423 3380 bic.w r3, r3, #65536 @ 0x10000 - 8001bc4: 6013 str r3, [r2, #0] - 8001bc6: 4b69 ldr r3, [pc, #420] @ (8001d6c ) - 8001bc8: 681b ldr r3, [r3, #0] - 8001bca: 4a68 ldr r2, [pc, #416] @ (8001d6c ) - 8001bcc: f423 2380 bic.w r3, r3, #262144 @ 0x40000 - 8001bd0: 6013 str r3, [r2, #0] + 800328e: 687b ldr r3, [r7, #4] + 8003290: 685b ldr r3, [r3, #4] + 8003292: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8003296: d106 bne.n 80032a6 + 8003298: 4b78 ldr r3, [pc, #480] @ (800347c ) + 800329a: 681b ldr r3, [r3, #0] + 800329c: 4a77 ldr r2, [pc, #476] @ (800347c ) + 800329e: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 80032a2: 6013 str r3, [r2, #0] + 80032a4: e01d b.n 80032e2 + 80032a6: 687b ldr r3, [r7, #4] + 80032a8: 685b ldr r3, [r3, #4] + 80032aa: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 + 80032ae: d10c bne.n 80032ca + 80032b0: 4b72 ldr r3, [pc, #456] @ (800347c ) + 80032b2: 681b ldr r3, [r3, #0] + 80032b4: 4a71 ldr r2, [pc, #452] @ (800347c ) + 80032b6: f443 2380 orr.w r3, r3, #262144 @ 0x40000 + 80032ba: 6013 str r3, [r2, #0] + 80032bc: 4b6f ldr r3, [pc, #444] @ (800347c ) + 80032be: 681b ldr r3, [r3, #0] + 80032c0: 4a6e ldr r2, [pc, #440] @ (800347c ) + 80032c2: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 80032c6: 6013 str r3, [r2, #0] + 80032c8: e00b b.n 80032e2 + 80032ca: 4b6c ldr r3, [pc, #432] @ (800347c ) + 80032cc: 681b ldr r3, [r3, #0] + 80032ce: 4a6b ldr r2, [pc, #428] @ (800347c ) + 80032d0: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 80032d4: 6013 str r3, [r2, #0] + 80032d6: 4b69 ldr r3, [pc, #420] @ (800347c ) + 80032d8: 681b ldr r3, [r3, #0] + 80032da: 4a68 ldr r2, [pc, #416] @ (800347c ) + 80032dc: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 80032e0: 6013 str r3, [r2, #0] /* Check the HSE State */ if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) - 8001bd2: 687b ldr r3, [r7, #4] - 8001bd4: 685b ldr r3, [r3, #4] - 8001bd6: 2b00 cmp r3, #0 - 8001bd8: d013 beq.n 8001c02 + 80032e2: 687b ldr r3, [r7, #4] + 80032e4: 685b ldr r3, [r3, #4] + 80032e6: 2b00 cmp r3, #0 + 80032e8: d013 beq.n 8003312 { /* Get Start Tick */ tickstart = HAL_GetTick(); - 8001bda: f7ff f8a9 bl 8000d30 - 8001bde: 6138 str r0, [r7, #16] + 80032ea: f7fe f8a5 bl 8001438 + 80032ee: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - 8001be0: e008 b.n 8001bf4 + 80032f0: e008 b.n 8003304 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - 8001be2: f7ff f8a5 bl 8000d30 - 8001be6: 4602 mov r2, r0 - 8001be8: 693b ldr r3, [r7, #16] - 8001bea: 1ad3 subs r3, r2, r3 - 8001bec: 2b64 cmp r3, #100 @ 0x64 - 8001bee: d901 bls.n 8001bf4 + 80032f2: f7fe f8a1 bl 8001438 + 80032f6: 4602 mov r2, r0 + 80032f8: 693b ldr r3, [r7, #16] + 80032fa: 1ad3 subs r3, r2, r3 + 80032fc: 2b64 cmp r3, #100 @ 0x64 + 80032fe: d901 bls.n 8003304 { return HAL_TIMEOUT; - 8001bf0: 2303 movs r3, #3 - 8001bf2: e29d b.n 8002130 + 8003300: 2303 movs r3, #3 + 8003302: e29d b.n 8003840 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - 8001bf4: 4b5d ldr r3, [pc, #372] @ (8001d6c ) - 8001bf6: 681b ldr r3, [r3, #0] - 8001bf8: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8001bfc: 2b00 cmp r3, #0 - 8001bfe: d0f0 beq.n 8001be2 - 8001c00: e014 b.n 8001c2c + 8003304: 4b5d ldr r3, [pc, #372] @ (800347c ) + 8003306: 681b ldr r3, [r3, #0] + 8003308: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 800330c: 2b00 cmp r3, #0 + 800330e: d0f0 beq.n 80032f2 + 8003310: e014 b.n 800333c } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); - 8001c02: f7ff f895 bl 8000d30 - 8001c06: 6138 str r0, [r7, #16] + 8003312: f7fe f891 bl 8001438 + 8003316: 6138 str r0, [r7, #16] /* Wait till HSE is bypassed or disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - 8001c08: e008 b.n 8001c1c + 8003318: e008 b.n 800332c { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - 8001c0a: f7ff f891 bl 8000d30 - 8001c0e: 4602 mov r2, r0 - 8001c10: 693b ldr r3, [r7, #16] - 8001c12: 1ad3 subs r3, r2, r3 - 8001c14: 2b64 cmp r3, #100 @ 0x64 - 8001c16: d901 bls.n 8001c1c + 800331a: f7fe f88d bl 8001438 + 800331e: 4602 mov r2, r0 + 8003320: 693b ldr r3, [r7, #16] + 8003322: 1ad3 subs r3, r2, r3 + 8003324: 2b64 cmp r3, #100 @ 0x64 + 8003326: d901 bls.n 800332c { return HAL_TIMEOUT; - 8001c18: 2303 movs r3, #3 - 8001c1a: e289 b.n 8002130 + 8003328: 2303 movs r3, #3 + 800332a: e289 b.n 8003840 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - 8001c1c: 4b53 ldr r3, [pc, #332] @ (8001d6c ) - 8001c1e: 681b ldr r3, [r3, #0] - 8001c20: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8001c24: 2b00 cmp r3, #0 - 8001c26: d1f0 bne.n 8001c0a - 8001c28: e000 b.n 8001c2c + 800332c: 4b53 ldr r3, [pc, #332] @ (800347c ) + 800332e: 681b ldr r3, [r3, #0] + 8003330: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8003334: 2b00 cmp r3, #0 + 8003336: d1f0 bne.n 800331a + 8003338: e000 b.n 800333c if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - 8001c2a: bf00 nop + 800333a: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) - 8001c2c: 687b ldr r3, [r7, #4] - 8001c2e: 681b ldr r3, [r3, #0] - 8001c30: f003 0302 and.w r3, r3, #2 - 8001c34: 2b00 cmp r3, #0 - 8001c36: d079 beq.n 8001d2c + 800333c: 687b ldr r3, [r7, #4] + 800333e: 681b ldr r3, [r3, #0] + 8003340: f003 0302 and.w r3, r3, #2 + 8003344: 2b00 cmp r3, #0 + 8003346: d079 beq.n 800343c { /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); - 8001c38: 687b ldr r3, [r7, #4] - 8001c3a: 68db ldr r3, [r3, #12] - 8001c3c: 2b00 cmp r3, #0 - 8001c3e: d008 beq.n 8001c52 - 8001c40: 687b ldr r3, [r7, #4] - 8001c42: 68db ldr r3, [r3, #12] - 8001c44: 2b01 cmp r3, #1 - 8001c46: d004 beq.n 8001c52 - 8001c48: f240 111d movw r1, #285 @ 0x11d - 8001c4c: 4846 ldr r0, [pc, #280] @ (8001d68 ) - 8001c4e: f7fe fdfb bl 8000848 + 8003348: 687b ldr r3, [r7, #4] + 800334a: 68db ldr r3, [r3, #12] + 800334c: 2b00 cmp r3, #0 + 800334e: d008 beq.n 8003362 + 8003350: 687b ldr r3, [r7, #4] + 8003352: 68db ldr r3, [r3, #12] + 8003354: 2b01 cmp r3, #1 + 8003356: d004 beq.n 8003362 + 8003358: f240 111d movw r1, #285 @ 0x11d + 800335c: 4846 ldr r0, [pc, #280] @ (8003478 ) + 800335e: f7fd fce9 bl 8000d34 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); - 8001c52: 687b ldr r3, [r7, #4] - 8001c54: 691b ldr r3, [r3, #16] - 8001c56: 2b1f cmp r3, #31 - 8001c58: d904 bls.n 8001c64 - 8001c5a: f44f 718f mov.w r1, #286 @ 0x11e - 8001c5e: 4842 ldr r0, [pc, #264] @ (8001d68 ) - 8001c60: f7fe fdf2 bl 8000848 + 8003362: 687b ldr r3, [r7, #4] + 8003364: 691b ldr r3, [r3, #16] + 8003366: 2b1f cmp r3, #31 + 8003368: d904 bls.n 8003374 + 800336a: f44f 718f mov.w r1, #286 @ 0x11e + 800336e: 4842 ldr r0, [pc, #264] @ (8003478 ) + 8003370: f7fd fce0 bl 8000d34 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || \ - 8001c64: 4b41 ldr r3, [pc, #260] @ (8001d6c ) - 8001c66: 689b ldr r3, [r3, #8] - 8001c68: f003 030c and.w r3, r3, #12 - 8001c6c: 2b00 cmp r3, #0 - 8001c6e: d00b beq.n 8001c88 + 8003374: 4b41 ldr r3, [pc, #260] @ (800347c ) + 8003376: 689b ldr r3, [r3, #8] + 8003378: f003 030c and.w r3, r3, #12 + 800337c: 2b00 cmp r3, #0 + 800337e: d00b beq.n 8003398 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) - 8001c70: 4b3e ldr r3, [pc, #248] @ (8001d6c ) - 8001c72: 689b ldr r3, [r3, #8] - 8001c74: f003 030c and.w r3, r3, #12 + 8003380: 4b3e ldr r3, [pc, #248] @ (800347c ) + 8003382: 689b ldr r3, [r3, #8] + 8003384: f003 030c and.w r3, r3, #12 if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || \ - 8001c78: 2b08 cmp r3, #8 - 8001c7a: d11c bne.n 8001cb6 + 8003388: 2b08 cmp r3, #8 + 800338a: d11c bne.n 80033c6 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) - 8001c7c: 4b3b ldr r3, [pc, #236] @ (8001d6c ) - 8001c7e: 685b ldr r3, [r3, #4] - 8001c80: f403 0380 and.w r3, r3, #4194304 @ 0x400000 - 8001c84: 2b00 cmp r3, #0 - 8001c86: d116 bne.n 8001cb6 + 800338c: 4b3b ldr r3, [pc, #236] @ (800347c ) + 800338e: 685b ldr r3, [r3, #4] + 8003390: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 8003394: 2b00 cmp r3, #0 + 8003396: d116 bne.n 80033c6 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - 8001c88: 4b38 ldr r3, [pc, #224] @ (8001d6c ) - 8001c8a: 681b ldr r3, [r3, #0] - 8001c8c: f003 0302 and.w r3, r3, #2 - 8001c90: 2b00 cmp r3, #0 - 8001c92: d005 beq.n 8001ca0 - 8001c94: 687b ldr r3, [r7, #4] - 8001c96: 68db ldr r3, [r3, #12] - 8001c98: 2b01 cmp r3, #1 - 8001c9a: d001 beq.n 8001ca0 + 8003398: 4b38 ldr r3, [pc, #224] @ (800347c ) + 800339a: 681b ldr r3, [r3, #0] + 800339c: f003 0302 and.w r3, r3, #2 + 80033a0: 2b00 cmp r3, #0 + 80033a2: d005 beq.n 80033b0 + 80033a4: 687b ldr r3, [r7, #4] + 80033a6: 68db ldr r3, [r3, #12] + 80033a8: 2b01 cmp r3, #1 + 80033aa: d001 beq.n 80033b0 { return HAL_ERROR; - 8001c9c: 2301 movs r3, #1 - 8001c9e: e247 b.n 8002130 + 80033ac: 2301 movs r3, #1 + 80033ae: e247 b.n 8003840 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 8001ca0: 4b32 ldr r3, [pc, #200] @ (8001d6c ) - 8001ca2: 681b ldr r3, [r3, #0] - 8001ca4: f023 02f8 bic.w r2, r3, #248 @ 0xf8 - 8001ca8: 687b ldr r3, [r7, #4] - 8001caa: 691b ldr r3, [r3, #16] - 8001cac: 00db lsls r3, r3, #3 - 8001cae: 492f ldr r1, [pc, #188] @ (8001d6c ) - 8001cb0: 4313 orrs r3, r2 - 8001cb2: 600b str r3, [r1, #0] + 80033b0: 4b32 ldr r3, [pc, #200] @ (800347c ) + 80033b2: 681b ldr r3, [r3, #0] + 80033b4: f023 02f8 bic.w r2, r3, #248 @ 0xf8 + 80033b8: 687b ldr r3, [r7, #4] + 80033ba: 691b ldr r3, [r3, #16] + 80033bc: 00db lsls r3, r3, #3 + 80033be: 492f ldr r1, [pc, #188] @ (800347c ) + 80033c0: 4313 orrs r3, r2 + 80033c2: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - 8001cb4: e03a b.n 8001d2c + 80033c4: e03a b.n 800343c } } else { /* Check the HSI State */ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) - 8001cb6: 687b ldr r3, [r7, #4] - 8001cb8: 68db ldr r3, [r3, #12] - 8001cba: 2b00 cmp r3, #0 - 8001cbc: d020 beq.n 8001d00 + 80033c6: 687b ldr r3, [r7, #4] + 80033c8: 68db ldr r3, [r3, #12] + 80033ca: 2b00 cmp r3, #0 + 80033cc: d020 beq.n 8003410 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); - 8001cbe: 4b2c ldr r3, [pc, #176] @ (8001d70 ) - 8001cc0: 2201 movs r2, #1 - 8001cc2: 601a str r2, [r3, #0] + 80033ce: 4b2c ldr r3, [pc, #176] @ (8003480 ) + 80033d0: 2201 movs r2, #1 + 80033d2: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8001cc4: f7ff f834 bl 8000d30 - 8001cc8: 6138 str r0, [r7, #16] + 80033d4: f7fe f830 bl 8001438 + 80033d8: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - 8001cca: e008 b.n 8001cde + 80033da: e008 b.n 80033ee { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - 8001ccc: f7ff f830 bl 8000d30 - 8001cd0: 4602 mov r2, r0 - 8001cd2: 693b ldr r3, [r7, #16] - 8001cd4: 1ad3 subs r3, r2, r3 - 8001cd6: 2b02 cmp r3, #2 - 8001cd8: d901 bls.n 8001cde + 80033dc: f7fe f82c bl 8001438 + 80033e0: 4602 mov r2, r0 + 80033e2: 693b ldr r3, [r7, #16] + 80033e4: 1ad3 subs r3, r2, r3 + 80033e6: 2b02 cmp r3, #2 + 80033e8: d901 bls.n 80033ee { return HAL_TIMEOUT; - 8001cda: 2303 movs r3, #3 - 8001cdc: e228 b.n 8002130 + 80033ea: 2303 movs r3, #3 + 80033ec: e228 b.n 8003840 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - 8001cde: 4b23 ldr r3, [pc, #140] @ (8001d6c ) - 8001ce0: 681b ldr r3, [r3, #0] - 8001ce2: f003 0302 and.w r3, r3, #2 - 8001ce6: 2b00 cmp r3, #0 - 8001ce8: d0f0 beq.n 8001ccc + 80033ee: 4b23 ldr r3, [pc, #140] @ (800347c ) + 80033f0: 681b ldr r3, [r3, #0] + 80033f2: f003 0302 and.w r3, r3, #2 + 80033f6: 2b00 cmp r3, #0 + 80033f8: d0f0 beq.n 80033dc } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 8001cea: 4b20 ldr r3, [pc, #128] @ (8001d6c ) - 8001cec: 681b ldr r3, [r3, #0] - 8001cee: f023 02f8 bic.w r2, r3, #248 @ 0xf8 - 8001cf2: 687b ldr r3, [r7, #4] - 8001cf4: 691b ldr r3, [r3, #16] - 8001cf6: 00db lsls r3, r3, #3 - 8001cf8: 491c ldr r1, [pc, #112] @ (8001d6c ) - 8001cfa: 4313 orrs r3, r2 - 8001cfc: 600b str r3, [r1, #0] - 8001cfe: e015 b.n 8001d2c + 80033fa: 4b20 ldr r3, [pc, #128] @ (800347c ) + 80033fc: 681b ldr r3, [r3, #0] + 80033fe: f023 02f8 bic.w r2, r3, #248 @ 0xf8 + 8003402: 687b ldr r3, [r7, #4] + 8003404: 691b ldr r3, [r3, #16] + 8003406: 00db lsls r3, r3, #3 + 8003408: 491c ldr r1, [pc, #112] @ (800347c ) + 800340a: 4313 orrs r3, r2 + 800340c: 600b str r3, [r1, #0] + 800340e: e015 b.n 800343c } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); - 8001d00: 4b1b ldr r3, [pc, #108] @ (8001d70 ) - 8001d02: 2200 movs r2, #0 - 8001d04: 601a str r2, [r3, #0] + 8003410: 4b1b ldr r3, [pc, #108] @ (8003480 ) + 8003412: 2200 movs r2, #0 + 8003414: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8001d06: f7ff f813 bl 8000d30 - 8001d0a: 6138 str r0, [r7, #16] + 8003416: f7fe f80f bl 8001438 + 800341a: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) - 8001d0c: e008 b.n 8001d20 + 800341c: e008 b.n 8003430 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - 8001d0e: f7ff f80f bl 8000d30 - 8001d12: 4602 mov r2, r0 - 8001d14: 693b ldr r3, [r7, #16] - 8001d16: 1ad3 subs r3, r2, r3 - 8001d18: 2b02 cmp r3, #2 - 8001d1a: d901 bls.n 8001d20 + 800341e: f7fe f80b bl 8001438 + 8003422: 4602 mov r2, r0 + 8003424: 693b ldr r3, [r7, #16] + 8003426: 1ad3 subs r3, r2, r3 + 8003428: 2b02 cmp r3, #2 + 800342a: d901 bls.n 8003430 { return HAL_TIMEOUT; - 8001d1c: 2303 movs r3, #3 - 8001d1e: e207 b.n 8002130 + 800342c: 2303 movs r3, #3 + 800342e: e207 b.n 8003840 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) - 8001d20: 4b12 ldr r3, [pc, #72] @ (8001d6c ) - 8001d22: 681b ldr r3, [r3, #0] - 8001d24: f003 0302 and.w r3, r3, #2 - 8001d28: 2b00 cmp r3, #0 - 8001d2a: d1f0 bne.n 8001d0e + 8003430: 4b12 ldr r3, [pc, #72] @ (800347c ) + 8003432: 681b ldr r3, [r3, #0] + 8003434: f003 0302 and.w r3, r3, #2 + 8003438: 2b00 cmp r3, #0 + 800343a: d1f0 bne.n 800341e } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) - 8001d2c: 687b ldr r3, [r7, #4] - 8001d2e: 681b ldr r3, [r3, #0] - 8001d30: f003 0308 and.w r3, r3, #8 - 8001d34: 2b00 cmp r3, #0 - 8001d36: d045 beq.n 8001dc4 + 800343c: 687b ldr r3, [r7, #4] + 800343e: 681b ldr r3, [r3, #0] + 8003440: f003 0308 and.w r3, r3, #8 + 8003444: 2b00 cmp r3, #0 + 8003446: d045 beq.n 80034d4 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); - 8001d38: 687b ldr r3, [r7, #4] - 8001d3a: 695b ldr r3, [r3, #20] - 8001d3c: 2b00 cmp r3, #0 - 8001d3e: d008 beq.n 8001d52 - 8001d40: 687b ldr r3, [r7, #4] - 8001d42: 695b ldr r3, [r3, #20] - 8001d44: 2b01 cmp r3, #1 - 8001d46: d004 beq.n 8001d52 - 8001d48: f44f 71af mov.w r1, #350 @ 0x15e - 8001d4c: 4806 ldr r0, [pc, #24] @ (8001d68 ) - 8001d4e: f7fe fd7b bl 8000848 + 8003448: 687b ldr r3, [r7, #4] + 800344a: 695b ldr r3, [r3, #20] + 800344c: 2b00 cmp r3, #0 + 800344e: d008 beq.n 8003462 + 8003450: 687b ldr r3, [r7, #4] + 8003452: 695b ldr r3, [r3, #20] + 8003454: 2b01 cmp r3, #1 + 8003456: d004 beq.n 8003462 + 8003458: f44f 71af mov.w r1, #350 @ 0x15e + 800345c: 4806 ldr r0, [pc, #24] @ (8003478 ) + 800345e: f7fd fc69 bl 8000d34 /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) - 8001d52: 687b ldr r3, [r7, #4] - 8001d54: 695b ldr r3, [r3, #20] - 8001d56: 2b00 cmp r3, #0 - 8001d58: d01e beq.n 8001d98 + 8003462: 687b ldr r3, [r7, #4] + 8003464: 695b ldr r3, [r3, #20] + 8003466: 2b00 cmp r3, #0 + 8003468: d01e beq.n 80034a8 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); - 8001d5a: 4b06 ldr r3, [pc, #24] @ (8001d74 ) - 8001d5c: 2201 movs r2, #1 - 8001d5e: 601a str r2, [r3, #0] + 800346a: 4b06 ldr r3, [pc, #24] @ (8003484 ) + 800346c: 2201 movs r2, #1 + 800346e: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8001d60: f7fe ffe6 bl 8000d30 - 8001d64: 6138 str r0, [r7, #16] + 8003470: f7fd ffe2 bl 8001438 + 8003474: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) - 8001d66: e010 b.n 8001d8a - 8001d68: 08005c98 .word 0x08005c98 - 8001d6c: 40023800 .word 0x40023800 - 8001d70: 42470000 .word 0x42470000 - 8001d74: 42470e80 .word 0x42470e80 + 8003476: e010 b.n 800349a + 8003478: 0800a1a4 .word 0x0800a1a4 + 800347c: 40023800 .word 0x40023800 + 8003480: 42470000 .word 0x42470000 + 8003484: 42470e80 .word 0x42470e80 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) - 8001d78: f7fe ffda bl 8000d30 - 8001d7c: 4602 mov r2, r0 - 8001d7e: 693b ldr r3, [r7, #16] - 8001d80: 1ad3 subs r3, r2, r3 - 8001d82: 2b02 cmp r3, #2 - 8001d84: d901 bls.n 8001d8a + 8003488: f7fd ffd6 bl 8001438 + 800348c: 4602 mov r2, r0 + 800348e: 693b ldr r3, [r7, #16] + 8003490: 1ad3 subs r3, r2, r3 + 8003492: 2b02 cmp r3, #2 + 8003494: d901 bls.n 800349a { return HAL_TIMEOUT; - 8001d86: 2303 movs r3, #3 - 8001d88: e1d2 b.n 8002130 + 8003496: 2303 movs r3, #3 + 8003498: e1d2 b.n 8003840 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) - 8001d8a: 4b5e ldr r3, [pc, #376] @ (8001f04 ) - 8001d8c: 6f5b ldr r3, [r3, #116] @ 0x74 - 8001d8e: f003 0302 and.w r3, r3, #2 - 8001d92: 2b00 cmp r3, #0 - 8001d94: d0f0 beq.n 8001d78 - 8001d96: e015 b.n 8001dc4 + 800349a: 4b5e ldr r3, [pc, #376] @ (8003614 ) + 800349c: 6f5b ldr r3, [r3, #116] @ 0x74 + 800349e: f003 0302 and.w r3, r3, #2 + 80034a2: 2b00 cmp r3, #0 + 80034a4: d0f0 beq.n 8003488 + 80034a6: e015 b.n 80034d4 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); - 8001d98: 4b5b ldr r3, [pc, #364] @ (8001f08 ) - 8001d9a: 2200 movs r2, #0 - 8001d9c: 601a str r2, [r3, #0] + 80034a8: 4b5b ldr r3, [pc, #364] @ (8003618 ) + 80034aa: 2200 movs r2, #0 + 80034ac: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8001d9e: f7fe ffc7 bl 8000d30 - 8001da2: 6138 str r0, [r7, #16] + 80034ae: f7fd ffc3 bl 8001438 + 80034b2: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) - 8001da4: e008 b.n 8001db8 + 80034b4: e008 b.n 80034c8 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) - 8001da6: f7fe ffc3 bl 8000d30 - 8001daa: 4602 mov r2, r0 - 8001dac: 693b ldr r3, [r7, #16] - 8001dae: 1ad3 subs r3, r2, r3 - 8001db0: 2b02 cmp r3, #2 - 8001db2: d901 bls.n 8001db8 + 80034b6: f7fd ffbf bl 8001438 + 80034ba: 4602 mov r2, r0 + 80034bc: 693b ldr r3, [r7, #16] + 80034be: 1ad3 subs r3, r2, r3 + 80034c0: 2b02 cmp r3, #2 + 80034c2: d901 bls.n 80034c8 { return HAL_TIMEOUT; - 8001db4: 2303 movs r3, #3 - 8001db6: e1bb b.n 8002130 + 80034c4: 2303 movs r3, #3 + 80034c6: e1bb b.n 8003840 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) - 8001db8: 4b52 ldr r3, [pc, #328] @ (8001f04 ) - 8001dba: 6f5b ldr r3, [r3, #116] @ 0x74 - 8001dbc: f003 0302 and.w r3, r3, #2 - 8001dc0: 2b00 cmp r3, #0 - 8001dc2: d1f0 bne.n 8001da6 + 80034c8: 4b52 ldr r3, [pc, #328] @ (8003614 ) + 80034ca: 6f5b ldr r3, [r3, #116] @ 0x74 + 80034cc: f003 0302 and.w r3, r3, #2 + 80034d0: 2b00 cmp r3, #0 + 80034d2: d1f0 bne.n 80034b6 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) - 8001dc4: 687b ldr r3, [r7, #4] - 8001dc6: 681b ldr r3, [r3, #0] - 8001dc8: f003 0304 and.w r3, r3, #4 - 8001dcc: 2b00 cmp r3, #0 - 8001dce: f000 80b0 beq.w 8001f32 + 80034d4: 687b ldr r3, [r7, #4] + 80034d6: 681b ldr r3, [r3, #0] + 80034d8: f003 0304 and.w r3, r3, #4 + 80034dc: 2b00 cmp r3, #0 + 80034de: f000 80b0 beq.w 8003642 { FlagStatus pwrclkchanged = RESET; - 8001dd2: 2300 movs r3, #0 - 8001dd4: 75fb strb r3, [r7, #23] + 80034e2: 2300 movs r3, #0 + 80034e4: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); - 8001dd6: 687b ldr r3, [r7, #4] - 8001dd8: 689b ldr r3, [r3, #8] - 8001dda: 2b00 cmp r3, #0 - 8001ddc: d00c beq.n 8001df8 - 8001dde: 687b ldr r3, [r7, #4] - 8001de0: 689b ldr r3, [r3, #8] - 8001de2: 2b01 cmp r3, #1 - 8001de4: d008 beq.n 8001df8 - 8001de6: 687b ldr r3, [r7, #4] - 8001de8: 689b ldr r3, [r3, #8] - 8001dea: 2b05 cmp r3, #5 - 8001dec: d004 beq.n 8001df8 - 8001dee: f44f 71c5 mov.w r1, #394 @ 0x18a - 8001df2: 4846 ldr r0, [pc, #280] @ (8001f0c ) - 8001df4: f7fe fd28 bl 8000848 + 80034e6: 687b ldr r3, [r7, #4] + 80034e8: 689b ldr r3, [r3, #8] + 80034ea: 2b00 cmp r3, #0 + 80034ec: d00c beq.n 8003508 + 80034ee: 687b ldr r3, [r7, #4] + 80034f0: 689b ldr r3, [r3, #8] + 80034f2: 2b01 cmp r3, #1 + 80034f4: d008 beq.n 8003508 + 80034f6: 687b ldr r3, [r7, #4] + 80034f8: 689b ldr r3, [r3, #8] + 80034fa: 2b05 cmp r3, #5 + 80034fc: d004 beq.n 8003508 + 80034fe: f44f 71c5 mov.w r1, #394 @ 0x18a + 8003502: 4846 ldr r0, [pc, #280] @ (800361c ) + 8003504: f7fd fc16 bl 8000d34 /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) - 8001df8: 4b42 ldr r3, [pc, #264] @ (8001f04 ) - 8001dfa: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001dfc: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 8001e00: 2b00 cmp r3, #0 - 8001e02: d10f bne.n 8001e24 + 8003508: 4b42 ldr r3, [pc, #264] @ (8003614 ) + 800350a: 6c1b ldr r3, [r3, #64] @ 0x40 + 800350c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8003510: 2b00 cmp r3, #0 + 8003512: d10f bne.n 8003534 { __HAL_RCC_PWR_CLK_ENABLE(); - 8001e04: 2300 movs r3, #0 - 8001e06: 60bb str r3, [r7, #8] - 8001e08: 4b3e ldr r3, [pc, #248] @ (8001f04 ) - 8001e0a: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001e0c: 4a3d ldr r2, [pc, #244] @ (8001f04 ) - 8001e0e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 - 8001e12: 6413 str r3, [r2, #64] @ 0x40 - 8001e14: 4b3b ldr r3, [pc, #236] @ (8001f04 ) - 8001e16: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001e18: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 8001e1c: 60bb str r3, [r7, #8] - 8001e1e: 68bb ldr r3, [r7, #8] + 8003514: 2300 movs r3, #0 + 8003516: 60bb str r3, [r7, #8] + 8003518: 4b3e ldr r3, [pc, #248] @ (8003614 ) + 800351a: 6c1b ldr r3, [r3, #64] @ 0x40 + 800351c: 4a3d ldr r2, [pc, #244] @ (8003614 ) + 800351e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8003522: 6413 str r3, [r2, #64] @ 0x40 + 8003524: 4b3b ldr r3, [pc, #236] @ (8003614 ) + 8003526: 6c1b ldr r3, [r3, #64] @ 0x40 + 8003528: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 800352c: 60bb str r3, [r7, #8] + 800352e: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; - 8001e20: 2301 movs r3, #1 - 8001e22: 75fb strb r3, [r7, #23] + 8003530: 2301 movs r3, #1 + 8003532: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 8001e24: 4b3a ldr r3, [pc, #232] @ (8001f10 ) - 8001e26: 681b ldr r3, [r3, #0] - 8001e28: f403 7380 and.w r3, r3, #256 @ 0x100 - 8001e2c: 2b00 cmp r3, #0 - 8001e2e: d118 bne.n 8001e62 + 8003534: 4b3a ldr r3, [pc, #232] @ (8003620 ) + 8003536: 681b ldr r3, [r3, #0] + 8003538: f403 7380 and.w r3, r3, #256 @ 0x100 + 800353c: 2b00 cmp r3, #0 + 800353e: d118 bne.n 8003572 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); - 8001e30: 4b37 ldr r3, [pc, #220] @ (8001f10 ) - 8001e32: 681b ldr r3, [r3, #0] - 8001e34: 4a36 ldr r2, [pc, #216] @ (8001f10 ) - 8001e36: f443 7380 orr.w r3, r3, #256 @ 0x100 - 8001e3a: 6013 str r3, [r2, #0] + 8003540: 4b37 ldr r3, [pc, #220] @ (8003620 ) + 8003542: 681b ldr r3, [r3, #0] + 8003544: 4a36 ldr r2, [pc, #216] @ (8003620 ) + 8003546: f443 7380 orr.w r3, r3, #256 @ 0x100 + 800354a: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); - 8001e3c: f7fe ff78 bl 8000d30 - 8001e40: 6138 str r0, [r7, #16] + 800354c: f7fd ff74 bl 8001438 + 8003550: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 8001e42: e008 b.n 8001e56 + 8003552: e008 b.n 8003566 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - 8001e44: f7fe ff74 bl 8000d30 - 8001e48: 4602 mov r2, r0 - 8001e4a: 693b ldr r3, [r7, #16] - 8001e4c: 1ad3 subs r3, r2, r3 - 8001e4e: 2b02 cmp r3, #2 - 8001e50: d901 bls.n 8001e56 + 8003554: f7fd ff70 bl 8001438 + 8003558: 4602 mov r2, r0 + 800355a: 693b ldr r3, [r7, #16] + 800355c: 1ad3 subs r3, r2, r3 + 800355e: 2b02 cmp r3, #2 + 8003560: d901 bls.n 8003566 { return HAL_TIMEOUT; - 8001e52: 2303 movs r3, #3 - 8001e54: e16c b.n 8002130 + 8003562: 2303 movs r3, #3 + 8003564: e16c b.n 8003840 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 8001e56: 4b2e ldr r3, [pc, #184] @ (8001f10 ) - 8001e58: 681b ldr r3, [r3, #0] - 8001e5a: f403 7380 and.w r3, r3, #256 @ 0x100 - 8001e5e: 2b00 cmp r3, #0 - 8001e60: d0f0 beq.n 8001e44 + 8003566: 4b2e ldr r3, [pc, #184] @ (8003620 ) + 8003568: 681b ldr r3, [r3, #0] + 800356a: f403 7380 and.w r3, r3, #256 @ 0x100 + 800356e: 2b00 cmp r3, #0 + 8003570: d0f0 beq.n 8003554 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); - 8001e62: 687b ldr r3, [r7, #4] - 8001e64: 689b ldr r3, [r3, #8] - 8001e66: 2b01 cmp r3, #1 - 8001e68: d106 bne.n 8001e78 - 8001e6a: 4b26 ldr r3, [pc, #152] @ (8001f04 ) - 8001e6c: 6f1b ldr r3, [r3, #112] @ 0x70 - 8001e6e: 4a25 ldr r2, [pc, #148] @ (8001f04 ) - 8001e70: f043 0301 orr.w r3, r3, #1 - 8001e74: 6713 str r3, [r2, #112] @ 0x70 - 8001e76: e01c b.n 8001eb2 - 8001e78: 687b ldr r3, [r7, #4] - 8001e7a: 689b ldr r3, [r3, #8] - 8001e7c: 2b05 cmp r3, #5 - 8001e7e: d10c bne.n 8001e9a - 8001e80: 4b20 ldr r3, [pc, #128] @ (8001f04 ) - 8001e82: 6f1b ldr r3, [r3, #112] @ 0x70 - 8001e84: 4a1f ldr r2, [pc, #124] @ (8001f04 ) - 8001e86: f043 0304 orr.w r3, r3, #4 - 8001e8a: 6713 str r3, [r2, #112] @ 0x70 - 8001e8c: 4b1d ldr r3, [pc, #116] @ (8001f04 ) - 8001e8e: 6f1b ldr r3, [r3, #112] @ 0x70 - 8001e90: 4a1c ldr r2, [pc, #112] @ (8001f04 ) - 8001e92: f043 0301 orr.w r3, r3, #1 - 8001e96: 6713 str r3, [r2, #112] @ 0x70 - 8001e98: e00b b.n 8001eb2 - 8001e9a: 4b1a ldr r3, [pc, #104] @ (8001f04 ) - 8001e9c: 6f1b ldr r3, [r3, #112] @ 0x70 - 8001e9e: 4a19 ldr r2, [pc, #100] @ (8001f04 ) - 8001ea0: f023 0301 bic.w r3, r3, #1 - 8001ea4: 6713 str r3, [r2, #112] @ 0x70 - 8001ea6: 4b17 ldr r3, [pc, #92] @ (8001f04 ) - 8001ea8: 6f1b ldr r3, [r3, #112] @ 0x70 - 8001eaa: 4a16 ldr r2, [pc, #88] @ (8001f04 ) - 8001eac: f023 0304 bic.w r3, r3, #4 - 8001eb0: 6713 str r3, [r2, #112] @ 0x70 + 8003572: 687b ldr r3, [r7, #4] + 8003574: 689b ldr r3, [r3, #8] + 8003576: 2b01 cmp r3, #1 + 8003578: d106 bne.n 8003588 + 800357a: 4b26 ldr r3, [pc, #152] @ (8003614 ) + 800357c: 6f1b ldr r3, [r3, #112] @ 0x70 + 800357e: 4a25 ldr r2, [pc, #148] @ (8003614 ) + 8003580: f043 0301 orr.w r3, r3, #1 + 8003584: 6713 str r3, [r2, #112] @ 0x70 + 8003586: e01c b.n 80035c2 + 8003588: 687b ldr r3, [r7, #4] + 800358a: 689b ldr r3, [r3, #8] + 800358c: 2b05 cmp r3, #5 + 800358e: d10c bne.n 80035aa + 8003590: 4b20 ldr r3, [pc, #128] @ (8003614 ) + 8003592: 6f1b ldr r3, [r3, #112] @ 0x70 + 8003594: 4a1f ldr r2, [pc, #124] @ (8003614 ) + 8003596: f043 0304 orr.w r3, r3, #4 + 800359a: 6713 str r3, [r2, #112] @ 0x70 + 800359c: 4b1d ldr r3, [pc, #116] @ (8003614 ) + 800359e: 6f1b ldr r3, [r3, #112] @ 0x70 + 80035a0: 4a1c ldr r2, [pc, #112] @ (8003614 ) + 80035a2: f043 0301 orr.w r3, r3, #1 + 80035a6: 6713 str r3, [r2, #112] @ 0x70 + 80035a8: e00b b.n 80035c2 + 80035aa: 4b1a ldr r3, [pc, #104] @ (8003614 ) + 80035ac: 6f1b ldr r3, [r3, #112] @ 0x70 + 80035ae: 4a19 ldr r2, [pc, #100] @ (8003614 ) + 80035b0: f023 0301 bic.w r3, r3, #1 + 80035b4: 6713 str r3, [r2, #112] @ 0x70 + 80035b6: 4b17 ldr r3, [pc, #92] @ (8003614 ) + 80035b8: 6f1b ldr r3, [r3, #112] @ 0x70 + 80035ba: 4a16 ldr r2, [pc, #88] @ (8003614 ) + 80035bc: f023 0304 bic.w r3, r3, #4 + 80035c0: 6713 str r3, [r2, #112] @ 0x70 /* Check the LSE State */ if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) - 8001eb2: 687b ldr r3, [r7, #4] - 8001eb4: 689b ldr r3, [r3, #8] - 8001eb6: 2b00 cmp r3, #0 - 8001eb8: d015 beq.n 8001ee6 + 80035c2: 687b ldr r3, [r7, #4] + 80035c4: 689b ldr r3, [r3, #8] + 80035c6: 2b00 cmp r3, #0 + 80035c8: d015 beq.n 80035f6 { /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8001eba: f7fe ff39 bl 8000d30 - 8001ebe: 6138 str r0, [r7, #16] + 80035ca: f7fd ff35 bl 8001438 + 80035ce: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - 8001ec0: e00a b.n 8001ed8 + 80035d0: e00a b.n 80035e8 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - 8001ec2: f7fe ff35 bl 8000d30 - 8001ec6: 4602 mov r2, r0 - 8001ec8: 693b ldr r3, [r7, #16] - 8001eca: 1ad3 subs r3, r2, r3 - 8001ecc: f241 3288 movw r2, #5000 @ 0x1388 - 8001ed0: 4293 cmp r3, r2 - 8001ed2: d901 bls.n 8001ed8 + 80035d2: f7fd ff31 bl 8001438 + 80035d6: 4602 mov r2, r0 + 80035d8: 693b ldr r3, [r7, #16] + 80035da: 1ad3 subs r3, r2, r3 + 80035dc: f241 3288 movw r2, #5000 @ 0x1388 + 80035e0: 4293 cmp r3, r2 + 80035e2: d901 bls.n 80035e8 { return HAL_TIMEOUT; - 8001ed4: 2303 movs r3, #3 - 8001ed6: e12b b.n 8002130 + 80035e4: 2303 movs r3, #3 + 80035e6: e12b b.n 8003840 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - 8001ed8: 4b0a ldr r3, [pc, #40] @ (8001f04 ) - 8001eda: 6f1b ldr r3, [r3, #112] @ 0x70 - 8001edc: f003 0302 and.w r3, r3, #2 - 8001ee0: 2b00 cmp r3, #0 - 8001ee2: d0ee beq.n 8001ec2 - 8001ee4: e01c b.n 8001f20 + 80035e8: 4b0a ldr r3, [pc, #40] @ (8003614 ) + 80035ea: 6f1b ldr r3, [r3, #112] @ 0x70 + 80035ec: f003 0302 and.w r3, r3, #2 + 80035f0: 2b00 cmp r3, #0 + 80035f2: d0ee beq.n 80035d2 + 80035f4: e01c b.n 8003630 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); - 8001ee6: f7fe ff23 bl 8000d30 - 8001eea: 6138 str r0, [r7, #16] + 80035f6: f7fd ff1f bl 8001438 + 80035fa: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - 8001eec: e012 b.n 8001f14 + 80035fc: e012 b.n 8003624 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - 8001eee: f7fe ff1f bl 8000d30 - 8001ef2: 4602 mov r2, r0 - 8001ef4: 693b ldr r3, [r7, #16] - 8001ef6: 1ad3 subs r3, r2, r3 - 8001ef8: f241 3288 movw r2, #5000 @ 0x1388 - 8001efc: 4293 cmp r3, r2 - 8001efe: d909 bls.n 8001f14 + 80035fe: f7fd ff1b bl 8001438 + 8003602: 4602 mov r2, r0 + 8003604: 693b ldr r3, [r7, #16] + 8003606: 1ad3 subs r3, r2, r3 + 8003608: f241 3288 movw r2, #5000 @ 0x1388 + 800360c: 4293 cmp r3, r2 + 800360e: d909 bls.n 8003624 { return HAL_TIMEOUT; - 8001f00: 2303 movs r3, #3 - 8001f02: e115 b.n 8002130 - 8001f04: 40023800 .word 0x40023800 - 8001f08: 42470e80 .word 0x42470e80 - 8001f0c: 08005c98 .word 0x08005c98 - 8001f10: 40007000 .word 0x40007000 + 8003610: 2303 movs r3, #3 + 8003612: e115 b.n 8003840 + 8003614: 40023800 .word 0x40023800 + 8003618: 42470e80 .word 0x42470e80 + 800361c: 0800a1a4 .word 0x0800a1a4 + 8003620: 40007000 .word 0x40007000 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - 8001f14: 4b88 ldr r3, [pc, #544] @ (8002138 ) - 8001f16: 6f1b ldr r3, [r3, #112] @ 0x70 - 8001f18: f003 0302 and.w r3, r3, #2 - 8001f1c: 2b00 cmp r3, #0 - 8001f1e: d1e6 bne.n 8001eee + 8003624: 4b88 ldr r3, [pc, #544] @ (8003848 ) + 8003626: 6f1b ldr r3, [r3, #112] @ 0x70 + 8003628: f003 0302 and.w r3, r3, #2 + 800362c: 2b00 cmp r3, #0 + 800362e: d1e6 bne.n 80035fe } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) - 8001f20: 7dfb ldrb r3, [r7, #23] - 8001f22: 2b01 cmp r3, #1 - 8001f24: d105 bne.n 8001f32 + 8003630: 7dfb ldrb r3, [r7, #23] + 8003632: 2b01 cmp r3, #1 + 8003634: d105 bne.n 8003642 { __HAL_RCC_PWR_CLK_DISABLE(); - 8001f26: 4b84 ldr r3, [pc, #528] @ (8002138 ) - 8001f28: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001f2a: 4a83 ldr r2, [pc, #524] @ (8002138 ) - 8001f2c: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 - 8001f30: 6413 str r3, [r2, #64] @ 0x40 + 8003636: 4b84 ldr r3, [pc, #528] @ (8003848 ) + 8003638: 6c1b ldr r3, [r3, #64] @ 0x40 + 800363a: 4a83 ldr r2, [pc, #524] @ (8003848 ) + 800363c: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8003640: 6413 str r3, [r2, #64] @ 0x40 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); - 8001f32: 687b ldr r3, [r7, #4] - 8001f34: 699b ldr r3, [r3, #24] - 8001f36: 2b00 cmp r3, #0 - 8001f38: d00c beq.n 8001f54 - 8001f3a: 687b ldr r3, [r7, #4] - 8001f3c: 699b ldr r3, [r3, #24] - 8001f3e: 2b01 cmp r3, #1 - 8001f40: d008 beq.n 8001f54 - 8001f42: 687b ldr r3, [r7, #4] - 8001f44: 699b ldr r3, [r3, #24] - 8001f46: 2b02 cmp r3, #2 - 8001f48: d004 beq.n 8001f54 - 8001f4a: f240 11cd movw r1, #461 @ 0x1cd - 8001f4e: 487b ldr r0, [pc, #492] @ (800213c ) - 8001f50: f7fe fc7a bl 8000848 + 8003642: 687b ldr r3, [r7, #4] + 8003644: 699b ldr r3, [r3, #24] + 8003646: 2b00 cmp r3, #0 + 8003648: d00c beq.n 8003664 + 800364a: 687b ldr r3, [r7, #4] + 800364c: 699b ldr r3, [r3, #24] + 800364e: 2b01 cmp r3, #1 + 8003650: d008 beq.n 8003664 + 8003652: 687b ldr r3, [r7, #4] + 8003654: 699b ldr r3, [r3, #24] + 8003656: 2b02 cmp r3, #2 + 8003658: d004 beq.n 8003664 + 800365a: f240 11cd movw r1, #461 @ 0x1cd + 800365e: 487b ldr r0, [pc, #492] @ (800384c ) + 8003660: f7fd fb68 bl 8000d34 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) - 8001f54: 687b ldr r3, [r7, #4] - 8001f56: 699b ldr r3, [r3, #24] - 8001f58: 2b00 cmp r3, #0 - 8001f5a: f000 80e8 beq.w 800212e + 8003664: 687b ldr r3, [r7, #4] + 8003666: 699b ldr r3, [r3, #24] + 8003668: 2b00 cmp r3, #0 + 800366a: f000 80e8 beq.w 800383e { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) - 8001f5e: 4b76 ldr r3, [pc, #472] @ (8002138 ) - 8001f60: 689b ldr r3, [r3, #8] - 8001f62: f003 030c and.w r3, r3, #12 - 8001f66: 2b08 cmp r3, #8 - 8001f68: f000 80a9 beq.w 80020be + 800366e: 4b76 ldr r3, [pc, #472] @ (8003848 ) + 8003670: 689b ldr r3, [r3, #8] + 8003672: f003 030c and.w r3, r3, #12 + 8003676: 2b08 cmp r3, #8 + 8003678: f000 80a9 beq.w 80037ce { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) - 8001f6c: 687b ldr r3, [r7, #4] - 8001f6e: 699b ldr r3, [r3, #24] - 8001f70: 2b02 cmp r3, #2 - 8001f72: f040 808d bne.w 8002090 + 800367c: 687b ldr r3, [r7, #4] + 800367e: 699b ldr r3, [r3, #24] + 8003680: 2b02 cmp r3, #2 + 8003682: f040 808d bne.w 80037a0 { /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); - 8001f76: 687b ldr r3, [r7, #4] - 8001f78: 69db ldr r3, [r3, #28] - 8001f7a: 2b00 cmp r3, #0 - 8001f7c: d009 beq.n 8001f92 - 8001f7e: 687b ldr r3, [r7, #4] - 8001f80: 69db ldr r3, [r3, #28] - 8001f82: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 - 8001f86: d004 beq.n 8001f92 - 8001f88: f44f 71eb mov.w r1, #470 @ 0x1d6 - 8001f8c: 486b ldr r0, [pc, #428] @ (800213c ) - 8001f8e: f7fe fc5b bl 8000848 + 8003686: 687b ldr r3, [r7, #4] + 8003688: 69db ldr r3, [r3, #28] + 800368a: 2b00 cmp r3, #0 + 800368c: d009 beq.n 80036a2 + 800368e: 687b ldr r3, [r7, #4] + 8003690: 69db ldr r3, [r3, #28] + 8003692: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 + 8003696: d004 beq.n 80036a2 + 8003698: f44f 71eb mov.w r1, #470 @ 0x1d6 + 800369c: 486b ldr r0, [pc, #428] @ (800384c ) + 800369e: f7fd fb49 bl 8000d34 assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); - 8001f92: 687b ldr r3, [r7, #4] - 8001f94: 6a1b ldr r3, [r3, #32] - 8001f96: 2b01 cmp r3, #1 - 8001f98: d903 bls.n 8001fa2 - 8001f9a: 687b ldr r3, [r7, #4] - 8001f9c: 6a1b ldr r3, [r3, #32] - 8001f9e: 2b3f cmp r3, #63 @ 0x3f - 8001fa0: d904 bls.n 8001fac - 8001fa2: f240 11d7 movw r1, #471 @ 0x1d7 - 8001fa6: 4865 ldr r0, [pc, #404] @ (800213c ) - 8001fa8: f7fe fc4e bl 8000848 + 80036a2: 687b ldr r3, [r7, #4] + 80036a4: 6a1b ldr r3, [r3, #32] + 80036a6: 2b01 cmp r3, #1 + 80036a8: d903 bls.n 80036b2 + 80036aa: 687b ldr r3, [r7, #4] + 80036ac: 6a1b ldr r3, [r3, #32] + 80036ae: 2b3f cmp r3, #63 @ 0x3f + 80036b0: d904 bls.n 80036bc + 80036b2: f240 11d7 movw r1, #471 @ 0x1d7 + 80036b6: 4865 ldr r0, [pc, #404] @ (800384c ) + 80036b8: f7fd fb3c bl 8000d34 assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); - 8001fac: 687b ldr r3, [r7, #4] - 8001fae: 6a5b ldr r3, [r3, #36] @ 0x24 - 8001fb0: 2b31 cmp r3, #49 @ 0x31 - 8001fb2: d904 bls.n 8001fbe - 8001fb4: 687b ldr r3, [r7, #4] - 8001fb6: 6a5b ldr r3, [r3, #36] @ 0x24 - 8001fb8: f5b3 7fd8 cmp.w r3, #432 @ 0x1b0 - 8001fbc: d904 bls.n 8001fc8 - 8001fbe: f44f 71ec mov.w r1, #472 @ 0x1d8 - 8001fc2: 485e ldr r0, [pc, #376] @ (800213c ) - 8001fc4: f7fe fc40 bl 8000848 + 80036bc: 687b ldr r3, [r7, #4] + 80036be: 6a5b ldr r3, [r3, #36] @ 0x24 + 80036c0: 2b31 cmp r3, #49 @ 0x31 + 80036c2: d904 bls.n 80036ce + 80036c4: 687b ldr r3, [r7, #4] + 80036c6: 6a5b ldr r3, [r3, #36] @ 0x24 + 80036c8: f5b3 7fd8 cmp.w r3, #432 @ 0x1b0 + 80036cc: d904 bls.n 80036d8 + 80036ce: f44f 71ec mov.w r1, #472 @ 0x1d8 + 80036d2: 485e ldr r0, [pc, #376] @ (800384c ) + 80036d4: f7fd fb2e bl 8000d34 assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); - 8001fc8: 687b ldr r3, [r7, #4] - 8001fca: 6a9b ldr r3, [r3, #40] @ 0x28 - 8001fcc: 2b02 cmp r3, #2 - 8001fce: d010 beq.n 8001ff2 - 8001fd0: 687b ldr r3, [r7, #4] - 8001fd2: 6a9b ldr r3, [r3, #40] @ 0x28 - 8001fd4: 2b04 cmp r3, #4 - 8001fd6: d00c beq.n 8001ff2 - 8001fd8: 687b ldr r3, [r7, #4] - 8001fda: 6a9b ldr r3, [r3, #40] @ 0x28 - 8001fdc: 2b06 cmp r3, #6 - 8001fde: d008 beq.n 8001ff2 - 8001fe0: 687b ldr r3, [r7, #4] - 8001fe2: 6a9b ldr r3, [r3, #40] @ 0x28 - 8001fe4: 2b08 cmp r3, #8 - 8001fe6: d004 beq.n 8001ff2 - 8001fe8: f240 11d9 movw r1, #473 @ 0x1d9 - 8001fec: 4853 ldr r0, [pc, #332] @ (800213c ) - 8001fee: f7fe fc2b bl 8000848 + 80036d8: 687b ldr r3, [r7, #4] + 80036da: 6a9b ldr r3, [r3, #40] @ 0x28 + 80036dc: 2b02 cmp r3, #2 + 80036de: d010 beq.n 8003702 + 80036e0: 687b ldr r3, [r7, #4] + 80036e2: 6a9b ldr r3, [r3, #40] @ 0x28 + 80036e4: 2b04 cmp r3, #4 + 80036e6: d00c beq.n 8003702 + 80036e8: 687b ldr r3, [r7, #4] + 80036ea: 6a9b ldr r3, [r3, #40] @ 0x28 + 80036ec: 2b06 cmp r3, #6 + 80036ee: d008 beq.n 8003702 + 80036f0: 687b ldr r3, [r7, #4] + 80036f2: 6a9b ldr r3, [r3, #40] @ 0x28 + 80036f4: 2b08 cmp r3, #8 + 80036f6: d004 beq.n 8003702 + 80036f8: f240 11d9 movw r1, #473 @ 0x1d9 + 80036fc: 4853 ldr r0, [pc, #332] @ (800384c ) + 80036fe: f7fd fb19 bl 8000d34 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); - 8001ff2: 687b ldr r3, [r7, #4] - 8001ff4: 6adb ldr r3, [r3, #44] @ 0x2c - 8001ff6: 2b01 cmp r3, #1 - 8001ff8: d903 bls.n 8002002 - 8001ffa: 687b ldr r3, [r7, #4] - 8001ffc: 6adb ldr r3, [r3, #44] @ 0x2c - 8001ffe: 2b0f cmp r3, #15 - 8002000: d904 bls.n 800200c - 8002002: f44f 71ed mov.w r1, #474 @ 0x1da - 8002006: 484d ldr r0, [pc, #308] @ (800213c ) - 8002008: f7fe fc1e bl 8000848 + 8003702: 687b ldr r3, [r7, #4] + 8003704: 6adb ldr r3, [r3, #44] @ 0x2c + 8003706: 2b01 cmp r3, #1 + 8003708: d903 bls.n 8003712 + 800370a: 687b ldr r3, [r7, #4] + 800370c: 6adb ldr r3, [r3, #44] @ 0x2c + 800370e: 2b0f cmp r3, #15 + 8003710: d904 bls.n 800371c + 8003712: f44f 71ed mov.w r1, #474 @ 0x1da + 8003716: 484d ldr r0, [pc, #308] @ (800384c ) + 8003718: f7fd fb0c bl 8000d34 /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - 800200c: 4b4c ldr r3, [pc, #304] @ (8002140 ) - 800200e: 2200 movs r2, #0 - 8002010: 601a str r2, [r3, #0] + 800371c: 4b4c ldr r3, [pc, #304] @ (8003850 ) + 800371e: 2200 movs r2, #0 + 8003720: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8002012: f7fe fe8d bl 8000d30 - 8002016: 6138 str r0, [r7, #16] + 8003722: f7fd fe89 bl 8001438 + 8003726: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 8002018: e008 b.n 800202c + 8003728: e008 b.n 800373c { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - 800201a: f7fe fe89 bl 8000d30 - 800201e: 4602 mov r2, r0 - 8002020: 693b ldr r3, [r7, #16] - 8002022: 1ad3 subs r3, r2, r3 - 8002024: 2b02 cmp r3, #2 - 8002026: d901 bls.n 800202c + 800372a: f7fd fe85 bl 8001438 + 800372e: 4602 mov r2, r0 + 8003730: 693b ldr r3, [r7, #16] + 8003732: 1ad3 subs r3, r2, r3 + 8003734: 2b02 cmp r3, #2 + 8003736: d901 bls.n 800373c { return HAL_TIMEOUT; - 8002028: 2303 movs r3, #3 - 800202a: e081 b.n 8002130 + 8003738: 2303 movs r3, #3 + 800373a: e081 b.n 8003840 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 800202c: 4b42 ldr r3, [pc, #264] @ (8002138 ) - 800202e: 681b ldr r3, [r3, #0] - 8002030: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 - 8002034: 2b00 cmp r3, #0 - 8002036: d1f0 bne.n 800201a + 800373c: 4b42 ldr r3, [pc, #264] @ (8003848 ) + 800373e: 681b ldr r3, [r3, #0] + 8003740: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8003744: 2b00 cmp r3, #0 + 8003746: d1f0 bne.n 800372a } } /* Configure the main PLL clock source, multiplication and division factors. */ WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ - 8002038: 687b ldr r3, [r7, #4] - 800203a: 69da ldr r2, [r3, #28] - 800203c: 687b ldr r3, [r7, #4] - 800203e: 6a1b ldr r3, [r3, #32] - 8002040: 431a orrs r2, r3 - 8002042: 687b ldr r3, [r7, #4] - 8002044: 6a5b ldr r3, [r3, #36] @ 0x24 - 8002046: 019b lsls r3, r3, #6 - 8002048: 431a orrs r2, r3 - 800204a: 687b ldr r3, [r7, #4] - 800204c: 6a9b ldr r3, [r3, #40] @ 0x28 - 800204e: 085b lsrs r3, r3, #1 - 8002050: 3b01 subs r3, #1 - 8002052: 041b lsls r3, r3, #16 - 8002054: 431a orrs r2, r3 - 8002056: 687b ldr r3, [r7, #4] - 8002058: 6adb ldr r3, [r3, #44] @ 0x2c - 800205a: 061b lsls r3, r3, #24 - 800205c: 4936 ldr r1, [pc, #216] @ (8002138 ) - 800205e: 4313 orrs r3, r2 - 8002060: 604b str r3, [r1, #4] + 8003748: 687b ldr r3, [r7, #4] + 800374a: 69da ldr r2, [r3, #28] + 800374c: 687b ldr r3, [r7, #4] + 800374e: 6a1b ldr r3, [r3, #32] + 8003750: 431a orrs r2, r3 + 8003752: 687b ldr r3, [r7, #4] + 8003754: 6a5b ldr r3, [r3, #36] @ 0x24 + 8003756: 019b lsls r3, r3, #6 + 8003758: 431a orrs r2, r3 + 800375a: 687b ldr r3, [r7, #4] + 800375c: 6a9b ldr r3, [r3, #40] @ 0x28 + 800375e: 085b lsrs r3, r3, #1 + 8003760: 3b01 subs r3, #1 + 8003762: 041b lsls r3, r3, #16 + 8003764: 431a orrs r2, r3 + 8003766: 687b ldr r3, [r7, #4] + 8003768: 6adb ldr r3, [r3, #44] @ 0x2c + 800376a: 061b lsls r3, r3, #24 + 800376c: 4936 ldr r1, [pc, #216] @ (8003848 ) + 800376e: 4313 orrs r3, r2 + 8003770: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLM | \ (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); - 8002062: 4b37 ldr r3, [pc, #220] @ (8002140 ) - 8002064: 2201 movs r2, #1 - 8002066: 601a str r2, [r3, #0] + 8003772: 4b37 ldr r3, [pc, #220] @ (8003850 ) + 8003774: 2201 movs r2, #1 + 8003776: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8002068: f7fe fe62 bl 8000d30 - 800206c: 6138 str r0, [r7, #16] + 8003778: f7fd fe5e bl 8001438 + 800377c: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - 800206e: e008 b.n 8002082 + 800377e: e008 b.n 8003792 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - 8002070: f7fe fe5e bl 8000d30 - 8002074: 4602 mov r2, r0 - 8002076: 693b ldr r3, [r7, #16] - 8002078: 1ad3 subs r3, r2, r3 - 800207a: 2b02 cmp r3, #2 - 800207c: d901 bls.n 8002082 + 8003780: f7fd fe5a bl 8001438 + 8003784: 4602 mov r2, r0 + 8003786: 693b ldr r3, [r7, #16] + 8003788: 1ad3 subs r3, r2, r3 + 800378a: 2b02 cmp r3, #2 + 800378c: d901 bls.n 8003792 { return HAL_TIMEOUT; - 800207e: 2303 movs r3, #3 - 8002080: e056 b.n 8002130 + 800378e: 2303 movs r3, #3 + 8003790: e056 b.n 8003840 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - 8002082: 4b2d ldr r3, [pc, #180] @ (8002138 ) - 8002084: 681b ldr r3, [r3, #0] - 8002086: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 - 800208a: 2b00 cmp r3, #0 - 800208c: d0f0 beq.n 8002070 - 800208e: e04e b.n 800212e + 8003792: 4b2d ldr r3, [pc, #180] @ (8003848 ) + 8003794: 681b ldr r3, [r3, #0] + 8003796: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 800379a: 2b00 cmp r3, #0 + 800379c: d0f0 beq.n 8003780 + 800379e: e04e b.n 800383e } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - 8002090: 4b2b ldr r3, [pc, #172] @ (8002140 ) - 8002092: 2200 movs r2, #0 - 8002094: 601a str r2, [r3, #0] + 80037a0: 4b2b ldr r3, [pc, #172] @ (8003850 ) + 80037a2: 2200 movs r2, #0 + 80037a4: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8002096: f7fe fe4b bl 8000d30 - 800209a: 6138 str r0, [r7, #16] + 80037a6: f7fd fe47 bl 8001438 + 80037aa: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 800209c: e008 b.n 80020b0 + 80037ac: e008 b.n 80037c0 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - 800209e: f7fe fe47 bl 8000d30 - 80020a2: 4602 mov r2, r0 - 80020a4: 693b ldr r3, [r7, #16] - 80020a6: 1ad3 subs r3, r2, r3 - 80020a8: 2b02 cmp r3, #2 - 80020aa: d901 bls.n 80020b0 + 80037ae: f7fd fe43 bl 8001438 + 80037b2: 4602 mov r2, r0 + 80037b4: 693b ldr r3, [r7, #16] + 80037b6: 1ad3 subs r3, r2, r3 + 80037b8: 2b02 cmp r3, #2 + 80037ba: d901 bls.n 80037c0 { return HAL_TIMEOUT; - 80020ac: 2303 movs r3, #3 - 80020ae: e03f b.n 8002130 + 80037bc: 2303 movs r3, #3 + 80037be: e03f b.n 8003840 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 80020b0: 4b21 ldr r3, [pc, #132] @ (8002138 ) - 80020b2: 681b ldr r3, [r3, #0] - 80020b4: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 - 80020b8: 2b00 cmp r3, #0 - 80020ba: d1f0 bne.n 800209e - 80020bc: e037 b.n 800212e + 80037c0: 4b21 ldr r3, [pc, #132] @ (8003848 ) + 80037c2: 681b ldr r3, [r3, #0] + 80037c4: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 80037c8: 2b00 cmp r3, #0 + 80037ca: d1f0 bne.n 80037ae + 80037cc: e037 b.n 800383e } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) - 80020be: 687b ldr r3, [r7, #4] - 80020c0: 699b ldr r3, [r3, #24] - 80020c2: 2b01 cmp r3, #1 - 80020c4: d101 bne.n 80020ca + 80037ce: 687b ldr r3, [r7, #4] + 80037d0: 699b ldr r3, [r3, #24] + 80037d2: 2b01 cmp r3, #1 + 80037d4: d101 bne.n 80037da { return HAL_ERROR; - 80020c6: 2301 movs r3, #1 - 80020c8: e032 b.n 8002130 + 80037d6: 2301 movs r3, #1 + 80037d8: e032 b.n 8003840 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->PLLCFGR; - 80020ca: 4b1b ldr r3, [pc, #108] @ (8002138 ) - 80020cc: 685b ldr r3, [r3, #4] - 80020ce: 60fb str r3, [r7, #12] + 80037da: 4b1b ldr r3, [pc, #108] @ (8003848 ) + 80037dc: 685b ldr r3, [r3, #4] + 80037de: 60fb str r3, [r7, #12] (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) #else if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || - 80020d0: 687b ldr r3, [r7, #4] - 80020d2: 699b ldr r3, [r3, #24] - 80020d4: 2b01 cmp r3, #1 - 80020d6: d028 beq.n 800212a + 80037e0: 687b ldr r3, [r7, #4] + 80037e2: 699b ldr r3, [r3, #24] + 80037e4: 2b01 cmp r3, #1 + 80037e6: d028 beq.n 800383a (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - 80020d8: 68fb ldr r3, [r7, #12] - 80020da: f403 0280 and.w r2, r3, #4194304 @ 0x400000 - 80020de: 687b ldr r3, [r7, #4] - 80020e0: 69db ldr r3, [r3, #28] + 80037e8: 68fb ldr r3, [r7, #12] + 80037ea: f403 0280 and.w r2, r3, #4194304 @ 0x400000 + 80037ee: 687b ldr r3, [r7, #4] + 80037f0: 69db ldr r3, [r3, #28] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || - 80020e2: 429a cmp r2, r3 - 80020e4: d121 bne.n 800212a + 80037f2: 429a cmp r2, r3 + 80037f4: d121 bne.n 800383a (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || - 80020e6: 68fb ldr r3, [r7, #12] - 80020e8: f003 023f and.w r2, r3, #63 @ 0x3f - 80020ec: 687b ldr r3, [r7, #4] - 80020ee: 6a1b ldr r3, [r3, #32] + 80037f6: 68fb ldr r3, [r7, #12] + 80037f8: f003 023f and.w r2, r3, #63 @ 0x3f + 80037fc: 687b ldr r3, [r7, #4] + 80037fe: 6a1b ldr r3, [r3, #32] (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - 80020f0: 429a cmp r2, r3 - 80020f2: d11a bne.n 800212a + 8003800: 429a cmp r2, r3 + 8003802: d11a bne.n 800383a (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || - 80020f4: 68fa ldr r2, [r7, #12] - 80020f6: f647 73c0 movw r3, #32704 @ 0x7fc0 - 80020fa: 4013 ands r3, r2 - 80020fc: 687a ldr r2, [r7, #4] - 80020fe: 6a52 ldr r2, [r2, #36] @ 0x24 - 8002100: 0192 lsls r2, r2, #6 + 8003804: 68fa ldr r2, [r7, #12] + 8003806: f647 73c0 movw r3, #32704 @ 0x7fc0 + 800380a: 4013 ands r3, r2 + 800380c: 687a ldr r2, [r7, #4] + 800380e: 6a52 ldr r2, [r2, #36] @ 0x24 + 8003810: 0192 lsls r2, r2, #6 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || - 8002102: 4293 cmp r3, r2 - 8002104: d111 bne.n 800212a + 8003812: 4293 cmp r3, r2 + 8003814: d111 bne.n 800383a (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || - 8002106: 68fb ldr r3, [r7, #12] - 8002108: f403 3240 and.w r2, r3, #196608 @ 0x30000 - 800210c: 687b ldr r3, [r7, #4] - 800210e: 6a9b ldr r3, [r3, #40] @ 0x28 - 8002110: 085b lsrs r3, r3, #1 - 8002112: 3b01 subs r3, #1 - 8002114: 041b lsls r3, r3, #16 + 8003816: 68fb ldr r3, [r7, #12] + 8003818: f403 3240 and.w r2, r3, #196608 @ 0x30000 + 800381c: 687b ldr r3, [r7, #4] + 800381e: 6a9b ldr r3, [r3, #40] @ 0x28 + 8003820: 085b lsrs r3, r3, #1 + 8003822: 3b01 subs r3, #1 + 8003824: 041b lsls r3, r3, #16 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || - 8002116: 429a cmp r2, r3 - 8002118: d107 bne.n 800212a + 8003826: 429a cmp r2, r3 + 8003828: d107 bne.n 800383a (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) - 800211a: 68fb ldr r3, [r7, #12] - 800211c: f003 6270 and.w r2, r3, #251658240 @ 0xf000000 - 8002120: 687b ldr r3, [r7, #4] - 8002122: 6adb ldr r3, [r3, #44] @ 0x2c - 8002124: 061b lsls r3, r3, #24 + 800382a: 68fb ldr r3, [r7, #12] + 800382c: f003 6270 and.w r2, r3, #251658240 @ 0xf000000 + 8003830: 687b ldr r3, [r7, #4] + 8003832: 6adb ldr r3, [r3, #44] @ 0x2c + 8003834: 061b lsls r3, r3, #24 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || - 8002126: 429a cmp r2, r3 - 8002128: d001 beq.n 800212e + 8003836: 429a cmp r2, r3 + 8003838: d001 beq.n 800383e #endif /* RCC_PLLCFGR_PLLR */ { return HAL_ERROR; - 800212a: 2301 movs r3, #1 - 800212c: e000 b.n 8002130 + 800383a: 2301 movs r3, #1 + 800383c: e000 b.n 8003840 } } } } return HAL_OK; - 800212e: 2300 movs r3, #0 + 800383e: 2300 movs r3, #0 } - 8002130: 4618 mov r0, r3 - 8002132: 3718 adds r7, #24 - 8002134: 46bd mov sp, r7 - 8002136: bd80 pop {r7, pc} - 8002138: 40023800 .word 0x40023800 - 800213c: 08005c98 .word 0x08005c98 - 8002140: 42470060 .word 0x42470060 + 8003840: 4618 mov r0, r3 + 8003842: 3718 adds r7, #24 + 8003844: 46bd mov sp, r7 + 8003846: bd80 pop {r7, pc} + 8003848: 40023800 .word 0x40023800 + 800384c: 0800a1a4 .word 0x0800a1a4 + 8003850: 42470060 .word 0x42470060 -08002144 : +08003854 : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { - 8002144: b580 push {r7, lr} - 8002146: b084 sub sp, #16 - 8002148: af00 add r7, sp, #0 - 800214a: 6078 str r0, [r7, #4] - 800214c: 6039 str r1, [r7, #0] + 8003854: b580 push {r7, lr} + 8003856: b084 sub sp, #16 + 8003858: af00 add r7, sp, #0 + 800385a: 6078 str r0, [r7, #4] + 800385c: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) - 800214e: 687b ldr r3, [r7, #4] - 8002150: 2b00 cmp r3, #0 - 8002152: d101 bne.n 8002158 + 800385e: 687b ldr r3, [r7, #4] + 8003860: 2b00 cmp r3, #0 + 8003862: d101 bne.n 8003868 { return HAL_ERROR; - 8002154: 2301 movs r3, #1 - 8002156: e174 b.n 8002442 + 8003864: 2301 movs r3, #1 + 8003866: e174 b.n 8003b52 } /* Check the parameters */ assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); - 8002158: 687b ldr r3, [r7, #4] - 800215a: 681b ldr r3, [r3, #0] - 800215c: 2b00 cmp r3, #0 - 800215e: d003 beq.n 8002168 - 8002160: 687b ldr r3, [r7, #4] - 8002162: 681b ldr r3, [r3, #0] - 8002164: 2b0f cmp r3, #15 - 8002166: d904 bls.n 8002172 - 8002168: f240 215a movw r1, #602 @ 0x25a - 800216c: 487b ldr r0, [pc, #492] @ (800235c ) - 800216e: f7fe fb6b bl 8000848 + 8003868: 687b ldr r3, [r7, #4] + 800386a: 681b ldr r3, [r3, #0] + 800386c: 2b00 cmp r3, #0 + 800386e: d003 beq.n 8003878 + 8003870: 687b ldr r3, [r7, #4] + 8003872: 681b ldr r3, [r3, #0] + 8003874: 2b0f cmp r3, #15 + 8003876: d904 bls.n 8003882 + 8003878: f240 215a movw r1, #602 @ 0x25a + 800387c: 487b ldr r0, [pc, #492] @ (8003a6c ) + 800387e: f7fd fa59 bl 8000d34 assert_param(IS_FLASH_LATENCY(FLatency)); - 8002172: 683b ldr r3, [r7, #0] - 8002174: 2b00 cmp r3, #0 - 8002176: d019 beq.n 80021ac - 8002178: 683b ldr r3, [r7, #0] - 800217a: 2b01 cmp r3, #1 - 800217c: d016 beq.n 80021ac - 800217e: 683b ldr r3, [r7, #0] - 8002180: 2b02 cmp r3, #2 - 8002182: d013 beq.n 80021ac - 8002184: 683b ldr r3, [r7, #0] - 8002186: 2b03 cmp r3, #3 - 8002188: d010 beq.n 80021ac - 800218a: 683b ldr r3, [r7, #0] - 800218c: 2b04 cmp r3, #4 - 800218e: d00d beq.n 80021ac - 8002190: 683b ldr r3, [r7, #0] - 8002192: 2b05 cmp r3, #5 - 8002194: d00a beq.n 80021ac - 8002196: 683b ldr r3, [r7, #0] - 8002198: 2b06 cmp r3, #6 - 800219a: d007 beq.n 80021ac - 800219c: 683b ldr r3, [r7, #0] - 800219e: 2b07 cmp r3, #7 - 80021a0: d004 beq.n 80021ac - 80021a2: f240 215b movw r1, #603 @ 0x25b - 80021a6: 486d ldr r0, [pc, #436] @ (800235c ) - 80021a8: f7fe fb4e bl 8000848 + 8003882: 683b ldr r3, [r7, #0] + 8003884: 2b00 cmp r3, #0 + 8003886: d019 beq.n 80038bc + 8003888: 683b ldr r3, [r7, #0] + 800388a: 2b01 cmp r3, #1 + 800388c: d016 beq.n 80038bc + 800388e: 683b ldr r3, [r7, #0] + 8003890: 2b02 cmp r3, #2 + 8003892: d013 beq.n 80038bc + 8003894: 683b ldr r3, [r7, #0] + 8003896: 2b03 cmp r3, #3 + 8003898: d010 beq.n 80038bc + 800389a: 683b ldr r3, [r7, #0] + 800389c: 2b04 cmp r3, #4 + 800389e: d00d beq.n 80038bc + 80038a0: 683b ldr r3, [r7, #0] + 80038a2: 2b05 cmp r3, #5 + 80038a4: d00a beq.n 80038bc + 80038a6: 683b ldr r3, [r7, #0] + 80038a8: 2b06 cmp r3, #6 + 80038aa: d007 beq.n 80038bc + 80038ac: 683b ldr r3, [r7, #0] + 80038ae: 2b07 cmp r3, #7 + 80038b0: d004 beq.n 80038bc + 80038b2: f240 215b movw r1, #603 @ 0x25b + 80038b6: 486d ldr r0, [pc, #436] @ (8003a6c ) + 80038b8: f7fd fa3c bl 8000d34 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) - 80021ac: 4b6c ldr r3, [pc, #432] @ (8002360 ) - 80021ae: 681b ldr r3, [r3, #0] - 80021b0: f003 0307 and.w r3, r3, #7 - 80021b4: 683a ldr r2, [r7, #0] - 80021b6: 429a cmp r2, r3 - 80021b8: d90c bls.n 80021d4 + 80038bc: 4b6c ldr r3, [pc, #432] @ (8003a70 ) + 80038be: 681b ldr r3, [r3, #0] + 80038c0: f003 0307 and.w r3, r3, #7 + 80038c4: 683a ldr r2, [r7, #0] + 80038c6: 429a cmp r2, r3 + 80038c8: d90c bls.n 80038e4 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - 80021ba: 4b69 ldr r3, [pc, #420] @ (8002360 ) - 80021bc: 683a ldr r2, [r7, #0] - 80021be: b2d2 uxtb r2, r2 - 80021c0: 701a strb r2, [r3, #0] + 80038ca: 4b69 ldr r3, [pc, #420] @ (8003a70 ) + 80038cc: 683a ldr r2, [r7, #0] + 80038ce: b2d2 uxtb r2, r2 + 80038d0: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) - 80021c2: 4b67 ldr r3, [pc, #412] @ (8002360 ) - 80021c4: 681b ldr r3, [r3, #0] - 80021c6: f003 0307 and.w r3, r3, #7 - 80021ca: 683a ldr r2, [r7, #0] - 80021cc: 429a cmp r2, r3 - 80021ce: d001 beq.n 80021d4 + 80038d2: 4b67 ldr r3, [pc, #412] @ (8003a70 ) + 80038d4: 681b ldr r3, [r3, #0] + 80038d6: f003 0307 and.w r3, r3, #7 + 80038da: 683a ldr r2, [r7, #0] + 80038dc: 429a cmp r2, r3 + 80038de: d001 beq.n 80038e4 { return HAL_ERROR; - 80021d0: 2301 movs r3, #1 - 80021d2: e136 b.n 8002442 + 80038e0: 2301 movs r3, #1 + 80038e2: e136 b.n 8003b52 } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - 80021d4: 687b ldr r3, [r7, #4] - 80021d6: 681b ldr r3, [r3, #0] - 80021d8: f003 0302 and.w r3, r3, #2 - 80021dc: 2b00 cmp r3, #0 - 80021de: d049 beq.n 8002274 + 80038e4: 687b ldr r3, [r7, #4] + 80038e6: 681b ldr r3, [r3, #0] + 80038e8: f003 0302 and.w r3, r3, #2 + 80038ec: 2b00 cmp r3, #0 + 80038ee: d049 beq.n 8003984 { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - 80021e0: 687b ldr r3, [r7, #4] - 80021e2: 681b ldr r3, [r3, #0] - 80021e4: f003 0304 and.w r3, r3, #4 - 80021e8: 2b00 cmp r3, #0 - 80021ea: d005 beq.n 80021f8 + 80038f0: 687b ldr r3, [r7, #4] + 80038f2: 681b ldr r3, [r3, #0] + 80038f4: f003 0304 and.w r3, r3, #4 + 80038f8: 2b00 cmp r3, #0 + 80038fa: d005 beq.n 8003908 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); - 80021ec: 4b5d ldr r3, [pc, #372] @ (8002364 ) - 80021ee: 689b ldr r3, [r3, #8] - 80021f0: 4a5c ldr r2, [pc, #368] @ (8002364 ) - 80021f2: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00 - 80021f6: 6093 str r3, [r2, #8] + 80038fc: 4b5d ldr r3, [pc, #372] @ (8003a74 ) + 80038fe: 689b ldr r3, [r3, #8] + 8003900: 4a5c ldr r2, [pc, #368] @ (8003a74 ) + 8003902: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00 + 8003906: 6093 str r3, [r2, #8] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - 80021f8: 687b ldr r3, [r7, #4] - 80021fa: 681b ldr r3, [r3, #0] - 80021fc: f003 0308 and.w r3, r3, #8 - 8002200: 2b00 cmp r3, #0 - 8002202: d005 beq.n 8002210 + 8003908: 687b ldr r3, [r7, #4] + 800390a: 681b ldr r3, [r3, #0] + 800390c: f003 0308 and.w r3, r3, #8 + 8003910: 2b00 cmp r3, #0 + 8003912: d005 beq.n 8003920 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); - 8002204: 4b57 ldr r3, [pc, #348] @ (8002364 ) - 8002206: 689b ldr r3, [r3, #8] - 8002208: 4a56 ldr r2, [pc, #344] @ (8002364 ) - 800220a: f443 4360 orr.w r3, r3, #57344 @ 0xe000 - 800220e: 6093 str r3, [r2, #8] + 8003914: 4b57 ldr r3, [pc, #348] @ (8003a74 ) + 8003916: 689b ldr r3, [r3, #8] + 8003918: 4a56 ldr r2, [pc, #344] @ (8003a74 ) + 800391a: f443 4360 orr.w r3, r3, #57344 @ 0xe000 + 800391e: 6093 str r3, [r2, #8] } assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); - 8002210: 687b ldr r3, [r7, #4] - 8002212: 689b ldr r3, [r3, #8] - 8002214: 2b00 cmp r3, #0 - 8002216: d024 beq.n 8002262 - 8002218: 687b ldr r3, [r7, #4] - 800221a: 689b ldr r3, [r3, #8] - 800221c: 2b80 cmp r3, #128 @ 0x80 - 800221e: d020 beq.n 8002262 - 8002220: 687b ldr r3, [r7, #4] - 8002222: 689b ldr r3, [r3, #8] - 8002224: 2b90 cmp r3, #144 @ 0x90 - 8002226: d01c beq.n 8002262 - 8002228: 687b ldr r3, [r7, #4] - 800222a: 689b ldr r3, [r3, #8] - 800222c: 2ba0 cmp r3, #160 @ 0xa0 - 800222e: d018 beq.n 8002262 - 8002230: 687b ldr r3, [r7, #4] - 8002232: 689b ldr r3, [r3, #8] - 8002234: 2bb0 cmp r3, #176 @ 0xb0 - 8002236: d014 beq.n 8002262 - 8002238: 687b ldr r3, [r7, #4] - 800223a: 689b ldr r3, [r3, #8] - 800223c: 2bc0 cmp r3, #192 @ 0xc0 - 800223e: d010 beq.n 8002262 - 8002240: 687b ldr r3, [r7, #4] - 8002242: 689b ldr r3, [r3, #8] - 8002244: 2bd0 cmp r3, #208 @ 0xd0 - 8002246: d00c beq.n 8002262 - 8002248: 687b ldr r3, [r7, #4] - 800224a: 689b ldr r3, [r3, #8] - 800224c: 2be0 cmp r3, #224 @ 0xe0 - 800224e: d008 beq.n 8002262 - 8002250: 687b ldr r3, [r7, #4] - 8002252: 689b ldr r3, [r3, #8] - 8002254: 2bf0 cmp r3, #240 @ 0xf0 - 8002256: d004 beq.n 8002262 - 8002258: f240 217e movw r1, #638 @ 0x27e - 800225c: 483f ldr r0, [pc, #252] @ (800235c ) - 800225e: f7fe faf3 bl 8000848 + 8003920: 687b ldr r3, [r7, #4] + 8003922: 689b ldr r3, [r3, #8] + 8003924: 2b00 cmp r3, #0 + 8003926: d024 beq.n 8003972 + 8003928: 687b ldr r3, [r7, #4] + 800392a: 689b ldr r3, [r3, #8] + 800392c: 2b80 cmp r3, #128 @ 0x80 + 800392e: d020 beq.n 8003972 + 8003930: 687b ldr r3, [r7, #4] + 8003932: 689b ldr r3, [r3, #8] + 8003934: 2b90 cmp r3, #144 @ 0x90 + 8003936: d01c beq.n 8003972 + 8003938: 687b ldr r3, [r7, #4] + 800393a: 689b ldr r3, [r3, #8] + 800393c: 2ba0 cmp r3, #160 @ 0xa0 + 800393e: d018 beq.n 8003972 + 8003940: 687b ldr r3, [r7, #4] + 8003942: 689b ldr r3, [r3, #8] + 8003944: 2bb0 cmp r3, #176 @ 0xb0 + 8003946: d014 beq.n 8003972 + 8003948: 687b ldr r3, [r7, #4] + 800394a: 689b ldr r3, [r3, #8] + 800394c: 2bc0 cmp r3, #192 @ 0xc0 + 800394e: d010 beq.n 8003972 + 8003950: 687b ldr r3, [r7, #4] + 8003952: 689b ldr r3, [r3, #8] + 8003954: 2bd0 cmp r3, #208 @ 0xd0 + 8003956: d00c beq.n 8003972 + 8003958: 687b ldr r3, [r7, #4] + 800395a: 689b ldr r3, [r3, #8] + 800395c: 2be0 cmp r3, #224 @ 0xe0 + 800395e: d008 beq.n 8003972 + 8003960: 687b ldr r3, [r7, #4] + 8003962: 689b ldr r3, [r3, #8] + 8003964: 2bf0 cmp r3, #240 @ 0xf0 + 8003966: d004 beq.n 8003972 + 8003968: f240 217e movw r1, #638 @ 0x27e + 800396c: 483f ldr r0, [pc, #252] @ (8003a6c ) + 800396e: f7fd f9e1 bl 8000d34 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - 8002262: 4b40 ldr r3, [pc, #256] @ (8002364 ) - 8002264: 689b ldr r3, [r3, #8] - 8002266: f023 02f0 bic.w r2, r3, #240 @ 0xf0 - 800226a: 687b ldr r3, [r7, #4] - 800226c: 689b ldr r3, [r3, #8] - 800226e: 493d ldr r1, [pc, #244] @ (8002364 ) - 8002270: 4313 orrs r3, r2 - 8002272: 608b str r3, [r1, #8] + 8003972: 4b40 ldr r3, [pc, #256] @ (8003a74 ) + 8003974: 689b ldr r3, [r3, #8] + 8003976: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 800397a: 687b ldr r3, [r7, #4] + 800397c: 689b ldr r3, [r3, #8] + 800397e: 493d ldr r1, [pc, #244] @ (8003a74 ) + 8003980: 4313 orrs r3, r2 + 8003982: 608b str r3, [r1, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - 8002274: 687b ldr r3, [r7, #4] - 8002276: 681b ldr r3, [r3, #0] - 8002278: f003 0301 and.w r3, r3, #1 - 800227c: 2b00 cmp r3, #0 - 800227e: d059 beq.n 8002334 + 8003984: 687b ldr r3, [r7, #4] + 8003986: 681b ldr r3, [r3, #0] + 8003988: f003 0301 and.w r3, r3, #1 + 800398c: 2b00 cmp r3, #0 + 800398e: d059 beq.n 8003a44 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - 8002280: 687b ldr r3, [r7, #4] - 8002282: 685b ldr r3, [r3, #4] - 8002284: 2b00 cmp r3, #0 - 8002286: d010 beq.n 80022aa - 8002288: 687b ldr r3, [r7, #4] - 800228a: 685b ldr r3, [r3, #4] - 800228c: 2b01 cmp r3, #1 - 800228e: d00c beq.n 80022aa - 8002290: 687b ldr r3, [r7, #4] - 8002292: 685b ldr r3, [r3, #4] - 8002294: 2b02 cmp r3, #2 - 8002296: d008 beq.n 80022aa - 8002298: 687b ldr r3, [r7, #4] - 800229a: 685b ldr r3, [r3, #4] - 800229c: 2b03 cmp r3, #3 - 800229e: d004 beq.n 80022aa - 80022a0: f240 2185 movw r1, #645 @ 0x285 - 80022a4: 482d ldr r0, [pc, #180] @ (800235c ) - 80022a6: f7fe facf bl 8000848 + 8003990: 687b ldr r3, [r7, #4] + 8003992: 685b ldr r3, [r3, #4] + 8003994: 2b00 cmp r3, #0 + 8003996: d010 beq.n 80039ba + 8003998: 687b ldr r3, [r7, #4] + 800399a: 685b ldr r3, [r3, #4] + 800399c: 2b01 cmp r3, #1 + 800399e: d00c beq.n 80039ba + 80039a0: 687b ldr r3, [r7, #4] + 80039a2: 685b ldr r3, [r3, #4] + 80039a4: 2b02 cmp r3, #2 + 80039a6: d008 beq.n 80039ba + 80039a8: 687b ldr r3, [r7, #4] + 80039aa: 685b ldr r3, [r3, #4] + 80039ac: 2b03 cmp r3, #3 + 80039ae: d004 beq.n 80039ba + 80039b0: f240 2185 movw r1, #645 @ 0x285 + 80039b4: 482d ldr r0, [pc, #180] @ (8003a6c ) + 80039b6: f7fd f9bd bl 8000d34 /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - 80022aa: 687b ldr r3, [r7, #4] - 80022ac: 685b ldr r3, [r3, #4] - 80022ae: 2b01 cmp r3, #1 - 80022b0: d107 bne.n 80022c2 + 80039ba: 687b ldr r3, [r7, #4] + 80039bc: 685b ldr r3, [r3, #4] + 80039be: 2b01 cmp r3, #1 + 80039c0: d107 bne.n 80039d2 { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - 80022b2: 4b2c ldr r3, [pc, #176] @ (8002364 ) - 80022b4: 681b ldr r3, [r3, #0] - 80022b6: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 80022ba: 2b00 cmp r3, #0 - 80022bc: d119 bne.n 80022f2 + 80039c2: 4b2c ldr r3, [pc, #176] @ (8003a74 ) + 80039c4: 681b ldr r3, [r3, #0] + 80039c6: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80039ca: 2b00 cmp r3, #0 + 80039cc: d119 bne.n 8003a02 { return HAL_ERROR; - 80022be: 2301 movs r3, #1 - 80022c0: e0bf b.n 8002442 + 80039ce: 2301 movs r3, #1 + 80039d0: e0bf b.n 8003b52 } } /* PLL is selected as System Clock Source */ else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || - 80022c2: 687b ldr r3, [r7, #4] - 80022c4: 685b ldr r3, [r3, #4] - 80022c6: 2b02 cmp r3, #2 - 80022c8: d003 beq.n 80022d2 + 80039d2: 687b ldr r3, [r7, #4] + 80039d4: 685b ldr r3, [r3, #4] + 80039d6: 2b02 cmp r3, #2 + 80039d8: d003 beq.n 80039e2 (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)) - 80022ca: 687b ldr r3, [r7, #4] - 80022cc: 685b ldr r3, [r3, #4] + 80039da: 687b ldr r3, [r7, #4] + 80039dc: 685b ldr r3, [r3, #4] else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || - 80022ce: 2b03 cmp r3, #3 - 80022d0: d107 bne.n 80022e2 + 80039de: 2b03 cmp r3, #3 + 80039e0: d107 bne.n 80039f2 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - 80022d2: 4b24 ldr r3, [pc, #144] @ (8002364 ) - 80022d4: 681b ldr r3, [r3, #0] - 80022d6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 - 80022da: 2b00 cmp r3, #0 - 80022dc: d109 bne.n 80022f2 + 80039e2: 4b24 ldr r3, [pc, #144] @ (8003a74 ) + 80039e4: 681b ldr r3, [r3, #0] + 80039e6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 80039ea: 2b00 cmp r3, #0 + 80039ec: d109 bne.n 8003a02 { return HAL_ERROR; - 80022de: 2301 movs r3, #1 - 80022e0: e0af b.n 8002442 + 80039ee: 2301 movs r3, #1 + 80039f0: e0af b.n 8003b52 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - 80022e2: 4b20 ldr r3, [pc, #128] @ (8002364 ) - 80022e4: 681b ldr r3, [r3, #0] - 80022e6: f003 0302 and.w r3, r3, #2 - 80022ea: 2b00 cmp r3, #0 - 80022ec: d101 bne.n 80022f2 + 80039f2: 4b20 ldr r3, [pc, #128] @ (8003a74 ) + 80039f4: 681b ldr r3, [r3, #0] + 80039f6: f003 0302 and.w r3, r3, #2 + 80039fa: 2b00 cmp r3, #0 + 80039fc: d101 bne.n 8003a02 { return HAL_ERROR; - 80022ee: 2301 movs r3, #1 - 80022f0: e0a7 b.n 8002442 + 80039fe: 2301 movs r3, #1 + 8003a00: e0a7 b.n 8003b52 } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); - 80022f2: 4b1c ldr r3, [pc, #112] @ (8002364 ) - 80022f4: 689b ldr r3, [r3, #8] - 80022f6: f023 0203 bic.w r2, r3, #3 - 80022fa: 687b ldr r3, [r7, #4] - 80022fc: 685b ldr r3, [r3, #4] - 80022fe: 4919 ldr r1, [pc, #100] @ (8002364 ) - 8002300: 4313 orrs r3, r2 - 8002302: 608b str r3, [r1, #8] + 8003a02: 4b1c ldr r3, [pc, #112] @ (8003a74 ) + 8003a04: 689b ldr r3, [r3, #8] + 8003a06: f023 0203 bic.w r2, r3, #3 + 8003a0a: 687b ldr r3, [r7, #4] + 8003a0c: 685b ldr r3, [r3, #4] + 8003a0e: 4919 ldr r1, [pc, #100] @ (8003a74 ) + 8003a10: 4313 orrs r3, r2 + 8003a12: 608b str r3, [r1, #8] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8002304: f7fe fd14 bl 8000d30 - 8002308: 60f8 str r0, [r7, #12] + 8003a14: f7fd fd10 bl 8001438 + 8003a18: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - 800230a: e00a b.n 8002322 + 8003a1a: e00a b.n 8003a32 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - 800230c: f7fe fd10 bl 8000d30 - 8002310: 4602 mov r2, r0 - 8002312: 68fb ldr r3, [r7, #12] - 8002314: 1ad3 subs r3, r2, r3 - 8002316: f241 3288 movw r2, #5000 @ 0x1388 - 800231a: 4293 cmp r3, r2 - 800231c: d901 bls.n 8002322 + 8003a1c: f7fd fd0c bl 8001438 + 8003a20: 4602 mov r2, r0 + 8003a22: 68fb ldr r3, [r7, #12] + 8003a24: 1ad3 subs r3, r2, r3 + 8003a26: f241 3288 movw r2, #5000 @ 0x1388 + 8003a2a: 4293 cmp r3, r2 + 8003a2c: d901 bls.n 8003a32 { return HAL_TIMEOUT; - 800231e: 2303 movs r3, #3 - 8002320: e08f b.n 8002442 + 8003a2e: 2303 movs r3, #3 + 8003a30: e08f b.n 8003b52 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - 8002322: 4b10 ldr r3, [pc, #64] @ (8002364 ) - 8002324: 689b ldr r3, [r3, #8] - 8002326: f003 020c and.w r2, r3, #12 - 800232a: 687b ldr r3, [r7, #4] - 800232c: 685b ldr r3, [r3, #4] - 800232e: 009b lsls r3, r3, #2 - 8002330: 429a cmp r2, r3 - 8002332: d1eb bne.n 800230c + 8003a32: 4b10 ldr r3, [pc, #64] @ (8003a74 ) + 8003a34: 689b ldr r3, [r3, #8] + 8003a36: f003 020c and.w r2, r3, #12 + 8003a3a: 687b ldr r3, [r7, #4] + 8003a3c: 685b ldr r3, [r3, #4] + 8003a3e: 009b lsls r3, r3, #2 + 8003a40: 429a cmp r2, r3 + 8003a42: d1eb bne.n 8003a1c } } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) - 8002334: 4b0a ldr r3, [pc, #40] @ (8002360 ) - 8002336: 681b ldr r3, [r3, #0] - 8002338: f003 0307 and.w r3, r3, #7 - 800233c: 683a ldr r2, [r7, #0] - 800233e: 429a cmp r2, r3 - 8002340: d212 bcs.n 8002368 + 8003a44: 4b0a ldr r3, [pc, #40] @ (8003a70 ) + 8003a46: 681b ldr r3, [r3, #0] + 8003a48: f003 0307 and.w r3, r3, #7 + 8003a4c: 683a ldr r2, [r7, #0] + 8003a4e: 429a cmp r2, r3 + 8003a50: d212 bcs.n 8003a78 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - 8002342: 4b07 ldr r3, [pc, #28] @ (8002360 ) - 8002344: 683a ldr r2, [r7, #0] - 8002346: b2d2 uxtb r2, r2 - 8002348: 701a strb r2, [r3, #0] + 8003a52: 4b07 ldr r3, [pc, #28] @ (8003a70 ) + 8003a54: 683a ldr r2, [r7, #0] + 8003a56: b2d2 uxtb r2, r2 + 8003a58: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) - 800234a: 4b05 ldr r3, [pc, #20] @ (8002360 ) - 800234c: 681b ldr r3, [r3, #0] - 800234e: f003 0307 and.w r3, r3, #7 - 8002352: 683a ldr r2, [r7, #0] - 8002354: 429a cmp r2, r3 - 8002356: d007 beq.n 8002368 + 8003a5a: 4b05 ldr r3, [pc, #20] @ (8003a70 ) + 8003a5c: 681b ldr r3, [r3, #0] + 8003a5e: f003 0307 and.w r3, r3, #7 + 8003a62: 683a ldr r2, [r7, #0] + 8003a64: 429a cmp r2, r3 + 8003a66: d007 beq.n 8003a78 { return HAL_ERROR; - 8002358: 2301 movs r3, #1 - 800235a: e072 b.n 8002442 - 800235c: 08005c98 .word 0x08005c98 - 8002360: 40023c00 .word 0x40023c00 - 8002364: 40023800 .word 0x40023800 + 8003a68: 2301 movs r3, #1 + 8003a6a: e072 b.n 8003b52 + 8003a6c: 0800a1a4 .word 0x0800a1a4 + 8003a70: 40023c00 .word 0x40023c00 + 8003a74: 40023800 .word 0x40023800 } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - 8002368: 687b ldr r3, [r7, #4] - 800236a: 681b ldr r3, [r3, #0] - 800236c: f003 0304 and.w r3, r3, #4 - 8002370: 2b00 cmp r3, #0 - 8002372: d025 beq.n 80023c0 + 8003a78: 687b ldr r3, [r7, #4] + 8003a7a: 681b ldr r3, [r3, #0] + 8003a7c: f003 0304 and.w r3, r3, #4 + 8003a80: 2b00 cmp r3, #0 + 8003a82: d025 beq.n 8003ad0 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); - 8002374: 687b ldr r3, [r7, #4] - 8002376: 68db ldr r3, [r3, #12] - 8002378: 2b00 cmp r3, #0 - 800237a: d018 beq.n 80023ae - 800237c: 687b ldr r3, [r7, #4] - 800237e: 68db ldr r3, [r3, #12] - 8002380: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 - 8002384: d013 beq.n 80023ae - 8002386: 687b ldr r3, [r7, #4] - 8002388: 68db ldr r3, [r3, #12] - 800238a: f5b3 5fa0 cmp.w r3, #5120 @ 0x1400 - 800238e: d00e beq.n 80023ae - 8002390: 687b ldr r3, [r7, #4] - 8002392: 68db ldr r3, [r3, #12] - 8002394: f5b3 5fc0 cmp.w r3, #6144 @ 0x1800 - 8002398: d009 beq.n 80023ae - 800239a: 687b ldr r3, [r7, #4] - 800239c: 68db ldr r3, [r3, #12] - 800239e: f5b3 5fe0 cmp.w r3, #7168 @ 0x1c00 - 80023a2: d004 beq.n 80023ae - 80023a4: f240 21c3 movw r1, #707 @ 0x2c3 - 80023a8: 4828 ldr r0, [pc, #160] @ (800244c ) - 80023aa: f7fe fa4d bl 8000848 + 8003a84: 687b ldr r3, [r7, #4] + 8003a86: 68db ldr r3, [r3, #12] + 8003a88: 2b00 cmp r3, #0 + 8003a8a: d018 beq.n 8003abe + 8003a8c: 687b ldr r3, [r7, #4] + 8003a8e: 68db ldr r3, [r3, #12] + 8003a90: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 8003a94: d013 beq.n 8003abe + 8003a96: 687b ldr r3, [r7, #4] + 8003a98: 68db ldr r3, [r3, #12] + 8003a9a: f5b3 5fa0 cmp.w r3, #5120 @ 0x1400 + 8003a9e: d00e beq.n 8003abe + 8003aa0: 687b ldr r3, [r7, #4] + 8003aa2: 68db ldr r3, [r3, #12] + 8003aa4: f5b3 5fc0 cmp.w r3, #6144 @ 0x1800 + 8003aa8: d009 beq.n 8003abe + 8003aaa: 687b ldr r3, [r7, #4] + 8003aac: 68db ldr r3, [r3, #12] + 8003aae: f5b3 5fe0 cmp.w r3, #7168 @ 0x1c00 + 8003ab2: d004 beq.n 8003abe + 8003ab4: f240 21c3 movw r1, #707 @ 0x2c3 + 8003ab8: 4828 ldr r0, [pc, #160] @ (8003b5c ) + 8003aba: f7fd f93b bl 8000d34 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); - 80023ae: 4b28 ldr r3, [pc, #160] @ (8002450 ) - 80023b0: 689b ldr r3, [r3, #8] - 80023b2: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00 - 80023b6: 687b ldr r3, [r7, #4] - 80023b8: 68db ldr r3, [r3, #12] - 80023ba: 4925 ldr r1, [pc, #148] @ (8002450 ) - 80023bc: 4313 orrs r3, r2 - 80023be: 608b str r3, [r1, #8] + 8003abe: 4b28 ldr r3, [pc, #160] @ (8003b60 ) + 8003ac0: 689b ldr r3, [r3, #8] + 8003ac2: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00 + 8003ac6: 687b ldr r3, [r7, #4] + 8003ac8: 68db ldr r3, [r3, #12] + 8003aca: 4925 ldr r1, [pc, #148] @ (8003b60 ) + 8003acc: 4313 orrs r3, r2 + 8003ace: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - 80023c0: 687b ldr r3, [r7, #4] - 80023c2: 681b ldr r3, [r3, #0] - 80023c4: f003 0308 and.w r3, r3, #8 - 80023c8: 2b00 cmp r3, #0 - 80023ca: d026 beq.n 800241a + 8003ad0: 687b ldr r3, [r7, #4] + 8003ad2: 681b ldr r3, [r3, #0] + 8003ad4: f003 0308 and.w r3, r3, #8 + 8003ad8: 2b00 cmp r3, #0 + 8003ada: d026 beq.n 8003b2a { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); - 80023cc: 687b ldr r3, [r7, #4] - 80023ce: 691b ldr r3, [r3, #16] - 80023d0: 2b00 cmp r3, #0 - 80023d2: d018 beq.n 8002406 - 80023d4: 687b ldr r3, [r7, #4] - 80023d6: 691b ldr r3, [r3, #16] - 80023d8: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 - 80023dc: d013 beq.n 8002406 - 80023de: 687b ldr r3, [r7, #4] - 80023e0: 691b ldr r3, [r3, #16] - 80023e2: f5b3 5fa0 cmp.w r3, #5120 @ 0x1400 - 80023e6: d00e beq.n 8002406 - 80023e8: 687b ldr r3, [r7, #4] - 80023ea: 691b ldr r3, [r3, #16] - 80023ec: f5b3 5fc0 cmp.w r3, #6144 @ 0x1800 - 80023f0: d009 beq.n 8002406 - 80023f2: 687b ldr r3, [r7, #4] - 80023f4: 691b ldr r3, [r3, #16] - 80023f6: f5b3 5fe0 cmp.w r3, #7168 @ 0x1c00 - 80023fa: d004 beq.n 8002406 - 80023fc: f240 21ca movw r1, #714 @ 0x2ca - 8002400: 4812 ldr r0, [pc, #72] @ (800244c ) - 8002402: f7fe fa21 bl 8000848 + 8003adc: 687b ldr r3, [r7, #4] + 8003ade: 691b ldr r3, [r3, #16] + 8003ae0: 2b00 cmp r3, #0 + 8003ae2: d018 beq.n 8003b16 + 8003ae4: 687b ldr r3, [r7, #4] + 8003ae6: 691b ldr r3, [r3, #16] + 8003ae8: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 8003aec: d013 beq.n 8003b16 + 8003aee: 687b ldr r3, [r7, #4] + 8003af0: 691b ldr r3, [r3, #16] + 8003af2: f5b3 5fa0 cmp.w r3, #5120 @ 0x1400 + 8003af6: d00e beq.n 8003b16 + 8003af8: 687b ldr r3, [r7, #4] + 8003afa: 691b ldr r3, [r3, #16] + 8003afc: f5b3 5fc0 cmp.w r3, #6144 @ 0x1800 + 8003b00: d009 beq.n 8003b16 + 8003b02: 687b ldr r3, [r7, #4] + 8003b04: 691b ldr r3, [r3, #16] + 8003b06: f5b3 5fe0 cmp.w r3, #7168 @ 0x1c00 + 8003b0a: d004 beq.n 8003b16 + 8003b0c: f240 21ca movw r1, #714 @ 0x2ca + 8003b10: 4812 ldr r0, [pc, #72] @ (8003b5c ) + 8003b12: f7fd f90f bl 8000d34 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); - 8002406: 4b12 ldr r3, [pc, #72] @ (8002450 ) - 8002408: 689b ldr r3, [r3, #8] - 800240a: f423 4260 bic.w r2, r3, #57344 @ 0xe000 - 800240e: 687b ldr r3, [r7, #4] - 8002410: 691b ldr r3, [r3, #16] - 8002412: 00db lsls r3, r3, #3 - 8002414: 490e ldr r1, [pc, #56] @ (8002450 ) - 8002416: 4313 orrs r3, r2 - 8002418: 608b str r3, [r1, #8] + 8003b16: 4b12 ldr r3, [pc, #72] @ (8003b60 ) + 8003b18: 689b ldr r3, [r3, #8] + 8003b1a: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 8003b1e: 687b ldr r3, [r7, #4] + 8003b20: 691b ldr r3, [r3, #16] + 8003b22: 00db lsls r3, r3, #3 + 8003b24: 490e ldr r1, [pc, #56] @ (8003b60 ) + 8003b26: 4313 orrs r3, r2 + 8003b28: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; - 800241a: f000 f821 bl 8002460 - 800241e: 4602 mov r2, r0 - 8002420: 4b0b ldr r3, [pc, #44] @ (8002450 ) - 8002422: 689b ldr r3, [r3, #8] - 8002424: 091b lsrs r3, r3, #4 - 8002426: f003 030f and.w r3, r3, #15 - 800242a: 490a ldr r1, [pc, #40] @ (8002454 ) - 800242c: 5ccb ldrb r3, [r1, r3] - 800242e: fa22 f303 lsr.w r3, r2, r3 - 8002432: 4a09 ldr r2, [pc, #36] @ (8002458 ) - 8002434: 6013 str r3, [r2, #0] + 8003b2a: f000 f821 bl 8003b70 + 8003b2e: 4602 mov r2, r0 + 8003b30: 4b0b ldr r3, [pc, #44] @ (8003b60 ) + 8003b32: 689b ldr r3, [r3, #8] + 8003b34: 091b lsrs r3, r3, #4 + 8003b36: f003 030f and.w r3, r3, #15 + 8003b3a: 490a ldr r1, [pc, #40] @ (8003b64 ) + 8003b3c: 5ccb ldrb r3, [r1, r3] + 8003b3e: fa22 f303 lsr.w r3, r2, r3 + 8003b42: 4a09 ldr r2, [pc, #36] @ (8003b68 ) + 8003b44: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings */ HAL_InitTick(uwTickPrio); - 8002436: 4b09 ldr r3, [pc, #36] @ (800245c ) - 8002438: 681b ldr r3, [r3, #0] - 800243a: 4618 mov r0, r3 - 800243c: f7fe fadc bl 80009f8 + 8003b46: 4b09 ldr r3, [pc, #36] @ (8003b6c ) + 8003b48: 681b ldr r3, [r3, #0] + 8003b4a: 4618 mov r0, r3 + 8003b4c: f7fd faba bl 80010c4 return HAL_OK; - 8002440: 2300 movs r3, #0 + 8003b50: 2300 movs r3, #0 } - 8002442: 4618 mov r0, r3 - 8002444: 3710 adds r7, #16 - 8002446: 46bd mov sp, r7 - 8002448: bd80 pop {r7, pc} - 800244a: bf00 nop - 800244c: 08005c98 .word 0x08005c98 - 8002450: 40023800 .word 0x40023800 - 8002454: 08005d44 .word 0x08005d44 - 8002458: 20000000 .word 0x20000000 - 800245c: 20000004 .word 0x20000004 + 8003b52: 4618 mov r0, r3 + 8003b54: 3710 adds r7, #16 + 8003b56: 46bd mov sp, r7 + 8003b58: bd80 pop {r7, pc} + 8003b5a: bf00 nop + 8003b5c: 0800a1a4 .word 0x0800a1a4 + 8003b60: 40023800 .word 0x40023800 + 8003b64: 0800a2a0 .word 0x0800a2a0 + 8003b68: 20000018 .word 0x20000018 + 8003b6c: 2000001c .word 0x2000001c -08002460 : +08003b70 : * * * @retval SYSCLK frequency */ __weak uint32_t HAL_RCC_GetSysClockFreq(void) { - 8002460: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} - 8002464: b090 sub sp, #64 @ 0x40 - 8002466: af00 add r7, sp, #0 + 8003b70: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} + 8003b74: b090 sub sp, #64 @ 0x40 + 8003b76: af00 add r7, sp, #0 uint32_t pllm = 0U; - 8002468: 2300 movs r3, #0 - 800246a: 637b str r3, [r7, #52] @ 0x34 + 8003b78: 2300 movs r3, #0 + 8003b7a: 637b str r3, [r7, #52] @ 0x34 uint32_t pllvco = 0U; - 800246c: 2300 movs r3, #0 - 800246e: 63fb str r3, [r7, #60] @ 0x3c + 8003b7c: 2300 movs r3, #0 + 8003b7e: 63fb str r3, [r7, #60] @ 0x3c uint32_t pllp = 0U; - 8002470: 2300 movs r3, #0 - 8002472: 633b str r3, [r7, #48] @ 0x30 + 8003b80: 2300 movs r3, #0 + 8003b82: 633b str r3, [r7, #48] @ 0x30 uint32_t sysclockfreq = 0U; - 8002474: 2300 movs r3, #0 - 8002476: 63bb str r3, [r7, #56] @ 0x38 + 8003b84: 2300 movs r3, #0 + 8003b86: 63bb str r3, [r7, #56] @ 0x38 /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) - 8002478: 4b58 ldr r3, [pc, #352] @ (80025dc ) - 800247a: 689b ldr r3, [r3, #8] - 800247c: f003 030c and.w r3, r3, #12 - 8002480: 2b08 cmp r3, #8 - 8002482: d00d beq.n 80024a0 - 8002484: 2b08 cmp r3, #8 - 8002486: f200 80a0 bhi.w 80025ca - 800248a: 2b00 cmp r3, #0 - 800248c: d002 beq.n 8002494 - 800248e: 2b04 cmp r3, #4 - 8002490: d003 beq.n 800249a - 8002492: e09a b.n 80025ca + 8003b88: 4b58 ldr r3, [pc, #352] @ (8003cec ) + 8003b8a: 689b ldr r3, [r3, #8] + 8003b8c: f003 030c and.w r3, r3, #12 + 8003b90: 2b08 cmp r3, #8 + 8003b92: d00d beq.n 8003bb0 + 8003b94: 2b08 cmp r3, #8 + 8003b96: f200 80a0 bhi.w 8003cda + 8003b9a: 2b00 cmp r3, #0 + 8003b9c: d002 beq.n 8003ba4 + 8003b9e: 2b04 cmp r3, #4 + 8003ba0: d003 beq.n 8003baa + 8003ba2: e09a b.n 8003cda { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ { sysclockfreq = HSI_VALUE; - 8002494: 4b52 ldr r3, [pc, #328] @ (80025e0 ) - 8002496: 63bb str r3, [r7, #56] @ 0x38 + 8003ba4: 4b52 ldr r3, [pc, #328] @ (8003cf0 ) + 8003ba6: 63bb str r3, [r7, #56] @ 0x38 break; - 8002498: e09a b.n 80025d0 + 8003ba8: e09a b.n 8003ce0 } case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ { sysclockfreq = HSE_VALUE; - 800249a: 4b52 ldr r3, [pc, #328] @ (80025e4 ) - 800249c: 63bb str r3, [r7, #56] @ 0x38 + 8003baa: 4b52 ldr r3, [pc, #328] @ (8003cf4 ) + 8003bac: 63bb str r3, [r7, #56] @ 0x38 break; - 800249e: e097 b.n 80025d0 + 8003bae: e097 b.n 8003ce0 } case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLP */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - 80024a0: 4b4e ldr r3, [pc, #312] @ (80025dc ) - 80024a2: 685b ldr r3, [r3, #4] - 80024a4: f003 033f and.w r3, r3, #63 @ 0x3f - 80024a8: 637b str r3, [r7, #52] @ 0x34 + 8003bb0: 4b4e ldr r3, [pc, #312] @ (8003cec ) + 8003bb2: 685b ldr r3, [r3, #4] + 8003bb4: f003 033f and.w r3, r3, #63 @ 0x3f + 8003bb8: 637b str r3, [r7, #52] @ 0x34 if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) - 80024aa: 4b4c ldr r3, [pc, #304] @ (80025dc ) - 80024ac: 685b ldr r3, [r3, #4] - 80024ae: f403 0380 and.w r3, r3, #4194304 @ 0x400000 - 80024b2: 2b00 cmp r3, #0 - 80024b4: d027 beq.n 8002506 + 8003bba: 4b4c ldr r3, [pc, #304] @ (8003cec ) + 8003bbc: 685b ldr r3, [r3, #4] + 8003bbe: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 8003bc2: 2b00 cmp r3, #0 + 8003bc4: d027 beq.n 8003c16 { /* HSE used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); - 80024b6: 4b49 ldr r3, [pc, #292] @ (80025dc ) - 80024b8: 685b ldr r3, [r3, #4] - 80024ba: 099b lsrs r3, r3, #6 - 80024bc: 2200 movs r2, #0 - 80024be: 623b str r3, [r7, #32] - 80024c0: 627a str r2, [r7, #36] @ 0x24 - 80024c2: 6a3b ldr r3, [r7, #32] - 80024c4: f3c3 0008 ubfx r0, r3, #0, #9 - 80024c8: 2100 movs r1, #0 - 80024ca: 4b46 ldr r3, [pc, #280] @ (80025e4 ) - 80024cc: fb03 f201 mul.w r2, r3, r1 - 80024d0: 2300 movs r3, #0 - 80024d2: fb00 f303 mul.w r3, r0, r3 - 80024d6: 4413 add r3, r2 - 80024d8: 4a42 ldr r2, [pc, #264] @ (80025e4 ) - 80024da: fba0 2102 umull r2, r1, r0, r2 - 80024de: 62f9 str r1, [r7, #44] @ 0x2c - 80024e0: 62ba str r2, [r7, #40] @ 0x28 - 80024e2: 6afa ldr r2, [r7, #44] @ 0x2c - 80024e4: 4413 add r3, r2 - 80024e6: 62fb str r3, [r7, #44] @ 0x2c - 80024e8: 6b7b ldr r3, [r7, #52] @ 0x34 - 80024ea: 2200 movs r2, #0 - 80024ec: 61bb str r3, [r7, #24] - 80024ee: 61fa str r2, [r7, #28] - 80024f0: e9d7 2306 ldrd r2, r3, [r7, #24] - 80024f4: e9d7 010a ldrd r0, r1, [r7, #40] @ 0x28 - 80024f8: f7fd fe6a bl 80001d0 <__aeabi_uldivmod> - 80024fc: 4602 mov r2, r0 - 80024fe: 460b mov r3, r1 - 8002500: 4613 mov r3, r2 - 8002502: 63fb str r3, [r7, #60] @ 0x3c - 8002504: e053 b.n 80025ae + 8003bc6: 4b49 ldr r3, [pc, #292] @ (8003cec ) + 8003bc8: 685b ldr r3, [r3, #4] + 8003bca: 099b lsrs r3, r3, #6 + 8003bcc: 2200 movs r2, #0 + 8003bce: 623b str r3, [r7, #32] + 8003bd0: 627a str r2, [r7, #36] @ 0x24 + 8003bd2: 6a3b ldr r3, [r7, #32] + 8003bd4: f3c3 0008 ubfx r0, r3, #0, #9 + 8003bd8: 2100 movs r1, #0 + 8003bda: 4b46 ldr r3, [pc, #280] @ (8003cf4 ) + 8003bdc: fb03 f201 mul.w r2, r3, r1 + 8003be0: 2300 movs r3, #0 + 8003be2: fb00 f303 mul.w r3, r0, r3 + 8003be6: 4413 add r3, r2 + 8003be8: 4a42 ldr r2, [pc, #264] @ (8003cf4 ) + 8003bea: fba0 2102 umull r2, r1, r0, r2 + 8003bee: 62f9 str r1, [r7, #44] @ 0x2c + 8003bf0: 62ba str r2, [r7, #40] @ 0x28 + 8003bf2: 6afa ldr r2, [r7, #44] @ 0x2c + 8003bf4: 4413 add r3, r2 + 8003bf6: 62fb str r3, [r7, #44] @ 0x2c + 8003bf8: 6b7b ldr r3, [r7, #52] @ 0x34 + 8003bfa: 2200 movs r2, #0 + 8003bfc: 61bb str r3, [r7, #24] + 8003bfe: 61fa str r2, [r7, #28] + 8003c00: e9d7 2306 ldrd r2, r3, [r7, #24] + 8003c04: e9d7 010a ldrd r0, r1, [r7, #40] @ 0x28 + 8003c08: f7fc fae2 bl 80001d0 <__aeabi_uldivmod> + 8003c0c: 4602 mov r2, r0 + 8003c0e: 460b mov r3, r1 + 8003c10: 4613 mov r3, r2 + 8003c12: 63fb str r3, [r7, #60] @ 0x3c + 8003c14: e053 b.n 8003cbe } else { /* HSI used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); - 8002506: 4b35 ldr r3, [pc, #212] @ (80025dc ) - 8002508: 685b ldr r3, [r3, #4] - 800250a: 099b lsrs r3, r3, #6 - 800250c: 2200 movs r2, #0 - 800250e: 613b str r3, [r7, #16] - 8002510: 617a str r2, [r7, #20] - 8002512: 693b ldr r3, [r7, #16] - 8002514: f3c3 0a08 ubfx sl, r3, #0, #9 - 8002518: f04f 0b00 mov.w fp, #0 - 800251c: 4652 mov r2, sl - 800251e: 465b mov r3, fp - 8002520: f04f 0000 mov.w r0, #0 - 8002524: f04f 0100 mov.w r1, #0 - 8002528: 0159 lsls r1, r3, #5 - 800252a: ea41 61d2 orr.w r1, r1, r2, lsr #27 - 800252e: 0150 lsls r0, r2, #5 - 8002530: 4602 mov r2, r0 - 8002532: 460b mov r3, r1 - 8002534: ebb2 080a subs.w r8, r2, sl - 8002538: eb63 090b sbc.w r9, r3, fp - 800253c: f04f 0200 mov.w r2, #0 - 8002540: f04f 0300 mov.w r3, #0 - 8002544: ea4f 1389 mov.w r3, r9, lsl #6 - 8002548: ea43 6398 orr.w r3, r3, r8, lsr #26 - 800254c: ea4f 1288 mov.w r2, r8, lsl #6 - 8002550: ebb2 0408 subs.w r4, r2, r8 - 8002554: eb63 0509 sbc.w r5, r3, r9 - 8002558: f04f 0200 mov.w r2, #0 - 800255c: f04f 0300 mov.w r3, #0 - 8002560: 00eb lsls r3, r5, #3 - 8002562: ea43 7354 orr.w r3, r3, r4, lsr #29 - 8002566: 00e2 lsls r2, r4, #3 - 8002568: 4614 mov r4, r2 - 800256a: 461d mov r5, r3 - 800256c: eb14 030a adds.w r3, r4, sl - 8002570: 603b str r3, [r7, #0] - 8002572: eb45 030b adc.w r3, r5, fp - 8002576: 607b str r3, [r7, #4] - 8002578: f04f 0200 mov.w r2, #0 - 800257c: f04f 0300 mov.w r3, #0 - 8002580: e9d7 4500 ldrd r4, r5, [r7] - 8002584: 4629 mov r1, r5 - 8002586: 028b lsls r3, r1, #10 - 8002588: 4621 mov r1, r4 - 800258a: ea43 5391 orr.w r3, r3, r1, lsr #22 - 800258e: 4621 mov r1, r4 - 8002590: 028a lsls r2, r1, #10 - 8002592: 4610 mov r0, r2 - 8002594: 4619 mov r1, r3 - 8002596: 6b7b ldr r3, [r7, #52] @ 0x34 - 8002598: 2200 movs r2, #0 - 800259a: 60bb str r3, [r7, #8] - 800259c: 60fa str r2, [r7, #12] - 800259e: e9d7 2302 ldrd r2, r3, [r7, #8] - 80025a2: f7fd fe15 bl 80001d0 <__aeabi_uldivmod> - 80025a6: 4602 mov r2, r0 - 80025a8: 460b mov r3, r1 - 80025aa: 4613 mov r3, r2 - 80025ac: 63fb str r3, [r7, #60] @ 0x3c + 8003c16: 4b35 ldr r3, [pc, #212] @ (8003cec ) + 8003c18: 685b ldr r3, [r3, #4] + 8003c1a: 099b lsrs r3, r3, #6 + 8003c1c: 2200 movs r2, #0 + 8003c1e: 613b str r3, [r7, #16] + 8003c20: 617a str r2, [r7, #20] + 8003c22: 693b ldr r3, [r7, #16] + 8003c24: f3c3 0a08 ubfx sl, r3, #0, #9 + 8003c28: f04f 0b00 mov.w fp, #0 + 8003c2c: 4652 mov r2, sl + 8003c2e: 465b mov r3, fp + 8003c30: f04f 0000 mov.w r0, #0 + 8003c34: f04f 0100 mov.w r1, #0 + 8003c38: 0159 lsls r1, r3, #5 + 8003c3a: ea41 61d2 orr.w r1, r1, r2, lsr #27 + 8003c3e: 0150 lsls r0, r2, #5 + 8003c40: 4602 mov r2, r0 + 8003c42: 460b mov r3, r1 + 8003c44: ebb2 080a subs.w r8, r2, sl + 8003c48: eb63 090b sbc.w r9, r3, fp + 8003c4c: f04f 0200 mov.w r2, #0 + 8003c50: f04f 0300 mov.w r3, #0 + 8003c54: ea4f 1389 mov.w r3, r9, lsl #6 + 8003c58: ea43 6398 orr.w r3, r3, r8, lsr #26 + 8003c5c: ea4f 1288 mov.w r2, r8, lsl #6 + 8003c60: ebb2 0408 subs.w r4, r2, r8 + 8003c64: eb63 0509 sbc.w r5, r3, r9 + 8003c68: f04f 0200 mov.w r2, #0 + 8003c6c: f04f 0300 mov.w r3, #0 + 8003c70: 00eb lsls r3, r5, #3 + 8003c72: ea43 7354 orr.w r3, r3, r4, lsr #29 + 8003c76: 00e2 lsls r2, r4, #3 + 8003c78: 4614 mov r4, r2 + 8003c7a: 461d mov r5, r3 + 8003c7c: eb14 030a adds.w r3, r4, sl + 8003c80: 603b str r3, [r7, #0] + 8003c82: eb45 030b adc.w r3, r5, fp + 8003c86: 607b str r3, [r7, #4] + 8003c88: f04f 0200 mov.w r2, #0 + 8003c8c: f04f 0300 mov.w r3, #0 + 8003c90: e9d7 4500 ldrd r4, r5, [r7] + 8003c94: 4629 mov r1, r5 + 8003c96: 028b lsls r3, r1, #10 + 8003c98: 4621 mov r1, r4 + 8003c9a: ea43 5391 orr.w r3, r3, r1, lsr #22 + 8003c9e: 4621 mov r1, r4 + 8003ca0: 028a lsls r2, r1, #10 + 8003ca2: 4610 mov r0, r2 + 8003ca4: 4619 mov r1, r3 + 8003ca6: 6b7b ldr r3, [r7, #52] @ 0x34 + 8003ca8: 2200 movs r2, #0 + 8003caa: 60bb str r3, [r7, #8] + 8003cac: 60fa str r2, [r7, #12] + 8003cae: e9d7 2302 ldrd r2, r3, [r7, #8] + 8003cb2: f7fc fa8d bl 80001d0 <__aeabi_uldivmod> + 8003cb6: 4602 mov r2, r0 + 8003cb8: 460b mov r3, r1 + 8003cba: 4613 mov r3, r2 + 8003cbc: 63fb str r3, [r7, #60] @ 0x3c } pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U); - 80025ae: 4b0b ldr r3, [pc, #44] @ (80025dc ) - 80025b0: 685b ldr r3, [r3, #4] - 80025b2: 0c1b lsrs r3, r3, #16 - 80025b4: f003 0303 and.w r3, r3, #3 - 80025b8: 3301 adds r3, #1 - 80025ba: 005b lsls r3, r3, #1 - 80025bc: 633b str r3, [r7, #48] @ 0x30 + 8003cbe: 4b0b ldr r3, [pc, #44] @ (8003cec ) + 8003cc0: 685b ldr r3, [r3, #4] + 8003cc2: 0c1b lsrs r3, r3, #16 + 8003cc4: f003 0303 and.w r3, r3, #3 + 8003cc8: 3301 adds r3, #1 + 8003cca: 005b lsls r3, r3, #1 + 8003ccc: 633b str r3, [r7, #48] @ 0x30 sysclockfreq = pllvco / pllp; - 80025be: 6bfa ldr r2, [r7, #60] @ 0x3c - 80025c0: 6b3b ldr r3, [r7, #48] @ 0x30 - 80025c2: fbb2 f3f3 udiv r3, r2, r3 - 80025c6: 63bb str r3, [r7, #56] @ 0x38 + 8003cce: 6bfa ldr r2, [r7, #60] @ 0x3c + 8003cd0: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003cd2: fbb2 f3f3 udiv r3, r2, r3 + 8003cd6: 63bb str r3, [r7, #56] @ 0x38 break; - 80025c8: e002 b.n 80025d0 + 8003cd8: e002 b.n 8003ce0 } default: { sysclockfreq = HSI_VALUE; - 80025ca: 4b05 ldr r3, [pc, #20] @ (80025e0 ) - 80025cc: 63bb str r3, [r7, #56] @ 0x38 + 8003cda: 4b05 ldr r3, [pc, #20] @ (8003cf0 ) + 8003cdc: 63bb str r3, [r7, #56] @ 0x38 break; - 80025ce: bf00 nop + 8003cde: bf00 nop } } return sysclockfreq; - 80025d0: 6bbb ldr r3, [r7, #56] @ 0x38 + 8003ce0: 6bbb ldr r3, [r7, #56] @ 0x38 } - 80025d2: 4618 mov r0, r3 - 80025d4: 3740 adds r7, #64 @ 0x40 - 80025d6: 46bd mov sp, r7 - 80025d8: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} - 80025dc: 40023800 .word 0x40023800 - 80025e0: 00f42400 .word 0x00f42400 - 80025e4: 017d7840 .word 0x017d7840 + 8003ce2: 4618 mov r0, r3 + 8003ce4: 3740 adds r7, #64 @ 0x40 + 8003ce6: 46bd mov sp, r7 + 8003ce8: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} + 8003cec: 40023800 .word 0x40023800 + 8003cf0: 00f42400 .word 0x00f42400 + 8003cf4: 017d7840 .word 0x017d7840 -080025e8 : +08003cf8 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { - 80025e8: b480 push {r7} - 80025ea: af00 add r7, sp, #0 + 8003cf8: b480 push {r7} + 8003cfa: af00 add r7, sp, #0 return SystemCoreClock; - 80025ec: 4b03 ldr r3, [pc, #12] @ (80025fc ) - 80025ee: 681b ldr r3, [r3, #0] + 8003cfc: 4b03 ldr r3, [pc, #12] @ (8003d0c ) + 8003cfe: 681b ldr r3, [r3, #0] } - 80025f0: 4618 mov r0, r3 - 80025f2: 46bd mov sp, r7 - 80025f4: f85d 7b04 ldr.w r7, [sp], #4 - 80025f8: 4770 bx lr - 80025fa: bf00 nop - 80025fc: 20000000 .word 0x20000000 + 8003d00: 4618 mov r0, r3 + 8003d02: 46bd mov sp, r7 + 8003d04: f85d 7b04 ldr.w r7, [sp], #4 + 8003d08: 4770 bx lr + 8003d0a: bf00 nop + 8003d0c: 20000018 .word 0x20000018 -08002600 : +08003d10 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { - 8002600: b580 push {r7, lr} - 8002602: af00 add r7, sp, #0 + 8003d10: b580 push {r7, lr} + 8003d12: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); - 8002604: f7ff fff0 bl 80025e8 - 8002608: 4602 mov r2, r0 - 800260a: 4b05 ldr r3, [pc, #20] @ (8002620 ) - 800260c: 689b ldr r3, [r3, #8] - 800260e: 0a9b lsrs r3, r3, #10 - 8002610: f003 0307 and.w r3, r3, #7 - 8002614: 4903 ldr r1, [pc, #12] @ (8002624 ) - 8002616: 5ccb ldrb r3, [r1, r3] - 8002618: fa22 f303 lsr.w r3, r2, r3 + 8003d14: f7ff fff0 bl 8003cf8 + 8003d18: 4602 mov r2, r0 + 8003d1a: 4b05 ldr r3, [pc, #20] @ (8003d30 ) + 8003d1c: 689b ldr r3, [r3, #8] + 8003d1e: 0a9b lsrs r3, r3, #10 + 8003d20: f003 0307 and.w r3, r3, #7 + 8003d24: 4903 ldr r1, [pc, #12] @ (8003d34 ) + 8003d26: 5ccb ldrb r3, [r1, r3] + 8003d28: fa22 f303 lsr.w r3, r2, r3 } - 800261c: 4618 mov r0, r3 - 800261e: bd80 pop {r7, pc} - 8002620: 40023800 .word 0x40023800 - 8002624: 08005d54 .word 0x08005d54 + 8003d2c: 4618 mov r0, r3 + 8003d2e: bd80 pop {r7, pc} + 8003d30: 40023800 .word 0x40023800 + 8003d34: 0800a2b0 .word 0x0800a2b0 -08002628 : +08003d38 : * will be configured. * @param pFLatency Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { - 8002628: b480 push {r7} - 800262a: b083 sub sp, #12 - 800262c: af00 add r7, sp, #0 - 800262e: 6078 str r0, [r7, #4] - 8002630: 6039 str r1, [r7, #0] + 8003d38: b480 push {r7} + 8003d3a: b083 sub sp, #12 + 8003d3c: af00 add r7, sp, #0 + 8003d3e: 6078 str r0, [r7, #4] + 8003d40: 6039 str r1, [r7, #0] /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; - 8002632: 687b ldr r3, [r7, #4] - 8002634: 220f movs r2, #15 - 8002636: 601a str r2, [r3, #0] + 8003d42: 687b ldr r3, [r7, #4] + 8003d44: 220f movs r2, #15 + 8003d46: 601a str r2, [r3, #0] /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); - 8002638: 4b12 ldr r3, [pc, #72] @ (8002684 ) - 800263a: 689b ldr r3, [r3, #8] - 800263c: f003 0203 and.w r2, r3, #3 - 8002640: 687b ldr r3, [r7, #4] - 8002642: 605a str r2, [r3, #4] + 8003d48: 4b12 ldr r3, [pc, #72] @ (8003d94 ) + 8003d4a: 689b ldr r3, [r3, #8] + 8003d4c: f003 0203 and.w r2, r3, #3 + 8003d50: 687b ldr r3, [r7, #4] + 8003d52: 605a str r2, [r3, #4] /* Get the HCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); - 8002644: 4b0f ldr r3, [pc, #60] @ (8002684 ) - 8002646: 689b ldr r3, [r3, #8] - 8002648: f003 02f0 and.w r2, r3, #240 @ 0xf0 - 800264c: 687b ldr r3, [r7, #4] - 800264e: 609a str r2, [r3, #8] + 8003d54: 4b0f ldr r3, [pc, #60] @ (8003d94 ) + 8003d56: 689b ldr r3, [r3, #8] + 8003d58: f003 02f0 and.w r2, r3, #240 @ 0xf0 + 8003d5c: 687b ldr r3, [r7, #4] + 8003d5e: 609a str r2, [r3, #8] /* Get the APB1 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); - 8002650: 4b0c ldr r3, [pc, #48] @ (8002684 ) - 8002652: 689b ldr r3, [r3, #8] - 8002654: f403 52e0 and.w r2, r3, #7168 @ 0x1c00 - 8002658: 687b ldr r3, [r7, #4] - 800265a: 60da str r2, [r3, #12] + 8003d60: 4b0c ldr r3, [pc, #48] @ (8003d94 ) + 8003d62: 689b ldr r3, [r3, #8] + 8003d64: f403 52e0 and.w r2, r3, #7168 @ 0x1c00 + 8003d68: 687b ldr r3, [r7, #4] + 8003d6a: 60da str r2, [r3, #12] /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U); - 800265c: 4b09 ldr r3, [pc, #36] @ (8002684 ) - 800265e: 689b ldr r3, [r3, #8] - 8002660: 08db lsrs r3, r3, #3 - 8002662: f403 52e0 and.w r2, r3, #7168 @ 0x1c00 - 8002666: 687b ldr r3, [r7, #4] - 8002668: 611a str r2, [r3, #16] + 8003d6c: 4b09 ldr r3, [pc, #36] @ (8003d94 ) + 8003d6e: 689b ldr r3, [r3, #8] + 8003d70: 08db lsrs r3, r3, #3 + 8003d72: f403 52e0 and.w r2, r3, #7168 @ 0x1c00 + 8003d76: 687b ldr r3, [r7, #4] + 8003d78: 611a str r2, [r3, #16] /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); - 800266a: 4b07 ldr r3, [pc, #28] @ (8002688 ) - 800266c: 681b ldr r3, [r3, #0] - 800266e: f003 0207 and.w r2, r3, #7 - 8002672: 683b ldr r3, [r7, #0] - 8002674: 601a str r2, [r3, #0] + 8003d7a: 4b07 ldr r3, [pc, #28] @ (8003d98 ) + 8003d7c: 681b ldr r3, [r3, #0] + 8003d7e: f003 0207 and.w r2, r3, #7 + 8003d82: 683b ldr r3, [r7, #0] + 8003d84: 601a str r2, [r3, #0] } - 8002676: bf00 nop - 8002678: 370c adds r7, #12 - 800267a: 46bd mov sp, r7 - 800267c: f85d 7b04 ldr.w r7, [sp], #4 - 8002680: 4770 bx lr - 8002682: bf00 nop - 8002684: 40023800 .word 0x40023800 - 8002688: 40023c00 .word 0x40023c00 + 8003d86: bf00 nop + 8003d88: 370c adds r7, #12 + 8003d8a: 46bd mov sp, r7 + 8003d8c: f85d 7b04 ldr.w r7, [sp], #4 + 8003d90: 4770 bx lr + 8003d92: bf00 nop + 8003d94: 40023800 .word 0x40023800 + 8003d98: 40023c00 .word 0x40023c00 -0800268c : +08003d9c : + SD_HandleTypeDef and create the associated handle. + * @param hsd: Pointer to the SD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) +{ + 8003d9c: b580 push {r7, lr} + 8003d9e: b082 sub sp, #8 + 8003da0: af00 add r7, sp, #0 + 8003da2: 6078 str r0, [r7, #4] + /* Check the SD handle allocation */ + if(hsd == NULL) + 8003da4: 687b ldr r3, [r7, #4] + 8003da6: 2b00 cmp r3, #0 + 8003da8: d101 bne.n 8003dae + { + return HAL_ERROR; + 8003daa: 2301 movs r3, #1 + 8003dac: e080 b.n 8003eb0 + } + + /* Check the parameters */ + assert_param(IS_SDIO_ALL_INSTANCE(hsd->Instance)); + 8003dae: 687b ldr r3, [r7, #4] + 8003db0: 681b ldr r3, [r3, #0] + 8003db2: 4a41 ldr r2, [pc, #260] @ (8003eb8 ) + 8003db4: 4293 cmp r3, r2 + 8003db6: d004 beq.n 8003dc2 + 8003db8: f44f 71ac mov.w r1, #344 @ 0x158 + 8003dbc: 483f ldr r0, [pc, #252] @ (8003ebc ) + 8003dbe: f7fc ffb9 bl 8000d34 + assert_param(IS_SDIO_CLOCK_EDGE(hsd->Init.ClockEdge)); + 8003dc2: 687b ldr r3, [r7, #4] + 8003dc4: 685b ldr r3, [r3, #4] + 8003dc6: 2b00 cmp r3, #0 + 8003dc8: d009 beq.n 8003dde + 8003dca: 687b ldr r3, [r7, #4] + 8003dcc: 685b ldr r3, [r3, #4] + 8003dce: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 8003dd2: d004 beq.n 8003dde + 8003dd4: f240 1159 movw r1, #345 @ 0x159 + 8003dd8: 4838 ldr r0, [pc, #224] @ (8003ebc ) + 8003dda: f7fc ffab bl 8000d34 + assert_param(IS_SDIO_CLOCK_BYPASS(hsd->Init.ClockBypass)); + 8003dde: 687b ldr r3, [r7, #4] + 8003de0: 689b ldr r3, [r3, #8] + 8003de2: 2b00 cmp r3, #0 + 8003de4: d009 beq.n 8003dfa + 8003de6: 687b ldr r3, [r7, #4] + 8003de8: 689b ldr r3, [r3, #8] + 8003dea: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 8003dee: d004 beq.n 8003dfa + 8003df0: f44f 71ad mov.w r1, #346 @ 0x15a + 8003df4: 4831 ldr r0, [pc, #196] @ (8003ebc ) + 8003df6: f7fc ff9d bl 8000d34 + assert_param(IS_SDIO_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave)); + 8003dfa: 687b ldr r3, [r7, #4] + 8003dfc: 68db ldr r3, [r3, #12] + 8003dfe: 2b00 cmp r3, #0 + 8003e00: d009 beq.n 8003e16 + 8003e02: 687b ldr r3, [r7, #4] + 8003e04: 68db ldr r3, [r3, #12] + 8003e06: f5b3 7f00 cmp.w r3, #512 @ 0x200 + 8003e0a: d004 beq.n 8003e16 + 8003e0c: f240 115b movw r1, #347 @ 0x15b + 8003e10: 482a ldr r0, [pc, #168] @ (8003ebc ) + 8003e12: f7fc ff8f bl 8000d34 + assert_param(IS_SDIO_BUS_WIDE(hsd->Init.BusWide)); + 8003e16: 687b ldr r3, [r7, #4] + 8003e18: 691b ldr r3, [r3, #16] + 8003e1a: 2b00 cmp r3, #0 + 8003e1c: d00e beq.n 8003e3c + 8003e1e: 687b ldr r3, [r7, #4] + 8003e20: 691b ldr r3, [r3, #16] + 8003e22: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 8003e26: d009 beq.n 8003e3c + 8003e28: 687b ldr r3, [r7, #4] + 8003e2a: 691b ldr r3, [r3, #16] + 8003e2c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 8003e30: d004 beq.n 8003e3c + 8003e32: f44f 71ae mov.w r1, #348 @ 0x15c + 8003e36: 4821 ldr r0, [pc, #132] @ (8003ebc ) + 8003e38: f7fc ff7c bl 8000d34 + assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl)); + 8003e3c: 687b ldr r3, [r7, #4] + 8003e3e: 695b ldr r3, [r3, #20] + 8003e40: 2b00 cmp r3, #0 + 8003e42: d009 beq.n 8003e58 + 8003e44: 687b ldr r3, [r7, #4] + 8003e46: 695b ldr r3, [r3, #20] + 8003e48: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 + 8003e4c: d004 beq.n 8003e58 + 8003e4e: f240 115d movw r1, #349 @ 0x15d + 8003e52: 481a ldr r0, [pc, #104] @ (8003ebc ) + 8003e54: f7fc ff6e bl 8000d34 + assert_param(IS_SDIO_CLKDIV(hsd->Init.ClockDiv)); + 8003e58: 687b ldr r3, [r7, #4] + 8003e5a: 699b ldr r3, [r3, #24] + 8003e5c: 2bff cmp r3, #255 @ 0xff + 8003e5e: d904 bls.n 8003e6a + 8003e60: f44f 71af mov.w r1, #350 @ 0x15e + 8003e64: 4815 ldr r0, [pc, #84] @ (8003ebc ) + 8003e66: f7fc ff65 bl 8000d34 + + if(hsd->State == HAL_SD_STATE_RESET) + 8003e6a: 687b ldr r3, [r7, #4] + 8003e6c: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 + 8003e70: b2db uxtb r3, r3 + 8003e72: 2b00 cmp r3, #0 + 8003e74: d105 bne.n 8003e82 + { + /* Allocate lock resource and initialize it */ + hsd->Lock = HAL_UNLOCKED; + 8003e76: 687b ldr r3, [r7, #4] + 8003e78: 2200 movs r2, #0 + 8003e7a: 771a strb r2, [r3, #28] + + /* Init the low level hardware */ + hsd->MspInitCallback(hsd); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_SD_MspInit(hsd); + 8003e7c: 6878 ldr r0, [r7, #4] + 8003e7e: f7fd f831 bl 8000ee4 +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + + hsd->State = HAL_SD_STATE_BUSY; + 8003e82: 687b ldr r3, [r7, #4] + 8003e84: 2203 movs r2, #3 + 8003e86: f883 2034 strb.w r2, [r3, #52] @ 0x34 + + /* Initialize the Card parameters */ + if (HAL_SD_InitCard(hsd) != HAL_OK) + 8003e8a: 6878 ldr r0, [r7, #4] + 8003e8c: f000 f818 bl 8003ec0 + 8003e90: 4603 mov r3, r0 + 8003e92: 2b00 cmp r3, #0 + 8003e94: d001 beq.n 8003e9a + { + return HAL_ERROR; + 8003e96: 2301 movs r3, #1 + 8003e98: e00a b.n 8003eb0 + } + + /* Initialize the error code */ + hsd->ErrorCode = HAL_SD_ERROR_NONE; + 8003e9a: 687b ldr r3, [r7, #4] + 8003e9c: 2200 movs r2, #0 + 8003e9e: 639a str r2, [r3, #56] @ 0x38 + + /* Initialize the SD operation */ + hsd->Context = SD_CONTEXT_NONE; + 8003ea0: 687b ldr r3, [r7, #4] + 8003ea2: 2200 movs r2, #0 + 8003ea4: 631a str r2, [r3, #48] @ 0x30 + + /* Initialize the SD state */ + hsd->State = HAL_SD_STATE_READY; + 8003ea6: 687b ldr r3, [r7, #4] + 8003ea8: 2201 movs r2, #1 + 8003eaa: f883 2034 strb.w r2, [r3, #52] @ 0x34 + + return HAL_OK; + 8003eae: 2300 movs r3, #0 +} + 8003eb0: 4618 mov r0, r3 + 8003eb2: 3708 adds r7, #8 + 8003eb4: 46bd mov sp, r7 + 8003eb6: bd80 pop {r7, pc} + 8003eb8: 40012c00 .word 0x40012c00 + 8003ebc: 0800a1dc .word 0x0800a1dc + +08003ec0 : + * @note This function initializes the SD card. It could be used when a card + re-initialization is needed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) +{ + 8003ec0: b5b0 push {r4, r5, r7, lr} + 8003ec2: b08e sub sp, #56 @ 0x38 + 8003ec4: af04 add r7, sp, #16 + 8003ec6: 6078 str r0, [r7, #4] + uint32_t errorstate; + SD_InitTypeDef Init; + + /* Default SDIO peripheral configuration for SD card initialization */ + Init.ClockEdge = SDIO_CLOCK_EDGE_RISING; + 8003ec8: 2300 movs r3, #0 + 8003eca: 60fb str r3, [r7, #12] + Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; + 8003ecc: 2300 movs r3, #0 + 8003ece: 613b str r3, [r7, #16] + Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; + 8003ed0: 2300 movs r3, #0 + 8003ed2: 617b str r3, [r7, #20] + Init.BusWide = SDIO_BUS_WIDE_1B; + 8003ed4: 2300 movs r3, #0 + 8003ed6: 61bb str r3, [r7, #24] + Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; + 8003ed8: 2300 movs r3, #0 + 8003eda: 61fb str r3, [r7, #28] + Init.ClockDiv = SDIO_INIT_CLK_DIV; + 8003edc: 2376 movs r3, #118 @ 0x76 + 8003ede: 623b str r3, [r7, #32] + + /* Initialize SDIO peripheral interface with default configuration */ + SDIO_Init(hsd->Instance, Init); + 8003ee0: 687b ldr r3, [r7, #4] + 8003ee2: 681d ldr r5, [r3, #0] + 8003ee4: 466c mov r4, sp + 8003ee6: f107 0318 add.w r3, r7, #24 + 8003eea: e893 0007 ldmia.w r3, {r0, r1, r2} + 8003eee: e884 0007 stmia.w r4, {r0, r1, r2} + 8003ef2: f107 030c add.w r3, r7, #12 + 8003ef6: cb0e ldmia r3, {r1, r2, r3} + 8003ef8: 4628 mov r0, r5 + 8003efa: f001 fc3d bl 8005778 + + /* Disable SDIO Clock */ + __HAL_SD_DISABLE(hsd); + 8003efe: 4b2a ldr r3, [pc, #168] @ (8003fa8 ) + 8003f00: 2200 movs r2, #0 + 8003f02: 601a str r2, [r3, #0] + + /* Set Power State to ON */ + (void)SDIO_PowerState_ON(hsd->Instance); + 8003f04: 687b ldr r3, [r7, #4] + 8003f06: 681b ldr r3, [r3, #0] + 8003f08: 4618 mov r0, r3 + 8003f0a: f001 fccd bl 80058a8 + + /* Enable SDIO Clock */ + __HAL_SD_ENABLE(hsd); + 8003f0e: 4b26 ldr r3, [pc, #152] @ (8003fa8 ) + 8003f10: 2201 movs r2, #1 + 8003f12: 601a str r2, [r3, #0] + + /* Required power up waiting time before starting the SD initialization sequence */ + HAL_Delay(2); + 8003f14: 2002 movs r0, #2 + 8003f16: f7fd fa9b bl 8001450 + + /* Identify card operating voltage */ + errorstate = SD_PowerON(hsd); + 8003f1a: 6878 ldr r0, [r7, #4] + 8003f1c: f000 fda2 bl 8004a64 + 8003f20: 6278 str r0, [r7, #36] @ 0x24 + if(errorstate != HAL_SD_ERROR_NONE) + 8003f22: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003f24: 2b00 cmp r3, #0 + 8003f26: d00b beq.n 8003f40 + { + hsd->State = HAL_SD_STATE_READY; + 8003f28: 687b ldr r3, [r7, #4] + 8003f2a: 2201 movs r2, #1 + 8003f2c: f883 2034 strb.w r2, [r3, #52] @ 0x34 + hsd->ErrorCode |= errorstate; + 8003f30: 687b ldr r3, [r7, #4] + 8003f32: 6b9a ldr r2, [r3, #56] @ 0x38 + 8003f34: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003f36: 431a orrs r2, r3 + 8003f38: 687b ldr r3, [r7, #4] + 8003f3a: 639a str r2, [r3, #56] @ 0x38 + return HAL_ERROR; + 8003f3c: 2301 movs r3, #1 + 8003f3e: e02e b.n 8003f9e + } + + /* Card initialization */ + errorstate = SD_InitCard(hsd); + 8003f40: 6878 ldr r0, [r7, #4] + 8003f42: f000 fcc1 bl 80048c8 + 8003f46: 6278 str r0, [r7, #36] @ 0x24 + if(errorstate != HAL_SD_ERROR_NONE) + 8003f48: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003f4a: 2b00 cmp r3, #0 + 8003f4c: d00b beq.n 8003f66 + { + hsd->State = HAL_SD_STATE_READY; + 8003f4e: 687b ldr r3, [r7, #4] + 8003f50: 2201 movs r2, #1 + 8003f52: f883 2034 strb.w r2, [r3, #52] @ 0x34 + hsd->ErrorCode |= errorstate; + 8003f56: 687b ldr r3, [r7, #4] + 8003f58: 6b9a ldr r2, [r3, #56] @ 0x38 + 8003f5a: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003f5c: 431a orrs r2, r3 + 8003f5e: 687b ldr r3, [r7, #4] + 8003f60: 639a str r2, [r3, #56] @ 0x38 + return HAL_ERROR; + 8003f62: 2301 movs r3, #1 + 8003f64: e01b b.n 8003f9e + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + 8003f66: 687b ldr r3, [r7, #4] + 8003f68: 681b ldr r3, [r3, #0] + 8003f6a: f44f 7100 mov.w r1, #512 @ 0x200 + 8003f6e: 4618 mov r0, r3 + 8003f70: f001 fdec bl 8005b4c + 8003f74: 6278 str r0, [r7, #36] @ 0x24 + if(errorstate != HAL_SD_ERROR_NONE) + 8003f76: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003f78: 2b00 cmp r3, #0 + 8003f7a: d00f beq.n 8003f9c + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + 8003f7c: 687b ldr r3, [r7, #4] + 8003f7e: 681b ldr r3, [r3, #0] + 8003f80: 4a0a ldr r2, [pc, #40] @ (8003fac ) + 8003f82: 639a str r2, [r3, #56] @ 0x38 + hsd->ErrorCode |= errorstate; + 8003f84: 687b ldr r3, [r7, #4] + 8003f86: 6b9a ldr r2, [r3, #56] @ 0x38 + 8003f88: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003f8a: 431a orrs r2, r3 + 8003f8c: 687b ldr r3, [r7, #4] + 8003f8e: 639a str r2, [r3, #56] @ 0x38 + hsd->State = HAL_SD_STATE_READY; + 8003f90: 687b ldr r3, [r7, #4] + 8003f92: 2201 movs r2, #1 + 8003f94: f883 2034 strb.w r2, [r3, #52] @ 0x34 + return HAL_ERROR; + 8003f98: 2301 movs r3, #1 + 8003f9a: e000 b.n 8003f9e + } + + return HAL_OK; + 8003f9c: 2300 movs r3, #0 +} + 8003f9e: 4618 mov r0, r3 + 8003fa0: 3728 adds r7, #40 @ 0x28 + 8003fa2: 46bd mov sp, r7 + 8003fa4: bdb0 pop {r4, r5, r7, pc} + 8003fa6: bf00 nop + 8003fa8: 422580a0 .word 0x422580a0 + 8003fac: 004005ff .word 0x004005ff + +08003fb0 : + * @brief This function handles SD card interrupt request. + * @param hsd: Pointer to SD handle + * @retval None + */ +void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) +{ + 8003fb0: b580 push {r7, lr} + 8003fb2: b084 sub sp, #16 + 8003fb4: af00 add r7, sp, #0 + 8003fb6: 6078 str r0, [r7, #4] + uint32_t errorstate; + uint32_t context = hsd->Context; + 8003fb8: 687b ldr r3, [r7, #4] + 8003fba: 6b1b ldr r3, [r3, #48] @ 0x30 + 8003fbc: 60fb str r3, [r7, #12] + + /* Check for SDIO interrupt flags */ + if((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U)) + 8003fbe: 687b ldr r3, [r7, #4] + 8003fc0: 681b ldr r3, [r3, #0] + 8003fc2: 6b5b ldr r3, [r3, #52] @ 0x34 + 8003fc4: f403 4300 and.w r3, r3, #32768 @ 0x8000 + 8003fc8: 2b00 cmp r3, #0 + 8003fca: d008 beq.n 8003fde + 8003fcc: 68fb ldr r3, [r7, #12] + 8003fce: f003 0308 and.w r3, r3, #8 + 8003fd2: 2b00 cmp r3, #0 + 8003fd4: d003 beq.n 8003fde + { + SD_Read_IT(hsd); + 8003fd6: 6878 ldr r0, [r7, #4] + 8003fd8: f000 ff6a bl 8004eb0 + 8003fdc: e165 b.n 80042aa + } + + else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) != RESET) + 8003fde: 687b ldr r3, [r7, #4] + 8003fe0: 681b ldr r3, [r3, #0] + 8003fe2: 6b5b ldr r3, [r3, #52] @ 0x34 + 8003fe4: f403 7380 and.w r3, r3, #256 @ 0x100 + 8003fe8: 2b00 cmp r3, #0 + 8003fea: f000 808f beq.w 800410c + { + __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DATAEND); + 8003fee: 687b ldr r3, [r7, #4] + 8003ff0: 681b ldr r3, [r3, #0] + 8003ff2: f44f 7280 mov.w r2, #256 @ 0x100 + 8003ff6: 639a str r2, [r3, #56] @ 0x38 + +#if defined(SDIO_STA_STBITERR) + __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\ + 8003ff8: 687b ldr r3, [r7, #4] + 8003ffa: 681b ldr r3, [r3, #0] + 8003ffc: 6bdb ldr r3, [r3, #60] @ 0x3c + 8003ffe: 687a ldr r2, [r7, #4] + 8004000: 6812 ldr r2, [r2, #0] + 8004002: f423 4343 bic.w r3, r3, #49920 @ 0xc300 + 8004006: f023 033a bic.w r3, r3, #58 @ 0x3a + 800400a: 63d3 str r3, [r2, #60] @ 0x3c + __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\ + SDIO_IT_TXUNDERR | SDIO_IT_RXOVERR | SDIO_IT_TXFIFOHE |\ + SDIO_IT_RXFIFOHF); +#endif /* SDIO_STA_STBITERR */ + + hsd->Instance->DCTRL &= ~(SDIO_DCTRL_DTEN); + 800400c: 687b ldr r3, [r7, #4] + 800400e: 681b ldr r3, [r3, #0] + 8004010: 6ada ldr r2, [r3, #44] @ 0x2c + 8004012: 687b ldr r3, [r7, #4] + 8004014: 681b ldr r3, [r3, #0] + 8004016: f022 0201 bic.w r2, r2, #1 + 800401a: 62da str r2, [r3, #44] @ 0x2c + + if((context & SD_CONTEXT_IT) != 0U) + 800401c: 68fb ldr r3, [r7, #12] + 800401e: f003 0308 and.w r3, r3, #8 + 8004022: 2b00 cmp r3, #0 + 8004024: d039 beq.n 800409a + { + if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + 8004026: 68fb ldr r3, [r7, #12] + 8004028: f003 0302 and.w r3, r3, #2 + 800402c: 2b00 cmp r3, #0 + 800402e: d104 bne.n 800403a + 8004030: 68fb ldr r3, [r7, #12] + 8004032: f003 0320 and.w r3, r3, #32 + 8004036: 2b00 cmp r3, #0 + 8004038: d011 beq.n 800405e + { + errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + 800403a: 687b ldr r3, [r7, #4] + 800403c: 681b ldr r3, [r3, #0] + 800403e: 4618 mov r0, r3 + 8004040: f001 fda6 bl 8005b90 + 8004044: 60b8 str r0, [r7, #8] + if(errorstate != HAL_SD_ERROR_NONE) + 8004046: 68bb ldr r3, [r7, #8] + 8004048: 2b00 cmp r3, #0 + 800404a: d008 beq.n 800405e + { + hsd->ErrorCode |= errorstate; + 800404c: 687b ldr r3, [r7, #4] + 800404e: 6b9a ldr r2, [r3, #56] @ 0x38 + 8004050: 68bb ldr r3, [r7, #8] + 8004052: 431a orrs r2, r3 + 8004054: 687b ldr r3, [r7, #4] + 8004056: 639a str r2, [r3, #56] @ 0x38 +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->ErrorCallback(hsd); +#else + HAL_SD_ErrorCallback(hsd); + 8004058: 6878 ldr r0, [r7, #4] + 800405a: f000 f943 bl 80042e4 +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + } + + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS); + 800405e: 687b ldr r3, [r7, #4] + 8004060: 681b ldr r3, [r3, #0] + 8004062: f240 523a movw r2, #1338 @ 0x53a + 8004066: 639a str r2, [r3, #56] @ 0x38 + + hsd->State = HAL_SD_STATE_READY; + 8004068: 687b ldr r3, [r7, #4] + 800406a: 2201 movs r2, #1 + 800406c: f883 2034 strb.w r2, [r3, #52] @ 0x34 + hsd->Context = SD_CONTEXT_NONE; + 8004070: 687b ldr r3, [r7, #4] + 8004072: 2200 movs r2, #0 + 8004074: 631a str r2, [r3, #48] @ 0x30 + if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + 8004076: 68fb ldr r3, [r7, #12] + 8004078: f003 0301 and.w r3, r3, #1 + 800407c: 2b00 cmp r3, #0 + 800407e: d104 bne.n 800408a + 8004080: 68fb ldr r3, [r7, #12] + 8004082: f003 0302 and.w r3, r3, #2 + 8004086: 2b00 cmp r3, #0 + 8004088: d003 beq.n 8004092 + { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->RxCpltCallback(hsd); +#else + HAL_SD_RxCpltCallback(hsd); + 800408a: 6878 ldr r0, [r7, #4] + 800408c: f000 f920 bl 80042d0 + 8004090: e10b b.n 80042aa + else + { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->TxCpltCallback(hsd); +#else + HAL_SD_TxCpltCallback(hsd); + 8004092: 6878 ldr r0, [r7, #4] + 8004094: f000 f912 bl 80042bc + } + else + { + /* Nothing to do */ + } +} + 8004098: e107 b.n 80042aa + else if((context & SD_CONTEXT_DMA) != 0U) + 800409a: 68fb ldr r3, [r7, #12] + 800409c: f003 0380 and.w r3, r3, #128 @ 0x80 + 80040a0: 2b00 cmp r3, #0 + 80040a2: f000 8102 beq.w 80042aa + if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) + 80040a6: 68fb ldr r3, [r7, #12] + 80040a8: f003 0320 and.w r3, r3, #32 + 80040ac: 2b00 cmp r3, #0 + 80040ae: d011 beq.n 80040d4 + errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + 80040b0: 687b ldr r3, [r7, #4] + 80040b2: 681b ldr r3, [r3, #0] + 80040b4: 4618 mov r0, r3 + 80040b6: f001 fd6b bl 8005b90 + 80040ba: 60b8 str r0, [r7, #8] + if(errorstate != HAL_SD_ERROR_NONE) + 80040bc: 68bb ldr r3, [r7, #8] + 80040be: 2b00 cmp r3, #0 + 80040c0: d008 beq.n 80040d4 + hsd->ErrorCode |= errorstate; + 80040c2: 687b ldr r3, [r7, #4] + 80040c4: 6b9a ldr r2, [r3, #56] @ 0x38 + 80040c6: 68bb ldr r3, [r7, #8] + 80040c8: 431a orrs r2, r3 + 80040ca: 687b ldr r3, [r7, #4] + 80040cc: 639a str r2, [r3, #56] @ 0x38 + HAL_SD_ErrorCallback(hsd); + 80040ce: 6878 ldr r0, [r7, #4] + 80040d0: f000 f908 bl 80042e4 + if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) == 0U) && ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == 0U)) + 80040d4: 68fb ldr r3, [r7, #12] + 80040d6: f003 0301 and.w r3, r3, #1 + 80040da: 2b00 cmp r3, #0 + 80040dc: f040 80e5 bne.w 80042aa + 80040e0: 68fb ldr r3, [r7, #12] + 80040e2: f003 0302 and.w r3, r3, #2 + 80040e6: 2b00 cmp r3, #0 + 80040e8: f040 80df bne.w 80042aa + hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN); + 80040ec: 687b ldr r3, [r7, #4] + 80040ee: 681b ldr r3, [r3, #0] + 80040f0: 6ada ldr r2, [r3, #44] @ 0x2c + 80040f2: 687b ldr r3, [r7, #4] + 80040f4: 681b ldr r3, [r3, #0] + 80040f6: f022 0208 bic.w r2, r2, #8 + 80040fa: 62da str r2, [r3, #44] @ 0x2c + hsd->State = HAL_SD_STATE_READY; + 80040fc: 687b ldr r3, [r7, #4] + 80040fe: 2201 movs r2, #1 + 8004100: f883 2034 strb.w r2, [r3, #52] @ 0x34 + HAL_SD_TxCpltCallback(hsd); + 8004104: 6878 ldr r0, [r7, #4] + 8004106: f000 f8d9 bl 80042bc +} + 800410a: e0ce b.n 80042aa + else if((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U)) + 800410c: 687b ldr r3, [r7, #4] + 800410e: 681b ldr r3, [r3, #0] + 8004110: 6b5b ldr r3, [r3, #52] @ 0x34 + 8004112: f403 4380 and.w r3, r3, #16384 @ 0x4000 + 8004116: 2b00 cmp r3, #0 + 8004118: d008 beq.n 800412c + 800411a: 68fb ldr r3, [r7, #12] + 800411c: f003 0308 and.w r3, r3, #8 + 8004120: 2b00 cmp r3, #0 + 8004122: d003 beq.n 800412c + SD_Write_IT(hsd); + 8004124: 6878 ldr r0, [r7, #4] + 8004126: f000 ff14 bl 8004f52 + 800412a: e0be b.n 80042aa + else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_RXOVERR | SDIO_FLAG_TXUNDERR | SDIO_FLAG_STBITERR) != RESET) + 800412c: 687b ldr r3, [r7, #4] + 800412e: 681b ldr r3, [r3, #0] + 8004130: 6b5a ldr r2, [r3, #52] @ 0x34 + 8004132: f240 233a movw r3, #570 @ 0x23a + 8004136: 4013 ands r3, r2 + 8004138: 2b00 cmp r3, #0 + 800413a: f000 80b6 beq.w 80042aa + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL) != RESET) + 800413e: 687b ldr r3, [r7, #4] + 8004140: 681b ldr r3, [r3, #0] + 8004142: 6b5b ldr r3, [r3, #52] @ 0x34 + 8004144: f003 0302 and.w r3, r3, #2 + 8004148: 2b00 cmp r3, #0 + 800414a: d005 beq.n 8004158 + hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; + 800414c: 687b ldr r3, [r7, #4] + 800414e: 6b9b ldr r3, [r3, #56] @ 0x38 + 8004150: f043 0202 orr.w r2, r3, #2 + 8004154: 687b ldr r3, [r7, #4] + 8004156: 639a str r2, [r3, #56] @ 0x38 + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) != RESET) + 8004158: 687b ldr r3, [r7, #4] + 800415a: 681b ldr r3, [r3, #0] + 800415c: 6b5b ldr r3, [r3, #52] @ 0x34 + 800415e: f003 0308 and.w r3, r3, #8 + 8004162: 2b00 cmp r3, #0 + 8004164: d005 beq.n 8004172 + hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; + 8004166: 687b ldr r3, [r7, #4] + 8004168: 6b9b ldr r3, [r3, #56] @ 0x38 + 800416a: f043 0208 orr.w r2, r3, #8 + 800416e: 687b ldr r3, [r7, #4] + 8004170: 639a str r2, [r3, #56] @ 0x38 + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR) != RESET) + 8004172: 687b ldr r3, [r7, #4] + 8004174: 681b ldr r3, [r3, #0] + 8004176: 6b5b ldr r3, [r3, #52] @ 0x34 + 8004178: f003 0320 and.w r3, r3, #32 + 800417c: 2b00 cmp r3, #0 + 800417e: d005 beq.n 800418c + hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN; + 8004180: 687b ldr r3, [r7, #4] + 8004182: 6b9b ldr r3, [r3, #56] @ 0x38 + 8004184: f043 0220 orr.w r2, r3, #32 + 8004188: 687b ldr r3, [r7, #4] + 800418a: 639a str r2, [r3, #56] @ 0x38 + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR) != RESET) + 800418c: 687b ldr r3, [r7, #4] + 800418e: 681b ldr r3, [r3, #0] + 8004190: 6b5b ldr r3, [r3, #52] @ 0x34 + 8004192: f003 0310 and.w r3, r3, #16 + 8004196: 2b00 cmp r3, #0 + 8004198: d005 beq.n 80041a6 + hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; + 800419a: 687b ldr r3, [r7, #4] + 800419c: 6b9b ldr r3, [r3, #56] @ 0x38 + 800419e: f043 0210 orr.w r2, r3, #16 + 80041a2: 687b ldr r3, [r7, #4] + 80041a4: 639a str r2, [r3, #56] @ 0x38 + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR) != RESET) + 80041a6: 687b ldr r3, [r7, #4] + 80041a8: 681b ldr r3, [r3, #0] + 80041aa: 6b5b ldr r3, [r3, #52] @ 0x34 + 80041ac: f403 7300 and.w r3, r3, #512 @ 0x200 + 80041b0: 2b00 cmp r3, #0 + 80041b2: d005 beq.n 80041c0 + hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; + 80041b4: 687b ldr r3, [r7, #4] + 80041b6: 6b9b ldr r3, [r3, #56] @ 0x38 + 80041b8: f043 0208 orr.w r2, r3, #8 + 80041bc: 687b ldr r3, [r7, #4] + 80041be: 639a str r2, [r3, #56] @ 0x38 + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS | SDIO_FLAG_STBITERR); + 80041c0: 687b ldr r3, [r7, #4] + 80041c2: 681b ldr r3, [r3, #0] + 80041c4: f240 723a movw r2, #1850 @ 0x73a + 80041c8: 639a str r2, [r3, #56] @ 0x38 + __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\ + 80041ca: 687b ldr r3, [r7, #4] + 80041cc: 681b ldr r3, [r3, #0] + 80041ce: 6bdb ldr r3, [r3, #60] @ 0x3c + 80041d0: 687a ldr r2, [r7, #4] + 80041d2: 6812 ldr r2, [r2, #0] + 80041d4: f423 734e bic.w r3, r3, #824 @ 0x338 + 80041d8: f023 0302 bic.w r3, r3, #2 + 80041dc: 63d3 str r3, [r2, #60] @ 0x3c + hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); + 80041de: 687b ldr r3, [r7, #4] + 80041e0: 681b ldr r3, [r3, #0] + 80041e2: 4618 mov r0, r3 + 80041e4: f001 fcd4 bl 8005b90 + 80041e8: 4602 mov r2, r0 + 80041ea: 687b ldr r3, [r7, #4] + 80041ec: 6b9b ldr r3, [r3, #56] @ 0x38 + 80041ee: 431a orrs r2, r3 + 80041f0: 687b ldr r3, [r7, #4] + 80041f2: 639a str r2, [r3, #56] @ 0x38 + if((context & SD_CONTEXT_IT) != 0U) + 80041f4: 68fb ldr r3, [r7, #12] + 80041f6: f003 0308 and.w r3, r3, #8 + 80041fa: 2b00 cmp r3, #0 + 80041fc: d00a beq.n 8004214 + hsd->State = HAL_SD_STATE_READY; + 80041fe: 687b ldr r3, [r7, #4] + 8004200: 2201 movs r2, #1 + 8004202: f883 2034 strb.w r2, [r3, #52] @ 0x34 + hsd->Context = SD_CONTEXT_NONE; + 8004206: 687b ldr r3, [r7, #4] + 8004208: 2200 movs r2, #0 + 800420a: 631a str r2, [r3, #48] @ 0x30 + HAL_SD_ErrorCallback(hsd); + 800420c: 6878 ldr r0, [r7, #4] + 800420e: f000 f869 bl 80042e4 +} + 8004212: e04a b.n 80042aa + else if((context & SD_CONTEXT_DMA) != 0U) + 8004214: 68fb ldr r3, [r7, #12] + 8004216: f003 0380 and.w r3, r3, #128 @ 0x80 + 800421a: 2b00 cmp r3, #0 + 800421c: d045 beq.n 80042aa + if(((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + 800421e: 68fb ldr r3, [r7, #12] + 8004220: f003 0310 and.w r3, r3, #16 + 8004224: 2b00 cmp r3, #0 + 8004226: d104 bne.n 8004232 + 8004228: 68fb ldr r3, [r7, #12] + 800422a: f003 0320 and.w r3, r3, #32 + 800422e: 2b00 cmp r3, #0 + 8004230: d011 beq.n 8004256 + hsd->hdmatx->XferAbortCallback = SD_DMATxAbort; + 8004232: 687b ldr r3, [r7, #4] + 8004234: 6bdb ldr r3, [r3, #60] @ 0x3c + 8004236: 4a1f ldr r2, [pc, #124] @ (80042b4 ) + 8004238: 651a str r2, [r3, #80] @ 0x50 + if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK) + 800423a: 687b ldr r3, [r7, #4] + 800423c: 6bdb ldr r3, [r3, #60] @ 0x3c + 800423e: 4618 mov r0, r3 + 8004240: f7fe fa5c bl 80026fc + 8004244: 4603 mov r3, r0 + 8004246: 2b00 cmp r3, #0 + 8004248: d02f beq.n 80042aa + SD_DMATxAbort(hsd->hdmatx); + 800424a: 687b ldr r3, [r7, #4] + 800424c: 6bdb ldr r3, [r3, #60] @ 0x3c + 800424e: 4618 mov r0, r3 + 8004250: f000 facc bl 80047ec + if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK) + 8004254: e029 b.n 80042aa + else if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + 8004256: 68fb ldr r3, [r7, #12] + 8004258: f003 0301 and.w r3, r3, #1 + 800425c: 2b00 cmp r3, #0 + 800425e: d104 bne.n 800426a + 8004260: 68fb ldr r3, [r7, #12] + 8004262: f003 0302 and.w r3, r3, #2 + 8004266: 2b00 cmp r3, #0 + 8004268: d011 beq.n 800428e + hsd->hdmarx->XferAbortCallback = SD_DMARxAbort; + 800426a: 687b ldr r3, [r7, #4] + 800426c: 6c1b ldr r3, [r3, #64] @ 0x40 + 800426e: 4a12 ldr r2, [pc, #72] @ (80042b8 ) + 8004270: 651a str r2, [r3, #80] @ 0x50 + if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK) + 8004272: 687b ldr r3, [r7, #4] + 8004274: 6c1b ldr r3, [r3, #64] @ 0x40 + 8004276: 4618 mov r0, r3 + 8004278: f7fe fa40 bl 80026fc + 800427c: 4603 mov r3, r0 + 800427e: 2b00 cmp r3, #0 + 8004280: d013 beq.n 80042aa + SD_DMARxAbort(hsd->hdmarx); + 8004282: 687b ldr r3, [r7, #4] + 8004284: 6c1b ldr r3, [r3, #64] @ 0x40 + 8004286: 4618 mov r0, r3 + 8004288: f000 fae7 bl 800485a + if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK) + 800428c: e00d b.n 80042aa + hsd->ErrorCode = HAL_SD_ERROR_NONE; + 800428e: 687b ldr r3, [r7, #4] + 8004290: 2200 movs r2, #0 + 8004292: 639a str r2, [r3, #56] @ 0x38 + hsd->State = HAL_SD_STATE_READY; + 8004294: 687b ldr r3, [r7, #4] + 8004296: 2201 movs r2, #1 + 8004298: f883 2034 strb.w r2, [r3, #52] @ 0x34 + hsd->Context = SD_CONTEXT_NONE; + 800429c: 687b ldr r3, [r7, #4] + 800429e: 2200 movs r2, #0 + 80042a0: 631a str r2, [r3, #48] @ 0x30 + HAL_SD_AbortCallback(hsd); + 80042a2: 6878 ldr r0, [r7, #4] + 80042a4: f000 f828 bl 80042f8 +} + 80042a8: e7ff b.n 80042aa + 80042aa: bf00 nop + 80042ac: 3710 adds r7, #16 + 80042ae: 46bd mov sp, r7 + 80042b0: bd80 pop {r7, pc} + 80042b2: bf00 nop + 80042b4: 080047ed .word 0x080047ed + 80042b8: 0800485b .word 0x0800485b + +080042bc : + * @brief Tx Transfer completed callbacks + * @param hsd: Pointer to SD handle + * @retval None + */ +__weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd) +{ + 80042bc: b480 push {r7} + 80042be: b083 sub sp, #12 + 80042c0: af00 add r7, sp, #0 + 80042c2: 6078 str r0, [r7, #4] + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_TxCpltCallback can be implemented in the user file + */ +} + 80042c4: bf00 nop + 80042c6: 370c adds r7, #12 + 80042c8: 46bd mov sp, r7 + 80042ca: f85d 7b04 ldr.w r7, [sp], #4 + 80042ce: 4770 bx lr + +080042d0 : + * @brief Rx Transfer completed callbacks + * @param hsd: Pointer SD handle + * @retval None + */ +__weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd) +{ + 80042d0: b480 push {r7} + 80042d2: b083 sub sp, #12 + 80042d4: af00 add r7, sp, #0 + 80042d6: 6078 str r0, [r7, #4] + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_RxCpltCallback can be implemented in the user file + */ +} + 80042d8: bf00 nop + 80042da: 370c adds r7, #12 + 80042dc: 46bd mov sp, r7 + 80042de: f85d 7b04 ldr.w r7, [sp], #4 + 80042e2: 4770 bx lr + +080042e4 : + * @brief SD error callbacks + * @param hsd: Pointer SD handle + * @retval None + */ +__weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd) +{ + 80042e4: b480 push {r7} + 80042e6: b083 sub sp, #12 + 80042e8: af00 add r7, sp, #0 + 80042ea: 6078 str r0, [r7, #4] + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_ErrorCallback can be implemented in the user file + */ +} + 80042ec: bf00 nop + 80042ee: 370c adds r7, #12 + 80042f0: 46bd mov sp, r7 + 80042f2: f85d 7b04 ldr.w r7, [sp], #4 + 80042f6: 4770 bx lr + +080042f8 : + * @brief SD Abort callbacks + * @param hsd: Pointer SD handle + * @retval None + */ +__weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd) +{ + 80042f8: b480 push {r7} + 80042fa: b083 sub sp, #12 + 80042fc: af00 add r7, sp, #0 + 80042fe: 6078 str r0, [r7, #4] + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_AbortCallback can be implemented in the user file + */ +} + 8004300: bf00 nop + 8004302: 370c adds r7, #12 + 8004304: 46bd mov sp, r7 + 8004306: f85d 7b04 ldr.w r7, [sp], #4 + 800430a: 4770 bx lr + +0800430c : + * @param pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that + * contains all CSD register parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD) +{ + 800430c: b480 push {r7} + 800430e: b083 sub sp, #12 + 8004310: af00 add r7, sp, #0 + 8004312: 6078 str r0, [r7, #4] + 8004314: 6039 str r1, [r7, #0] + pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U); + 8004316: 687b ldr r3, [r7, #4] + 8004318: 6e5b ldr r3, [r3, #100] @ 0x64 + 800431a: 0f9b lsrs r3, r3, #30 + 800431c: b2da uxtb r2, r3 + 800431e: 683b ldr r3, [r7, #0] + 8004320: 701a strb r2, [r3, #0] + + pCSD->SysSpecVersion = (uint8_t)((hsd->CSD[0] & 0x3C000000U) >> 26U); + 8004322: 687b ldr r3, [r7, #4] + 8004324: 6e5b ldr r3, [r3, #100] @ 0x64 + 8004326: 0e9b lsrs r3, r3, #26 + 8004328: b2db uxtb r3, r3 + 800432a: f003 030f and.w r3, r3, #15 + 800432e: b2da uxtb r2, r3 + 8004330: 683b ldr r3, [r7, #0] + 8004332: 705a strb r2, [r3, #1] + + pCSD->Reserved1 = (uint8_t)((hsd->CSD[0] & 0x03000000U) >> 24U); + 8004334: 687b ldr r3, [r7, #4] + 8004336: 6e5b ldr r3, [r3, #100] @ 0x64 + 8004338: 0e1b lsrs r3, r3, #24 + 800433a: b2db uxtb r3, r3 + 800433c: f003 0303 and.w r3, r3, #3 + 8004340: b2da uxtb r2, r3 + 8004342: 683b ldr r3, [r7, #0] + 8004344: 709a strb r2, [r3, #2] + + pCSD->TAAC = (uint8_t)((hsd->CSD[0] & 0x00FF0000U) >> 16U); + 8004346: 687b ldr r3, [r7, #4] + 8004348: 6e5b ldr r3, [r3, #100] @ 0x64 + 800434a: 0c1b lsrs r3, r3, #16 + 800434c: b2da uxtb r2, r3 + 800434e: 683b ldr r3, [r7, #0] + 8004350: 70da strb r2, [r3, #3] + + pCSD->NSAC = (uint8_t)((hsd->CSD[0] & 0x0000FF00U) >> 8U); + 8004352: 687b ldr r3, [r7, #4] + 8004354: 6e5b ldr r3, [r3, #100] @ 0x64 + 8004356: 0a1b lsrs r3, r3, #8 + 8004358: b2da uxtb r2, r3 + 800435a: 683b ldr r3, [r7, #0] + 800435c: 711a strb r2, [r3, #4] + + pCSD->MaxBusClkFrec = (uint8_t)(hsd->CSD[0] & 0x000000FFU); + 800435e: 687b ldr r3, [r7, #4] + 8004360: 6e5b ldr r3, [r3, #100] @ 0x64 + 8004362: b2da uxtb r2, r3 + 8004364: 683b ldr r3, [r7, #0] + 8004366: 715a strb r2, [r3, #5] + + pCSD->CardComdClasses = (uint16_t)((hsd->CSD[1] & 0xFFF00000U) >> 20U); + 8004368: 687b ldr r3, [r7, #4] + 800436a: 6e9b ldr r3, [r3, #104] @ 0x68 + 800436c: 0d1b lsrs r3, r3, #20 + 800436e: b29a uxth r2, r3 + 8004370: 683b ldr r3, [r7, #0] + 8004372: 80da strh r2, [r3, #6] + + pCSD->RdBlockLen = (uint8_t)((hsd->CSD[1] & 0x000F0000U) >> 16U); + 8004374: 687b ldr r3, [r7, #4] + 8004376: 6e9b ldr r3, [r3, #104] @ 0x68 + 8004378: 0c1b lsrs r3, r3, #16 + 800437a: b2db uxtb r3, r3 + 800437c: f003 030f and.w r3, r3, #15 + 8004380: b2da uxtb r2, r3 + 8004382: 683b ldr r3, [r7, #0] + 8004384: 721a strb r2, [r3, #8] + + pCSD->PartBlockRead = (uint8_t)((hsd->CSD[1] & 0x00008000U) >> 15U); + 8004386: 687b ldr r3, [r7, #4] + 8004388: 6e9b ldr r3, [r3, #104] @ 0x68 + 800438a: 0bdb lsrs r3, r3, #15 + 800438c: b2db uxtb r3, r3 + 800438e: f003 0301 and.w r3, r3, #1 + 8004392: b2da uxtb r2, r3 + 8004394: 683b ldr r3, [r7, #0] + 8004396: 725a strb r2, [r3, #9] + + pCSD->WrBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00004000U) >> 14U); + 8004398: 687b ldr r3, [r7, #4] + 800439a: 6e9b ldr r3, [r3, #104] @ 0x68 + 800439c: 0b9b lsrs r3, r3, #14 + 800439e: b2db uxtb r3, r3 + 80043a0: f003 0301 and.w r3, r3, #1 + 80043a4: b2da uxtb r2, r3 + 80043a6: 683b ldr r3, [r7, #0] + 80043a8: 729a strb r2, [r3, #10] + + pCSD->RdBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00002000U) >> 13U); + 80043aa: 687b ldr r3, [r7, #4] + 80043ac: 6e9b ldr r3, [r3, #104] @ 0x68 + 80043ae: 0b5b lsrs r3, r3, #13 + 80043b0: b2db uxtb r3, r3 + 80043b2: f003 0301 and.w r3, r3, #1 + 80043b6: b2da uxtb r2, r3 + 80043b8: 683b ldr r3, [r7, #0] + 80043ba: 72da strb r2, [r3, #11] + + pCSD->DSRImpl = (uint8_t)((hsd->CSD[1] & 0x00001000U) >> 12U); + 80043bc: 687b ldr r3, [r7, #4] + 80043be: 6e9b ldr r3, [r3, #104] @ 0x68 + 80043c0: 0b1b lsrs r3, r3, #12 + 80043c2: b2db uxtb r3, r3 + 80043c4: f003 0301 and.w r3, r3, #1 + 80043c8: b2da uxtb r2, r3 + 80043ca: 683b ldr r3, [r7, #0] + 80043cc: 731a strb r2, [r3, #12] + + pCSD->Reserved2 = 0U; /*!< Reserved */ + 80043ce: 683b ldr r3, [r7, #0] + 80043d0: 2200 movs r2, #0 + 80043d2: 735a strb r2, [r3, #13] + + if(hsd->SdCard.CardType == CARD_SDSC) + 80043d4: 687b ldr r3, [r7, #4] + 80043d6: 6c5b ldr r3, [r3, #68] @ 0x44 + 80043d8: 2b00 cmp r3, #0 + 80043da: d163 bne.n 80044a4 + { + pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U)); + 80043dc: 687b ldr r3, [r7, #4] + 80043de: 6e9b ldr r3, [r3, #104] @ 0x68 + 80043e0: 009a lsls r2, r3, #2 + 80043e2: f640 73fc movw r3, #4092 @ 0xffc + 80043e6: 4013 ands r3, r2 + 80043e8: 687a ldr r2, [r7, #4] + 80043ea: 6ed2 ldr r2, [r2, #108] @ 0x6c + 80043ec: 0f92 lsrs r2, r2, #30 + 80043ee: 431a orrs r2, r3 + 80043f0: 683b ldr r3, [r7, #0] + 80043f2: 611a str r2, [r3, #16] + + pCSD->MaxRdCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x38000000U) >> 27U); + 80043f4: 687b ldr r3, [r7, #4] + 80043f6: 6edb ldr r3, [r3, #108] @ 0x6c + 80043f8: 0edb lsrs r3, r3, #27 + 80043fa: b2db uxtb r3, r3 + 80043fc: f003 0307 and.w r3, r3, #7 + 8004400: b2da uxtb r2, r3 + 8004402: 683b ldr r3, [r7, #0] + 8004404: 751a strb r2, [r3, #20] + + pCSD->MaxRdCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x07000000U) >> 24U); + 8004406: 687b ldr r3, [r7, #4] + 8004408: 6edb ldr r3, [r3, #108] @ 0x6c + 800440a: 0e1b lsrs r3, r3, #24 + 800440c: b2db uxtb r3, r3 + 800440e: f003 0307 and.w r3, r3, #7 + 8004412: b2da uxtb r2, r3 + 8004414: 683b ldr r3, [r7, #0] + 8004416: 755a strb r2, [r3, #21] + + pCSD->MaxWrCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x00E00000U) >> 21U); + 8004418: 687b ldr r3, [r7, #4] + 800441a: 6edb ldr r3, [r3, #108] @ 0x6c + 800441c: 0d5b lsrs r3, r3, #21 + 800441e: b2db uxtb r3, r3 + 8004420: f003 0307 and.w r3, r3, #7 + 8004424: b2da uxtb r2, r3 + 8004426: 683b ldr r3, [r7, #0] + 8004428: 759a strb r2, [r3, #22] + + pCSD->MaxWrCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x001C0000U) >> 18U); + 800442a: 687b ldr r3, [r7, #4] + 800442c: 6edb ldr r3, [r3, #108] @ 0x6c + 800442e: 0c9b lsrs r3, r3, #18 + 8004430: b2db uxtb r3, r3 + 8004432: f003 0307 and.w r3, r3, #7 + 8004436: b2da uxtb r2, r3 + 8004438: 683b ldr r3, [r7, #0] + 800443a: 75da strb r2, [r3, #23] + + pCSD->DeviceSizeMul = (uint8_t)((hsd->CSD[2] & 0x00038000U) >> 15U); + 800443c: 687b ldr r3, [r7, #4] + 800443e: 6edb ldr r3, [r3, #108] @ 0x6c + 8004440: 0bdb lsrs r3, r3, #15 + 8004442: b2db uxtb r3, r3 + 8004444: f003 0307 and.w r3, r3, #7 + 8004448: b2da uxtb r2, r3 + 800444a: 683b ldr r3, [r7, #0] + 800444c: 761a strb r2, [r3, #24] + + hsd->SdCard.BlockNbr = (pCSD->DeviceSize + 1U) ; + 800444e: 683b ldr r3, [r7, #0] + 8004450: 691b ldr r3, [r3, #16] + 8004452: 1c5a adds r2, r3, #1 + 8004454: 687b ldr r3, [r7, #4] + 8004456: 655a str r2, [r3, #84] @ 0x54 + hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); + 8004458: 683b ldr r3, [r7, #0] + 800445a: 7e1b ldrb r3, [r3, #24] + 800445c: b2db uxtb r3, r3 + 800445e: f003 0307 and.w r3, r3, #7 + 8004462: 3302 adds r3, #2 + 8004464: 2201 movs r2, #1 + 8004466: fa02 f303 lsl.w r3, r2, r3 + 800446a: 687a ldr r2, [r7, #4] + 800446c: 6d52 ldr r2, [r2, #84] @ 0x54 + 800446e: fb03 f202 mul.w r2, r3, r2 + 8004472: 687b ldr r3, [r7, #4] + 8004474: 655a str r2, [r3, #84] @ 0x54 + hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); + 8004476: 683b ldr r3, [r7, #0] + 8004478: 7a1b ldrb r3, [r3, #8] + 800447a: b2db uxtb r3, r3 + 800447c: f003 030f and.w r3, r3, #15 + 8004480: 2201 movs r2, #1 + 8004482: 409a lsls r2, r3 + 8004484: 687b ldr r3, [r7, #4] + 8004486: 659a str r2, [r3, #88] @ 0x58 + + hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U); + 8004488: 687b ldr r3, [r7, #4] + 800448a: 6d5b ldr r3, [r3, #84] @ 0x54 + 800448c: 687a ldr r2, [r7, #4] + 800448e: 6d92 ldr r2, [r2, #88] @ 0x58 + 8004490: 0a52 lsrs r2, r2, #9 + 8004492: fb03 f202 mul.w r2, r3, r2 + 8004496: 687b ldr r3, [r7, #4] + 8004498: 65da str r2, [r3, #92] @ 0x5c + hsd->SdCard.LogBlockSize = 512U; + 800449a: 687b ldr r3, [r7, #4] + 800449c: f44f 7200 mov.w r2, #512 @ 0x200 + 80044a0: 661a str r2, [r3, #96] @ 0x60 + 80044a2: e031 b.n 8004508 + } + else if(hsd->SdCard.CardType == CARD_SDHC_SDXC) + 80044a4: 687b ldr r3, [r7, #4] + 80044a6: 6c5b ldr r3, [r3, #68] @ 0x44 + 80044a8: 2b01 cmp r3, #1 + 80044aa: d11d bne.n 80044e8 + { + /* Byte 7 */ + pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U)); + 80044ac: 687b ldr r3, [r7, #4] + 80044ae: 6e9b ldr r3, [r3, #104] @ 0x68 + 80044b0: 041b lsls r3, r3, #16 + 80044b2: f403 127c and.w r2, r3, #4128768 @ 0x3f0000 + 80044b6: 687b ldr r3, [r7, #4] + 80044b8: 6edb ldr r3, [r3, #108] @ 0x6c + 80044ba: 0c1b lsrs r3, r3, #16 + 80044bc: 431a orrs r2, r3 + 80044be: 683b ldr r3, [r7, #0] + 80044c0: 611a str r2, [r3, #16] + + hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U); + 80044c2: 683b ldr r3, [r7, #0] + 80044c4: 691b ldr r3, [r3, #16] + 80044c6: 3301 adds r3, #1 + 80044c8: 029a lsls r2, r3, #10 + 80044ca: 687b ldr r3, [r7, #4] + 80044cc: 655a str r2, [r3, #84] @ 0x54 + hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr; + 80044ce: 687b ldr r3, [r7, #4] + 80044d0: 6d5a ldr r2, [r3, #84] @ 0x54 + 80044d2: 687b ldr r3, [r7, #4] + 80044d4: 65da str r2, [r3, #92] @ 0x5c + hsd->SdCard.BlockSize = 512U; + 80044d6: 687b ldr r3, [r7, #4] + 80044d8: f44f 7200 mov.w r2, #512 @ 0x200 + 80044dc: 659a str r2, [r3, #88] @ 0x58 + hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize; + 80044de: 687b ldr r3, [r7, #4] + 80044e0: 6d9a ldr r2, [r3, #88] @ 0x58 + 80044e2: 687b ldr r3, [r7, #4] + 80044e4: 661a str r2, [r3, #96] @ 0x60 + 80044e6: e00f b.n 8004508 + } + else + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + 80044e8: 687b ldr r3, [r7, #4] + 80044ea: 681b ldr r3, [r3, #0] + 80044ec: 4a58 ldr r2, [pc, #352] @ (8004650 ) + 80044ee: 639a str r2, [r3, #56] @ 0x38 + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + 80044f0: 687b ldr r3, [r7, #4] + 80044f2: 6b9b ldr r3, [r3, #56] @ 0x38 + 80044f4: f043 5280 orr.w r2, r3, #268435456 @ 0x10000000 + 80044f8: 687b ldr r3, [r7, #4] + 80044fa: 639a str r2, [r3, #56] @ 0x38 + hsd->State = HAL_SD_STATE_READY; + 80044fc: 687b ldr r3, [r7, #4] + 80044fe: 2201 movs r2, #1 + 8004500: f883 2034 strb.w r2, [r3, #52] @ 0x34 + return HAL_ERROR; + 8004504: 2301 movs r3, #1 + 8004506: e09d b.n 8004644 + } + + pCSD->EraseGrSize = (uint8_t)((hsd->CSD[2] & 0x00004000U) >> 14U); + 8004508: 687b ldr r3, [r7, #4] + 800450a: 6edb ldr r3, [r3, #108] @ 0x6c + 800450c: 0b9b lsrs r3, r3, #14 + 800450e: b2db uxtb r3, r3 + 8004510: f003 0301 and.w r3, r3, #1 + 8004514: b2da uxtb r2, r3 + 8004516: 683b ldr r3, [r7, #0] + 8004518: 765a strb r2, [r3, #25] + + pCSD->EraseGrMul = (uint8_t)((hsd->CSD[2] & 0x00003F80U) >> 7U); + 800451a: 687b ldr r3, [r7, #4] + 800451c: 6edb ldr r3, [r3, #108] @ 0x6c + 800451e: 09db lsrs r3, r3, #7 + 8004520: b2db uxtb r3, r3 + 8004522: f003 037f and.w r3, r3, #127 @ 0x7f + 8004526: b2da uxtb r2, r3 + 8004528: 683b ldr r3, [r7, #0] + 800452a: 769a strb r2, [r3, #26] + + pCSD->WrProtectGrSize = (uint8_t)(hsd->CSD[2] & 0x0000007FU); + 800452c: 687b ldr r3, [r7, #4] + 800452e: 6edb ldr r3, [r3, #108] @ 0x6c + 8004530: b2db uxtb r3, r3 + 8004532: f003 037f and.w r3, r3, #127 @ 0x7f + 8004536: b2da uxtb r2, r3 + 8004538: 683b ldr r3, [r7, #0] + 800453a: 76da strb r2, [r3, #27] + + pCSD->WrProtectGrEnable = (uint8_t)((hsd->CSD[3] & 0x80000000U) >> 31U); + 800453c: 687b ldr r3, [r7, #4] + 800453e: 6f1b ldr r3, [r3, #112] @ 0x70 + 8004540: 0fdb lsrs r3, r3, #31 + 8004542: b2da uxtb r2, r3 + 8004544: 683b ldr r3, [r7, #0] + 8004546: 771a strb r2, [r3, #28] + + pCSD->ManDeflECC = (uint8_t)((hsd->CSD[3] & 0x60000000U) >> 29U); + 8004548: 687b ldr r3, [r7, #4] + 800454a: 6f1b ldr r3, [r3, #112] @ 0x70 + 800454c: 0f5b lsrs r3, r3, #29 + 800454e: b2db uxtb r3, r3 + 8004550: f003 0303 and.w r3, r3, #3 + 8004554: b2da uxtb r2, r3 + 8004556: 683b ldr r3, [r7, #0] + 8004558: 775a strb r2, [r3, #29] + + pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U); + 800455a: 687b ldr r3, [r7, #4] + 800455c: 6f1b ldr r3, [r3, #112] @ 0x70 + 800455e: 0e9b lsrs r3, r3, #26 + 8004560: b2db uxtb r3, r3 + 8004562: f003 0307 and.w r3, r3, #7 + 8004566: b2da uxtb r2, r3 + 8004568: 683b ldr r3, [r7, #0] + 800456a: 779a strb r2, [r3, #30] + + pCSD->MaxWrBlockLen= (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U); + 800456c: 687b ldr r3, [r7, #4] + 800456e: 6f1b ldr r3, [r3, #112] @ 0x70 + 8004570: 0d9b lsrs r3, r3, #22 + 8004572: b2db uxtb r3, r3 + 8004574: f003 030f and.w r3, r3, #15 + 8004578: b2da uxtb r2, r3 + 800457a: 683b ldr r3, [r7, #0] + 800457c: 77da strb r2, [r3, #31] + + pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U); + 800457e: 687b ldr r3, [r7, #4] + 8004580: 6f1b ldr r3, [r3, #112] @ 0x70 + 8004582: 0d5b lsrs r3, r3, #21 + 8004584: b2db uxtb r3, r3 + 8004586: f003 0301 and.w r3, r3, #1 + 800458a: b2da uxtb r2, r3 + 800458c: 683b ldr r3, [r7, #0] + 800458e: f883 2020 strb.w r2, [r3, #32] + + pCSD->Reserved3 = 0; + 8004592: 683b ldr r3, [r7, #0] + 8004594: 2200 movs r2, #0 + 8004596: f883 2021 strb.w r2, [r3, #33] @ 0x21 + + pCSD->ContentProtectAppli = (uint8_t)((hsd->CSD[3] & 0x00010000U) >> 16U); + 800459a: 687b ldr r3, [r7, #4] + 800459c: 6f1b ldr r3, [r3, #112] @ 0x70 + 800459e: 0c1b lsrs r3, r3, #16 + 80045a0: b2db uxtb r3, r3 + 80045a2: f003 0301 and.w r3, r3, #1 + 80045a6: b2da uxtb r2, r3 + 80045a8: 683b ldr r3, [r7, #0] + 80045aa: f883 2022 strb.w r2, [r3, #34] @ 0x22 + + pCSD->FileFormatGroup = (uint8_t)((hsd->CSD[3] & 0x00008000U) >> 15U); + 80045ae: 687b ldr r3, [r7, #4] + 80045b0: 6f1b ldr r3, [r3, #112] @ 0x70 + 80045b2: 0bdb lsrs r3, r3, #15 + 80045b4: b2db uxtb r3, r3 + 80045b6: f003 0301 and.w r3, r3, #1 + 80045ba: b2da uxtb r2, r3 + 80045bc: 683b ldr r3, [r7, #0] + 80045be: f883 2023 strb.w r2, [r3, #35] @ 0x23 + + pCSD->CopyFlag = (uint8_t)((hsd->CSD[3] & 0x00004000U) >> 14U); + 80045c2: 687b ldr r3, [r7, #4] + 80045c4: 6f1b ldr r3, [r3, #112] @ 0x70 + 80045c6: 0b9b lsrs r3, r3, #14 + 80045c8: b2db uxtb r3, r3 + 80045ca: f003 0301 and.w r3, r3, #1 + 80045ce: b2da uxtb r2, r3 + 80045d0: 683b ldr r3, [r7, #0] + 80045d2: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + pCSD->PermWrProtect = (uint8_t)((hsd->CSD[3] & 0x00002000U) >> 13U); + 80045d6: 687b ldr r3, [r7, #4] + 80045d8: 6f1b ldr r3, [r3, #112] @ 0x70 + 80045da: 0b5b lsrs r3, r3, #13 + 80045dc: b2db uxtb r3, r3 + 80045de: f003 0301 and.w r3, r3, #1 + 80045e2: b2da uxtb r2, r3 + 80045e4: 683b ldr r3, [r7, #0] + 80045e6: f883 2025 strb.w r2, [r3, #37] @ 0x25 + + pCSD->TempWrProtect = (uint8_t)((hsd->CSD[3] & 0x00001000U) >> 12U); + 80045ea: 687b ldr r3, [r7, #4] + 80045ec: 6f1b ldr r3, [r3, #112] @ 0x70 + 80045ee: 0b1b lsrs r3, r3, #12 + 80045f0: b2db uxtb r3, r3 + 80045f2: f003 0301 and.w r3, r3, #1 + 80045f6: b2da uxtb r2, r3 + 80045f8: 683b ldr r3, [r7, #0] + 80045fa: f883 2026 strb.w r2, [r3, #38] @ 0x26 + + pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U); + 80045fe: 687b ldr r3, [r7, #4] + 8004600: 6f1b ldr r3, [r3, #112] @ 0x70 + 8004602: 0a9b lsrs r3, r3, #10 + 8004604: b2db uxtb r3, r3 + 8004606: f003 0303 and.w r3, r3, #3 + 800460a: b2da uxtb r2, r3 + 800460c: 683b ldr r3, [r7, #0] + 800460e: f883 2027 strb.w r2, [r3, #39] @ 0x27 + + pCSD->ECC= (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U); + 8004612: 687b ldr r3, [r7, #4] + 8004614: 6f1b ldr r3, [r3, #112] @ 0x70 + 8004616: 0a1b lsrs r3, r3, #8 + 8004618: b2db uxtb r3, r3 + 800461a: f003 0303 and.w r3, r3, #3 + 800461e: b2da uxtb r2, r3 + 8004620: 683b ldr r3, [r7, #0] + 8004622: f883 2028 strb.w r2, [r3, #40] @ 0x28 + + pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U); + 8004626: 687b ldr r3, [r7, #4] + 8004628: 6f1b ldr r3, [r3, #112] @ 0x70 + 800462a: 085b lsrs r3, r3, #1 + 800462c: b2db uxtb r3, r3 + 800462e: f003 037f and.w r3, r3, #127 @ 0x7f + 8004632: b2da uxtb r2, r3 + 8004634: 683b ldr r3, [r7, #0] + 8004636: f883 2029 strb.w r2, [r3, #41] @ 0x29 + + pCSD->Reserved4 = 1; + 800463a: 683b ldr r3, [r7, #0] + 800463c: 2201 movs r2, #1 + 800463e: f883 202a strb.w r2, [r3, #42] @ 0x2a + + return HAL_OK; + 8004642: 2300 movs r3, #0 +} + 8004644: 4618 mov r0, r3 + 8004646: 370c adds r7, #12 + 8004648: 46bd mov sp, r7 + 800464a: f85d 7b04 ldr.w r7, [sp], #4 + 800464e: 4770 bx lr + 8004650: 004005ff .word 0x004005ff + +08004654 : + * @arg SDIO_BUS_WIDE_4B: 4-bit data transfer + * @arg SDIO_BUS_WIDE_1B: 1-bit data transfer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode) +{ + 8004654: b5b0 push {r4, r5, r7, lr} + 8004656: b08e sub sp, #56 @ 0x38 + 8004658: af04 add r7, sp, #16 + 800465a: 6078 str r0, [r7, #4] + 800465c: 6039 str r1, [r7, #0] + SDIO_InitTypeDef Init; + uint32_t errorstate; + HAL_StatusTypeDef status = HAL_OK; + 800465e: 2300 movs r3, #0 + 8004660: f887 3027 strb.w r3, [r7, #39] @ 0x27 + + /* Check the parameters */ + assert_param(IS_SDIO_BUS_WIDE(WideMode)); + 8004664: 683b ldr r3, [r7, #0] + 8004666: 2b00 cmp r3, #0 + 8004668: d00c beq.n 8004684 + 800466a: 683b ldr r3, [r7, #0] + 800466c: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 8004670: d008 beq.n 8004684 + 8004672: 683b ldr r3, [r7, #0] + 8004674: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 8004678: d004 beq.n 8004684 + 800467a: f640 01c7 movw r1, #2247 @ 0x8c7 + 800467e: 4849 ldr r0, [pc, #292] @ (80047a4 ) + 8004680: f7fc fb58 bl 8000d34 + + /* Change State */ + hsd->State = HAL_SD_STATE_BUSY; + 8004684: 687b ldr r3, [r7, #4] + 8004686: 2203 movs r2, #3 + 8004688: f883 2034 strb.w r2, [r3, #52] @ 0x34 + + if(hsd->SdCard.CardType != CARD_SECURED) + 800468c: 687b ldr r3, [r7, #4] + 800468e: 6c5b ldr r3, [r3, #68] @ 0x44 + 8004690: 2b03 cmp r3, #3 + 8004692: d02e beq.n 80046f2 + { + if(WideMode == SDIO_BUS_WIDE_8B) + 8004694: 683b ldr r3, [r7, #0] + 8004696: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 800469a: d106 bne.n 80046aa + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + 800469c: 687b ldr r3, [r7, #4] + 800469e: 6b9b ldr r3, [r3, #56] @ 0x38 + 80046a0: f043 5280 orr.w r2, r3, #268435456 @ 0x10000000 + 80046a4: 687b ldr r3, [r7, #4] + 80046a6: 639a str r2, [r3, #56] @ 0x38 + 80046a8: e029 b.n 80046fe + } + else if(WideMode == SDIO_BUS_WIDE_4B) + 80046aa: 683b ldr r3, [r7, #0] + 80046ac: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 80046b0: d10a bne.n 80046c8 + { + errorstate = SD_WideBus_Enable(hsd); + 80046b2: 6878 ldr r0, [r7, #4] + 80046b4: f000 fa8c bl 8004bd0 + 80046b8: 6238 str r0, [r7, #32] + + hsd->ErrorCode |= errorstate; + 80046ba: 687b ldr r3, [r7, #4] + 80046bc: 6b9a ldr r2, [r3, #56] @ 0x38 + 80046be: 6a3b ldr r3, [r7, #32] + 80046c0: 431a orrs r2, r3 + 80046c2: 687b ldr r3, [r7, #4] + 80046c4: 639a str r2, [r3, #56] @ 0x38 + 80046c6: e01a b.n 80046fe + } + else if(WideMode == SDIO_BUS_WIDE_1B) + 80046c8: 683b ldr r3, [r7, #0] + 80046ca: 2b00 cmp r3, #0 + 80046cc: d10a bne.n 80046e4 + { + errorstate = SD_WideBus_Disable(hsd); + 80046ce: 6878 ldr r0, [r7, #4] + 80046d0: f000 fac9 bl 8004c66 + 80046d4: 6238 str r0, [r7, #32] + + hsd->ErrorCode |= errorstate; + 80046d6: 687b ldr r3, [r7, #4] + 80046d8: 6b9a ldr r2, [r3, #56] @ 0x38 + 80046da: 6a3b ldr r3, [r7, #32] + 80046dc: 431a orrs r2, r3 + 80046de: 687b ldr r3, [r7, #4] + 80046e0: 639a str r2, [r3, #56] @ 0x38 + 80046e2: e00c b.n 80046fe + } + else + { + /* WideMode is not a valid argument*/ + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + 80046e4: 687b ldr r3, [r7, #4] + 80046e6: 6b9b ldr r3, [r3, #56] @ 0x38 + 80046e8: f043 6200 orr.w r2, r3, #134217728 @ 0x8000000 + 80046ec: 687b ldr r3, [r7, #4] + 80046ee: 639a str r2, [r3, #56] @ 0x38 + 80046f0: e005 b.n 80046fe + } + } + else + { + /* MMC Card does not support this feature */ + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + 80046f2: 687b ldr r3, [r7, #4] + 80046f4: 6b9b ldr r3, [r3, #56] @ 0x38 + 80046f6: f043 5280 orr.w r2, r3, #268435456 @ 0x10000000 + 80046fa: 687b ldr r3, [r7, #4] + 80046fc: 639a str r2, [r3, #56] @ 0x38 + } + + if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + 80046fe: 687b ldr r3, [r7, #4] + 8004700: 6b9b ldr r3, [r3, #56] @ 0x38 + 8004702: 2b00 cmp r3, #0 + 8004704: d00b beq.n 800471e + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + 8004706: 687b ldr r3, [r7, #4] + 8004708: 681b ldr r3, [r3, #0] + 800470a: 4a27 ldr r2, [pc, #156] @ (80047a8 ) + 800470c: 639a str r2, [r3, #56] @ 0x38 + hsd->State = HAL_SD_STATE_READY; + 800470e: 687b ldr r3, [r7, #4] + 8004710: 2201 movs r2, #1 + 8004712: f883 2034 strb.w r2, [r3, #52] @ 0x34 + status = HAL_ERROR; + 8004716: 2301 movs r3, #1 + 8004718: f887 3027 strb.w r3, [r7, #39] @ 0x27 + 800471c: e01f b.n 800475e + } + else + { + /* Configure the SDIO peripheral */ + Init.ClockEdge = hsd->Init.ClockEdge; + 800471e: 687b ldr r3, [r7, #4] + 8004720: 685b ldr r3, [r3, #4] + 8004722: 60bb str r3, [r7, #8] + Init.ClockBypass = hsd->Init.ClockBypass; + 8004724: 687b ldr r3, [r7, #4] + 8004726: 689b ldr r3, [r3, #8] + 8004728: 60fb str r3, [r7, #12] + Init.ClockPowerSave = hsd->Init.ClockPowerSave; + 800472a: 687b ldr r3, [r7, #4] + 800472c: 68db ldr r3, [r3, #12] + 800472e: 613b str r3, [r7, #16] + Init.BusWide = WideMode; + 8004730: 683b ldr r3, [r7, #0] + 8004732: 617b str r3, [r7, #20] + Init.HardwareFlowControl = hsd->Init.HardwareFlowControl; + 8004734: 687b ldr r3, [r7, #4] + 8004736: 695b ldr r3, [r3, #20] + 8004738: 61bb str r3, [r7, #24] + Init.ClockDiv = hsd->Init.ClockDiv; + 800473a: 687b ldr r3, [r7, #4] + 800473c: 699b ldr r3, [r3, #24] + 800473e: 61fb str r3, [r7, #28] + (void)SDIO_Init(hsd->Instance, Init); + 8004740: 687b ldr r3, [r7, #4] + 8004742: 681d ldr r5, [r3, #0] + 8004744: 466c mov r4, sp + 8004746: f107 0314 add.w r3, r7, #20 + 800474a: e893 0007 ldmia.w r3, {r0, r1, r2} + 800474e: e884 0007 stmia.w r4, {r0, r1, r2} + 8004752: f107 0308 add.w r3, r7, #8 + 8004756: cb0e ldmia r3, {r1, r2, r3} + 8004758: 4628 mov r0, r5 + 800475a: f001 f80d bl 8005778 + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + 800475e: 687b ldr r3, [r7, #4] + 8004760: 681b ldr r3, [r3, #0] + 8004762: f44f 7100 mov.w r1, #512 @ 0x200 + 8004766: 4618 mov r0, r3 + 8004768: f001 f9f0 bl 8005b4c + 800476c: 6238 str r0, [r7, #32] + if(errorstate != HAL_SD_ERROR_NONE) + 800476e: 6a3b ldr r3, [r7, #32] + 8004770: 2b00 cmp r3, #0 + 8004772: d00c beq.n 800478e + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + 8004774: 687b ldr r3, [r7, #4] + 8004776: 681b ldr r3, [r3, #0] + 8004778: 4a0b ldr r2, [pc, #44] @ (80047a8 ) + 800477a: 639a str r2, [r3, #56] @ 0x38 + hsd->ErrorCode |= errorstate; + 800477c: 687b ldr r3, [r7, #4] + 800477e: 6b9a ldr r2, [r3, #56] @ 0x38 + 8004780: 6a3b ldr r3, [r7, #32] + 8004782: 431a orrs r2, r3 + 8004784: 687b ldr r3, [r7, #4] + 8004786: 639a str r2, [r3, #56] @ 0x38 + status = HAL_ERROR; + 8004788: 2301 movs r3, #1 + 800478a: f887 3027 strb.w r3, [r7, #39] @ 0x27 + } + + /* Change State */ + hsd->State = HAL_SD_STATE_READY; + 800478e: 687b ldr r3, [r7, #4] + 8004790: 2201 movs r2, #1 + 8004792: f883 2034 strb.w r2, [r3, #52] @ 0x34 + + return status; + 8004796: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 +} + 800479a: 4618 mov r0, r3 + 800479c: 3728 adds r7, #40 @ 0x28 + 800479e: 46bd mov sp, r7 + 80047a0: bdb0 pop {r4, r5, r7, pc} + 80047a2: bf00 nop + 80047a4: 0800a1dc .word 0x0800a1dc + 80047a8: 004005ff .word 0x004005ff + +080047ac : + * @brief Gets the current sd card data state. + * @param hsd: pointer to SD handle + * @retval Card state + */ +HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) +{ + 80047ac: b580 push {r7, lr} + 80047ae: b086 sub sp, #24 + 80047b0: af00 add r7, sp, #0 + 80047b2: 6078 str r0, [r7, #4] + uint32_t cardstate; + uint32_t errorstate; + uint32_t resp1 = 0; + 80047b4: 2300 movs r3, #0 + 80047b6: 60fb str r3, [r7, #12] + + errorstate = SD_SendStatus(hsd, &resp1); + 80047b8: f107 030c add.w r3, r7, #12 + 80047bc: 4619 mov r1, r3 + 80047be: 6878 ldr r0, [r7, #4] + 80047c0: f000 f9de bl 8004b80 + 80047c4: 6178 str r0, [r7, #20] + if(errorstate != HAL_SD_ERROR_NONE) + 80047c6: 697b ldr r3, [r7, #20] + 80047c8: 2b00 cmp r3, #0 + 80047ca: d005 beq.n 80047d8 + { + hsd->ErrorCode |= errorstate; + 80047cc: 687b ldr r3, [r7, #4] + 80047ce: 6b9a ldr r2, [r3, #56] @ 0x38 + 80047d0: 697b ldr r3, [r7, #20] + 80047d2: 431a orrs r2, r3 + 80047d4: 687b ldr r3, [r7, #4] + 80047d6: 639a str r2, [r3, #56] @ 0x38 + } + + cardstate = ((resp1 >> 9U) & 0x0FU); + 80047d8: 68fb ldr r3, [r7, #12] + 80047da: 0a5b lsrs r3, r3, #9 + 80047dc: f003 030f and.w r3, r3, #15 + 80047e0: 613b str r3, [r7, #16] + + return (HAL_SD_CardStateTypeDef)cardstate; + 80047e2: 693b ldr r3, [r7, #16] +} + 80047e4: 4618 mov r0, r3 + 80047e6: 3718 adds r7, #24 + 80047e8: 46bd mov sp, r7 + 80047ea: bd80 pop {r7, pc} + +080047ec : + * @brief DMA SD Tx Abort callback + * @param hdma: DMA handle + * @retval None + */ +static void SD_DMATxAbort(DMA_HandleTypeDef *hdma) +{ + 80047ec: b580 push {r7, lr} + 80047ee: b084 sub sp, #16 + 80047f0: af00 add r7, sp, #0 + 80047f2: 6078 str r0, [r7, #4] + SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); + 80047f4: 687b ldr r3, [r7, #4] + 80047f6: 6b9b ldr r3, [r3, #56] @ 0x38 + 80047f8: 60fb str r3, [r7, #12] + HAL_SD_CardStateTypeDef CardState; + + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS); + 80047fa: 68fb ldr r3, [r7, #12] + 80047fc: 681b ldr r3, [r3, #0] + 80047fe: f240 523a movw r2, #1338 @ 0x53a + 8004802: 639a str r2, [r3, #56] @ 0x38 + + CardState = HAL_SD_GetCardState(hsd); + 8004804: 68f8 ldr r0, [r7, #12] + 8004806: f7ff ffd1 bl 80047ac + 800480a: 60b8 str r0, [r7, #8] + hsd->State = HAL_SD_STATE_READY; + 800480c: 68fb ldr r3, [r7, #12] + 800480e: 2201 movs r2, #1 + 8004810: f883 2034 strb.w r2, [r3, #52] @ 0x34 + hsd->Context = SD_CONTEXT_NONE; + 8004814: 68fb ldr r3, [r7, #12] + 8004816: 2200 movs r2, #0 + 8004818: 631a str r2, [r3, #48] @ 0x30 + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + 800481a: 68bb ldr r3, [r7, #8] + 800481c: 2b06 cmp r3, #6 + 800481e: d002 beq.n 8004826 + 8004820: 68bb ldr r3, [r7, #8] + 8004822: 2b05 cmp r3, #5 + 8004824: d10a bne.n 800483c + { + hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); + 8004826: 68fb ldr r3, [r7, #12] + 8004828: 681b ldr r3, [r3, #0] + 800482a: 4618 mov r0, r3 + 800482c: f001 f9b0 bl 8005b90 + 8004830: 4602 mov r2, r0 + 8004832: 68fb ldr r3, [r7, #12] + 8004834: 6b9b ldr r3, [r3, #56] @ 0x38 + 8004836: 431a orrs r2, r3 + 8004838: 68fb ldr r3, [r7, #12] + 800483a: 639a str r2, [r3, #56] @ 0x38 + } + + if(hsd->ErrorCode == HAL_SD_ERROR_NONE) + 800483c: 68fb ldr r3, [r7, #12] + 800483e: 6b9b ldr r3, [r3, #56] @ 0x38 + 8004840: 2b00 cmp r3, #0 + 8004842: d103 bne.n 800484c + { +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->AbortCpltCallback(hsd); +#else + HAL_SD_AbortCallback(hsd); + 8004844: 68f8 ldr r0, [r7, #12] + 8004846: f7ff fd57 bl 80042f8 + hsd->ErrorCallback(hsd); +#else + HAL_SD_ErrorCallback(hsd); +#endif + } +} + 800484a: e002 b.n 8004852 + HAL_SD_ErrorCallback(hsd); + 800484c: 68f8 ldr r0, [r7, #12] + 800484e: f7ff fd49 bl 80042e4 +} + 8004852: bf00 nop + 8004854: 3710 adds r7, #16 + 8004856: 46bd mov sp, r7 + 8004858: bd80 pop {r7, pc} + +0800485a : + * @brief DMA SD Rx Abort callback + * @param hdma: DMA handle + * @retval None + */ +static void SD_DMARxAbort(DMA_HandleTypeDef *hdma) +{ + 800485a: b580 push {r7, lr} + 800485c: b084 sub sp, #16 + 800485e: af00 add r7, sp, #0 + 8004860: 6078 str r0, [r7, #4] + SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); + 8004862: 687b ldr r3, [r7, #4] + 8004864: 6b9b ldr r3, [r3, #56] @ 0x38 + 8004866: 60fb str r3, [r7, #12] + HAL_SD_CardStateTypeDef CardState; + + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS); + 8004868: 68fb ldr r3, [r7, #12] + 800486a: 681b ldr r3, [r3, #0] + 800486c: f240 523a movw r2, #1338 @ 0x53a + 8004870: 639a str r2, [r3, #56] @ 0x38 + + CardState = HAL_SD_GetCardState(hsd); + 8004872: 68f8 ldr r0, [r7, #12] + 8004874: f7ff ff9a bl 80047ac + 8004878: 60b8 str r0, [r7, #8] + hsd->State = HAL_SD_STATE_READY; + 800487a: 68fb ldr r3, [r7, #12] + 800487c: 2201 movs r2, #1 + 800487e: f883 2034 strb.w r2, [r3, #52] @ 0x34 + hsd->Context = SD_CONTEXT_NONE; + 8004882: 68fb ldr r3, [r7, #12] + 8004884: 2200 movs r2, #0 + 8004886: 631a str r2, [r3, #48] @ 0x30 + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + 8004888: 68bb ldr r3, [r7, #8] + 800488a: 2b06 cmp r3, #6 + 800488c: d002 beq.n 8004894 + 800488e: 68bb ldr r3, [r7, #8] + 8004890: 2b05 cmp r3, #5 + 8004892: d10a bne.n 80048aa + { + hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); + 8004894: 68fb ldr r3, [r7, #12] + 8004896: 681b ldr r3, [r3, #0] + 8004898: 4618 mov r0, r3 + 800489a: f001 f979 bl 8005b90 + 800489e: 4602 mov r2, r0 + 80048a0: 68fb ldr r3, [r7, #12] + 80048a2: 6b9b ldr r3, [r3, #56] @ 0x38 + 80048a4: 431a orrs r2, r3 + 80048a6: 68fb ldr r3, [r7, #12] + 80048a8: 639a str r2, [r3, #56] @ 0x38 + } + + if(hsd->ErrorCode == HAL_SD_ERROR_NONE) + 80048aa: 68fb ldr r3, [r7, #12] + 80048ac: 6b9b ldr r3, [r3, #56] @ 0x38 + 80048ae: 2b00 cmp r3, #0 + 80048b0: d103 bne.n 80048ba + { +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->AbortCpltCallback(hsd); +#else + HAL_SD_AbortCallback(hsd); + 80048b2: 68f8 ldr r0, [r7, #12] + 80048b4: f7ff fd20 bl 80042f8 + hsd->ErrorCallback(hsd); +#else + HAL_SD_ErrorCallback(hsd); +#endif + } +} + 80048b8: e002 b.n 80048c0 + HAL_SD_ErrorCallback(hsd); + 80048ba: 68f8 ldr r0, [r7, #12] + 80048bc: f7ff fd12 bl 80042e4 +} + 80048c0: bf00 nop + 80048c2: 3710 adds r7, #16 + 80048c4: 46bd mov sp, r7 + 80048c6: bd80 pop {r7, pc} + +080048c8 : + * @brief Initializes the sd card. + * @param hsd: Pointer to SD handle + * @retval SD Card error state + */ +static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) +{ + 80048c8: b5b0 push {r4, r5, r7, lr} + 80048ca: b094 sub sp, #80 @ 0x50 + 80048cc: af04 add r7, sp, #16 + 80048ce: 6078 str r0, [r7, #4] + HAL_SD_CardCSDTypeDef CSD; + uint32_t errorstate; + uint16_t sd_rca = 1U; + 80048d0: 2301 movs r3, #1 + 80048d2: 81fb strh r3, [r7, #14] + + /* Check the power State */ + if(SDIO_GetPowerState(hsd->Instance) == 0U) + 80048d4: 687b ldr r3, [r7, #4] + 80048d6: 681b ldr r3, [r3, #0] + 80048d8: 4618 mov r0, r3 + 80048da: f000 fff3 bl 80058c4 + 80048de: 4603 mov r3, r0 + 80048e0: 2b00 cmp r3, #0 + 80048e2: d102 bne.n 80048ea + { + /* Power off */ + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + 80048e4: f04f 6380 mov.w r3, #67108864 @ 0x4000000 + 80048e8: e0b8 b.n 8004a5c + } + + if(hsd->SdCard.CardType != CARD_SECURED) + 80048ea: 687b ldr r3, [r7, #4] + 80048ec: 6c5b ldr r3, [r3, #68] @ 0x44 + 80048ee: 2b03 cmp r3, #3 + 80048f0: d02f beq.n 8004952 + { + /* Send CMD2 ALL_SEND_CID */ + errorstate = SDMMC_CmdSendCID(hsd->Instance); + 80048f2: 687b ldr r3, [r7, #4] + 80048f4: 681b ldr r3, [r3, #0] + 80048f6: 4618 mov r0, r3 + 80048f8: f001 fa54 bl 8005da4 + 80048fc: 63f8 str r0, [r7, #60] @ 0x3c + if(errorstate != HAL_SD_ERROR_NONE) + 80048fe: 6bfb ldr r3, [r7, #60] @ 0x3c + 8004900: 2b00 cmp r3, #0 + 8004902: d001 beq.n 8004908 + { + return errorstate; + 8004904: 6bfb ldr r3, [r7, #60] @ 0x3c + 8004906: e0a9 b.n 8004a5c + } + else + { + /* Get Card identification number data */ + hsd->CID[0U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1); + 8004908: 687b ldr r3, [r7, #4] + 800490a: 681b ldr r3, [r3, #0] + 800490c: 2100 movs r1, #0 + 800490e: 4618 mov r0, r3 + 8004910: f001 f85a bl 80059c8 + 8004914: 4602 mov r2, r0 + 8004916: 687b ldr r3, [r7, #4] + 8004918: 675a str r2, [r3, #116] @ 0x74 + hsd->CID[1U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2); + 800491a: 687b ldr r3, [r7, #4] + 800491c: 681b ldr r3, [r3, #0] + 800491e: 2104 movs r1, #4 + 8004920: 4618 mov r0, r3 + 8004922: f001 f851 bl 80059c8 + 8004926: 4602 mov r2, r0 + 8004928: 687b ldr r3, [r7, #4] + 800492a: 679a str r2, [r3, #120] @ 0x78 + hsd->CID[2U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3); + 800492c: 687b ldr r3, [r7, #4] + 800492e: 681b ldr r3, [r3, #0] + 8004930: 2108 movs r1, #8 + 8004932: 4618 mov r0, r3 + 8004934: f001 f848 bl 80059c8 + 8004938: 4602 mov r2, r0 + 800493a: 687b ldr r3, [r7, #4] + 800493c: 67da str r2, [r3, #124] @ 0x7c + hsd->CID[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4); + 800493e: 687b ldr r3, [r7, #4] + 8004940: 681b ldr r3, [r3, #0] + 8004942: 210c movs r1, #12 + 8004944: 4618 mov r0, r3 + 8004946: f001 f83f bl 80059c8 + 800494a: 4602 mov r2, r0 + 800494c: 687b ldr r3, [r7, #4] + 800494e: f8c3 2080 str.w r2, [r3, #128] @ 0x80 + } + } + + if(hsd->SdCard.CardType != CARD_SECURED) + 8004952: 687b ldr r3, [r7, #4] + 8004954: 6c5b ldr r3, [r3, #68] @ 0x44 + 8004956: 2b03 cmp r3, #3 + 8004958: d00d beq.n 8004976 + { + /* Send CMD3 SET_REL_ADDR with argument 0 */ + /* SD Card publishes its RCA. */ + errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca); + 800495a: 687b ldr r3, [r7, #4] + 800495c: 681b ldr r3, [r3, #0] + 800495e: f107 020e add.w r2, r7, #14 + 8004962: 4611 mov r1, r2 + 8004964: 4618 mov r0, r3 + 8004966: f001 fa5a bl 8005e1e + 800496a: 63f8 str r0, [r7, #60] @ 0x3c + if(errorstate != HAL_SD_ERROR_NONE) + 800496c: 6bfb ldr r3, [r7, #60] @ 0x3c + 800496e: 2b00 cmp r3, #0 + 8004970: d001 beq.n 8004976 + { + return errorstate; + 8004972: 6bfb ldr r3, [r7, #60] @ 0x3c + 8004974: e072 b.n 8004a5c + } + } + if(hsd->SdCard.CardType != CARD_SECURED) + 8004976: 687b ldr r3, [r7, #4] + 8004978: 6c5b ldr r3, [r3, #68] @ 0x44 + 800497a: 2b03 cmp r3, #3 + 800497c: d036 beq.n 80049ec + { + /* Get the SD card RCA */ + hsd->SdCard.RelCardAdd = sd_rca; + 800497e: 89fb ldrh r3, [r7, #14] + 8004980: 461a mov r2, r3 + 8004982: 687b ldr r3, [r7, #4] + 8004984: 651a str r2, [r3, #80] @ 0x50 + + /* Send CMD9 SEND_CSD with argument as card's RCA */ + errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + 8004986: 687b ldr r3, [r7, #4] + 8004988: 681a ldr r2, [r3, #0] + 800498a: 687b ldr r3, [r7, #4] + 800498c: 6d1b ldr r3, [r3, #80] @ 0x50 + 800498e: 041b lsls r3, r3, #16 + 8004990: 4619 mov r1, r3 + 8004992: 4610 mov r0, r2 + 8004994: f001 fa24 bl 8005de0 + 8004998: 63f8 str r0, [r7, #60] @ 0x3c + if(errorstate != HAL_SD_ERROR_NONE) + 800499a: 6bfb ldr r3, [r7, #60] @ 0x3c + 800499c: 2b00 cmp r3, #0 + 800499e: d001 beq.n 80049a4 + { + return errorstate; + 80049a0: 6bfb ldr r3, [r7, #60] @ 0x3c + 80049a2: e05b b.n 8004a5c + } + else + { + /* Get Card Specific Data */ + hsd->CSD[0U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1); + 80049a4: 687b ldr r3, [r7, #4] + 80049a6: 681b ldr r3, [r3, #0] + 80049a8: 2100 movs r1, #0 + 80049aa: 4618 mov r0, r3 + 80049ac: f001 f80c bl 80059c8 + 80049b0: 4602 mov r2, r0 + 80049b2: 687b ldr r3, [r7, #4] + 80049b4: 665a str r2, [r3, #100] @ 0x64 + hsd->CSD[1U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2); + 80049b6: 687b ldr r3, [r7, #4] + 80049b8: 681b ldr r3, [r3, #0] + 80049ba: 2104 movs r1, #4 + 80049bc: 4618 mov r0, r3 + 80049be: f001 f803 bl 80059c8 + 80049c2: 4602 mov r2, r0 + 80049c4: 687b ldr r3, [r7, #4] + 80049c6: 669a str r2, [r3, #104] @ 0x68 + hsd->CSD[2U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3); + 80049c8: 687b ldr r3, [r7, #4] + 80049ca: 681b ldr r3, [r3, #0] + 80049cc: 2108 movs r1, #8 + 80049ce: 4618 mov r0, r3 + 80049d0: f000 fffa bl 80059c8 + 80049d4: 4602 mov r2, r0 + 80049d6: 687b ldr r3, [r7, #4] + 80049d8: 66da str r2, [r3, #108] @ 0x6c + hsd->CSD[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4); + 80049da: 687b ldr r3, [r7, #4] + 80049dc: 681b ldr r3, [r3, #0] + 80049de: 210c movs r1, #12 + 80049e0: 4618 mov r0, r3 + 80049e2: f000 fff1 bl 80059c8 + 80049e6: 4602 mov r2, r0 + 80049e8: 687b ldr r3, [r7, #4] + 80049ea: 671a str r2, [r3, #112] @ 0x70 + } + } + + /* Get the Card Class */ + hsd->SdCard.Class = (SDIO_GetResponse(hsd->Instance, SDIO_RESP2) >> 20U); + 80049ec: 687b ldr r3, [r7, #4] + 80049ee: 681b ldr r3, [r3, #0] + 80049f0: 2104 movs r1, #4 + 80049f2: 4618 mov r0, r3 + 80049f4: f000 ffe8 bl 80059c8 + 80049f8: 4603 mov r3, r0 + 80049fa: 0d1a lsrs r2, r3, #20 + 80049fc: 687b ldr r3, [r7, #4] + 80049fe: 64da str r2, [r3, #76] @ 0x4c + + /* Get CSD parameters */ + if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK) + 8004a00: f107 0310 add.w r3, r7, #16 + 8004a04: 4619 mov r1, r3 + 8004a06: 6878 ldr r0, [r7, #4] + 8004a08: f7ff fc80 bl 800430c + 8004a0c: 4603 mov r3, r0 + 8004a0e: 2b00 cmp r3, #0 + 8004a10: d002 beq.n 8004a18 + { + return HAL_SD_ERROR_UNSUPPORTED_FEATURE; + 8004a12: f04f 5380 mov.w r3, #268435456 @ 0x10000000 + 8004a16: e021 b.n 8004a5c + } + + /* Select the Card */ + errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U)); + 8004a18: 687b ldr r3, [r7, #4] + 8004a1a: 6819 ldr r1, [r3, #0] + 8004a1c: 687b ldr r3, [r7, #4] + 8004a1e: 6d1b ldr r3, [r3, #80] @ 0x50 + 8004a20: 041b lsls r3, r3, #16 + 8004a22: 2200 movs r2, #0 + 8004a24: 461c mov r4, r3 + 8004a26: 4615 mov r5, r2 + 8004a28: 4622 mov r2, r4 + 8004a2a: 462b mov r3, r5 + 8004a2c: 4608 mov r0, r1 + 8004a2e: f001 f8d1 bl 8005bd4 + 8004a32: 63f8 str r0, [r7, #60] @ 0x3c + if(errorstate != HAL_SD_ERROR_NONE) + 8004a34: 6bfb ldr r3, [r7, #60] @ 0x3c + 8004a36: 2b00 cmp r3, #0 + 8004a38: d001 beq.n 8004a3e + { + return errorstate; + 8004a3a: 6bfb ldr r3, [r7, #60] @ 0x3c + 8004a3c: e00e b.n 8004a5c + } + + /* Configure SDIO peripheral interface */ + (void)SDIO_Init(hsd->Instance, hsd->Init); + 8004a3e: 687b ldr r3, [r7, #4] + 8004a40: 681d ldr r5, [r3, #0] + 8004a42: 687b ldr r3, [r7, #4] + 8004a44: 466c mov r4, sp + 8004a46: f103 0210 add.w r2, r3, #16 + 8004a4a: ca07 ldmia r2, {r0, r1, r2} + 8004a4c: e884 0007 stmia.w r4, {r0, r1, r2} + 8004a50: 3304 adds r3, #4 + 8004a52: cb0e ldmia r3, {r1, r2, r3} + 8004a54: 4628 mov r0, r5 + 8004a56: f000 fe8f bl 8005778 + + /* All cards are initialized */ + return HAL_SD_ERROR_NONE; + 8004a5a: 2300 movs r3, #0 +} + 8004a5c: 4618 mov r0, r3 + 8004a5e: 3740 adds r7, #64 @ 0x40 + 8004a60: 46bd mov sp, r7 + 8004a62: bdb0 pop {r4, r5, r7, pc} + +08004a64 : + * in the SD handle. + * @param hsd: Pointer to SD handle + * @retval error state + */ +static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) +{ + 8004a64: b580 push {r7, lr} + 8004a66: b086 sub sp, #24 + 8004a68: af00 add r7, sp, #0 + 8004a6a: 6078 str r0, [r7, #4] + __IO uint32_t count = 0U; + 8004a6c: 2300 movs r3, #0 + 8004a6e: 60bb str r3, [r7, #8] + uint32_t response = 0U, validvoltage = 0U; + 8004a70: 2300 movs r3, #0 + 8004a72: 617b str r3, [r7, #20] + 8004a74: 2300 movs r3, #0 + 8004a76: 613b str r3, [r7, #16] + uint32_t errorstate; + + /* CMD0: GO_IDLE_STATE */ + errorstate = SDMMC_CmdGoIdleState(hsd->Instance); + 8004a78: 687b ldr r3, [r7, #4] + 8004a7a: 681b ldr r3, [r3, #0] + 8004a7c: 4618 mov r0, r3 + 8004a7e: f001 f8cc bl 8005c1a + 8004a82: 60f8 str r0, [r7, #12] + if(errorstate != HAL_SD_ERROR_NONE) + 8004a84: 68fb ldr r3, [r7, #12] + 8004a86: 2b00 cmp r3, #0 + 8004a88: d001 beq.n 8004a8e + { + return errorstate; + 8004a8a: 68fb ldr r3, [r7, #12] + 8004a8c: e072 b.n 8004b74 + } + + /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */ + errorstate = SDMMC_CmdOperCond(hsd->Instance); + 8004a8e: 687b ldr r3, [r7, #4] + 8004a90: 681b ldr r3, [r3, #0] + 8004a92: 4618 mov r0, r3 + 8004a94: f001 f8df bl 8005c56 + 8004a98: 60f8 str r0, [r7, #12] + if(errorstate != HAL_SD_ERROR_NONE) + 8004a9a: 68fb ldr r3, [r7, #12] + 8004a9c: 2b00 cmp r3, #0 + 8004a9e: d00d beq.n 8004abc + { + hsd->SdCard.CardVersion = CARD_V1_X; + 8004aa0: 687b ldr r3, [r7, #4] + 8004aa2: 2200 movs r2, #0 + 8004aa4: 649a str r2, [r3, #72] @ 0x48 + /* CMD0: GO_IDLE_STATE */ + errorstate = SDMMC_CmdGoIdleState(hsd->Instance); + 8004aa6: 687b ldr r3, [r7, #4] + 8004aa8: 681b ldr r3, [r3, #0] + 8004aaa: 4618 mov r0, r3 + 8004aac: f001 f8b5 bl 8005c1a + 8004ab0: 60f8 str r0, [r7, #12] + if(errorstate != HAL_SD_ERROR_NONE) + 8004ab2: 68fb ldr r3, [r7, #12] + 8004ab4: 2b00 cmp r3, #0 + 8004ab6: d004 beq.n 8004ac2 + { + return errorstate; + 8004ab8: 68fb ldr r3, [r7, #12] + 8004aba: e05b b.n 8004b74 + } + + } + else + { + hsd->SdCard.CardVersion = CARD_V2_X; + 8004abc: 687b ldr r3, [r7, #4] + 8004abe: 2201 movs r2, #1 + 8004ac0: 649a str r2, [r3, #72] @ 0x48 + } + + if( hsd->SdCard.CardVersion == CARD_V2_X) + 8004ac2: 687b ldr r3, [r7, #4] + 8004ac4: 6c9b ldr r3, [r3, #72] @ 0x48 + 8004ac6: 2b01 cmp r3, #1 + 8004ac8: d137 bne.n 8004b3a + { + /* SEND CMD55 APP_CMD with RCA as 0 */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); + 8004aca: 687b ldr r3, [r7, #4] + 8004acc: 681b ldr r3, [r3, #0] + 8004ace: 2100 movs r1, #0 + 8004ad0: 4618 mov r0, r3 + 8004ad2: f001 f8df bl 8005c94 + 8004ad6: 60f8 str r0, [r7, #12] + if(errorstate != HAL_SD_ERROR_NONE) + 8004ad8: 68fb ldr r3, [r7, #12] + 8004ada: 2b00 cmp r3, #0 + 8004adc: d02d beq.n 8004b3a + { + return HAL_SD_ERROR_UNSUPPORTED_FEATURE; + 8004ade: f04f 5380 mov.w r3, #268435456 @ 0x10000000 + 8004ae2: e047 b.n 8004b74 + /* SD CARD */ + /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ + while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U)) + { + /* SEND CMD55 APP_CMD with RCA as 0 */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); + 8004ae4: 687b ldr r3, [r7, #4] + 8004ae6: 681b ldr r3, [r3, #0] + 8004ae8: 2100 movs r1, #0 + 8004aea: 4618 mov r0, r3 + 8004aec: f001 f8d2 bl 8005c94 + 8004af0: 60f8 str r0, [r7, #12] + if(errorstate != HAL_SD_ERROR_NONE) + 8004af2: 68fb ldr r3, [r7, #12] + 8004af4: 2b00 cmp r3, #0 + 8004af6: d001 beq.n 8004afc + { + return errorstate; + 8004af8: 68fb ldr r3, [r7, #12] + 8004afa: e03b b.n 8004b74 + } + + /* Send CMD41 */ + errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | SD_SWITCH_1_8V_CAPACITY); + 8004afc: 687b ldr r3, [r7, #4] + 8004afe: 681b ldr r3, [r3, #0] + 8004b00: 491e ldr r1, [pc, #120] @ (8004b7c ) + 8004b02: 4618 mov r0, r3 + 8004b04: f001 f8e8 bl 8005cd8 + 8004b08: 60f8 str r0, [r7, #12] + if(errorstate != HAL_SD_ERROR_NONE) + 8004b0a: 68fb ldr r3, [r7, #12] + 8004b0c: 2b00 cmp r3, #0 + 8004b0e: d002 beq.n 8004b16 + { + return HAL_SD_ERROR_UNSUPPORTED_FEATURE; + 8004b10: f04f 5380 mov.w r3, #268435456 @ 0x10000000 + 8004b14: e02e b.n 8004b74 + } + + /* Get command response */ + response = SDIO_GetResponse(hsd->Instance, SDIO_RESP1); + 8004b16: 687b ldr r3, [r7, #4] + 8004b18: 681b ldr r3, [r3, #0] + 8004b1a: 2100 movs r1, #0 + 8004b1c: 4618 mov r0, r3 + 8004b1e: f000 ff53 bl 80059c8 + 8004b22: 6178 str r0, [r7, #20] + + /* Get operating voltage*/ + validvoltage = (((response >> 31U) == 1U) ? 1U : 0U); + 8004b24: 697b ldr r3, [r7, #20] + 8004b26: 0fdb lsrs r3, r3, #31 + 8004b28: 2b01 cmp r3, #1 + 8004b2a: d101 bne.n 8004b30 + 8004b2c: 2301 movs r3, #1 + 8004b2e: e000 b.n 8004b32 + 8004b30: 2300 movs r3, #0 + 8004b32: 613b str r3, [r7, #16] + + count++; + 8004b34: 68bb ldr r3, [r7, #8] + 8004b36: 3301 adds r3, #1 + 8004b38: 60bb str r3, [r7, #8] + while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U)) + 8004b3a: 68bb ldr r3, [r7, #8] + 8004b3c: f64f 72fe movw r2, #65534 @ 0xfffe + 8004b40: 4293 cmp r3, r2 + 8004b42: d802 bhi.n 8004b4a + 8004b44: 693b ldr r3, [r7, #16] + 8004b46: 2b00 cmp r3, #0 + 8004b48: d0cc beq.n 8004ae4 + } + + if(count >= SDMMC_MAX_VOLT_TRIAL) + 8004b4a: 68bb ldr r3, [r7, #8] + 8004b4c: f64f 72fe movw r2, #65534 @ 0xfffe + 8004b50: 4293 cmp r3, r2 + 8004b52: d902 bls.n 8004b5a + { + return HAL_SD_ERROR_INVALID_VOLTRANGE; + 8004b54: f04f 7380 mov.w r3, #16777216 @ 0x1000000 + 8004b58: e00c b.n 8004b74 + } + + if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */ + 8004b5a: 697b ldr r3, [r7, #20] + 8004b5c: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 + 8004b60: 2b00 cmp r3, #0 + 8004b62: d003 beq.n 8004b6c + { + hsd->SdCard.CardType = CARD_SDHC_SDXC; + 8004b64: 687b ldr r3, [r7, #4] + 8004b66: 2201 movs r2, #1 + 8004b68: 645a str r2, [r3, #68] @ 0x44 + 8004b6a: e002 b.n 8004b72 + } + else + { + hsd->SdCard.CardType = CARD_SDSC; + 8004b6c: 687b ldr r3, [r7, #4] + 8004b6e: 2200 movs r2, #0 + 8004b70: 645a str r2, [r3, #68] @ 0x44 + } + + + return HAL_SD_ERROR_NONE; + 8004b72: 2300 movs r3, #0 +} + 8004b74: 4618 mov r0, r3 + 8004b76: 3718 adds r7, #24 + 8004b78: 46bd mov sp, r7 + 8004b7a: bd80 pop {r7, pc} + 8004b7c: c1100000 .word 0xc1100000 + +08004b80 : + * @param pCardStatus: pointer to the buffer that will contain the SD card + * status (Card Status register) + * @retval error state + */ +static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) +{ + 8004b80: b580 push {r7, lr} + 8004b82: b084 sub sp, #16 + 8004b84: af00 add r7, sp, #0 + 8004b86: 6078 str r0, [r7, #4] + 8004b88: 6039 str r1, [r7, #0] + uint32_t errorstate; + + if(pCardStatus == NULL) + 8004b8a: 683b ldr r3, [r7, #0] + 8004b8c: 2b00 cmp r3, #0 + 8004b8e: d102 bne.n 8004b96 + { + return HAL_SD_ERROR_PARAM; + 8004b90: f04f 6300 mov.w r3, #134217728 @ 0x8000000 + 8004b94: e018 b.n 8004bc8 + } + + /* Send Status command */ + errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + 8004b96: 687b ldr r3, [r7, #4] + 8004b98: 681a ldr r2, [r3, #0] + 8004b9a: 687b ldr r3, [r7, #4] + 8004b9c: 6d1b ldr r3, [r3, #80] @ 0x50 + 8004b9e: 041b lsls r3, r3, #16 + 8004ba0: 4619 mov r1, r3 + 8004ba2: 4610 mov r0, r2 + 8004ba4: f001 f95c bl 8005e60 + 8004ba8: 60f8 str r0, [r7, #12] + if(errorstate != HAL_SD_ERROR_NONE) + 8004baa: 68fb ldr r3, [r7, #12] + 8004bac: 2b00 cmp r3, #0 + 8004bae: d001 beq.n 8004bb4 + { + return errorstate; + 8004bb0: 68fb ldr r3, [r7, #12] + 8004bb2: e009 b.n 8004bc8 + } + + /* Get SD card status */ + *pCardStatus = SDIO_GetResponse(hsd->Instance, SDIO_RESP1); + 8004bb4: 687b ldr r3, [r7, #4] + 8004bb6: 681b ldr r3, [r3, #0] + 8004bb8: 2100 movs r1, #0 + 8004bba: 4618 mov r0, r3 + 8004bbc: f000 ff04 bl 80059c8 + 8004bc0: 4602 mov r2, r0 + 8004bc2: 683b ldr r3, [r7, #0] + 8004bc4: 601a str r2, [r3, #0] + + return HAL_SD_ERROR_NONE; + 8004bc6: 2300 movs r3, #0 +} + 8004bc8: 4618 mov r0, r3 + 8004bca: 3710 adds r7, #16 + 8004bcc: 46bd mov sp, r7 + 8004bce: bd80 pop {r7, pc} + +08004bd0 : + * @brief Enables the SDIO wide bus mode. + * @param hsd: pointer to SD handle + * @retval error state + */ +static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) +{ + 8004bd0: b580 push {r7, lr} + 8004bd2: b086 sub sp, #24 + 8004bd4: af00 add r7, sp, #0 + 8004bd6: 6078 str r0, [r7, #4] + uint32_t scr[2U] = {0U, 0U}; + 8004bd8: 2300 movs r3, #0 + 8004bda: 60fb str r3, [r7, #12] + 8004bdc: 2300 movs r3, #0 + 8004bde: 613b str r3, [r7, #16] + uint32_t errorstate; + + if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + 8004be0: 687b ldr r3, [r7, #4] + 8004be2: 681b ldr r3, [r3, #0] + 8004be4: 2100 movs r1, #0 + 8004be6: 4618 mov r0, r3 + 8004be8: f000 feee bl 80059c8 + 8004bec: 4603 mov r3, r0 + 8004bee: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8004bf2: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 + 8004bf6: d102 bne.n 8004bfe + { + return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; + 8004bf8: f44f 6300 mov.w r3, #2048 @ 0x800 + 8004bfc: e02f b.n 8004c5e + } + + /* Get SCR Register */ + errorstate = SD_FindSCR(hsd, scr); + 8004bfe: f107 030c add.w r3, r7, #12 + 8004c02: 4619 mov r1, r3 + 8004c04: 6878 ldr r0, [r7, #4] + 8004c06: f000 f879 bl 8004cfc + 8004c0a: 6178 str r0, [r7, #20] + if(errorstate != HAL_SD_ERROR_NONE) + 8004c0c: 697b ldr r3, [r7, #20] + 8004c0e: 2b00 cmp r3, #0 + 8004c10: d001 beq.n 8004c16 + { + return errorstate; + 8004c12: 697b ldr r3, [r7, #20] + 8004c14: e023 b.n 8004c5e + } + + /* If requested card supports wide bus operation */ + if((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO) + 8004c16: 693b ldr r3, [r7, #16] + 8004c18: f403 2380 and.w r3, r3, #262144 @ 0x40000 + 8004c1c: 2b00 cmp r3, #0 + 8004c1e: d01c beq.n 8004c5a + { + /* Send CMD55 APP_CMD with argument as card's RCA.*/ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + 8004c20: 687b ldr r3, [r7, #4] + 8004c22: 681a ldr r2, [r3, #0] + 8004c24: 687b ldr r3, [r7, #4] + 8004c26: 6d1b ldr r3, [r3, #80] @ 0x50 + 8004c28: 041b lsls r3, r3, #16 + 8004c2a: 4619 mov r1, r3 + 8004c2c: 4610 mov r0, r2 + 8004c2e: f001 f831 bl 8005c94 + 8004c32: 6178 str r0, [r7, #20] + if(errorstate != HAL_SD_ERROR_NONE) + 8004c34: 697b ldr r3, [r7, #20] + 8004c36: 2b00 cmp r3, #0 + 8004c38: d001 beq.n 8004c3e + { + return errorstate; + 8004c3a: 697b ldr r3, [r7, #20] + 8004c3c: e00f b.n 8004c5e + } + + /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ + errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U); + 8004c3e: 687b ldr r3, [r7, #4] + 8004c40: 681b ldr r3, [r3, #0] + 8004c42: 2102 movs r1, #2 + 8004c44: 4618 mov r0, r3 + 8004c46: f001 f86a bl 8005d1e + 8004c4a: 6178 str r0, [r7, #20] + if(errorstate != HAL_SD_ERROR_NONE) + 8004c4c: 697b ldr r3, [r7, #20] + 8004c4e: 2b00 cmp r3, #0 + 8004c50: d001 beq.n 8004c56 + { + return errorstate; + 8004c52: 697b ldr r3, [r7, #20] + 8004c54: e003 b.n 8004c5e + } + + return HAL_SD_ERROR_NONE; + 8004c56: 2300 movs r3, #0 + 8004c58: e001 b.n 8004c5e + } + else + { + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + 8004c5a: f04f 6380 mov.w r3, #67108864 @ 0x4000000 + } +} + 8004c5e: 4618 mov r0, r3 + 8004c60: 3718 adds r7, #24 + 8004c62: 46bd mov sp, r7 + 8004c64: bd80 pop {r7, pc} + +08004c66 : + * @brief Disables the SDIO wide bus mode. + * @param hsd: Pointer to SD handle + * @retval error state + */ +static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) +{ + 8004c66: b580 push {r7, lr} + 8004c68: b086 sub sp, #24 + 8004c6a: af00 add r7, sp, #0 + 8004c6c: 6078 str r0, [r7, #4] + uint32_t scr[2U] = {0U, 0U}; + 8004c6e: 2300 movs r3, #0 + 8004c70: 60fb str r3, [r7, #12] + 8004c72: 2300 movs r3, #0 + 8004c74: 613b str r3, [r7, #16] + uint32_t errorstate; + + if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + 8004c76: 687b ldr r3, [r7, #4] + 8004c78: 681b ldr r3, [r3, #0] + 8004c7a: 2100 movs r1, #0 + 8004c7c: 4618 mov r0, r3 + 8004c7e: f000 fea3 bl 80059c8 + 8004c82: 4603 mov r3, r0 + 8004c84: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8004c88: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 + 8004c8c: d102 bne.n 8004c94 + { + return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; + 8004c8e: f44f 6300 mov.w r3, #2048 @ 0x800 + 8004c92: e02f b.n 8004cf4 + } + + /* Get SCR Register */ + errorstate = SD_FindSCR(hsd, scr); + 8004c94: f107 030c add.w r3, r7, #12 + 8004c98: 4619 mov r1, r3 + 8004c9a: 6878 ldr r0, [r7, #4] + 8004c9c: f000 f82e bl 8004cfc + 8004ca0: 6178 str r0, [r7, #20] + if(errorstate != HAL_SD_ERROR_NONE) + 8004ca2: 697b ldr r3, [r7, #20] + 8004ca4: 2b00 cmp r3, #0 + 8004ca6: d001 beq.n 8004cac + { + return errorstate; + 8004ca8: 697b ldr r3, [r7, #20] + 8004caa: e023 b.n 8004cf4 + } + + /* If requested card supports 1 bit mode operation */ + if((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO) + 8004cac: 693b ldr r3, [r7, #16] + 8004cae: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8004cb2: 2b00 cmp r3, #0 + 8004cb4: d01c beq.n 8004cf0 + { + /* Send CMD55 APP_CMD with argument as card's RCA */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + 8004cb6: 687b ldr r3, [r7, #4] + 8004cb8: 681a ldr r2, [r3, #0] + 8004cba: 687b ldr r3, [r7, #4] + 8004cbc: 6d1b ldr r3, [r3, #80] @ 0x50 + 8004cbe: 041b lsls r3, r3, #16 + 8004cc0: 4619 mov r1, r3 + 8004cc2: 4610 mov r0, r2 + 8004cc4: f000 ffe6 bl 8005c94 + 8004cc8: 6178 str r0, [r7, #20] + if(errorstate != HAL_SD_ERROR_NONE) + 8004cca: 697b ldr r3, [r7, #20] + 8004ccc: 2b00 cmp r3, #0 + 8004cce: d001 beq.n 8004cd4 + { + return errorstate; + 8004cd0: 697b ldr r3, [r7, #20] + 8004cd2: e00f b.n 8004cf4 + } + + /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */ + errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U); + 8004cd4: 687b ldr r3, [r7, #4] + 8004cd6: 681b ldr r3, [r3, #0] + 8004cd8: 2100 movs r1, #0 + 8004cda: 4618 mov r0, r3 + 8004cdc: f001 f81f bl 8005d1e + 8004ce0: 6178 str r0, [r7, #20] + if(errorstate != HAL_SD_ERROR_NONE) + 8004ce2: 697b ldr r3, [r7, #20] + 8004ce4: 2b00 cmp r3, #0 + 8004ce6: d001 beq.n 8004cec + { + return errorstate; + 8004ce8: 697b ldr r3, [r7, #20] + 8004cea: e003 b.n 8004cf4 + } + + return HAL_SD_ERROR_NONE; + 8004cec: 2300 movs r3, #0 + 8004cee: e001 b.n 8004cf4 + } + else + { + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + 8004cf0: f04f 6380 mov.w r3, #67108864 @ 0x4000000 + } +} + 8004cf4: 4618 mov r0, r3 + 8004cf6: 3718 adds r7, #24 + 8004cf8: 46bd mov sp, r7 + 8004cfa: bd80 pop {r7, pc} + +08004cfc : + * @param hsd: Pointer to SD handle + * @param pSCR: pointer to the buffer that will contain the SCR value + * @retval error state + */ +static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) +{ + 8004cfc: b590 push {r4, r7, lr} + 8004cfe: b08f sub sp, #60 @ 0x3c + 8004d00: af00 add r7, sp, #0 + 8004d02: 6078 str r0, [r7, #4] + 8004d04: 6039 str r1, [r7, #0] + SDIO_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + 8004d06: f7fc fb97 bl 8001438 + 8004d0a: 6338 str r0, [r7, #48] @ 0x30 + uint32_t index = 0U; + 8004d0c: 2300 movs r3, #0 + 8004d0e: 637b str r3, [r7, #52] @ 0x34 + uint32_t tempscr[2U] = {0U, 0U}; + 8004d10: 2300 movs r3, #0 + 8004d12: 60bb str r3, [r7, #8] + 8004d14: 2300 movs r3, #0 + 8004d16: 60fb str r3, [r7, #12] + uint32_t *scr = pSCR; + 8004d18: 683b ldr r3, [r7, #0] + 8004d1a: 62fb str r3, [r7, #44] @ 0x2c + + /* Set Block Size To 8 Bytes */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U); + 8004d1c: 687b ldr r3, [r7, #4] + 8004d1e: 681b ldr r3, [r3, #0] + 8004d20: 2108 movs r1, #8 + 8004d22: 4618 mov r0, r3 + 8004d24: f000 ff12 bl 8005b4c + 8004d28: 62b8 str r0, [r7, #40] @ 0x28 + if(errorstate != HAL_SD_ERROR_NONE) + 8004d2a: 6abb ldr r3, [r7, #40] @ 0x28 + 8004d2c: 2b00 cmp r3, #0 + 8004d2e: d001 beq.n 8004d34 + { + return errorstate; + 8004d30: 6abb ldr r3, [r7, #40] @ 0x28 + 8004d32: e0b9 b.n 8004ea8 + } + + /* Send CMD55 APP_CMD with argument as card's RCA */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U)); + 8004d34: 687b ldr r3, [r7, #4] + 8004d36: 681a ldr r2, [r3, #0] + 8004d38: 687b ldr r3, [r7, #4] + 8004d3a: 6d1b ldr r3, [r3, #80] @ 0x50 + 8004d3c: 041b lsls r3, r3, #16 + 8004d3e: 4619 mov r1, r3 + 8004d40: 4610 mov r0, r2 + 8004d42: f000 ffa7 bl 8005c94 + 8004d46: 62b8 str r0, [r7, #40] @ 0x28 + if(errorstate != HAL_SD_ERROR_NONE) + 8004d48: 6abb ldr r3, [r7, #40] @ 0x28 + 8004d4a: 2b00 cmp r3, #0 + 8004d4c: d001 beq.n 8004d52 + { + return errorstate; + 8004d4e: 6abb ldr r3, [r7, #40] @ 0x28 + 8004d50: e0aa b.n 8004ea8 + } + + config.DataTimeOut = SDMMC_DATATIMEOUT; + 8004d52: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 8004d56: 613b str r3, [r7, #16] + config.DataLength = 8U; + 8004d58: 2308 movs r3, #8 + 8004d5a: 617b str r3, [r7, #20] + config.DataBlockSize = SDIO_DATABLOCK_SIZE_8B; + 8004d5c: 2330 movs r3, #48 @ 0x30 + 8004d5e: 61bb str r3, [r7, #24] + config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + 8004d60: 2302 movs r3, #2 + 8004d62: 61fb str r3, [r7, #28] + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + 8004d64: 2300 movs r3, #0 + 8004d66: 623b str r3, [r7, #32] + config.DPSM = SDIO_DPSM_ENABLE; + 8004d68: 2301 movs r3, #1 + 8004d6a: 627b str r3, [r7, #36] @ 0x24 + (void)SDIO_ConfigData(hsd->Instance, &config); + 8004d6c: 687b ldr r3, [r7, #4] + 8004d6e: 681b ldr r3, [r3, #0] + 8004d70: f107 0210 add.w r2, r7, #16 + 8004d74: 4611 mov r1, r2 + 8004d76: 4618 mov r0, r3 + 8004d78: f000 fe4a bl 8005a10 + + /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */ + errorstate = SDMMC_CmdSendSCR(hsd->Instance); + 8004d7c: 687b ldr r3, [r7, #4] + 8004d7e: 681b ldr r3, [r3, #0] + 8004d80: 4618 mov r0, r3 + 8004d82: f000 ffee bl 8005d62 + 8004d86: 62b8 str r0, [r7, #40] @ 0x28 + if(errorstate != HAL_SD_ERROR_NONE) + 8004d88: 6abb ldr r3, [r7, #40] @ 0x28 + 8004d8a: 2b00 cmp r3, #0 + 8004d8c: d02a beq.n 8004de4 + { + return errorstate; + 8004d8e: 6abb ldr r3, [r7, #40] @ 0x28 + 8004d90: e08a b.n 8004ea8 + } + + while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT)) + { + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) + 8004d92: 687b ldr r3, [r7, #4] + 8004d94: 681b ldr r3, [r3, #0] + 8004d96: 6b5b ldr r3, [r3, #52] @ 0x34 + 8004d98: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 8004d9c: 2b00 cmp r3, #0 + 8004d9e: d00f beq.n 8004dc0 + { + *(tempscr + index) = SDIO_ReadFIFO(hsd->Instance); + 8004da0: 687b ldr r3, [r7, #4] + 8004da2: 6819 ldr r1, [r3, #0] + 8004da4: 6b7b ldr r3, [r7, #52] @ 0x34 + 8004da6: 009b lsls r3, r3, #2 + 8004da8: f107 0208 add.w r2, r7, #8 + 8004dac: 18d4 adds r4, r2, r3 + 8004dae: 4608 mov r0, r1 + 8004db0: f000 fd5c bl 800586c + 8004db4: 4603 mov r3, r0 + 8004db6: 6023 str r3, [r4, #0] + index++; + 8004db8: 6b7b ldr r3, [r7, #52] @ 0x34 + 8004dba: 3301 adds r3, #1 + 8004dbc: 637b str r3, [r7, #52] @ 0x34 + 8004dbe: e006 b.n 8004dce + } + else if(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXACT)) + 8004dc0: 687b ldr r3, [r7, #4] + 8004dc2: 681b ldr r3, [r3, #0] + 8004dc4: 6b5b ldr r3, [r3, #52] @ 0x34 + 8004dc6: f403 5300 and.w r3, r3, #8192 @ 0x2000 + 8004dca: 2b00 cmp r3, #0 + 8004dcc: d012 beq.n 8004df4 + { + break; + } + + if((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) + 8004dce: f7fc fb33 bl 8001438 + 8004dd2: 4602 mov r2, r0 + 8004dd4: 6b3b ldr r3, [r7, #48] @ 0x30 + 8004dd6: 1ad3 subs r3, r2, r3 + 8004dd8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8004ddc: d102 bne.n 8004de4 + { + return HAL_SD_ERROR_TIMEOUT; + 8004dde: f04f 4300 mov.w r3, #2147483648 @ 0x80000000 + 8004de2: e061 b.n 8004ea8 + while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT)) + 8004de4: 687b ldr r3, [r7, #4] + 8004de6: 681b ldr r3, [r3, #0] + 8004de8: 6b5b ldr r3, [r3, #52] @ 0x34 + 8004dea: f003 032a and.w r3, r3, #42 @ 0x2a + 8004dee: 2b00 cmp r3, #0 + 8004df0: d0cf beq.n 8004d92 + 8004df2: e000 b.n 8004df6 + break; + 8004df4: bf00 nop + } + } + +#if defined(SDIO_STA_STBITERR) + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR))) + 8004df6: 687b ldr r3, [r7, #4] + 8004df8: 681b ldr r3, [r3, #0] + 8004dfa: 6b5b ldr r3, [r3, #52] @ 0x34 + 8004dfc: f003 0308 and.w r3, r3, #8 + 8004e00: 2b00 cmp r3, #0 + 8004e02: d106 bne.n 8004e12 + 8004e04: 687b ldr r3, [r7, #4] + 8004e06: 681b ldr r3, [r3, #0] + 8004e08: 6b5b ldr r3, [r3, #52] @ 0x34 + 8004e0a: f403 7300 and.w r3, r3, #512 @ 0x200 + 8004e0e: 2b00 cmp r3, #0 + 8004e10: d005 beq.n 8004e1e +#else /* SDIO_STA_STBITERR not defined */ + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) +#endif /* SDIO_STA_STBITERR */ + { + __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT); + 8004e12: 687b ldr r3, [r7, #4] + 8004e14: 681b ldr r3, [r3, #0] + 8004e16: 2208 movs r2, #8 + 8004e18: 639a str r2, [r3, #56] @ 0x38 + + return HAL_SD_ERROR_DATA_TIMEOUT; + 8004e1a: 2308 movs r3, #8 + 8004e1c: e044 b.n 8004ea8 + } + else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) + 8004e1e: 687b ldr r3, [r7, #4] + 8004e20: 681b ldr r3, [r3, #0] + 8004e22: 6b5b ldr r3, [r3, #52] @ 0x34 + 8004e24: f003 0302 and.w r3, r3, #2 + 8004e28: 2b00 cmp r3, #0 + 8004e2a: d005 beq.n 8004e38 + { + __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL); + 8004e2c: 687b ldr r3, [r7, #4] + 8004e2e: 681b ldr r3, [r3, #0] + 8004e30: 2202 movs r2, #2 + 8004e32: 639a str r2, [r3, #56] @ 0x38 + + return HAL_SD_ERROR_DATA_CRC_FAIL; + 8004e34: 2302 movs r3, #2 + 8004e36: e037 b.n 8004ea8 + } + else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR)) + 8004e38: 687b ldr r3, [r7, #4] + 8004e3a: 681b ldr r3, [r3, #0] + 8004e3c: 6b5b ldr r3, [r3, #52] @ 0x34 + 8004e3e: f003 0320 and.w r3, r3, #32 + 8004e42: 2b00 cmp r3, #0 + 8004e44: d005 beq.n 8004e52 + { + __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR); + 8004e46: 687b ldr r3, [r7, #4] + 8004e48: 681b ldr r3, [r3, #0] + 8004e4a: 2220 movs r2, #32 + 8004e4c: 639a str r2, [r3, #56] @ 0x38 + + return HAL_SD_ERROR_RX_OVERRUN; + 8004e4e: 2320 movs r3, #32 + 8004e50: e02a b.n 8004ea8 + } + else + { + /* No error flag set */ + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS); + 8004e52: 687b ldr r3, [r7, #4] + 8004e54: 681b ldr r3, [r3, #0] + 8004e56: f240 523a movw r2, #1338 @ 0x53a + 8004e5a: 639a str r2, [r3, #56] @ 0x38 + + *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\ + 8004e5c: 68fb ldr r3, [r7, #12] + 8004e5e: 061a lsls r2, r3, #24 + 8004e60: 68fb ldr r3, [r7, #12] + 8004e62: 021b lsls r3, r3, #8 + 8004e64: f403 037f and.w r3, r3, #16711680 @ 0xff0000 + 8004e68: 431a orrs r2, r3 + ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24)); + 8004e6a: 68fb ldr r3, [r7, #12] + 8004e6c: 0a1b lsrs r3, r3, #8 + 8004e6e: f403 437f and.w r3, r3, #65280 @ 0xff00 + *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\ + 8004e72: 431a orrs r2, r3 + ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24)); + 8004e74: 68fb ldr r3, [r7, #12] + 8004e76: 0e1b lsrs r3, r3, #24 + 8004e78: 431a orrs r2, r3 + *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\ + 8004e7a: 6afb ldr r3, [r7, #44] @ 0x2c + 8004e7c: 601a str r2, [r3, #0] + scr++; + 8004e7e: 6afb ldr r3, [r7, #44] @ 0x2c + 8004e80: 3304 adds r3, #4 + 8004e82: 62fb str r3, [r7, #44] @ 0x2c + *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\ + 8004e84: 68bb ldr r3, [r7, #8] + 8004e86: 061a lsls r2, r3, #24 + 8004e88: 68bb ldr r3, [r7, #8] + 8004e8a: 021b lsls r3, r3, #8 + 8004e8c: f403 037f and.w r3, r3, #16711680 @ 0xff0000 + 8004e90: 431a orrs r2, r3 + ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24)); + 8004e92: 68bb ldr r3, [r7, #8] + 8004e94: 0a1b lsrs r3, r3, #8 + 8004e96: f403 437f and.w r3, r3, #65280 @ 0xff00 + *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\ + 8004e9a: 431a orrs r2, r3 + ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24)); + 8004e9c: 68bb ldr r3, [r7, #8] + 8004e9e: 0e1b lsrs r3, r3, #24 + 8004ea0: 431a orrs r2, r3 + *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\ + 8004ea2: 6afb ldr r3, [r7, #44] @ 0x2c + 8004ea4: 601a str r2, [r3, #0] + + } + + return HAL_SD_ERROR_NONE; + 8004ea6: 2300 movs r3, #0 +} + 8004ea8: 4618 mov r0, r3 + 8004eaa: 373c adds r7, #60 @ 0x3c + 8004eac: 46bd mov sp, r7 + 8004eae: bd90 pop {r4, r7, pc} + +08004eb0 : + * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * the configuration information. + * @retval None + */ +static void SD_Read_IT(SD_HandleTypeDef *hsd) +{ + 8004eb0: b580 push {r7, lr} + 8004eb2: b086 sub sp, #24 + 8004eb4: af00 add r7, sp, #0 + 8004eb6: 6078 str r0, [r7, #4] + uint32_t count, data, dataremaining; + uint8_t* tmp; + + tmp = hsd->pRxBuffPtr; + 8004eb8: 687b ldr r3, [r7, #4] + 8004eba: 6a9b ldr r3, [r3, #40] @ 0x28 + 8004ebc: 60fb str r3, [r7, #12] + dataremaining = hsd->RxXferSize; + 8004ebe: 687b ldr r3, [r7, #4] + 8004ec0: 6adb ldr r3, [r3, #44] @ 0x2c + 8004ec2: 613b str r3, [r7, #16] + + if (dataremaining > 0U) + 8004ec4: 693b ldr r3, [r7, #16] + 8004ec6: 2b00 cmp r3, #0 + 8004ec8: d03f beq.n 8004f4a + { + /* Read data from SDIO Rx FIFO */ + for(count = 0U; count < 8U; count++) + 8004eca: 2300 movs r3, #0 + 8004ecc: 617b str r3, [r7, #20] + 8004ece: e033 b.n 8004f38 + { + data = SDIO_ReadFIFO(hsd->Instance); + 8004ed0: 687b ldr r3, [r7, #4] + 8004ed2: 681b ldr r3, [r3, #0] + 8004ed4: 4618 mov r0, r3 + 8004ed6: f000 fcc9 bl 800586c + 8004eda: 60b8 str r0, [r7, #8] + *tmp = (uint8_t)(data & 0xFFU); + 8004edc: 68bb ldr r3, [r7, #8] + 8004ede: b2da uxtb r2, r3 + 8004ee0: 68fb ldr r3, [r7, #12] + 8004ee2: 701a strb r2, [r3, #0] + tmp++; + 8004ee4: 68fb ldr r3, [r7, #12] + 8004ee6: 3301 adds r3, #1 + 8004ee8: 60fb str r3, [r7, #12] + dataremaining--; + 8004eea: 693b ldr r3, [r7, #16] + 8004eec: 3b01 subs r3, #1 + 8004eee: 613b str r3, [r7, #16] + *tmp = (uint8_t)((data >> 8U) & 0xFFU); + 8004ef0: 68bb ldr r3, [r7, #8] + 8004ef2: 0a1b lsrs r3, r3, #8 + 8004ef4: b2da uxtb r2, r3 + 8004ef6: 68fb ldr r3, [r7, #12] + 8004ef8: 701a strb r2, [r3, #0] + tmp++; + 8004efa: 68fb ldr r3, [r7, #12] + 8004efc: 3301 adds r3, #1 + 8004efe: 60fb str r3, [r7, #12] + dataremaining--; + 8004f00: 693b ldr r3, [r7, #16] + 8004f02: 3b01 subs r3, #1 + 8004f04: 613b str r3, [r7, #16] + *tmp = (uint8_t)((data >> 16U) & 0xFFU); + 8004f06: 68bb ldr r3, [r7, #8] + 8004f08: 0c1b lsrs r3, r3, #16 + 8004f0a: b2da uxtb r2, r3 + 8004f0c: 68fb ldr r3, [r7, #12] + 8004f0e: 701a strb r2, [r3, #0] + tmp++; + 8004f10: 68fb ldr r3, [r7, #12] + 8004f12: 3301 adds r3, #1 + 8004f14: 60fb str r3, [r7, #12] + dataremaining--; + 8004f16: 693b ldr r3, [r7, #16] + 8004f18: 3b01 subs r3, #1 + 8004f1a: 613b str r3, [r7, #16] + *tmp = (uint8_t)((data >> 24U) & 0xFFU); + 8004f1c: 68bb ldr r3, [r7, #8] + 8004f1e: 0e1b lsrs r3, r3, #24 + 8004f20: b2da uxtb r2, r3 + 8004f22: 68fb ldr r3, [r7, #12] + 8004f24: 701a strb r2, [r3, #0] + tmp++; + 8004f26: 68fb ldr r3, [r7, #12] + 8004f28: 3301 adds r3, #1 + 8004f2a: 60fb str r3, [r7, #12] + dataremaining--; + 8004f2c: 693b ldr r3, [r7, #16] + 8004f2e: 3b01 subs r3, #1 + 8004f30: 613b str r3, [r7, #16] + for(count = 0U; count < 8U; count++) + 8004f32: 697b ldr r3, [r7, #20] + 8004f34: 3301 adds r3, #1 + 8004f36: 617b str r3, [r7, #20] + 8004f38: 697b ldr r3, [r7, #20] + 8004f3a: 2b07 cmp r3, #7 + 8004f3c: d9c8 bls.n 8004ed0 + } + + hsd->pRxBuffPtr = tmp; + 8004f3e: 687b ldr r3, [r7, #4] + 8004f40: 68fa ldr r2, [r7, #12] + 8004f42: 629a str r2, [r3, #40] @ 0x28 + hsd->RxXferSize = dataremaining; + 8004f44: 687b ldr r3, [r7, #4] + 8004f46: 693a ldr r2, [r7, #16] + 8004f48: 62da str r2, [r3, #44] @ 0x2c + } +} + 8004f4a: bf00 nop + 8004f4c: 3718 adds r7, #24 + 8004f4e: 46bd mov sp, r7 + 8004f50: bd80 pop {r7, pc} + +08004f52 : + * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * the configuration information. + * @retval None + */ +static void SD_Write_IT(SD_HandleTypeDef *hsd) +{ + 8004f52: b580 push {r7, lr} + 8004f54: b086 sub sp, #24 + 8004f56: af00 add r7, sp, #0 + 8004f58: 6078 str r0, [r7, #4] + uint32_t count, data, dataremaining; + uint8_t* tmp; + + tmp = hsd->pTxBuffPtr; + 8004f5a: 687b ldr r3, [r7, #4] + 8004f5c: 6a1b ldr r3, [r3, #32] + 8004f5e: 60fb str r3, [r7, #12] + dataremaining = hsd->TxXferSize; + 8004f60: 687b ldr r3, [r7, #4] + 8004f62: 6a5b ldr r3, [r3, #36] @ 0x24 + 8004f64: 613b str r3, [r7, #16] + + if (dataremaining > 0U) + 8004f66: 693b ldr r3, [r7, #16] + 8004f68: 2b00 cmp r3, #0 + 8004f6a: d043 beq.n 8004ff4 + { + /* Write data to SDIO Tx FIFO */ + for(count = 0U; count < 8U; count++) + 8004f6c: 2300 movs r3, #0 + 8004f6e: 617b str r3, [r7, #20] + 8004f70: e037 b.n 8004fe2 + { + data = (uint32_t)(*tmp); + 8004f72: 68fb ldr r3, [r7, #12] + 8004f74: 781b ldrb r3, [r3, #0] + 8004f76: 60bb str r3, [r7, #8] + tmp++; + 8004f78: 68fb ldr r3, [r7, #12] + 8004f7a: 3301 adds r3, #1 + 8004f7c: 60fb str r3, [r7, #12] + dataremaining--; + 8004f7e: 693b ldr r3, [r7, #16] + 8004f80: 3b01 subs r3, #1 + 8004f82: 613b str r3, [r7, #16] + data |= ((uint32_t)(*tmp) << 8U); + 8004f84: 68fb ldr r3, [r7, #12] + 8004f86: 781b ldrb r3, [r3, #0] + 8004f88: 021a lsls r2, r3, #8 + 8004f8a: 68bb ldr r3, [r7, #8] + 8004f8c: 4313 orrs r3, r2 + 8004f8e: 60bb str r3, [r7, #8] + tmp++; + 8004f90: 68fb ldr r3, [r7, #12] + 8004f92: 3301 adds r3, #1 + 8004f94: 60fb str r3, [r7, #12] + dataremaining--; + 8004f96: 693b ldr r3, [r7, #16] + 8004f98: 3b01 subs r3, #1 + 8004f9a: 613b str r3, [r7, #16] + data |= ((uint32_t)(*tmp) << 16U); + 8004f9c: 68fb ldr r3, [r7, #12] + 8004f9e: 781b ldrb r3, [r3, #0] + 8004fa0: 041a lsls r2, r3, #16 + 8004fa2: 68bb ldr r3, [r7, #8] + 8004fa4: 4313 orrs r3, r2 + 8004fa6: 60bb str r3, [r7, #8] + tmp++; + 8004fa8: 68fb ldr r3, [r7, #12] + 8004faa: 3301 adds r3, #1 + 8004fac: 60fb str r3, [r7, #12] + dataremaining--; + 8004fae: 693b ldr r3, [r7, #16] + 8004fb0: 3b01 subs r3, #1 + 8004fb2: 613b str r3, [r7, #16] + data |= ((uint32_t)(*tmp) << 24U); + 8004fb4: 68fb ldr r3, [r7, #12] + 8004fb6: 781b ldrb r3, [r3, #0] + 8004fb8: 061a lsls r2, r3, #24 + 8004fba: 68bb ldr r3, [r7, #8] + 8004fbc: 4313 orrs r3, r2 + 8004fbe: 60bb str r3, [r7, #8] + tmp++; + 8004fc0: 68fb ldr r3, [r7, #12] + 8004fc2: 3301 adds r3, #1 + 8004fc4: 60fb str r3, [r7, #12] + dataremaining--; + 8004fc6: 693b ldr r3, [r7, #16] + 8004fc8: 3b01 subs r3, #1 + 8004fca: 613b str r3, [r7, #16] + (void)SDIO_WriteFIFO(hsd->Instance, &data); + 8004fcc: 687b ldr r3, [r7, #4] + 8004fce: 681b ldr r3, [r3, #0] + 8004fd0: f107 0208 add.w r2, r7, #8 + 8004fd4: 4611 mov r1, r2 + 8004fd6: 4618 mov r0, r3 + 8004fd8: f000 fc55 bl 8005886 + for(count = 0U; count < 8U; count++) + 8004fdc: 697b ldr r3, [r7, #20] + 8004fde: 3301 adds r3, #1 + 8004fe0: 617b str r3, [r7, #20] + 8004fe2: 697b ldr r3, [r7, #20] + 8004fe4: 2b07 cmp r3, #7 + 8004fe6: d9c4 bls.n 8004f72 + } + + hsd->pTxBuffPtr = tmp; + 8004fe8: 687b ldr r3, [r7, #4] + 8004fea: 68fa ldr r2, [r7, #12] + 8004fec: 621a str r2, [r3, #32] + hsd->TxXferSize = dataremaining; + 8004fee: 687b ldr r3, [r7, #4] + 8004ff0: 693a ldr r2, [r7, #16] + 8004ff2: 625a str r2, [r3, #36] @ 0x24 + } +} + 8004ff4: bf00 nop + 8004ff6: 3718 adds r7, #24 + 8004ff8: 46bd mov sp, r7 + 8004ffa: bd80 pop {r7, pc} + +08004ffc : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { - 800268c: b580 push {r7, lr} - 800268e: b082 sub sp, #8 - 8002690: af00 add r7, sp, #0 - 8002692: 6078 str r0, [r7, #4] + 8004ffc: b580 push {r7, lr} + 8004ffe: b082 sub sp, #8 + 8005000: af00 add r7, sp, #0 + 8005002: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) - 8002694: 687b ldr r3, [r7, #4] - 8002696: 2b00 cmp r3, #0 - 8002698: d101 bne.n 800269e + 8005004: 687b ldr r3, [r7, #4] + 8005006: 2b00 cmp r3, #0 + 8005008: d101 bne.n 800500e { return HAL_ERROR; - 800269a: 2301 movs r3, #1 - 800269c: e0f2 b.n 8002884 + 800500a: 2301 movs r3, #1 + 800500c: e0f2 b.n 80051f4 } /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); - 800269e: 687b ldr r3, [r7, #4] - 80026a0: 681b ldr r3, [r3, #0] - 80026a2: 4a7a ldr r2, [pc, #488] @ (800288c ) - 80026a4: 4293 cmp r3, r2 - 80026a6: d045 beq.n 8002734 - 80026a8: 687b ldr r3, [r7, #4] - 80026aa: 681b ldr r3, [r3, #0] - 80026ac: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 - 80026b0: d040 beq.n 8002734 - 80026b2: 687b ldr r3, [r7, #4] - 80026b4: 681b ldr r3, [r3, #0] - 80026b6: 4a76 ldr r2, [pc, #472] @ (8002890 ) - 80026b8: 4293 cmp r3, r2 - 80026ba: d03b beq.n 8002734 - 80026bc: 687b ldr r3, [r7, #4] - 80026be: 681b ldr r3, [r3, #0] - 80026c0: 4a74 ldr r2, [pc, #464] @ (8002894 ) - 80026c2: 4293 cmp r3, r2 - 80026c4: d036 beq.n 8002734 - 80026c6: 687b ldr r3, [r7, #4] - 80026c8: 681b ldr r3, [r3, #0] - 80026ca: 4a73 ldr r2, [pc, #460] @ (8002898 ) - 80026cc: 4293 cmp r3, r2 - 80026ce: d031 beq.n 8002734 - 80026d0: 687b ldr r3, [r7, #4] - 80026d2: 681b ldr r3, [r3, #0] - 80026d4: 4a71 ldr r2, [pc, #452] @ (800289c ) - 80026d6: 4293 cmp r3, r2 - 80026d8: d02c beq.n 8002734 - 80026da: 687b ldr r3, [r7, #4] - 80026dc: 681b ldr r3, [r3, #0] - 80026de: 4a70 ldr r2, [pc, #448] @ (80028a0 ) - 80026e0: 4293 cmp r3, r2 - 80026e2: d027 beq.n 8002734 - 80026e4: 687b ldr r3, [r7, #4] - 80026e6: 681b ldr r3, [r3, #0] - 80026e8: 4a6e ldr r2, [pc, #440] @ (80028a4 ) - 80026ea: 4293 cmp r3, r2 - 80026ec: d022 beq.n 8002734 - 80026ee: 687b ldr r3, [r7, #4] - 80026f0: 681b ldr r3, [r3, #0] - 80026f2: 4a6d ldr r2, [pc, #436] @ (80028a8 ) - 80026f4: 4293 cmp r3, r2 - 80026f6: d01d beq.n 8002734 - 80026f8: 687b ldr r3, [r7, #4] - 80026fa: 681b ldr r3, [r3, #0] - 80026fc: 4a6b ldr r2, [pc, #428] @ (80028ac ) - 80026fe: 4293 cmp r3, r2 - 8002700: d018 beq.n 8002734 - 8002702: 687b ldr r3, [r7, #4] - 8002704: 681b ldr r3, [r3, #0] - 8002706: 4a6a ldr r2, [pc, #424] @ (80028b0 ) - 8002708: 4293 cmp r3, r2 - 800270a: d013 beq.n 8002734 - 800270c: 687b ldr r3, [r7, #4] - 800270e: 681b ldr r3, [r3, #0] - 8002710: 4a68 ldr r2, [pc, #416] @ (80028b4 ) - 8002712: 4293 cmp r3, r2 - 8002714: d00e beq.n 8002734 - 8002716: 687b ldr r3, [r7, #4] - 8002718: 681b ldr r3, [r3, #0] - 800271a: 4a67 ldr r2, [pc, #412] @ (80028b8 ) - 800271c: 4293 cmp r3, r2 - 800271e: d009 beq.n 8002734 - 8002720: 687b ldr r3, [r7, #4] - 8002722: 681b ldr r3, [r3, #0] - 8002724: 4a65 ldr r2, [pc, #404] @ (80028bc ) - 8002726: 4293 cmp r3, r2 - 8002728: d004 beq.n 8002734 - 800272a: f240 1113 movw r1, #275 @ 0x113 - 800272e: 4864 ldr r0, [pc, #400] @ (80028c0 ) - 8002730: f7fe f88a bl 8000848 + 800500e: 687b ldr r3, [r7, #4] + 8005010: 681b ldr r3, [r3, #0] + 8005012: 4a7a ldr r2, [pc, #488] @ (80051fc ) + 8005014: 4293 cmp r3, r2 + 8005016: d045 beq.n 80050a4 + 8005018: 687b ldr r3, [r7, #4] + 800501a: 681b ldr r3, [r3, #0] + 800501c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8005020: d040 beq.n 80050a4 + 8005022: 687b ldr r3, [r7, #4] + 8005024: 681b ldr r3, [r3, #0] + 8005026: 4a76 ldr r2, [pc, #472] @ (8005200 ) + 8005028: 4293 cmp r3, r2 + 800502a: d03b beq.n 80050a4 + 800502c: 687b ldr r3, [r7, #4] + 800502e: 681b ldr r3, [r3, #0] + 8005030: 4a74 ldr r2, [pc, #464] @ (8005204 ) + 8005032: 4293 cmp r3, r2 + 8005034: d036 beq.n 80050a4 + 8005036: 687b ldr r3, [r7, #4] + 8005038: 681b ldr r3, [r3, #0] + 800503a: 4a73 ldr r2, [pc, #460] @ (8005208 ) + 800503c: 4293 cmp r3, r2 + 800503e: d031 beq.n 80050a4 + 8005040: 687b ldr r3, [r7, #4] + 8005042: 681b ldr r3, [r3, #0] + 8005044: 4a71 ldr r2, [pc, #452] @ (800520c ) + 8005046: 4293 cmp r3, r2 + 8005048: d02c beq.n 80050a4 + 800504a: 687b ldr r3, [r7, #4] + 800504c: 681b ldr r3, [r3, #0] + 800504e: 4a70 ldr r2, [pc, #448] @ (8005210 ) + 8005050: 4293 cmp r3, r2 + 8005052: d027 beq.n 80050a4 + 8005054: 687b ldr r3, [r7, #4] + 8005056: 681b ldr r3, [r3, #0] + 8005058: 4a6e ldr r2, [pc, #440] @ (8005214 ) + 800505a: 4293 cmp r3, r2 + 800505c: d022 beq.n 80050a4 + 800505e: 687b ldr r3, [r7, #4] + 8005060: 681b ldr r3, [r3, #0] + 8005062: 4a6d ldr r2, [pc, #436] @ (8005218 ) + 8005064: 4293 cmp r3, r2 + 8005066: d01d beq.n 80050a4 + 8005068: 687b ldr r3, [r7, #4] + 800506a: 681b ldr r3, [r3, #0] + 800506c: 4a6b ldr r2, [pc, #428] @ (800521c ) + 800506e: 4293 cmp r3, r2 + 8005070: d018 beq.n 80050a4 + 8005072: 687b ldr r3, [r7, #4] + 8005074: 681b ldr r3, [r3, #0] + 8005076: 4a6a ldr r2, [pc, #424] @ (8005220 ) + 8005078: 4293 cmp r3, r2 + 800507a: d013 beq.n 80050a4 + 800507c: 687b ldr r3, [r7, #4] + 800507e: 681b ldr r3, [r3, #0] + 8005080: 4a68 ldr r2, [pc, #416] @ (8005224 ) + 8005082: 4293 cmp r3, r2 + 8005084: d00e beq.n 80050a4 + 8005086: 687b ldr r3, [r7, #4] + 8005088: 681b ldr r3, [r3, #0] + 800508a: 4a67 ldr r2, [pc, #412] @ (8005228 ) + 800508c: 4293 cmp r3, r2 + 800508e: d009 beq.n 80050a4 + 8005090: 687b ldr r3, [r7, #4] + 8005092: 681b ldr r3, [r3, #0] + 8005094: 4a65 ldr r2, [pc, #404] @ (800522c ) + 8005096: 4293 cmp r3, r2 + 8005098: d004 beq.n 80050a4 + 800509a: f240 1113 movw r1, #275 @ 0x113 + 800509e: 4864 ldr r0, [pc, #400] @ (8005230 ) + 80050a0: f7fb fe48 bl 8000d34 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - 8002734: 687b ldr r3, [r7, #4] - 8002736: 689b ldr r3, [r3, #8] - 8002738: 2b00 cmp r3, #0 - 800273a: d014 beq.n 8002766 - 800273c: 687b ldr r3, [r7, #4] - 800273e: 689b ldr r3, [r3, #8] - 8002740: 2b10 cmp r3, #16 - 8002742: d010 beq.n 8002766 - 8002744: 687b ldr r3, [r7, #4] - 8002746: 689b ldr r3, [r3, #8] - 8002748: 2b20 cmp r3, #32 - 800274a: d00c beq.n 8002766 - 800274c: 687b ldr r3, [r7, #4] - 800274e: 689b ldr r3, [r3, #8] - 8002750: 2b40 cmp r3, #64 @ 0x40 - 8002752: d008 beq.n 8002766 - 8002754: 687b ldr r3, [r7, #4] - 8002756: 689b ldr r3, [r3, #8] - 8002758: 2b60 cmp r3, #96 @ 0x60 - 800275a: d004 beq.n 8002766 - 800275c: f44f 718a mov.w r1, #276 @ 0x114 - 8002760: 4857 ldr r0, [pc, #348] @ (80028c0 ) - 8002762: f7fe f871 bl 8000848 + 80050a4: 687b ldr r3, [r7, #4] + 80050a6: 689b ldr r3, [r3, #8] + 80050a8: 2b00 cmp r3, #0 + 80050aa: d014 beq.n 80050d6 + 80050ac: 687b ldr r3, [r7, #4] + 80050ae: 689b ldr r3, [r3, #8] + 80050b0: 2b10 cmp r3, #16 + 80050b2: d010 beq.n 80050d6 + 80050b4: 687b ldr r3, [r7, #4] + 80050b6: 689b ldr r3, [r3, #8] + 80050b8: 2b20 cmp r3, #32 + 80050ba: d00c beq.n 80050d6 + 80050bc: 687b ldr r3, [r7, #4] + 80050be: 689b ldr r3, [r3, #8] + 80050c0: 2b40 cmp r3, #64 @ 0x40 + 80050c2: d008 beq.n 80050d6 + 80050c4: 687b ldr r3, [r7, #4] + 80050c6: 689b ldr r3, [r3, #8] + 80050c8: 2b60 cmp r3, #96 @ 0x60 + 80050ca: d004 beq.n 80050d6 + 80050cc: f44f 718a mov.w r1, #276 @ 0x114 + 80050d0: 4857 ldr r0, [pc, #348] @ (8005230 ) + 80050d2: f7fb fe2f bl 8000d34 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - 8002766: 687b ldr r3, [r7, #4] - 8002768: 691b ldr r3, [r3, #16] - 800276a: 2b00 cmp r3, #0 - 800276c: d00e beq.n 800278c - 800276e: 687b ldr r3, [r7, #4] - 8002770: 691b ldr r3, [r3, #16] - 8002772: f5b3 7f80 cmp.w r3, #256 @ 0x100 - 8002776: d009 beq.n 800278c - 8002778: 687b ldr r3, [r7, #4] - 800277a: 691b ldr r3, [r3, #16] - 800277c: f5b3 7f00 cmp.w r3, #512 @ 0x200 - 8002780: d004 beq.n 800278c - 8002782: f240 1115 movw r1, #277 @ 0x115 - 8002786: 484e ldr r0, [pc, #312] @ (80028c0 ) - 8002788: f7fe f85e bl 8000848 + 80050d6: 687b ldr r3, [r7, #4] + 80050d8: 691b ldr r3, [r3, #16] + 80050da: 2b00 cmp r3, #0 + 80050dc: d00e beq.n 80050fc + 80050de: 687b ldr r3, [r7, #4] + 80050e0: 691b ldr r3, [r3, #16] + 80050e2: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 80050e6: d009 beq.n 80050fc + 80050e8: 687b ldr r3, [r7, #4] + 80050ea: 691b ldr r3, [r3, #16] + 80050ec: f5b3 7f00 cmp.w r3, #512 @ 0x200 + 80050f0: d004 beq.n 80050fc + 80050f2: f240 1115 movw r1, #277 @ 0x115 + 80050f6: 484e ldr r0, [pc, #312] @ (8005230 ) + 80050f8: f7fb fe1c bl 8000d34 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); - 800278c: 687b ldr r3, [r7, #4] - 800278e: 681b ldr r3, [r3, #0] - 8002790: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 - 8002794: d004 beq.n 80027a0 - 8002796: 687b ldr r3, [r7, #4] - 8002798: 681b ldr r3, [r3, #0] - 800279a: 4a3f ldr r2, [pc, #252] @ (8002898 ) - 800279c: 4293 cmp r3, r2 - 800279e: d101 bne.n 80027a4 - 80027a0: 2301 movs r3, #1 - 80027a2: e000 b.n 80027a6 - 80027a4: 2300 movs r3, #0 - 80027a6: 2b00 cmp r3, #0 - 80027a8: d10f bne.n 80027ca - 80027aa: 687b ldr r3, [r7, #4] - 80027ac: 68db ldr r3, [r3, #12] - 80027ae: 2b00 cmp r3, #0 - 80027b0: d006 beq.n 80027c0 - 80027b2: 687b ldr r3, [r7, #4] - 80027b4: 68db ldr r3, [r3, #12] - 80027b6: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 - 80027ba: d201 bcs.n 80027c0 - 80027bc: 2301 movs r3, #1 - 80027be: e000 b.n 80027c2 - 80027c0: 2300 movs r3, #0 - 80027c2: f003 0301 and.w r3, r3, #1 - 80027c6: b2db uxtb r3, r3 - 80027c8: e006 b.n 80027d8 - 80027ca: 687b ldr r3, [r7, #4] - 80027cc: 68db ldr r3, [r3, #12] - 80027ce: 2b00 cmp r3, #0 - 80027d0: bf14 ite ne - 80027d2: 2301 movne r3, #1 - 80027d4: 2300 moveq r3, #0 - 80027d6: b2db uxtb r3, r3 - 80027d8: 2b00 cmp r3, #0 - 80027da: d104 bne.n 80027e6 - 80027dc: f44f 718b mov.w r1, #278 @ 0x116 - 80027e0: 4837 ldr r0, [pc, #220] @ (80028c0 ) - 80027e2: f7fe f831 bl 8000848 + 80050fc: 687b ldr r3, [r7, #4] + 80050fe: 681b ldr r3, [r3, #0] + 8005100: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8005104: d004 beq.n 8005110 + 8005106: 687b ldr r3, [r7, #4] + 8005108: 681b ldr r3, [r3, #0] + 800510a: 4a3f ldr r2, [pc, #252] @ (8005208 ) + 800510c: 4293 cmp r3, r2 + 800510e: d101 bne.n 8005114 + 8005110: 2301 movs r3, #1 + 8005112: e000 b.n 8005116 + 8005114: 2300 movs r3, #0 + 8005116: 2b00 cmp r3, #0 + 8005118: d10f bne.n 800513a + 800511a: 687b ldr r3, [r7, #4] + 800511c: 68db ldr r3, [r3, #12] + 800511e: 2b00 cmp r3, #0 + 8005120: d006 beq.n 8005130 + 8005122: 687b ldr r3, [r7, #4] + 8005124: 68db ldr r3, [r3, #12] + 8005126: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 800512a: d201 bcs.n 8005130 + 800512c: 2301 movs r3, #1 + 800512e: e000 b.n 8005132 + 8005130: 2300 movs r3, #0 + 8005132: f003 0301 and.w r3, r3, #1 + 8005136: b2db uxtb r3, r3 + 8005138: e006 b.n 8005148 + 800513a: 687b ldr r3, [r7, #4] + 800513c: 68db ldr r3, [r3, #12] + 800513e: 2b00 cmp r3, #0 + 8005140: bf14 ite ne + 8005142: 2301 movne r3, #1 + 8005144: 2300 moveq r3, #0 + 8005146: b2db uxtb r3, r3 + 8005148: 2b00 cmp r3, #0 + 800514a: d104 bne.n 8005156 + 800514c: f44f 718b mov.w r1, #278 @ 0x116 + 8005150: 4837 ldr r0, [pc, #220] @ (8005230 ) + 8005152: f7fb fdef bl 8000d34 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - 80027e6: 687b ldr r3, [r7, #4] - 80027e8: 699b ldr r3, [r3, #24] - 80027ea: 2b00 cmp r3, #0 - 80027ec: d008 beq.n 8002800 - 80027ee: 687b ldr r3, [r7, #4] - 80027f0: 699b ldr r3, [r3, #24] - 80027f2: 2b80 cmp r3, #128 @ 0x80 - 80027f4: d004 beq.n 8002800 - 80027f6: f240 1117 movw r1, #279 @ 0x117 - 80027fa: 4831 ldr r0, [pc, #196] @ (80028c0 ) - 80027fc: f7fe f824 bl 8000848 + 8005156: 687b ldr r3, [r7, #4] + 8005158: 699b ldr r3, [r3, #24] + 800515a: 2b00 cmp r3, #0 + 800515c: d008 beq.n 8005170 + 800515e: 687b ldr r3, [r7, #4] + 8005160: 699b ldr r3, [r3, #24] + 8005162: 2b80 cmp r3, #128 @ 0x80 + 8005164: d004 beq.n 8005170 + 8005166: f240 1117 movw r1, #279 @ 0x117 + 800516a: 4831 ldr r0, [pc, #196] @ (8005230 ) + 800516c: f7fb fde2 bl 8000d34 if (htim->State == HAL_TIM_STATE_RESET) - 8002800: 687b ldr r3, [r7, #4] - 8002802: f893 303d ldrb.w r3, [r3, #61] @ 0x3d - 8002806: b2db uxtb r3, r3 - 8002808: 2b00 cmp r3, #0 - 800280a: d106 bne.n 800281a + 8005170: 687b ldr r3, [r7, #4] + 8005172: f893 303d ldrb.w r3, [r3, #61] @ 0x3d + 8005176: b2db uxtb r3, r3 + 8005178: 2b00 cmp r3, #0 + 800517a: d106 bne.n 800518a { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; - 800280c: 687b ldr r3, [r7, #4] - 800280e: 2200 movs r2, #0 - 8002810: f883 203c strb.w r2, [r3, #60] @ 0x3c + 800517c: 687b ldr r3, [r7, #4] + 800517e: 2200 movs r2, #0 + 8005180: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); - 8002814: 6878 ldr r0, [r7, #4] - 8002816: f000 f855 bl 80028c4 + 8005184: 6878 ldr r0, [r7, #4] + 8005186: f000 f855 bl 8005234 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; - 800281a: 687b ldr r3, [r7, #4] - 800281c: 2202 movs r2, #2 - 800281e: f883 203d strb.w r2, [r3, #61] @ 0x3d + 800518a: 687b ldr r3, [r7, #4] + 800518c: 2202 movs r2, #2 + 800518e: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); - 8002822: 687b ldr r3, [r7, #4] - 8002824: 681a ldr r2, [r3, #0] - 8002826: 687b ldr r3, [r7, #4] - 8002828: 3304 adds r3, #4 - 800282a: 4619 mov r1, r3 - 800282c: 4610 mov r0, r2 - 800282e: f000 fa31 bl 8002c94 + 8005192: 687b ldr r3, [r7, #4] + 8005194: 681a ldr r2, [r3, #0] + 8005196: 687b ldr r3, [r7, #4] + 8005198: 3304 adds r3, #4 + 800519a: 4619 mov r1, r3 + 800519c: 4610 mov r0, r2 + 800519e: f000 fa31 bl 8005604 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - 8002832: 687b ldr r3, [r7, #4] - 8002834: 2201 movs r2, #1 - 8002836: f883 2046 strb.w r2, [r3, #70] @ 0x46 + 80051a2: 687b ldr r3, [r7, #4] + 80051a4: 2201 movs r2, #1 + 80051a6: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - 800283a: 687b ldr r3, [r7, #4] - 800283c: 2201 movs r2, #1 - 800283e: f883 203e strb.w r2, [r3, #62] @ 0x3e - 8002842: 687b ldr r3, [r7, #4] - 8002844: 2201 movs r2, #1 - 8002846: f883 203f strb.w r2, [r3, #63] @ 0x3f - 800284a: 687b ldr r3, [r7, #4] - 800284c: 2201 movs r2, #1 - 800284e: f883 2040 strb.w r2, [r3, #64] @ 0x40 - 8002852: 687b ldr r3, [r7, #4] - 8002854: 2201 movs r2, #1 - 8002856: f883 2041 strb.w r2, [r3, #65] @ 0x41 + 80051aa: 687b ldr r3, [r7, #4] + 80051ac: 2201 movs r2, #1 + 80051ae: f883 203e strb.w r2, [r3, #62] @ 0x3e + 80051b2: 687b ldr r3, [r7, #4] + 80051b4: 2201 movs r2, #1 + 80051b6: f883 203f strb.w r2, [r3, #63] @ 0x3f + 80051ba: 687b ldr r3, [r7, #4] + 80051bc: 2201 movs r2, #1 + 80051be: f883 2040 strb.w r2, [r3, #64] @ 0x40 + 80051c2: 687b ldr r3, [r7, #4] + 80051c4: 2201 movs r2, #1 + 80051c6: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - 800285a: 687b ldr r3, [r7, #4] - 800285c: 2201 movs r2, #1 - 800285e: f883 2042 strb.w r2, [r3, #66] @ 0x42 - 8002862: 687b ldr r3, [r7, #4] - 8002864: 2201 movs r2, #1 - 8002866: f883 2043 strb.w r2, [r3, #67] @ 0x43 - 800286a: 687b ldr r3, [r7, #4] - 800286c: 2201 movs r2, #1 - 800286e: f883 2044 strb.w r2, [r3, #68] @ 0x44 - 8002872: 687b ldr r3, [r7, #4] - 8002874: 2201 movs r2, #1 - 8002876: f883 2045 strb.w r2, [r3, #69] @ 0x45 + 80051ca: 687b ldr r3, [r7, #4] + 80051cc: 2201 movs r2, #1 + 80051ce: f883 2042 strb.w r2, [r3, #66] @ 0x42 + 80051d2: 687b ldr r3, [r7, #4] + 80051d4: 2201 movs r2, #1 + 80051d6: f883 2043 strb.w r2, [r3, #67] @ 0x43 + 80051da: 687b ldr r3, [r7, #4] + 80051dc: 2201 movs r2, #1 + 80051de: f883 2044 strb.w r2, [r3, #68] @ 0x44 + 80051e2: 687b ldr r3, [r7, #4] + 80051e4: 2201 movs r2, #1 + 80051e6: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; - 800287a: 687b ldr r3, [r7, #4] - 800287c: 2201 movs r2, #1 - 800287e: f883 203d strb.w r2, [r3, #61] @ 0x3d + 80051ea: 687b ldr r3, [r7, #4] + 80051ec: 2201 movs r2, #1 + 80051ee: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; - 8002882: 2300 movs r3, #0 + 80051f2: 2300 movs r3, #0 } - 8002884: 4618 mov r0, r3 - 8002886: 3708 adds r7, #8 - 8002888: 46bd mov sp, r7 - 800288a: bd80 pop {r7, pc} - 800288c: 40010000 .word 0x40010000 - 8002890: 40000400 .word 0x40000400 - 8002894: 40000800 .word 0x40000800 - 8002898: 40000c00 .word 0x40000c00 - 800289c: 40001000 .word 0x40001000 - 80028a0: 40001400 .word 0x40001400 - 80028a4: 40010400 .word 0x40010400 - 80028a8: 40014000 .word 0x40014000 - 80028ac: 40014400 .word 0x40014400 - 80028b0: 40014800 .word 0x40014800 - 80028b4: 40001800 .word 0x40001800 - 80028b8: 40001c00 .word 0x40001c00 - 80028bc: 40002000 .word 0x40002000 - 80028c0: 08005cd0 .word 0x08005cd0 + 80051f4: 4618 mov r0, r3 + 80051f6: 3708 adds r7, #8 + 80051f8: 46bd mov sp, r7 + 80051fa: bd80 pop {r7, pc} + 80051fc: 40010000 .word 0x40010000 + 8005200: 40000400 .word 0x40000400 + 8005204: 40000800 .word 0x40000800 + 8005208: 40000c00 .word 0x40000c00 + 800520c: 40001000 .word 0x40001000 + 8005210: 40001400 .word 0x40001400 + 8005214: 40010400 .word 0x40010400 + 8005218: 40014000 .word 0x40014000 + 800521c: 40014400 .word 0x40014400 + 8005220: 40014800 .word 0x40014800 + 8005224: 40001800 .word 0x40001800 + 8005228: 40001c00 .word 0x40001c00 + 800522c: 40002000 .word 0x40002000 + 8005230: 0800a214 .word 0x0800a214 -080028c4 : +08005234 : * @brief Initializes the TIM Base MSP. * @param htim TIM Base handle * @retval None */ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) { - 80028c4: b480 push {r7} - 80028c6: b083 sub sp, #12 - 80028c8: af00 add r7, sp, #0 - 80028ca: 6078 str r0, [r7, #4] + 8005234: b480 push {r7} + 8005236: b083 sub sp, #12 + 8005238: af00 add r7, sp, #0 + 800523a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_Base_MspInit could be implemented in the user file */ } - 80028cc: bf00 nop - 80028ce: 370c adds r7, #12 - 80028d0: 46bd mov sp, r7 - 80028d2: f85d 7b04 ldr.w r7, [sp], #4 - 80028d6: 4770 bx lr + 800523c: bf00 nop + 800523e: 370c adds r7, #12 + 8005240: 46bd mov sp, r7 + 8005242: f85d 7b04 ldr.w r7, [sp], #4 + 8005246: 4770 bx lr -080028d8 : +08005248 : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { - 80028d8: b580 push {r7, lr} - 80028da: b084 sub sp, #16 - 80028dc: af00 add r7, sp, #0 - 80028de: 6078 str r0, [r7, #4] + 8005248: b580 push {r7, lr} + 800524a: b084 sub sp, #16 + 800524c: af00 add r7, sp, #0 + 800524e: 6078 str r0, [r7, #4] uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); - 80028e0: 687b ldr r3, [r7, #4] - 80028e2: 681b ldr r3, [r3, #0] - 80028e4: 4a51 ldr r2, [pc, #324] @ (8002a2c ) - 80028e6: 4293 cmp r3, r2 - 80028e8: d045 beq.n 8002976 - 80028ea: 687b ldr r3, [r7, #4] - 80028ec: 681b ldr r3, [r3, #0] - 80028ee: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 - 80028f2: d040 beq.n 8002976 - 80028f4: 687b ldr r3, [r7, #4] - 80028f6: 681b ldr r3, [r3, #0] - 80028f8: 4a4d ldr r2, [pc, #308] @ (8002a30 ) - 80028fa: 4293 cmp r3, r2 - 80028fc: d03b beq.n 8002976 - 80028fe: 687b ldr r3, [r7, #4] - 8002900: 681b ldr r3, [r3, #0] - 8002902: 4a4c ldr r2, [pc, #304] @ (8002a34 ) - 8002904: 4293 cmp r3, r2 - 8002906: d036 beq.n 8002976 - 8002908: 687b ldr r3, [r7, #4] - 800290a: 681b ldr r3, [r3, #0] - 800290c: 4a4a ldr r2, [pc, #296] @ (8002a38 ) - 800290e: 4293 cmp r3, r2 - 8002910: d031 beq.n 8002976 - 8002912: 687b ldr r3, [r7, #4] - 8002914: 681b ldr r3, [r3, #0] - 8002916: 4a49 ldr r2, [pc, #292] @ (8002a3c ) - 8002918: 4293 cmp r3, r2 - 800291a: d02c beq.n 8002976 - 800291c: 687b ldr r3, [r7, #4] - 800291e: 681b ldr r3, [r3, #0] - 8002920: 4a47 ldr r2, [pc, #284] @ (8002a40 ) - 8002922: 4293 cmp r3, r2 - 8002924: d027 beq.n 8002976 - 8002926: 687b ldr r3, [r7, #4] - 8002928: 681b ldr r3, [r3, #0] - 800292a: 4a46 ldr r2, [pc, #280] @ (8002a44 ) - 800292c: 4293 cmp r3, r2 - 800292e: d022 beq.n 8002976 - 8002930: 687b ldr r3, [r7, #4] - 8002932: 681b ldr r3, [r3, #0] - 8002934: 4a44 ldr r2, [pc, #272] @ (8002a48 ) - 8002936: 4293 cmp r3, r2 - 8002938: d01d beq.n 8002976 - 800293a: 687b ldr r3, [r7, #4] - 800293c: 681b ldr r3, [r3, #0] - 800293e: 4a43 ldr r2, [pc, #268] @ (8002a4c ) - 8002940: 4293 cmp r3, r2 - 8002942: d018 beq.n 8002976 - 8002944: 687b ldr r3, [r7, #4] - 8002946: 681b ldr r3, [r3, #0] - 8002948: 4a41 ldr r2, [pc, #260] @ (8002a50 ) - 800294a: 4293 cmp r3, r2 - 800294c: d013 beq.n 8002976 - 800294e: 687b ldr r3, [r7, #4] - 8002950: 681b ldr r3, [r3, #0] - 8002952: 4a40 ldr r2, [pc, #256] @ (8002a54 ) - 8002954: 4293 cmp r3, r2 - 8002956: d00e beq.n 8002976 - 8002958: 687b ldr r3, [r7, #4] - 800295a: 681b ldr r3, [r3, #0] - 800295c: 4a3e ldr r2, [pc, #248] @ (8002a58 ) - 800295e: 4293 cmp r3, r2 - 8002960: d009 beq.n 8002976 - 8002962: 687b ldr r3, [r7, #4] - 8002964: 681b ldr r3, [r3, #0] - 8002966: 4a3d ldr r2, [pc, #244] @ (8002a5c ) - 8002968: 4293 cmp r3, r2 - 800296a: d004 beq.n 8002976 - 800296c: f44f 71e8 mov.w r1, #464 @ 0x1d0 - 8002970: 483b ldr r0, [pc, #236] @ (8002a60 ) - 8002972: f7fd ff69 bl 8000848 + 8005250: 687b ldr r3, [r7, #4] + 8005252: 681b ldr r3, [r3, #0] + 8005254: 4a51 ldr r2, [pc, #324] @ (800539c ) + 8005256: 4293 cmp r3, r2 + 8005258: d045 beq.n 80052e6 + 800525a: 687b ldr r3, [r7, #4] + 800525c: 681b ldr r3, [r3, #0] + 800525e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8005262: d040 beq.n 80052e6 + 8005264: 687b ldr r3, [r7, #4] + 8005266: 681b ldr r3, [r3, #0] + 8005268: 4a4d ldr r2, [pc, #308] @ (80053a0 ) + 800526a: 4293 cmp r3, r2 + 800526c: d03b beq.n 80052e6 + 800526e: 687b ldr r3, [r7, #4] + 8005270: 681b ldr r3, [r3, #0] + 8005272: 4a4c ldr r2, [pc, #304] @ (80053a4 ) + 8005274: 4293 cmp r3, r2 + 8005276: d036 beq.n 80052e6 + 8005278: 687b ldr r3, [r7, #4] + 800527a: 681b ldr r3, [r3, #0] + 800527c: 4a4a ldr r2, [pc, #296] @ (80053a8 ) + 800527e: 4293 cmp r3, r2 + 8005280: d031 beq.n 80052e6 + 8005282: 687b ldr r3, [r7, #4] + 8005284: 681b ldr r3, [r3, #0] + 8005286: 4a49 ldr r2, [pc, #292] @ (80053ac ) + 8005288: 4293 cmp r3, r2 + 800528a: d02c beq.n 80052e6 + 800528c: 687b ldr r3, [r7, #4] + 800528e: 681b ldr r3, [r3, #0] + 8005290: 4a47 ldr r2, [pc, #284] @ (80053b0 ) + 8005292: 4293 cmp r3, r2 + 8005294: d027 beq.n 80052e6 + 8005296: 687b ldr r3, [r7, #4] + 8005298: 681b ldr r3, [r3, #0] + 800529a: 4a46 ldr r2, [pc, #280] @ (80053b4 ) + 800529c: 4293 cmp r3, r2 + 800529e: d022 beq.n 80052e6 + 80052a0: 687b ldr r3, [r7, #4] + 80052a2: 681b ldr r3, [r3, #0] + 80052a4: 4a44 ldr r2, [pc, #272] @ (80053b8 ) + 80052a6: 4293 cmp r3, r2 + 80052a8: d01d beq.n 80052e6 + 80052aa: 687b ldr r3, [r7, #4] + 80052ac: 681b ldr r3, [r3, #0] + 80052ae: 4a43 ldr r2, [pc, #268] @ (80053bc ) + 80052b0: 4293 cmp r3, r2 + 80052b2: d018 beq.n 80052e6 + 80052b4: 687b ldr r3, [r7, #4] + 80052b6: 681b ldr r3, [r3, #0] + 80052b8: 4a41 ldr r2, [pc, #260] @ (80053c0 ) + 80052ba: 4293 cmp r3, r2 + 80052bc: d013 beq.n 80052e6 + 80052be: 687b ldr r3, [r7, #4] + 80052c0: 681b ldr r3, [r3, #0] + 80052c2: 4a40 ldr r2, [pc, #256] @ (80053c4 ) + 80052c4: 4293 cmp r3, r2 + 80052c6: d00e beq.n 80052e6 + 80052c8: 687b ldr r3, [r7, #4] + 80052ca: 681b ldr r3, [r3, #0] + 80052cc: 4a3e ldr r2, [pc, #248] @ (80053c8 ) + 80052ce: 4293 cmp r3, r2 + 80052d0: d009 beq.n 80052e6 + 80052d2: 687b ldr r3, [r7, #4] + 80052d4: 681b ldr r3, [r3, #0] + 80052d6: 4a3d ldr r2, [pc, #244] @ (80053cc ) + 80052d8: 4293 cmp r3, r2 + 80052da: d004 beq.n 80052e6 + 80052dc: f44f 71e8 mov.w r1, #464 @ 0x1d0 + 80052e0: 483b ldr r0, [pc, #236] @ (80053d0 ) + 80052e2: f7fb fd27 bl 8000d34 /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) - 8002976: 687b ldr r3, [r7, #4] - 8002978: f893 303d ldrb.w r3, [r3, #61] @ 0x3d - 800297c: b2db uxtb r3, r3 - 800297e: 2b01 cmp r3, #1 - 8002980: d001 beq.n 8002986 + 80052e6: 687b ldr r3, [r7, #4] + 80052e8: f893 303d ldrb.w r3, [r3, #61] @ 0x3d + 80052ec: b2db uxtb r3, r3 + 80052ee: 2b01 cmp r3, #1 + 80052f0: d001 beq.n 80052f6 { return HAL_ERROR; - 8002982: 2301 movs r3, #1 - 8002984: e04e b.n 8002a24 + 80052f2: 2301 movs r3, #1 + 80052f4: e04e b.n 8005394 } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; - 8002986: 687b ldr r3, [r7, #4] - 8002988: 2202 movs r2, #2 - 800298a: f883 203d strb.w r2, [r3, #61] @ 0x3d + 80052f6: 687b ldr r3, [r7, #4] + 80052f8: 2202 movs r2, #2 + 80052fa: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); - 800298e: 687b ldr r3, [r7, #4] - 8002990: 681b ldr r3, [r3, #0] - 8002992: 68da ldr r2, [r3, #12] - 8002994: 687b ldr r3, [r7, #4] - 8002996: 681b ldr r3, [r3, #0] - 8002998: f042 0201 orr.w r2, r2, #1 - 800299c: 60da str r2, [r3, #12] + 80052fe: 687b ldr r3, [r7, #4] + 8005300: 681b ldr r3, [r3, #0] + 8005302: 68da ldr r2, [r3, #12] + 8005304: 687b ldr r3, [r7, #4] + 8005306: 681b ldr r3, [r3, #0] + 8005308: f042 0201 orr.w r2, r2, #1 + 800530c: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - 800299e: 687b ldr r3, [r7, #4] - 80029a0: 681b ldr r3, [r3, #0] - 80029a2: 4a22 ldr r2, [pc, #136] @ (8002a2c ) - 80029a4: 4293 cmp r3, r2 - 80029a6: d022 beq.n 80029ee - 80029a8: 687b ldr r3, [r7, #4] - 80029aa: 681b ldr r3, [r3, #0] - 80029ac: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 - 80029b0: d01d beq.n 80029ee - 80029b2: 687b ldr r3, [r7, #4] - 80029b4: 681b ldr r3, [r3, #0] - 80029b6: 4a1e ldr r2, [pc, #120] @ (8002a30 ) - 80029b8: 4293 cmp r3, r2 - 80029ba: d018 beq.n 80029ee - 80029bc: 687b ldr r3, [r7, #4] - 80029be: 681b ldr r3, [r3, #0] - 80029c0: 4a1c ldr r2, [pc, #112] @ (8002a34 ) - 80029c2: 4293 cmp r3, r2 - 80029c4: d013 beq.n 80029ee - 80029c6: 687b ldr r3, [r7, #4] - 80029c8: 681b ldr r3, [r3, #0] - 80029ca: 4a1b ldr r2, [pc, #108] @ (8002a38 ) - 80029cc: 4293 cmp r3, r2 - 80029ce: d00e beq.n 80029ee - 80029d0: 687b ldr r3, [r7, #4] - 80029d2: 681b ldr r3, [r3, #0] - 80029d4: 4a1b ldr r2, [pc, #108] @ (8002a44 ) - 80029d6: 4293 cmp r3, r2 - 80029d8: d009 beq.n 80029ee - 80029da: 687b ldr r3, [r7, #4] - 80029dc: 681b ldr r3, [r3, #0] - 80029de: 4a1a ldr r2, [pc, #104] @ (8002a48 ) - 80029e0: 4293 cmp r3, r2 - 80029e2: d004 beq.n 80029ee - 80029e4: 687b ldr r3, [r7, #4] - 80029e6: 681b ldr r3, [r3, #0] - 80029e8: 4a1a ldr r2, [pc, #104] @ (8002a54 ) - 80029ea: 4293 cmp r3, r2 - 80029ec: d111 bne.n 8002a12 + 800530e: 687b ldr r3, [r7, #4] + 8005310: 681b ldr r3, [r3, #0] + 8005312: 4a22 ldr r2, [pc, #136] @ (800539c ) + 8005314: 4293 cmp r3, r2 + 8005316: d022 beq.n 800535e + 8005318: 687b ldr r3, [r7, #4] + 800531a: 681b ldr r3, [r3, #0] + 800531c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8005320: d01d beq.n 800535e + 8005322: 687b ldr r3, [r7, #4] + 8005324: 681b ldr r3, [r3, #0] + 8005326: 4a1e ldr r2, [pc, #120] @ (80053a0 ) + 8005328: 4293 cmp r3, r2 + 800532a: d018 beq.n 800535e + 800532c: 687b ldr r3, [r7, #4] + 800532e: 681b ldr r3, [r3, #0] + 8005330: 4a1c ldr r2, [pc, #112] @ (80053a4 ) + 8005332: 4293 cmp r3, r2 + 8005334: d013 beq.n 800535e + 8005336: 687b ldr r3, [r7, #4] + 8005338: 681b ldr r3, [r3, #0] + 800533a: 4a1b ldr r2, [pc, #108] @ (80053a8 ) + 800533c: 4293 cmp r3, r2 + 800533e: d00e beq.n 800535e + 8005340: 687b ldr r3, [r7, #4] + 8005342: 681b ldr r3, [r3, #0] + 8005344: 4a1b ldr r2, [pc, #108] @ (80053b4 ) + 8005346: 4293 cmp r3, r2 + 8005348: d009 beq.n 800535e + 800534a: 687b ldr r3, [r7, #4] + 800534c: 681b ldr r3, [r3, #0] + 800534e: 4a1a ldr r2, [pc, #104] @ (80053b8 ) + 8005350: 4293 cmp r3, r2 + 8005352: d004 beq.n 800535e + 8005354: 687b ldr r3, [r7, #4] + 8005356: 681b ldr r3, [r3, #0] + 8005358: 4a1a ldr r2, [pc, #104] @ (80053c4 ) + 800535a: 4293 cmp r3, r2 + 800535c: d111 bne.n 8005382 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - 80029ee: 687b ldr r3, [r7, #4] - 80029f0: 681b ldr r3, [r3, #0] - 80029f2: 689b ldr r3, [r3, #8] - 80029f4: f003 0307 and.w r3, r3, #7 - 80029f8: 60fb str r3, [r7, #12] + 800535e: 687b ldr r3, [r7, #4] + 8005360: 681b ldr r3, [r3, #0] + 8005362: 689b ldr r3, [r3, #8] + 8005364: f003 0307 and.w r3, r3, #7 + 8005368: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - 80029fa: 68fb ldr r3, [r7, #12] - 80029fc: 2b06 cmp r3, #6 - 80029fe: d010 beq.n 8002a22 + 800536a: 68fb ldr r3, [r7, #12] + 800536c: 2b06 cmp r3, #6 + 800536e: d010 beq.n 8005392 { __HAL_TIM_ENABLE(htim); - 8002a00: 687b ldr r3, [r7, #4] - 8002a02: 681b ldr r3, [r3, #0] - 8002a04: 681a ldr r2, [r3, #0] - 8002a06: 687b ldr r3, [r7, #4] - 8002a08: 681b ldr r3, [r3, #0] - 8002a0a: f042 0201 orr.w r2, r2, #1 - 8002a0e: 601a str r2, [r3, #0] + 8005370: 687b ldr r3, [r7, #4] + 8005372: 681b ldr r3, [r3, #0] + 8005374: 681a ldr r2, [r3, #0] + 8005376: 687b ldr r3, [r7, #4] + 8005378: 681b ldr r3, [r3, #0] + 800537a: f042 0201 orr.w r2, r2, #1 + 800537e: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - 8002a10: e007 b.n 8002a22 + 8005380: e007 b.n 8005392 } } else { __HAL_TIM_ENABLE(htim); - 8002a12: 687b ldr r3, [r7, #4] - 8002a14: 681b ldr r3, [r3, #0] - 8002a16: 681a ldr r2, [r3, #0] - 8002a18: 687b ldr r3, [r7, #4] - 8002a1a: 681b ldr r3, [r3, #0] - 8002a1c: f042 0201 orr.w r2, r2, #1 - 8002a20: 601a str r2, [r3, #0] + 8005382: 687b ldr r3, [r7, #4] + 8005384: 681b ldr r3, [r3, #0] + 8005386: 681a ldr r2, [r3, #0] + 8005388: 687b ldr r3, [r7, #4] + 800538a: 681b ldr r3, [r3, #0] + 800538c: f042 0201 orr.w r2, r2, #1 + 8005390: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; - 8002a22: 2300 movs r3, #0 + 8005392: 2300 movs r3, #0 } - 8002a24: 4618 mov r0, r3 - 8002a26: 3710 adds r7, #16 - 8002a28: 46bd mov sp, r7 - 8002a2a: bd80 pop {r7, pc} - 8002a2c: 40010000 .word 0x40010000 - 8002a30: 40000400 .word 0x40000400 - 8002a34: 40000800 .word 0x40000800 - 8002a38: 40000c00 .word 0x40000c00 - 8002a3c: 40001000 .word 0x40001000 - 8002a40: 40001400 .word 0x40001400 - 8002a44: 40010400 .word 0x40010400 - 8002a48: 40014000 .word 0x40014000 - 8002a4c: 40014400 .word 0x40014400 - 8002a50: 40014800 .word 0x40014800 - 8002a54: 40001800 .word 0x40001800 - 8002a58: 40001c00 .word 0x40001c00 - 8002a5c: 40002000 .word 0x40002000 - 8002a60: 08005cd0 .word 0x08005cd0 + 8005394: 4618 mov r0, r3 + 8005396: 3710 adds r7, #16 + 8005398: 46bd mov sp, r7 + 800539a: bd80 pop {r7, pc} + 800539c: 40010000 .word 0x40010000 + 80053a0: 40000400 .word 0x40000400 + 80053a4: 40000800 .word 0x40000800 + 80053a8: 40000c00 .word 0x40000c00 + 80053ac: 40001000 .word 0x40001000 + 80053b0: 40001400 .word 0x40001400 + 80053b4: 40010400 .word 0x40010400 + 80053b8: 40014000 .word 0x40014000 + 80053bc: 40014400 .word 0x40014400 + 80053c0: 40014800 .word 0x40014800 + 80053c4: 40001800 .word 0x40001800 + 80053c8: 40001c00 .word 0x40001c00 + 80053cc: 40002000 .word 0x40002000 + 80053d0: 0800a214 .word 0x0800a214 -08002a64 : +080053d4 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { - 8002a64: b580 push {r7, lr} - 8002a66: b084 sub sp, #16 - 8002a68: af00 add r7, sp, #0 - 8002a6a: 6078 str r0, [r7, #4] + 80053d4: b580 push {r7, lr} + 80053d6: b084 sub sp, #16 + 80053d8: af00 add r7, sp, #0 + 80053da: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; - 8002a6c: 687b ldr r3, [r7, #4] - 8002a6e: 681b ldr r3, [r3, #0] - 8002a70: 68db ldr r3, [r3, #12] - 8002a72: 60fb str r3, [r7, #12] + 80053dc: 687b ldr r3, [r7, #4] + 80053de: 681b ldr r3, [r3, #0] + 80053e0: 68db ldr r3, [r3, #12] + 80053e2: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; - 8002a74: 687b ldr r3, [r7, #4] - 8002a76: 681b ldr r3, [r3, #0] - 8002a78: 691b ldr r3, [r3, #16] - 8002a7a: 60bb str r3, [r7, #8] + 80053e4: 687b ldr r3, [r7, #4] + 80053e6: 681b ldr r3, [r3, #0] + 80053e8: 691b ldr r3, [r3, #16] + 80053ea: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) - 8002a7c: 68bb ldr r3, [r7, #8] - 8002a7e: f003 0302 and.w r3, r3, #2 - 8002a82: 2b00 cmp r3, #0 - 8002a84: d020 beq.n 8002ac8 + 80053ec: 68bb ldr r3, [r7, #8] + 80053ee: f003 0302 and.w r3, r3, #2 + 80053f2: 2b00 cmp r3, #0 + 80053f4: d020 beq.n 8005438 { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) - 8002a86: 68fb ldr r3, [r7, #12] - 8002a88: f003 0302 and.w r3, r3, #2 - 8002a8c: 2b00 cmp r3, #0 - 8002a8e: d01b beq.n 8002ac8 + 80053f6: 68fb ldr r3, [r7, #12] + 80053f8: f003 0302 and.w r3, r3, #2 + 80053fc: 2b00 cmp r3, #0 + 80053fe: d01b beq.n 8005438 { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); - 8002a90: 687b ldr r3, [r7, #4] - 8002a92: 681b ldr r3, [r3, #0] - 8002a94: f06f 0202 mvn.w r2, #2 - 8002a98: 611a str r2, [r3, #16] + 8005400: 687b ldr r3, [r7, #4] + 8005402: 681b ldr r3, [r3, #0] + 8005404: f06f 0202 mvn.w r2, #2 + 8005408: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - 8002a9a: 687b ldr r3, [r7, #4] - 8002a9c: 2201 movs r2, #1 - 8002a9e: 771a strb r2, [r3, #28] + 800540a: 687b ldr r3, [r7, #4] + 800540c: 2201 movs r2, #1 + 800540e: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) - 8002aa0: 687b ldr r3, [r7, #4] - 8002aa2: 681b ldr r3, [r3, #0] - 8002aa4: 699b ldr r3, [r3, #24] - 8002aa6: f003 0303 and.w r3, r3, #3 - 8002aaa: 2b00 cmp r3, #0 - 8002aac: d003 beq.n 8002ab6 + 8005410: 687b ldr r3, [r7, #4] + 8005412: 681b ldr r3, [r3, #0] + 8005414: 699b ldr r3, [r3, #24] + 8005416: f003 0303 and.w r3, r3, #3 + 800541a: 2b00 cmp r3, #0 + 800541c: d003 beq.n 8005426 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); - 8002aae: 6878 ldr r0, [r7, #4] - 8002ab0: f000 f8d2 bl 8002c58 - 8002ab4: e005 b.n 8002ac2 + 800541e: 6878 ldr r0, [r7, #4] + 8005420: f000 f8d2 bl 80055c8 + 8005424: e005 b.n 8005432 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); - 8002ab6: 6878 ldr r0, [r7, #4] - 8002ab8: f000 f8c4 bl 8002c44 + 8005426: 6878 ldr r0, [r7, #4] + 8005428: f000 f8c4 bl 80055b4 HAL_TIM_PWM_PulseFinishedCallback(htim); - 8002abc: 6878 ldr r0, [r7, #4] - 8002abe: f000 f8d5 bl 8002c6c + 800542c: 6878 ldr r0, [r7, #4] + 800542e: f000 f8d5 bl 80055dc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 8002ac2: 687b ldr r3, [r7, #4] - 8002ac4: 2200 movs r2, #0 - 8002ac6: 771a strb r2, [r3, #28] + 8005432: 687b ldr r3, [r7, #4] + 8005434: 2200 movs r2, #0 + 8005436: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) - 8002ac8: 68bb ldr r3, [r7, #8] - 8002aca: f003 0304 and.w r3, r3, #4 - 8002ace: 2b00 cmp r3, #0 - 8002ad0: d020 beq.n 8002b14 + 8005438: 68bb ldr r3, [r7, #8] + 800543a: f003 0304 and.w r3, r3, #4 + 800543e: 2b00 cmp r3, #0 + 8005440: d020 beq.n 8005484 { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) - 8002ad2: 68fb ldr r3, [r7, #12] - 8002ad4: f003 0304 and.w r3, r3, #4 - 8002ad8: 2b00 cmp r3, #0 - 8002ada: d01b beq.n 8002b14 + 8005442: 68fb ldr r3, [r7, #12] + 8005444: f003 0304 and.w r3, r3, #4 + 8005448: 2b00 cmp r3, #0 + 800544a: d01b beq.n 8005484 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); - 8002adc: 687b ldr r3, [r7, #4] - 8002ade: 681b ldr r3, [r3, #0] - 8002ae0: f06f 0204 mvn.w r2, #4 - 8002ae4: 611a str r2, [r3, #16] + 800544c: 687b ldr r3, [r7, #4] + 800544e: 681b ldr r3, [r3, #0] + 8005450: f06f 0204 mvn.w r2, #4 + 8005454: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - 8002ae6: 687b ldr r3, [r7, #4] - 8002ae8: 2202 movs r2, #2 - 8002aea: 771a strb r2, [r3, #28] + 8005456: 687b ldr r3, [r7, #4] + 8005458: 2202 movs r2, #2 + 800545a: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) - 8002aec: 687b ldr r3, [r7, #4] - 8002aee: 681b ldr r3, [r3, #0] - 8002af0: 699b ldr r3, [r3, #24] - 8002af2: f403 7340 and.w r3, r3, #768 @ 0x300 - 8002af6: 2b00 cmp r3, #0 - 8002af8: d003 beq.n 8002b02 + 800545c: 687b ldr r3, [r7, #4] + 800545e: 681b ldr r3, [r3, #0] + 8005460: 699b ldr r3, [r3, #24] + 8005462: f403 7340 and.w r3, r3, #768 @ 0x300 + 8005466: 2b00 cmp r3, #0 + 8005468: d003 beq.n 8005472 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); - 8002afa: 6878 ldr r0, [r7, #4] - 8002afc: f000 f8ac bl 8002c58 - 8002b00: e005 b.n 8002b0e + 800546a: 6878 ldr r0, [r7, #4] + 800546c: f000 f8ac bl 80055c8 + 8005470: e005 b.n 800547e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); - 8002b02: 6878 ldr r0, [r7, #4] - 8002b04: f000 f89e bl 8002c44 + 8005472: 6878 ldr r0, [r7, #4] + 8005474: f000 f89e bl 80055b4 HAL_TIM_PWM_PulseFinishedCallback(htim); - 8002b08: 6878 ldr r0, [r7, #4] - 8002b0a: f000 f8af bl 8002c6c + 8005478: 6878 ldr r0, [r7, #4] + 800547a: f000 f8af bl 80055dc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 8002b0e: 687b ldr r3, [r7, #4] - 8002b10: 2200 movs r2, #0 - 8002b12: 771a strb r2, [r3, #28] + 800547e: 687b ldr r3, [r7, #4] + 8005480: 2200 movs r2, #0 + 8005482: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) - 8002b14: 68bb ldr r3, [r7, #8] - 8002b16: f003 0308 and.w r3, r3, #8 - 8002b1a: 2b00 cmp r3, #0 - 8002b1c: d020 beq.n 8002b60 + 8005484: 68bb ldr r3, [r7, #8] + 8005486: f003 0308 and.w r3, r3, #8 + 800548a: 2b00 cmp r3, #0 + 800548c: d020 beq.n 80054d0 { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) - 8002b1e: 68fb ldr r3, [r7, #12] - 8002b20: f003 0308 and.w r3, r3, #8 - 8002b24: 2b00 cmp r3, #0 - 8002b26: d01b beq.n 8002b60 + 800548e: 68fb ldr r3, [r7, #12] + 8005490: f003 0308 and.w r3, r3, #8 + 8005494: 2b00 cmp r3, #0 + 8005496: d01b beq.n 80054d0 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); - 8002b28: 687b ldr r3, [r7, #4] - 8002b2a: 681b ldr r3, [r3, #0] - 8002b2c: f06f 0208 mvn.w r2, #8 - 8002b30: 611a str r2, [r3, #16] + 8005498: 687b ldr r3, [r7, #4] + 800549a: 681b ldr r3, [r3, #0] + 800549c: f06f 0208 mvn.w r2, #8 + 80054a0: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - 8002b32: 687b ldr r3, [r7, #4] - 8002b34: 2204 movs r2, #4 - 8002b36: 771a strb r2, [r3, #28] + 80054a2: 687b ldr r3, [r7, #4] + 80054a4: 2204 movs r2, #4 + 80054a6: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) - 8002b38: 687b ldr r3, [r7, #4] - 8002b3a: 681b ldr r3, [r3, #0] - 8002b3c: 69db ldr r3, [r3, #28] - 8002b3e: f003 0303 and.w r3, r3, #3 - 8002b42: 2b00 cmp r3, #0 - 8002b44: d003 beq.n 8002b4e + 80054a8: 687b ldr r3, [r7, #4] + 80054aa: 681b ldr r3, [r3, #0] + 80054ac: 69db ldr r3, [r3, #28] + 80054ae: f003 0303 and.w r3, r3, #3 + 80054b2: 2b00 cmp r3, #0 + 80054b4: d003 beq.n 80054be { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); - 8002b46: 6878 ldr r0, [r7, #4] - 8002b48: f000 f886 bl 8002c58 - 8002b4c: e005 b.n 8002b5a + 80054b6: 6878 ldr r0, [r7, #4] + 80054b8: f000 f886 bl 80055c8 + 80054bc: e005 b.n 80054ca { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); - 8002b4e: 6878 ldr r0, [r7, #4] - 8002b50: f000 f878 bl 8002c44 + 80054be: 6878 ldr r0, [r7, #4] + 80054c0: f000 f878 bl 80055b4 HAL_TIM_PWM_PulseFinishedCallback(htim); - 8002b54: 6878 ldr r0, [r7, #4] - 8002b56: f000 f889 bl 8002c6c + 80054c4: 6878 ldr r0, [r7, #4] + 80054c6: f000 f889 bl 80055dc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 8002b5a: 687b ldr r3, [r7, #4] - 8002b5c: 2200 movs r2, #0 - 8002b5e: 771a strb r2, [r3, #28] + 80054ca: 687b ldr r3, [r7, #4] + 80054cc: 2200 movs r2, #0 + 80054ce: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) - 8002b60: 68bb ldr r3, [r7, #8] - 8002b62: f003 0310 and.w r3, r3, #16 - 8002b66: 2b00 cmp r3, #0 - 8002b68: d020 beq.n 8002bac + 80054d0: 68bb ldr r3, [r7, #8] + 80054d2: f003 0310 and.w r3, r3, #16 + 80054d6: 2b00 cmp r3, #0 + 80054d8: d020 beq.n 800551c { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) - 8002b6a: 68fb ldr r3, [r7, #12] - 8002b6c: f003 0310 and.w r3, r3, #16 - 8002b70: 2b00 cmp r3, #0 - 8002b72: d01b beq.n 8002bac + 80054da: 68fb ldr r3, [r7, #12] + 80054dc: f003 0310 and.w r3, r3, #16 + 80054e0: 2b00 cmp r3, #0 + 80054e2: d01b beq.n 800551c { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); - 8002b74: 687b ldr r3, [r7, #4] - 8002b76: 681b ldr r3, [r3, #0] - 8002b78: f06f 0210 mvn.w r2, #16 - 8002b7c: 611a str r2, [r3, #16] + 80054e4: 687b ldr r3, [r7, #4] + 80054e6: 681b ldr r3, [r3, #0] + 80054e8: f06f 0210 mvn.w r2, #16 + 80054ec: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - 8002b7e: 687b ldr r3, [r7, #4] - 8002b80: 2208 movs r2, #8 - 8002b82: 771a strb r2, [r3, #28] + 80054ee: 687b ldr r3, [r7, #4] + 80054f0: 2208 movs r2, #8 + 80054f2: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) - 8002b84: 687b ldr r3, [r7, #4] - 8002b86: 681b ldr r3, [r3, #0] - 8002b88: 69db ldr r3, [r3, #28] - 8002b8a: f403 7340 and.w r3, r3, #768 @ 0x300 - 8002b8e: 2b00 cmp r3, #0 - 8002b90: d003 beq.n 8002b9a + 80054f4: 687b ldr r3, [r7, #4] + 80054f6: 681b ldr r3, [r3, #0] + 80054f8: 69db ldr r3, [r3, #28] + 80054fa: f403 7340 and.w r3, r3, #768 @ 0x300 + 80054fe: 2b00 cmp r3, #0 + 8005500: d003 beq.n 800550a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); - 8002b92: 6878 ldr r0, [r7, #4] - 8002b94: f000 f860 bl 8002c58 - 8002b98: e005 b.n 8002ba6 + 8005502: 6878 ldr r0, [r7, #4] + 8005504: f000 f860 bl 80055c8 + 8005508: e005 b.n 8005516 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); - 8002b9a: 6878 ldr r0, [r7, #4] - 8002b9c: f000 f852 bl 8002c44 + 800550a: 6878 ldr r0, [r7, #4] + 800550c: f000 f852 bl 80055b4 HAL_TIM_PWM_PulseFinishedCallback(htim); - 8002ba0: 6878 ldr r0, [r7, #4] - 8002ba2: f000 f863 bl 8002c6c + 8005510: 6878 ldr r0, [r7, #4] + 8005512: f000 f863 bl 80055dc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 8002ba6: 687b ldr r3, [r7, #4] - 8002ba8: 2200 movs r2, #0 - 8002baa: 771a strb r2, [r3, #28] + 8005516: 687b ldr r3, [r7, #4] + 8005518: 2200 movs r2, #0 + 800551a: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) - 8002bac: 68bb ldr r3, [r7, #8] - 8002bae: f003 0301 and.w r3, r3, #1 - 8002bb2: 2b00 cmp r3, #0 - 8002bb4: d00c beq.n 8002bd0 + 800551c: 68bb ldr r3, [r7, #8] + 800551e: f003 0301 and.w r3, r3, #1 + 8005522: 2b00 cmp r3, #0 + 8005524: d00c beq.n 8005540 { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) - 8002bb6: 68fb ldr r3, [r7, #12] - 8002bb8: f003 0301 and.w r3, r3, #1 - 8002bbc: 2b00 cmp r3, #0 - 8002bbe: d007 beq.n 8002bd0 + 8005526: 68fb ldr r3, [r7, #12] + 8005528: f003 0301 and.w r3, r3, #1 + 800552c: 2b00 cmp r3, #0 + 800552e: d007 beq.n 8005540 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); - 8002bc0: 687b ldr r3, [r7, #4] - 8002bc2: 681b ldr r3, [r3, #0] - 8002bc4: f06f 0201 mvn.w r2, #1 - 8002bc8: 611a str r2, [r3, #16] + 8005530: 687b ldr r3, [r7, #4] + 8005532: 681b ldr r3, [r3, #0] + 8005534: f06f 0201 mvn.w r2, #1 + 8005538: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); - 8002bca: 6878 ldr r0, [r7, #4] - 8002bcc: f7fd fe24 bl 8000818 + 800553a: 6878 ldr r0, [r7, #4] + 800553c: f7fb fba8 bl 8000c90 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) - 8002bd0: 68bb ldr r3, [r7, #8] - 8002bd2: f003 0380 and.w r3, r3, #128 @ 0x80 - 8002bd6: 2b00 cmp r3, #0 - 8002bd8: d00c beq.n 8002bf4 + 8005540: 68bb ldr r3, [r7, #8] + 8005542: f003 0380 and.w r3, r3, #128 @ 0x80 + 8005546: 2b00 cmp r3, #0 + 8005548: d00c beq.n 8005564 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) - 8002bda: 68fb ldr r3, [r7, #12] - 8002bdc: f003 0380 and.w r3, r3, #128 @ 0x80 - 8002be0: 2b00 cmp r3, #0 - 8002be2: d007 beq.n 8002bf4 + 800554a: 68fb ldr r3, [r7, #12] + 800554c: f003 0380 and.w r3, r3, #128 @ 0x80 + 8005550: 2b00 cmp r3, #0 + 8005552: d007 beq.n 8005564 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK); - 8002be4: 687b ldr r3, [r7, #4] - 8002be6: 681b ldr r3, [r3, #0] - 8002be8: f06f 0280 mvn.w r2, #128 @ 0x80 - 8002bec: 611a str r2, [r3, #16] + 8005554: 687b ldr r3, [r7, #4] + 8005556: 681b ldr r3, [r3, #0] + 8005558: f06f 0280 mvn.w r2, #128 @ 0x80 + 800555c: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); - 8002bee: 6878 ldr r0, [r7, #4] - 8002bf0: f000 f900 bl 8002df4 + 800555e: 6878 ldr r0, [r7, #4] + 8005560: f000 f900 bl 8005764 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) - 8002bf4: 68bb ldr r3, [r7, #8] - 8002bf6: f003 0340 and.w r3, r3, #64 @ 0x40 - 8002bfa: 2b00 cmp r3, #0 - 8002bfc: d00c beq.n 8002c18 + 8005564: 68bb ldr r3, [r7, #8] + 8005566: f003 0340 and.w r3, r3, #64 @ 0x40 + 800556a: 2b00 cmp r3, #0 + 800556c: d00c beq.n 8005588 { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) - 8002bfe: 68fb ldr r3, [r7, #12] - 8002c00: f003 0340 and.w r3, r3, #64 @ 0x40 - 8002c04: 2b00 cmp r3, #0 - 8002c06: d007 beq.n 8002c18 + 800556e: 68fb ldr r3, [r7, #12] + 8005570: f003 0340 and.w r3, r3, #64 @ 0x40 + 8005574: 2b00 cmp r3, #0 + 8005576: d007 beq.n 8005588 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); - 8002c08: 687b ldr r3, [r7, #4] - 8002c0a: 681b ldr r3, [r3, #0] - 8002c0c: f06f 0240 mvn.w r2, #64 @ 0x40 - 8002c10: 611a str r2, [r3, #16] + 8005578: 687b ldr r3, [r7, #4] + 800557a: 681b ldr r3, [r3, #0] + 800557c: f06f 0240 mvn.w r2, #64 @ 0x40 + 8005580: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); - 8002c12: 6878 ldr r0, [r7, #4] - 8002c14: f000 f834 bl 8002c80 + 8005582: 6878 ldr r0, [r7, #4] + 8005584: f000 f834 bl 80055f0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) - 8002c18: 68bb ldr r3, [r7, #8] - 8002c1a: f003 0320 and.w r3, r3, #32 - 8002c1e: 2b00 cmp r3, #0 - 8002c20: d00c beq.n 8002c3c + 8005588: 68bb ldr r3, [r7, #8] + 800558a: f003 0320 and.w r3, r3, #32 + 800558e: 2b00 cmp r3, #0 + 8005590: d00c beq.n 80055ac { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) - 8002c22: 68fb ldr r3, [r7, #12] - 8002c24: f003 0320 and.w r3, r3, #32 - 8002c28: 2b00 cmp r3, #0 - 8002c2a: d007 beq.n 8002c3c + 8005592: 68fb ldr r3, [r7, #12] + 8005594: f003 0320 and.w r3, r3, #32 + 8005598: 2b00 cmp r3, #0 + 800559a: d007 beq.n 80055ac { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); - 8002c2c: 687b ldr r3, [r7, #4] - 8002c2e: 681b ldr r3, [r3, #0] - 8002c30: f06f 0220 mvn.w r2, #32 - 8002c34: 611a str r2, [r3, #16] + 800559c: 687b ldr r3, [r7, #4] + 800559e: 681b ldr r3, [r3, #0] + 80055a0: f06f 0220 mvn.w r2, #32 + 80055a4: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); - 8002c36: 6878 ldr r0, [r7, #4] - 8002c38: f000 f8d2 bl 8002de0 + 80055a6: 6878 ldr r0, [r7, #4] + 80055a8: f000 f8d2 bl 8005750 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } - 8002c3c: bf00 nop - 8002c3e: 3710 adds r7, #16 - 8002c40: 46bd mov sp, r7 - 8002c42: bd80 pop {r7, pc} + 80055ac: bf00 nop + 80055ae: 3710 adds r7, #16 + 80055b0: 46bd mov sp, r7 + 80055b2: bd80 pop {r7, pc} -08002c44 : +080055b4 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { - 8002c44: b480 push {r7} - 8002c46: b083 sub sp, #12 - 8002c48: af00 add r7, sp, #0 - 8002c4a: 6078 str r0, [r7, #4] + 80055b4: b480 push {r7} + 80055b6: b083 sub sp, #12 + 80055b8: af00 add r7, sp, #0 + 80055ba: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } - 8002c4c: bf00 nop - 8002c4e: 370c adds r7, #12 - 8002c50: 46bd mov sp, r7 - 8002c52: f85d 7b04 ldr.w r7, [sp], #4 - 8002c56: 4770 bx lr + 80055bc: bf00 nop + 80055be: 370c adds r7, #12 + 80055c0: 46bd mov sp, r7 + 80055c2: f85d 7b04 ldr.w r7, [sp], #4 + 80055c6: 4770 bx lr -08002c58 : +080055c8 : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { - 8002c58: b480 push {r7} - 8002c5a: b083 sub sp, #12 - 8002c5c: af00 add r7, sp, #0 - 8002c5e: 6078 str r0, [r7, #4] + 80055c8: b480 push {r7} + 80055ca: b083 sub sp, #12 + 80055cc: af00 add r7, sp, #0 + 80055ce: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } - 8002c60: bf00 nop - 8002c62: 370c adds r7, #12 - 8002c64: 46bd mov sp, r7 - 8002c66: f85d 7b04 ldr.w r7, [sp], #4 - 8002c6a: 4770 bx lr + 80055d0: bf00 nop + 80055d2: 370c adds r7, #12 + 80055d4: 46bd mov sp, r7 + 80055d6: f85d 7b04 ldr.w r7, [sp], #4 + 80055da: 4770 bx lr -08002c6c : +080055dc : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { - 8002c6c: b480 push {r7} - 8002c6e: b083 sub sp, #12 - 8002c70: af00 add r7, sp, #0 - 8002c72: 6078 str r0, [r7, #4] + 80055dc: b480 push {r7} + 80055de: b083 sub sp, #12 + 80055e0: af00 add r7, sp, #0 + 80055e2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } - 8002c74: bf00 nop - 8002c76: 370c adds r7, #12 - 8002c78: 46bd mov sp, r7 - 8002c7a: f85d 7b04 ldr.w r7, [sp], #4 - 8002c7e: 4770 bx lr + 80055e4: bf00 nop + 80055e6: 370c adds r7, #12 + 80055e8: 46bd mov sp, r7 + 80055ea: f85d 7b04 ldr.w r7, [sp], #4 + 80055ee: 4770 bx lr -08002c80 : +080055f0 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { - 8002c80: b480 push {r7} - 8002c82: b083 sub sp, #12 - 8002c84: af00 add r7, sp, #0 - 8002c86: 6078 str r0, [r7, #4] + 80055f0: b480 push {r7} + 80055f2: b083 sub sp, #12 + 80055f4: af00 add r7, sp, #0 + 80055f6: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } - 8002c88: bf00 nop - 8002c8a: 370c adds r7, #12 - 8002c8c: 46bd mov sp, r7 - 8002c8e: f85d 7b04 ldr.w r7, [sp], #4 - 8002c92: 4770 bx lr + 80055f8: bf00 nop + 80055fa: 370c adds r7, #12 + 80055fc: 46bd mov sp, r7 + 80055fe: f85d 7b04 ldr.w r7, [sp], #4 + 8005602: 4770 bx lr -08002c94 : +08005604 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { - 8002c94: b480 push {r7} - 8002c96: b085 sub sp, #20 - 8002c98: af00 add r7, sp, #0 - 8002c9a: 6078 str r0, [r7, #4] - 8002c9c: 6039 str r1, [r7, #0] + 8005604: b480 push {r7} + 8005606: b085 sub sp, #20 + 8005608: af00 add r7, sp, #0 + 800560a: 6078 str r0, [r7, #4] + 800560c: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; - 8002c9e: 687b ldr r3, [r7, #4] - 8002ca0: 681b ldr r3, [r3, #0] - 8002ca2: 60fb str r3, [r7, #12] + 800560e: 687b ldr r3, [r7, #4] + 8005610: 681b ldr r3, [r3, #0] + 8005612: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) - 8002ca4: 687b ldr r3, [r7, #4] - 8002ca6: 4a43 ldr r2, [pc, #268] @ (8002db4 ) - 8002ca8: 4293 cmp r3, r2 - 8002caa: d013 beq.n 8002cd4 - 8002cac: 687b ldr r3, [r7, #4] - 8002cae: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 - 8002cb2: d00f beq.n 8002cd4 - 8002cb4: 687b ldr r3, [r7, #4] - 8002cb6: 4a40 ldr r2, [pc, #256] @ (8002db8 ) - 8002cb8: 4293 cmp r3, r2 - 8002cba: d00b beq.n 8002cd4 - 8002cbc: 687b ldr r3, [r7, #4] - 8002cbe: 4a3f ldr r2, [pc, #252] @ (8002dbc ) - 8002cc0: 4293 cmp r3, r2 - 8002cc2: d007 beq.n 8002cd4 - 8002cc4: 687b ldr r3, [r7, #4] - 8002cc6: 4a3e ldr r2, [pc, #248] @ (8002dc0 ) - 8002cc8: 4293 cmp r3, r2 - 8002cca: d003 beq.n 8002cd4 - 8002ccc: 687b ldr r3, [r7, #4] - 8002cce: 4a3d ldr r2, [pc, #244] @ (8002dc4 ) - 8002cd0: 4293 cmp r3, r2 - 8002cd2: d108 bne.n 8002ce6 + 8005614: 687b ldr r3, [r7, #4] + 8005616: 4a43 ldr r2, [pc, #268] @ (8005724 ) + 8005618: 4293 cmp r3, r2 + 800561a: d013 beq.n 8005644 + 800561c: 687b ldr r3, [r7, #4] + 800561e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8005622: d00f beq.n 8005644 + 8005624: 687b ldr r3, [r7, #4] + 8005626: 4a40 ldr r2, [pc, #256] @ (8005728 ) + 8005628: 4293 cmp r3, r2 + 800562a: d00b beq.n 8005644 + 800562c: 687b ldr r3, [r7, #4] + 800562e: 4a3f ldr r2, [pc, #252] @ (800572c ) + 8005630: 4293 cmp r3, r2 + 8005632: d007 beq.n 8005644 + 8005634: 687b ldr r3, [r7, #4] + 8005636: 4a3e ldr r2, [pc, #248] @ (8005730 ) + 8005638: 4293 cmp r3, r2 + 800563a: d003 beq.n 8005644 + 800563c: 687b ldr r3, [r7, #4] + 800563e: 4a3d ldr r2, [pc, #244] @ (8005734 ) + 8005640: 4293 cmp r3, r2 + 8005642: d108 bne.n 8005656 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); - 8002cd4: 68fb ldr r3, [r7, #12] - 8002cd6: f023 0370 bic.w r3, r3, #112 @ 0x70 - 8002cda: 60fb str r3, [r7, #12] + 8005644: 68fb ldr r3, [r7, #12] + 8005646: f023 0370 bic.w r3, r3, #112 @ 0x70 + 800564a: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; - 8002cdc: 683b ldr r3, [r7, #0] - 8002cde: 685b ldr r3, [r3, #4] - 8002ce0: 68fa ldr r2, [r7, #12] - 8002ce2: 4313 orrs r3, r2 - 8002ce4: 60fb str r3, [r7, #12] + 800564c: 683b ldr r3, [r7, #0] + 800564e: 685b ldr r3, [r3, #4] + 8005650: 68fa ldr r2, [r7, #12] + 8005652: 4313 orrs r3, r2 + 8005654: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) - 8002ce6: 687b ldr r3, [r7, #4] - 8002ce8: 4a32 ldr r2, [pc, #200] @ (8002db4 ) - 8002cea: 4293 cmp r3, r2 - 8002cec: d02b beq.n 8002d46 - 8002cee: 687b ldr r3, [r7, #4] - 8002cf0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 - 8002cf4: d027 beq.n 8002d46 - 8002cf6: 687b ldr r3, [r7, #4] - 8002cf8: 4a2f ldr r2, [pc, #188] @ (8002db8 ) - 8002cfa: 4293 cmp r3, r2 - 8002cfc: d023 beq.n 8002d46 - 8002cfe: 687b ldr r3, [r7, #4] - 8002d00: 4a2e ldr r2, [pc, #184] @ (8002dbc ) - 8002d02: 4293 cmp r3, r2 - 8002d04: d01f beq.n 8002d46 - 8002d06: 687b ldr r3, [r7, #4] - 8002d08: 4a2d ldr r2, [pc, #180] @ (8002dc0 ) - 8002d0a: 4293 cmp r3, r2 - 8002d0c: d01b beq.n 8002d46 - 8002d0e: 687b ldr r3, [r7, #4] - 8002d10: 4a2c ldr r2, [pc, #176] @ (8002dc4 ) - 8002d12: 4293 cmp r3, r2 - 8002d14: d017 beq.n 8002d46 - 8002d16: 687b ldr r3, [r7, #4] - 8002d18: 4a2b ldr r2, [pc, #172] @ (8002dc8 ) - 8002d1a: 4293 cmp r3, r2 - 8002d1c: d013 beq.n 8002d46 - 8002d1e: 687b ldr r3, [r7, #4] - 8002d20: 4a2a ldr r2, [pc, #168] @ (8002dcc ) - 8002d22: 4293 cmp r3, r2 - 8002d24: d00f beq.n 8002d46 - 8002d26: 687b ldr r3, [r7, #4] - 8002d28: 4a29 ldr r2, [pc, #164] @ (8002dd0 ) - 8002d2a: 4293 cmp r3, r2 - 8002d2c: d00b beq.n 8002d46 - 8002d2e: 687b ldr r3, [r7, #4] - 8002d30: 4a28 ldr r2, [pc, #160] @ (8002dd4 ) - 8002d32: 4293 cmp r3, r2 - 8002d34: d007 beq.n 8002d46 - 8002d36: 687b ldr r3, [r7, #4] - 8002d38: 4a27 ldr r2, [pc, #156] @ (8002dd8 ) - 8002d3a: 4293 cmp r3, r2 - 8002d3c: d003 beq.n 8002d46 - 8002d3e: 687b ldr r3, [r7, #4] - 8002d40: 4a26 ldr r2, [pc, #152] @ (8002ddc ) - 8002d42: 4293 cmp r3, r2 - 8002d44: d108 bne.n 8002d58 + 8005656: 687b ldr r3, [r7, #4] + 8005658: 4a32 ldr r2, [pc, #200] @ (8005724 ) + 800565a: 4293 cmp r3, r2 + 800565c: d02b beq.n 80056b6 + 800565e: 687b ldr r3, [r7, #4] + 8005660: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8005664: d027 beq.n 80056b6 + 8005666: 687b ldr r3, [r7, #4] + 8005668: 4a2f ldr r2, [pc, #188] @ (8005728 ) + 800566a: 4293 cmp r3, r2 + 800566c: d023 beq.n 80056b6 + 800566e: 687b ldr r3, [r7, #4] + 8005670: 4a2e ldr r2, [pc, #184] @ (800572c ) + 8005672: 4293 cmp r3, r2 + 8005674: d01f beq.n 80056b6 + 8005676: 687b ldr r3, [r7, #4] + 8005678: 4a2d ldr r2, [pc, #180] @ (8005730 ) + 800567a: 4293 cmp r3, r2 + 800567c: d01b beq.n 80056b6 + 800567e: 687b ldr r3, [r7, #4] + 8005680: 4a2c ldr r2, [pc, #176] @ (8005734 ) + 8005682: 4293 cmp r3, r2 + 8005684: d017 beq.n 80056b6 + 8005686: 687b ldr r3, [r7, #4] + 8005688: 4a2b ldr r2, [pc, #172] @ (8005738 ) + 800568a: 4293 cmp r3, r2 + 800568c: d013 beq.n 80056b6 + 800568e: 687b ldr r3, [r7, #4] + 8005690: 4a2a ldr r2, [pc, #168] @ (800573c ) + 8005692: 4293 cmp r3, r2 + 8005694: d00f beq.n 80056b6 + 8005696: 687b ldr r3, [r7, #4] + 8005698: 4a29 ldr r2, [pc, #164] @ (8005740 ) + 800569a: 4293 cmp r3, r2 + 800569c: d00b beq.n 80056b6 + 800569e: 687b ldr r3, [r7, #4] + 80056a0: 4a28 ldr r2, [pc, #160] @ (8005744 ) + 80056a2: 4293 cmp r3, r2 + 80056a4: d007 beq.n 80056b6 + 80056a6: 687b ldr r3, [r7, #4] + 80056a8: 4a27 ldr r2, [pc, #156] @ (8005748 ) + 80056aa: 4293 cmp r3, r2 + 80056ac: d003 beq.n 80056b6 + 80056ae: 687b ldr r3, [r7, #4] + 80056b0: 4a26 ldr r2, [pc, #152] @ (800574c ) + 80056b2: 4293 cmp r3, r2 + 80056b4: d108 bne.n 80056c8 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; - 8002d46: 68fb ldr r3, [r7, #12] - 8002d48: f423 7340 bic.w r3, r3, #768 @ 0x300 - 8002d4c: 60fb str r3, [r7, #12] + 80056b6: 68fb ldr r3, [r7, #12] + 80056b8: f423 7340 bic.w r3, r3, #768 @ 0x300 + 80056bc: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; - 8002d4e: 683b ldr r3, [r7, #0] - 8002d50: 68db ldr r3, [r3, #12] - 8002d52: 68fa ldr r2, [r7, #12] - 8002d54: 4313 orrs r3, r2 - 8002d56: 60fb str r3, [r7, #12] + 80056be: 683b ldr r3, [r7, #0] + 80056c0: 68db ldr r3, [r3, #12] + 80056c2: 68fa ldr r2, [r7, #12] + 80056c4: 4313 orrs r3, r2 + 80056c6: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); - 8002d58: 68fb ldr r3, [r7, #12] - 8002d5a: f023 0280 bic.w r2, r3, #128 @ 0x80 - 8002d5e: 683b ldr r3, [r7, #0] - 8002d60: 695b ldr r3, [r3, #20] - 8002d62: 4313 orrs r3, r2 - 8002d64: 60fb str r3, [r7, #12] + 80056c8: 68fb ldr r3, [r7, #12] + 80056ca: f023 0280 bic.w r2, r3, #128 @ 0x80 + 80056ce: 683b ldr r3, [r7, #0] + 80056d0: 695b ldr r3, [r3, #20] + 80056d2: 4313 orrs r3, r2 + 80056d4: 60fb str r3, [r7, #12] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; - 8002d66: 683b ldr r3, [r7, #0] - 8002d68: 689a ldr r2, [r3, #8] - 8002d6a: 687b ldr r3, [r7, #4] - 8002d6c: 62da str r2, [r3, #44] @ 0x2c + 80056d6: 683b ldr r3, [r7, #0] + 80056d8: 689a ldr r2, [r3, #8] + 80056da: 687b ldr r3, [r7, #4] + 80056dc: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; - 8002d6e: 683b ldr r3, [r7, #0] - 8002d70: 681a ldr r2, [r3, #0] - 8002d72: 687b ldr r3, [r7, #4] - 8002d74: 629a str r2, [r3, #40] @ 0x28 + 80056de: 683b ldr r3, [r7, #0] + 80056e0: 681a ldr r2, [r3, #0] + 80056e2: 687b ldr r3, [r7, #4] + 80056e4: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) - 8002d76: 687b ldr r3, [r7, #4] - 8002d78: 4a0e ldr r2, [pc, #56] @ (8002db4 ) - 8002d7a: 4293 cmp r3, r2 - 8002d7c: d003 beq.n 8002d86 - 8002d7e: 687b ldr r3, [r7, #4] - 8002d80: 4a10 ldr r2, [pc, #64] @ (8002dc4 ) - 8002d82: 4293 cmp r3, r2 - 8002d84: d103 bne.n 8002d8e + 80056e6: 687b ldr r3, [r7, #4] + 80056e8: 4a0e ldr r2, [pc, #56] @ (8005724 ) + 80056ea: 4293 cmp r3, r2 + 80056ec: d003 beq.n 80056f6 + 80056ee: 687b ldr r3, [r7, #4] + 80056f0: 4a10 ldr r2, [pc, #64] @ (8005734 ) + 80056f2: 4293 cmp r3, r2 + 80056f4: d103 bne.n 80056fe { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; - 8002d86: 683b ldr r3, [r7, #0] - 8002d88: 691a ldr r2, [r3, #16] - 8002d8a: 687b ldr r3, [r7, #4] - 8002d8c: 631a str r2, [r3, #48] @ 0x30 + 80056f6: 683b ldr r3, [r7, #0] + 80056f8: 691a ldr r2, [r3, #16] + 80056fa: 687b ldr r3, [r7, #4] + 80056fc: 631a str r2, [r3, #48] @ 0x30 } /* Disable Update Event (UEV) with Update Generation (UG) by changing Update Request Source (URS) to avoid Update flag (UIF) */ SET_BIT(TIMx->CR1, TIM_CR1_URS); - 8002d8e: 687b ldr r3, [r7, #4] - 8002d90: 681b ldr r3, [r3, #0] - 8002d92: f043 0204 orr.w r2, r3, #4 - 8002d96: 687b ldr r3, [r7, #4] - 8002d98: 601a str r2, [r3, #0] + 80056fe: 687b ldr r3, [r7, #4] + 8005700: 681b ldr r3, [r3, #0] + 8005702: f043 0204 orr.w r2, r3, #4 + 8005706: 687b ldr r3, [r7, #4] + 8005708: 601a str r2, [r3, #0] /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; - 8002d9a: 687b ldr r3, [r7, #4] - 8002d9c: 2201 movs r2, #1 - 8002d9e: 615a str r2, [r3, #20] + 800570a: 687b ldr r3, [r7, #4] + 800570c: 2201 movs r2, #1 + 800570e: 615a str r2, [r3, #20] TIMx->CR1 = tmpcr1; - 8002da0: 687b ldr r3, [r7, #4] - 8002da2: 68fa ldr r2, [r7, #12] - 8002da4: 601a str r2, [r3, #0] + 8005710: 687b ldr r3, [r7, #4] + 8005712: 68fa ldr r2, [r7, #12] + 8005714: 601a str r2, [r3, #0] } - 8002da6: bf00 nop - 8002da8: 3714 adds r7, #20 - 8002daa: 46bd mov sp, r7 - 8002dac: f85d 7b04 ldr.w r7, [sp], #4 - 8002db0: 4770 bx lr - 8002db2: bf00 nop - 8002db4: 40010000 .word 0x40010000 - 8002db8: 40000400 .word 0x40000400 - 8002dbc: 40000800 .word 0x40000800 - 8002dc0: 40000c00 .word 0x40000c00 - 8002dc4: 40010400 .word 0x40010400 - 8002dc8: 40014000 .word 0x40014000 - 8002dcc: 40014400 .word 0x40014400 - 8002dd0: 40014800 .word 0x40014800 - 8002dd4: 40001800 .word 0x40001800 - 8002dd8: 40001c00 .word 0x40001c00 - 8002ddc: 40002000 .word 0x40002000 + 8005716: bf00 nop + 8005718: 3714 adds r7, #20 + 800571a: 46bd mov sp, r7 + 800571c: f85d 7b04 ldr.w r7, [sp], #4 + 8005720: 4770 bx lr + 8005722: bf00 nop + 8005724: 40010000 .word 0x40010000 + 8005728: 40000400 .word 0x40000400 + 800572c: 40000800 .word 0x40000800 + 8005730: 40000c00 .word 0x40000c00 + 8005734: 40010400 .word 0x40010400 + 8005738: 40014000 .word 0x40014000 + 800573c: 40014400 .word 0x40014400 + 8005740: 40014800 .word 0x40014800 + 8005744: 40001800 .word 0x40001800 + 8005748: 40001c00 .word 0x40001c00 + 800574c: 40002000 .word 0x40002000 -08002de0 : +08005750 : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { - 8002de0: b480 push {r7} - 8002de2: b083 sub sp, #12 - 8002de4: af00 add r7, sp, #0 - 8002de6: 6078 str r0, [r7, #4] + 8005750: b480 push {r7} + 8005752: b083 sub sp, #12 + 8005754: af00 add r7, sp, #0 + 8005756: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } - 8002de8: bf00 nop - 8002dea: 370c adds r7, #12 - 8002dec: 46bd mov sp, r7 - 8002dee: f85d 7b04 ldr.w r7, [sp], #4 - 8002df2: 4770 bx lr + 8005758: bf00 nop + 800575a: 370c adds r7, #12 + 800575c: 46bd mov sp, r7 + 800575e: f85d 7b04 ldr.w r7, [sp], #4 + 8005762: 4770 bx lr -08002df4 : +08005764 : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { - 8002df4: b480 push {r7} - 8002df6: b083 sub sp, #12 - 8002df8: af00 add r7, sp, #0 - 8002dfa: 6078 str r0, [r7, #4] + 8005764: b480 push {r7} + 8005766: b083 sub sp, #12 + 8005768: af00 add r7, sp, #0 + 800576a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } - 8002dfc: bf00 nop - 8002dfe: 370c adds r7, #12 - 8002e00: 46bd mov sp, r7 - 8002e02: f85d 7b04 ldr.w r7, [sp], #4 - 8002e06: 4770 bx lr + 800576c: bf00 nop + 800576e: 370c adds r7, #12 + 8005770: 46bd mov sp, r7 + 8005772: f85d 7b04 ldr.w r7, [sp], #4 + 8005776: 4770 bx lr -08002e08 <__NVIC_SetPriority>: +08005778 : + * @param SDIOx: Pointer to SDMMC register base + * @param Init: SDMMC initialization structure + * @retval HAL status + */ +HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init) { - 8002e08: b480 push {r7} - 8002e0a: b083 sub sp, #12 - 8002e0c: af00 add r7, sp, #0 - 8002e0e: 4603 mov r3, r0 - 8002e10: 6039 str r1, [r7, #0] - 8002e12: 71fb strb r3, [r7, #7] - if ((int32_t)(IRQn) >= 0) - 8002e14: f997 3007 ldrsb.w r3, [r7, #7] - 8002e18: 2b00 cmp r3, #0 - 8002e1a: db0a blt.n 8002e32 <__NVIC_SetPriority+0x2a> - NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 8002e1c: 683b ldr r3, [r7, #0] - 8002e1e: b2da uxtb r2, r3 - 8002e20: 490c ldr r1, [pc, #48] @ (8002e54 <__NVIC_SetPriority+0x4c>) - 8002e22: f997 3007 ldrsb.w r3, [r7, #7] - 8002e26: 0112 lsls r2, r2, #4 - 8002e28: b2d2 uxtb r2, r2 - 8002e2a: 440b add r3, r1 - 8002e2c: f883 2300 strb.w r2, [r3, #768] @ 0x300 -} - 8002e30: e00a b.n 8002e48 <__NVIC_SetPriority+0x40> - SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 8002e32: 683b ldr r3, [r7, #0] - 8002e34: b2da uxtb r2, r3 - 8002e36: 4908 ldr r1, [pc, #32] @ (8002e58 <__NVIC_SetPriority+0x50>) - 8002e38: 79fb ldrb r3, [r7, #7] - 8002e3a: f003 030f and.w r3, r3, #15 - 8002e3e: 3b04 subs r3, #4 - 8002e40: 0112 lsls r2, r2, #4 - 8002e42: b2d2 uxtb r2, r2 - 8002e44: 440b add r3, r1 - 8002e46: 761a strb r2, [r3, #24] -} - 8002e48: bf00 nop - 8002e4a: 370c adds r7, #12 - 8002e4c: 46bd mov sp, r7 - 8002e4e: f85d 7b04 ldr.w r7, [sp], #4 - 8002e52: 4770 bx lr - 8002e54: e000e100 .word 0xe000e100 - 8002e58: e000ed00 .word 0xe000ed00 + 8005778: b084 sub sp, #16 + 800577a: b580 push {r7, lr} + 800577c: b084 sub sp, #16 + 800577e: af00 add r7, sp, #0 + 8005780: 6078 str r0, [r7, #4] + 8005782: f107 001c add.w r0, r7, #28 + 8005786: e880 000e stmia.w r0, {r1, r2, r3} + uint32_t tmpreg = 0; + 800578a: 2300 movs r3, #0 + 800578c: 60fb str r3, [r7, #12] -08002e5c : + /* Check the parameters */ + assert_param(IS_SDIO_ALL_INSTANCE(SDIOx)); + 800578e: 687b ldr r3, [r7, #4] + 8005790: 4a34 ldr r2, [pc, #208] @ (8005864 ) + 8005792: 4293 cmp r3, r2 + 8005794: d003 beq.n 800579e + 8005796: 21d4 movs r1, #212 @ 0xd4 + 8005798: 4833 ldr r0, [pc, #204] @ (8005868 ) + 800579a: f7fb facb bl 8000d34 + assert_param(IS_SDIO_CLOCK_EDGE(Init.ClockEdge)); + 800579e: 69fb ldr r3, [r7, #28] + 80057a0: 2b00 cmp r3, #0 + 80057a2: d007 beq.n 80057b4 + 80057a4: 69fb ldr r3, [r7, #28] + 80057a6: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 80057aa: d003 beq.n 80057b4 + 80057ac: 21d5 movs r1, #213 @ 0xd5 + 80057ae: 482e ldr r0, [pc, #184] @ (8005868 ) + 80057b0: f7fb fac0 bl 8000d34 + assert_param(IS_SDIO_CLOCK_BYPASS(Init.ClockBypass)); + 80057b4: 6a3b ldr r3, [r7, #32] + 80057b6: 2b00 cmp r3, #0 + 80057b8: d007 beq.n 80057ca + 80057ba: 6a3b ldr r3, [r7, #32] + 80057bc: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 80057c0: d003 beq.n 80057ca + 80057c2: 21d6 movs r1, #214 @ 0xd6 + 80057c4: 4828 ldr r0, [pc, #160] @ (8005868 ) + 80057c6: f7fb fab5 bl 8000d34 + assert_param(IS_SDIO_CLOCK_POWER_SAVE(Init.ClockPowerSave)); + 80057ca: 6a7b ldr r3, [r7, #36] @ 0x24 + 80057cc: 2b00 cmp r3, #0 + 80057ce: d007 beq.n 80057e0 + 80057d0: 6a7b ldr r3, [r7, #36] @ 0x24 + 80057d2: f5b3 7f00 cmp.w r3, #512 @ 0x200 + 80057d6: d003 beq.n 80057e0 + 80057d8: 21d7 movs r1, #215 @ 0xd7 + 80057da: 4823 ldr r0, [pc, #140] @ (8005868 ) + 80057dc: f7fb faaa bl 8000d34 + assert_param(IS_SDIO_BUS_WIDE(Init.BusWide)); + 80057e0: 6abb ldr r3, [r7, #40] @ 0x28 + 80057e2: 2b00 cmp r3, #0 + 80057e4: d00b beq.n 80057fe + 80057e6: 6abb ldr r3, [r7, #40] @ 0x28 + 80057e8: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 80057ec: d007 beq.n 80057fe + 80057ee: 6abb ldr r3, [r7, #40] @ 0x28 + 80057f0: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 80057f4: d003 beq.n 80057fe + 80057f6: 21d8 movs r1, #216 @ 0xd8 + 80057f8: 481b ldr r0, [pc, #108] @ (8005868 ) + 80057fa: f7fb fa9b bl 8000d34 + assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl)); + 80057fe: 6afb ldr r3, [r7, #44] @ 0x2c + 8005800: 2b00 cmp r3, #0 + 8005802: d007 beq.n 8005814 + 8005804: 6afb ldr r3, [r7, #44] @ 0x2c + 8005806: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 + 800580a: d003 beq.n 8005814 + 800580c: 21d9 movs r1, #217 @ 0xd9 + 800580e: 4816 ldr r0, [pc, #88] @ (8005868 ) + 8005810: f7fb fa90 bl 8000d34 + assert_param(IS_SDIO_CLKDIV(Init.ClockDiv)); + 8005814: 6b3b ldr r3, [r7, #48] @ 0x30 + 8005816: 2bff cmp r3, #255 @ 0xff + 8005818: d903 bls.n 8005822 + 800581a: 21da movs r1, #218 @ 0xda + 800581c: 4812 ldr r0, [pc, #72] @ (8005868 ) + 800581e: f7fb fa89 bl 8000d34 + + /* Set SDMMC configuration parameters */ + tmpreg |= (Init.ClockEdge |\ + 8005822: 69fa ldr r2, [r7, #28] + Init.ClockBypass |\ + 8005824: 6a3b ldr r3, [r7, #32] + tmpreg |= (Init.ClockEdge |\ + 8005826: 431a orrs r2, r3 + Init.ClockPowerSave |\ + 8005828: 6a7b ldr r3, [r7, #36] @ 0x24 + Init.ClockBypass |\ + 800582a: 431a orrs r2, r3 + Init.BusWide |\ + 800582c: 6abb ldr r3, [r7, #40] @ 0x28 + Init.ClockPowerSave |\ + 800582e: 431a orrs r2, r3 + Init.HardwareFlowControl |\ + 8005830: 6afb ldr r3, [r7, #44] @ 0x2c + Init.BusWide |\ + 8005832: 431a orrs r2, r3 + Init.ClockDiv + 8005834: 6b3b ldr r3, [r7, #48] @ 0x30 + Init.HardwareFlowControl |\ + 8005836: 4313 orrs r3, r2 + tmpreg |= (Init.ClockEdge |\ + 8005838: 68fa ldr r2, [r7, #12] + 800583a: 4313 orrs r3, r2 + 800583c: 60fb str r3, [r7, #12] + ); + + /* Write to SDMMC CLKCR */ + MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, tmpreg); + 800583e: 687b ldr r3, [r7, #4] + 8005840: 685b ldr r3, [r3, #4] + 8005842: f423 43fd bic.w r3, r3, #32384 @ 0x7e80 + 8005846: f023 037f bic.w r3, r3, #127 @ 0x7f + 800584a: 68fa ldr r2, [r7, #12] + 800584c: 431a orrs r2, r3 + 800584e: 687b ldr r3, [r7, #4] + 8005850: 605a str r2, [r3, #4] + + return HAL_OK; + 8005852: 2300 movs r3, #0 +} + 8005854: 4618 mov r0, r3 + 8005856: 3710 adds r7, #16 + 8005858: 46bd mov sp, r7 + 800585a: e8bd 4080 ldmia.w sp!, {r7, lr} + 800585e: b004 add sp, #16 + 8005860: 4770 bx lr + 8005862: bf00 nop + 8005864: 40012c00 .word 0x40012c00 + 8005868: 0800a24c .word 0x0800a24c + +0800586c : + * @brief Read data (word) from Rx FIFO in blocking mode (polling) + * @param SDIOx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx) +{ + 800586c: b480 push {r7} + 800586e: b083 sub sp, #12 + 8005870: af00 add r7, sp, #0 + 8005872: 6078 str r0, [r7, #4] + /* Read data from Rx FIFO */ + return (SDIOx->FIFO); + 8005874: 687b ldr r3, [r7, #4] + 8005876: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 +} + 800587a: 4618 mov r0, r3 + 800587c: 370c adds r7, #12 + 800587e: 46bd mov sp, r7 + 8005880: f85d 7b04 ldr.w r7, [sp], #4 + 8005884: 4770 bx lr + +08005886 : + * @param SDIOx: Pointer to SDMMC register base + * @param pWriteData: pointer to data to write + * @retval HAL status + */ +HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData) +{ + 8005886: b480 push {r7} + 8005888: b083 sub sp, #12 + 800588a: af00 add r7, sp, #0 + 800588c: 6078 str r0, [r7, #4] + 800588e: 6039 str r1, [r7, #0] + /* Write data to FIFO */ + SDIOx->FIFO = *pWriteData; + 8005890: 683b ldr r3, [r7, #0] + 8005892: 681a ldr r2, [r3, #0] + 8005894: 687b ldr r3, [r7, #4] + 8005896: f8c3 2080 str.w r2, [r3, #128] @ 0x80 + + return HAL_OK; + 800589a: 2300 movs r3, #0 +} + 800589c: 4618 mov r0, r3 + 800589e: 370c adds r7, #12 + 80058a0: 46bd mov sp, r7 + 80058a2: f85d 7b04 ldr.w r7, [sp], #4 + 80058a6: 4770 bx lr + +080058a8 : + * @brief Set SDMMC Power state to ON. + * @param SDIOx: Pointer to SDMMC register base + * @retval HAL status + */ +HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx) +{ + 80058a8: b480 push {r7} + 80058aa: b083 sub sp, #12 + 80058ac: af00 add r7, sp, #0 + 80058ae: 6078 str r0, [r7, #4] + /* Set power state to ON */ + SDIOx->POWER = SDIO_POWER_PWRCTRL; + 80058b0: 687b ldr r3, [r7, #4] + 80058b2: 2203 movs r2, #3 + 80058b4: 601a str r2, [r3, #0] + + return HAL_OK; + 80058b6: 2300 movs r3, #0 +} + 80058b8: 4618 mov r0, r3 + 80058ba: 370c adds r7, #12 + 80058bc: 46bd mov sp, r7 + 80058be: f85d 7b04 ldr.w r7, [sp], #4 + 80058c2: 4770 bx lr + +080058c4 : + * - 0x00: Power OFF + * - 0x02: Power UP + * - 0x03: Power ON + */ +uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx) +{ + 80058c4: b480 push {r7} + 80058c6: b083 sub sp, #12 + 80058c8: af00 add r7, sp, #0 + 80058ca: 6078 str r0, [r7, #4] + return (SDIOx->POWER & SDIO_POWER_PWRCTRL); + 80058cc: 687b ldr r3, [r7, #4] + 80058ce: 681b ldr r3, [r3, #0] + 80058d0: f003 0303 and.w r3, r3, #3 +} + 80058d4: 4618 mov r0, r3 + 80058d6: 370c adds r7, #12 + 80058d8: 46bd mov sp, r7 + 80058da: f85d 7b04 ldr.w r7, [sp], #4 + 80058de: 4770 bx lr + +080058e0 : + * @param Command: pointer to a SDIO_CmdInitTypeDef structure that contains + * the configuration information for the SDMMC command + * @retval HAL status + */ +HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command) +{ + 80058e0: b580 push {r7, lr} + 80058e2: b084 sub sp, #16 + 80058e4: af00 add r7, sp, #0 + 80058e6: 6078 str r0, [r7, #4] + 80058e8: 6039 str r1, [r7, #0] + uint32_t tmpreg = 0; + 80058ea: 2300 movs r3, #0 + 80058ec: 60fb str r3, [r7, #12] + + /* Check the parameters */ + assert_param(IS_SDIO_CMD_INDEX(Command->CmdIndex)); + 80058ee: 683b ldr r3, [r7, #0] + 80058f0: 685b ldr r3, [r3, #4] + 80058f2: 2b3f cmp r3, #63 @ 0x3f + 80058f4: d904 bls.n 8005900 + 80058f6: f44f 71b0 mov.w r1, #352 @ 0x160 + 80058fa: 482b ldr r0, [pc, #172] @ (80059a8 ) + 80058fc: f7fb fa1a bl 8000d34 + assert_param(IS_SDIO_RESPONSE(Command->Response)); + 8005900: 683b ldr r3, [r7, #0] + 8005902: 689b ldr r3, [r3, #8] + 8005904: 2b00 cmp r3, #0 + 8005906: d00c beq.n 8005922 + 8005908: 683b ldr r3, [r7, #0] + 800590a: 689b ldr r3, [r3, #8] + 800590c: 2b40 cmp r3, #64 @ 0x40 + 800590e: d008 beq.n 8005922 + 8005910: 683b ldr r3, [r7, #0] + 8005912: 689b ldr r3, [r3, #8] + 8005914: 2bc0 cmp r3, #192 @ 0xc0 + 8005916: d004 beq.n 8005922 + 8005918: f240 1161 movw r1, #353 @ 0x161 + 800591c: 4822 ldr r0, [pc, #136] @ (80059a8 ) + 800591e: f7fb fa09 bl 8000d34 + assert_param(IS_SDIO_WAIT(Command->WaitForInterrupt)); + 8005922: 683b ldr r3, [r7, #0] + 8005924: 68db ldr r3, [r3, #12] + 8005926: 2b00 cmp r3, #0 + 8005928: d00e beq.n 8005948 + 800592a: 683b ldr r3, [r7, #0] + 800592c: 68db ldr r3, [r3, #12] + 800592e: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 8005932: d009 beq.n 8005948 + 8005934: 683b ldr r3, [r7, #0] + 8005936: 68db ldr r3, [r3, #12] + 8005938: f5b3 7f00 cmp.w r3, #512 @ 0x200 + 800593c: d004 beq.n 8005948 + 800593e: f44f 71b1 mov.w r1, #354 @ 0x162 + 8005942: 4819 ldr r0, [pc, #100] @ (80059a8 ) + 8005944: f7fb f9f6 bl 8000d34 + assert_param(IS_SDIO_CPSM(Command->CPSM)); + 8005948: 683b ldr r3, [r7, #0] + 800594a: 691b ldr r3, [r3, #16] + 800594c: 2b00 cmp r3, #0 + 800594e: d009 beq.n 8005964 + 8005950: 683b ldr r3, [r7, #0] + 8005952: 691b ldr r3, [r3, #16] + 8005954: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 8005958: d004 beq.n 8005964 + 800595a: f240 1163 movw r1, #355 @ 0x163 + 800595e: 4812 ldr r0, [pc, #72] @ (80059a8 ) + 8005960: f7fb f9e8 bl 8000d34 + + /* Set the SDMMC Argument value */ + SDIOx->ARG = Command->Argument; + 8005964: 683b ldr r3, [r7, #0] + 8005966: 681a ldr r2, [r3, #0] + 8005968: 687b ldr r3, [r7, #4] + 800596a: 609a str r2, [r3, #8] + + /* Set SDMMC command parameters */ + tmpreg |= (uint32_t)(Command->CmdIndex |\ + 800596c: 683b ldr r3, [r7, #0] + 800596e: 685a ldr r2, [r3, #4] + Command->Response |\ + 8005970: 683b ldr r3, [r7, #0] + 8005972: 689b ldr r3, [r3, #8] + tmpreg |= (uint32_t)(Command->CmdIndex |\ + 8005974: 431a orrs r2, r3 + Command->WaitForInterrupt |\ + 8005976: 683b ldr r3, [r7, #0] + 8005978: 68db ldr r3, [r3, #12] + Command->Response |\ + 800597a: 431a orrs r2, r3 + Command->CPSM); + 800597c: 683b ldr r3, [r7, #0] + 800597e: 691b ldr r3, [r3, #16] + Command->WaitForInterrupt |\ + 8005980: 4313 orrs r3, r2 + tmpreg |= (uint32_t)(Command->CmdIndex |\ + 8005982: 68fa ldr r2, [r7, #12] + 8005984: 4313 orrs r3, r2 + 8005986: 60fb str r3, [r7, #12] + + /* Write to SDMMC CMD register */ + MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, tmpreg); + 8005988: 687b ldr r3, [r7, #4] + 800598a: 68db ldr r3, [r3, #12] + 800598c: f423 637f bic.w r3, r3, #4080 @ 0xff0 + 8005990: f023 030f bic.w r3, r3, #15 + 8005994: 68fa ldr r2, [r7, #12] + 8005996: 431a orrs r2, r3 + 8005998: 687b ldr r3, [r7, #4] + 800599a: 60da str r2, [r3, #12] + + return HAL_OK; + 800599c: 2300 movs r3, #0 +} + 800599e: 4618 mov r0, r3 + 80059a0: 3710 adds r7, #16 + 80059a2: 46bd mov sp, r7 + 80059a4: bd80 pop {r7, pc} + 80059a6: bf00 nop + 80059a8: 0800a24c .word 0x0800a24c + +080059ac : + * @brief Return the command index of last command for which response received + * @param SDIOx: Pointer to SDMMC register base + * @retval Command index of the last command response received + */ +uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx) +{ + 80059ac: b480 push {r7} + 80059ae: b083 sub sp, #12 + 80059b0: af00 add r7, sp, #0 + 80059b2: 6078 str r0, [r7, #4] + return (uint8_t)(SDIOx->RESPCMD); + 80059b4: 687b ldr r3, [r7, #4] + 80059b6: 691b ldr r3, [r3, #16] + 80059b8: b2db uxtb r3, r3 +} + 80059ba: 4618 mov r0, r3 + 80059bc: 370c adds r7, #12 + 80059be: 46bd mov sp, r7 + 80059c0: f85d 7b04 ldr.w r7, [sp], #4 + 80059c4: 4770 bx lr + ... + +080059c8 : + * @arg SDIO_RESP3: Response Register 3 + * @arg SDIO_RESP4: Response Register 4 + * @retval The Corresponding response register value + */ +uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response) +{ + 80059c8: b580 push {r7, lr} + 80059ca: b084 sub sp, #16 + 80059cc: af00 add r7, sp, #0 + 80059ce: 6078 str r0, [r7, #4] + 80059d0: 6039 str r1, [r7, #0] + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_SDIO_RESP(Response)); + 80059d2: 683b ldr r3, [r7, #0] + 80059d4: 2b00 cmp r3, #0 + 80059d6: d00d beq.n 80059f4 + 80059d8: 683b ldr r3, [r7, #0] + 80059da: 2b04 cmp r3, #4 + 80059dc: d00a beq.n 80059f4 + 80059de: 683b ldr r3, [r7, #0] + 80059e0: 2b08 cmp r3, #8 + 80059e2: d007 beq.n 80059f4 + 80059e4: 683b ldr r3, [r7, #0] + 80059e6: 2b0c cmp r3, #12 + 80059e8: d004 beq.n 80059f4 + 80059ea: f240 118f movw r1, #399 @ 0x18f + 80059ee: 4807 ldr r0, [pc, #28] @ (8005a0c ) + 80059f0: f7fb f9a0 bl 8000d34 + + /* Get the response */ + tmp = (uint32_t)(&(SDIOx->RESP1)) + Response; + 80059f4: 687b ldr r3, [r7, #4] + 80059f6: 3314 adds r3, #20 + 80059f8: 461a mov r2, r3 + 80059fa: 683b ldr r3, [r7, #0] + 80059fc: 4413 add r3, r2 + 80059fe: 60fb str r3, [r7, #12] + + return (*(__IO uint32_t *) tmp); + 8005a00: 68fb ldr r3, [r7, #12] + 8005a02: 681b ldr r3, [r3, #0] +} + 8005a04: 4618 mov r0, r3 + 8005a06: 3710 adds r7, #16 + 8005a08: 46bd mov sp, r7 + 8005a0a: bd80 pop {r7, pc} + 8005a0c: 0800a24c .word 0x0800a24c + +08005a10 : + * @param Data : pointer to a SDIO_DataInitTypeDef structure + * that contains the configuration information for the SDMMC data. + * @retval HAL status + */ +HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data) +{ + 8005a10: b580 push {r7, lr} + 8005a12: b084 sub sp, #16 + 8005a14: af00 add r7, sp, #0 + 8005a16: 6078 str r0, [r7, #4] + 8005a18: 6039 str r1, [r7, #0] + uint32_t tmpreg = 0; + 8005a1a: 2300 movs r3, #0 + 8005a1c: 60fb str r3, [r7, #12] + + /* Check the parameters */ + assert_param(IS_SDIO_DATA_LENGTH(Data->DataLength)); + 8005a1e: 683b ldr r3, [r7, #0] + 8005a20: 685b ldr r3, [r3, #4] + 8005a22: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 + 8005a26: d304 bcc.n 8005a32 + 8005a28: f44f 71d2 mov.w r1, #420 @ 0x1a4 + 8005a2c: 4846 ldr r0, [pc, #280] @ (8005b48 ) + 8005a2e: f7fb f981 bl 8000d34 + assert_param(IS_SDIO_BLOCK_SIZE(Data->DataBlockSize)); + 8005a32: 683b ldr r3, [r7, #0] + 8005a34: 689b ldr r3, [r3, #8] + 8005a36: 2b00 cmp r3, #0 + 8005a38: d03c beq.n 8005ab4 + 8005a3a: 683b ldr r3, [r7, #0] + 8005a3c: 689b ldr r3, [r3, #8] + 8005a3e: 2b10 cmp r3, #16 + 8005a40: d038 beq.n 8005ab4 + 8005a42: 683b ldr r3, [r7, #0] + 8005a44: 689b ldr r3, [r3, #8] + 8005a46: 2b20 cmp r3, #32 + 8005a48: d034 beq.n 8005ab4 + 8005a4a: 683b ldr r3, [r7, #0] + 8005a4c: 689b ldr r3, [r3, #8] + 8005a4e: 2b30 cmp r3, #48 @ 0x30 + 8005a50: d030 beq.n 8005ab4 + 8005a52: 683b ldr r3, [r7, #0] + 8005a54: 689b ldr r3, [r3, #8] + 8005a56: 2b40 cmp r3, #64 @ 0x40 + 8005a58: d02c beq.n 8005ab4 + 8005a5a: 683b ldr r3, [r7, #0] + 8005a5c: 689b ldr r3, [r3, #8] + 8005a5e: 2b50 cmp r3, #80 @ 0x50 + 8005a60: d028 beq.n 8005ab4 + 8005a62: 683b ldr r3, [r7, #0] + 8005a64: 689b ldr r3, [r3, #8] + 8005a66: 2b60 cmp r3, #96 @ 0x60 + 8005a68: d024 beq.n 8005ab4 + 8005a6a: 683b ldr r3, [r7, #0] + 8005a6c: 689b ldr r3, [r3, #8] + 8005a6e: 2b70 cmp r3, #112 @ 0x70 + 8005a70: d020 beq.n 8005ab4 + 8005a72: 683b ldr r3, [r7, #0] + 8005a74: 689b ldr r3, [r3, #8] + 8005a76: 2b80 cmp r3, #128 @ 0x80 + 8005a78: d01c beq.n 8005ab4 + 8005a7a: 683b ldr r3, [r7, #0] + 8005a7c: 689b ldr r3, [r3, #8] + 8005a7e: 2b90 cmp r3, #144 @ 0x90 + 8005a80: d018 beq.n 8005ab4 + 8005a82: 683b ldr r3, [r7, #0] + 8005a84: 689b ldr r3, [r3, #8] + 8005a86: 2ba0 cmp r3, #160 @ 0xa0 + 8005a88: d014 beq.n 8005ab4 + 8005a8a: 683b ldr r3, [r7, #0] + 8005a8c: 689b ldr r3, [r3, #8] + 8005a8e: 2bb0 cmp r3, #176 @ 0xb0 + 8005a90: d010 beq.n 8005ab4 + 8005a92: 683b ldr r3, [r7, #0] + 8005a94: 689b ldr r3, [r3, #8] + 8005a96: 2bc0 cmp r3, #192 @ 0xc0 + 8005a98: d00c beq.n 8005ab4 + 8005a9a: 683b ldr r3, [r7, #0] + 8005a9c: 689b ldr r3, [r3, #8] + 8005a9e: 2bd0 cmp r3, #208 @ 0xd0 + 8005aa0: d008 beq.n 8005ab4 + 8005aa2: 683b ldr r3, [r7, #0] + 8005aa4: 689b ldr r3, [r3, #8] + 8005aa6: 2be0 cmp r3, #224 @ 0xe0 + 8005aa8: d004 beq.n 8005ab4 + 8005aaa: f240 11a5 movw r1, #421 @ 0x1a5 + 8005aae: 4826 ldr r0, [pc, #152] @ (8005b48 ) + 8005ab0: f7fb f940 bl 8000d34 + assert_param(IS_SDIO_TRANSFER_DIR(Data->TransferDir)); + 8005ab4: 683b ldr r3, [r7, #0] + 8005ab6: 68db ldr r3, [r3, #12] + 8005ab8: 2b00 cmp r3, #0 + 8005aba: d008 beq.n 8005ace + 8005abc: 683b ldr r3, [r7, #0] + 8005abe: 68db ldr r3, [r3, #12] + 8005ac0: 2b02 cmp r3, #2 + 8005ac2: d004 beq.n 8005ace + 8005ac4: f44f 71d3 mov.w r1, #422 @ 0x1a6 + 8005ac8: 481f ldr r0, [pc, #124] @ (8005b48 ) + 8005aca: f7fb f933 bl 8000d34 + assert_param(IS_SDIO_TRANSFER_MODE(Data->TransferMode)); + 8005ace: 683b ldr r3, [r7, #0] + 8005ad0: 691b ldr r3, [r3, #16] + 8005ad2: 2b00 cmp r3, #0 + 8005ad4: d008 beq.n 8005ae8 + 8005ad6: 683b ldr r3, [r7, #0] + 8005ad8: 691b ldr r3, [r3, #16] + 8005ada: 2b04 cmp r3, #4 + 8005adc: d004 beq.n 8005ae8 + 8005ade: f240 11a7 movw r1, #423 @ 0x1a7 + 8005ae2: 4819 ldr r0, [pc, #100] @ (8005b48 ) + 8005ae4: f7fb f926 bl 8000d34 + assert_param(IS_SDIO_DPSM(Data->DPSM)); + 8005ae8: 683b ldr r3, [r7, #0] + 8005aea: 695b ldr r3, [r3, #20] + 8005aec: 2b00 cmp r3, #0 + 8005aee: d008 beq.n 8005b02 + 8005af0: 683b ldr r3, [r7, #0] + 8005af2: 695b ldr r3, [r3, #20] + 8005af4: 2b01 cmp r3, #1 + 8005af6: d004 beq.n 8005b02 + 8005af8: f44f 71d4 mov.w r1, #424 @ 0x1a8 + 8005afc: 4812 ldr r0, [pc, #72] @ (8005b48 ) + 8005afe: f7fb f919 bl 8000d34 + + /* Set the SDMMC Data TimeOut value */ + SDIOx->DTIMER = Data->DataTimeOut; + 8005b02: 683b ldr r3, [r7, #0] + 8005b04: 681a ldr r2, [r3, #0] + 8005b06: 687b ldr r3, [r7, #4] + 8005b08: 625a str r2, [r3, #36] @ 0x24 + + /* Set the SDMMC DataLength value */ + SDIOx->DLEN = Data->DataLength; + 8005b0a: 683b ldr r3, [r7, #0] + 8005b0c: 685a ldr r2, [r3, #4] + 8005b0e: 687b ldr r3, [r7, #4] + 8005b10: 629a str r2, [r3, #40] @ 0x28 + + /* Set the SDMMC data configuration parameters */ + tmpreg |= (uint32_t)(Data->DataBlockSize |\ + 8005b12: 683b ldr r3, [r7, #0] + 8005b14: 689a ldr r2, [r3, #8] + Data->TransferDir |\ + 8005b16: 683b ldr r3, [r7, #0] + 8005b18: 68db ldr r3, [r3, #12] + tmpreg |= (uint32_t)(Data->DataBlockSize |\ + 8005b1a: 431a orrs r2, r3 + Data->TransferMode |\ + 8005b1c: 683b ldr r3, [r7, #0] + 8005b1e: 691b ldr r3, [r3, #16] + Data->TransferDir |\ + 8005b20: 431a orrs r2, r3 + Data->DPSM); + 8005b22: 683b ldr r3, [r7, #0] + 8005b24: 695b ldr r3, [r3, #20] + Data->TransferMode |\ + 8005b26: 4313 orrs r3, r2 + tmpreg |= (uint32_t)(Data->DataBlockSize |\ + 8005b28: 68fa ldr r2, [r7, #12] + 8005b2a: 4313 orrs r3, r2 + 8005b2c: 60fb str r3, [r7, #12] + + /* Write to SDMMC DCTRL */ + MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, tmpreg); + 8005b2e: 687b ldr r3, [r7, #4] + 8005b30: 6adb ldr r3, [r3, #44] @ 0x2c + 8005b32: f023 02f7 bic.w r2, r3, #247 @ 0xf7 + 8005b36: 68fb ldr r3, [r7, #12] + 8005b38: 431a orrs r2, r3 + 8005b3a: 687b ldr r3, [r7, #4] + 8005b3c: 62da str r2, [r3, #44] @ 0x2c + + return HAL_OK; + 8005b3e: 2300 movs r3, #0 + +} + 8005b40: 4618 mov r0, r3 + 8005b42: 3710 adds r7, #16 + 8005b44: 46bd mov sp, r7 + 8005b46: bd80 pop {r7, pc} + 8005b48: 0800a24c .word 0x0800a24c + +08005b4c : + * @brief Send the Data Block Length command and check the response + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize) +{ + 8005b4c: b580 push {r7, lr} + 8005b4e: b088 sub sp, #32 + 8005b50: af00 add r7, sp, #0 + 8005b52: 6078 str r0, [r7, #4] + 8005b54: 6039 str r1, [r7, #0] + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)BlockSize; + 8005b56: 683b ldr r3, [r7, #0] + 8005b58: 60bb str r3, [r7, #8] + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCKLEN; + 8005b5a: 2310 movs r3, #16 + 8005b5c: 60fb str r3, [r7, #12] + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + 8005b5e: 2340 movs r3, #64 @ 0x40 + 8005b60: 613b str r3, [r7, #16] + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + 8005b62: 2300 movs r3, #0 + 8005b64: 617b str r3, [r7, #20] + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + 8005b66: f44f 6380 mov.w r3, #1024 @ 0x400 + 8005b6a: 61bb str r3, [r7, #24] + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + 8005b6c: f107 0308 add.w r3, r7, #8 + 8005b70: 4619 mov r1, r3 + 8005b72: 6878 ldr r0, [r7, #4] + 8005b74: f7ff feb4 bl 80058e0 + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SET_BLOCKLEN, SDIO_CMDTIMEOUT); + 8005b78: f241 3288 movw r2, #5000 @ 0x1388 + 8005b7c: 2110 movs r1, #16 + 8005b7e: 6878 ldr r0, [r7, #4] + 8005b80: f000 f990 bl 8005ea4 + 8005b84: 61f8 str r0, [r7, #28] + + return errorstate; + 8005b86: 69fb ldr r3, [r7, #28] +} + 8005b88: 4618 mov r0, r3 + 8005b8a: 3720 adds r7, #32 + 8005b8c: 46bd mov sp, r7 + 8005b8e: bd80 pop {r7, pc} + +08005b90 : + * @brief Send the Stop Transfer command and check the response. + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx) +{ + 8005b90: b580 push {r7, lr} + 8005b92: b088 sub sp, #32 + 8005b94: af00 add r7, sp, #0 + 8005b96: 6078 str r0, [r7, #4] + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD12 STOP_TRANSMISSION */ + sdmmc_cmdinit.Argument = 0U; + 8005b98: 2300 movs r3, #0 + 8005b9a: 60bb str r3, [r7, #8] + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_STOP_TRANSMISSION; + 8005b9c: 230c movs r3, #12 + 8005b9e: 60fb str r3, [r7, #12] + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + 8005ba0: 2340 movs r3, #64 @ 0x40 + 8005ba2: 613b str r3, [r7, #16] + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + 8005ba4: 2300 movs r3, #0 + 8005ba6: 617b str r3, [r7, #20] + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + 8005ba8: f44f 6380 mov.w r3, #1024 @ 0x400 + 8005bac: 61bb str r3, [r7, #24] + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + 8005bae: f107 0308 add.w r3, r7, #8 + 8005bb2: 4619 mov r1, r3 + 8005bb4: 6878 ldr r0, [r7, #4] + 8005bb6: f7ff fe93 bl 80058e0 + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_STOP_TRANSMISSION, SDIO_STOPTRANSFERTIMEOUT); + 8005bba: 4a05 ldr r2, [pc, #20] @ (8005bd0 ) + 8005bbc: 210c movs r1, #12 + 8005bbe: 6878 ldr r0, [r7, #4] + 8005bc0: f000 f970 bl 8005ea4 + 8005bc4: 61f8 str r0, [r7, #28] + + return errorstate; + 8005bc6: 69fb ldr r3, [r7, #28] +} + 8005bc8: 4618 mov r0, r3 + 8005bca: 3720 adds r7, #32 + 8005bcc: 46bd mov sp, r7 + 8005bce: bd80 pop {r7, pc} + 8005bd0: 05f5e100 .word 0x05f5e100 + +08005bd4 : + * @param SDIOx: Pointer to SDIO register base + * @param addr: Address of the card to be selected + * @retval HAL status + */ +uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr) +{ + 8005bd4: b580 push {r7, lr} + 8005bd6: b08a sub sp, #40 @ 0x28 + 8005bd8: af00 add r7, sp, #0 + 8005bda: 60f8 str r0, [r7, #12] + 8005bdc: e9c7 2300 strd r2, r3, [r7] + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD7 SDMMC_SEL_DESEL_CARD */ + sdmmc_cmdinit.Argument = (uint32_t)Addr; + 8005be0: 683b ldr r3, [r7, #0] + 8005be2: 613b str r3, [r7, #16] + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEL_DESEL_CARD; + 8005be4: 2307 movs r3, #7 + 8005be6: 617b str r3, [r7, #20] + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + 8005be8: 2340 movs r3, #64 @ 0x40 + 8005bea: 61bb str r3, [r7, #24] + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + 8005bec: 2300 movs r3, #0 + 8005bee: 61fb str r3, [r7, #28] + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + 8005bf0: f44f 6380 mov.w r3, #1024 @ 0x400 + 8005bf4: 623b str r3, [r7, #32] + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + 8005bf6: f107 0310 add.w r3, r7, #16 + 8005bfa: 4619 mov r1, r3 + 8005bfc: 68f8 ldr r0, [r7, #12] + 8005bfe: f7ff fe6f bl 80058e0 + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEL_DESEL_CARD, SDIO_CMDTIMEOUT); + 8005c02: f241 3288 movw r2, #5000 @ 0x1388 + 8005c06: 2107 movs r1, #7 + 8005c08: 68f8 ldr r0, [r7, #12] + 8005c0a: f000 f94b bl 8005ea4 + 8005c0e: 6278 str r0, [r7, #36] @ 0x24 + + return errorstate; + 8005c10: 6a7b ldr r3, [r7, #36] @ 0x24 +} + 8005c12: 4618 mov r0, r3 + 8005c14: 3728 adds r7, #40 @ 0x28 + 8005c16: 46bd mov sp, r7 + 8005c18: bd80 pop {r7, pc} + +08005c1a : + * @brief Send the Go Idle State command and check the response. + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx) +{ + 8005c1a: b580 push {r7, lr} + 8005c1c: b088 sub sp, #32 + 8005c1e: af00 add r7, sp, #0 + 8005c20: 6078 str r0, [r7, #4] + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = 0U; + 8005c22: 2300 movs r3, #0 + 8005c24: 60bb str r3, [r7, #8] + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE; + 8005c26: 2300 movs r3, #0 + 8005c28: 60fb str r3, [r7, #12] + sdmmc_cmdinit.Response = SDIO_RESPONSE_NO; + 8005c2a: 2300 movs r3, #0 + 8005c2c: 613b str r3, [r7, #16] + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + 8005c2e: 2300 movs r3, #0 + 8005c30: 617b str r3, [r7, #20] + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + 8005c32: f44f 6380 mov.w r3, #1024 @ 0x400 + 8005c36: 61bb str r3, [r7, #24] + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + 8005c38: f107 0308 add.w r3, r7, #8 + 8005c3c: 4619 mov r1, r3 + 8005c3e: 6878 ldr r0, [r7, #4] + 8005c40: f7ff fe4e bl 80058e0 + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdError(SDIOx); + 8005c44: 6878 ldr r0, [r7, #4] + 8005c46: f000 fb65 bl 8006314 + 8005c4a: 61f8 str r0, [r7, #28] + + return errorstate; + 8005c4c: 69fb ldr r3, [r7, #28] +} + 8005c4e: 4618 mov r0, r3 + 8005c50: 3720 adds r7, #32 + 8005c52: 46bd mov sp, r7 + 8005c54: bd80 pop {r7, pc} + +08005c56 : + * @brief Send the Operating Condition command and check the response. + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx) +{ + 8005c56: b580 push {r7, lr} + 8005c58: b088 sub sp, #32 + 8005c5a: af00 add r7, sp, #0 + 8005c5c: 6078 str r0, [r7, #4] + /* Send CMD8 to verify SD card interface operating condition */ + /* Argument: - [31:12]: Reserved (shall be set to '0') + - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) + - [7:0]: Check Pattern (recommended 0xAA) */ + /* CMD Response: R7 */ + sdmmc_cmdinit.Argument = SDMMC_CHECK_PATTERN; + 8005c5e: f44f 73d5 mov.w r3, #426 @ 0x1aa + 8005c62: 60bb str r3, [r7, #8] + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; + 8005c64: 2308 movs r3, #8 + 8005c66: 60fb str r3, [r7, #12] + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + 8005c68: 2340 movs r3, #64 @ 0x40 + 8005c6a: 613b str r3, [r7, #16] + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + 8005c6c: 2300 movs r3, #0 + 8005c6e: 617b str r3, [r7, #20] + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + 8005c70: f44f 6380 mov.w r3, #1024 @ 0x400 + 8005c74: 61bb str r3, [r7, #24] + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + 8005c76: f107 0308 add.w r3, r7, #8 + 8005c7a: 4619 mov r1, r3 + 8005c7c: 6878 ldr r0, [r7, #4] + 8005c7e: f7ff fe2f bl 80058e0 + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp7(SDIOx); + 8005c82: 6878 ldr r0, [r7, #4] + 8005c84: f000 faf8 bl 8006278 + 8005c88: 61f8 str r0, [r7, #28] + + return errorstate; + 8005c8a: 69fb ldr r3, [r7, #28] +} + 8005c8c: 4618 mov r0, r3 + 8005c8e: 3720 adds r7, #32 + 8005c90: 46bd mov sp, r7 + 8005c92: bd80 pop {r7, pc} + +08005c94 : + * @param SDIOx: Pointer to SDIO register base + * @param Argument: Command Argument + * @retval HAL status + */ +uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument) +{ + 8005c94: b580 push {r7, lr} + 8005c96: b088 sub sp, #32 + 8005c98: af00 add r7, sp, #0 + 8005c9a: 6078 str r0, [r7, #4] + 8005c9c: 6039 str r1, [r7, #0] + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = (uint32_t)Argument; + 8005c9e: 683b ldr r3, [r7, #0] + 8005ca0: 60bb str r3, [r7, #8] + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_CMD; + 8005ca2: 2337 movs r3, #55 @ 0x37 + 8005ca4: 60fb str r3, [r7, #12] + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + 8005ca6: 2340 movs r3, #64 @ 0x40 + 8005ca8: 613b str r3, [r7, #16] + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + 8005caa: 2300 movs r3, #0 + 8005cac: 617b str r3, [r7, #20] + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + 8005cae: f44f 6380 mov.w r3, #1024 @ 0x400 + 8005cb2: 61bb str r3, [r7, #24] + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + 8005cb4: f107 0308 add.w r3, r7, #8 + 8005cb8: 4619 mov r1, r3 + 8005cba: 6878 ldr r0, [r7, #4] + 8005cbc: f7ff fe10 bl 80058e0 + + /* Check for error conditions */ + /* If there is a HAL_ERROR, it is a MMC card, else + it is a SD card: SD card 2.0 (voltage range mismatch) + or SD card 1.x */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_CMD, SDIO_CMDTIMEOUT); + 8005cc0: f241 3288 movw r2, #5000 @ 0x1388 + 8005cc4: 2137 movs r1, #55 @ 0x37 + 8005cc6: 6878 ldr r0, [r7, #4] + 8005cc8: f000 f8ec bl 8005ea4 + 8005ccc: 61f8 str r0, [r7, #28] + + return errorstate; + 8005cce: 69fb ldr r3, [r7, #28] +} + 8005cd0: 4618 mov r0, r3 + 8005cd2: 3720 adds r7, #32 + 8005cd4: 46bd mov sp, r7 + 8005cd6: bd80 pop {r7, pc} + +08005cd8 : + * @param SDIOx: Pointer to SDIO register base + * @param Argument: Command Argument + * @retval HAL status + */ +uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t Argument) +{ + 8005cd8: b580 push {r7, lr} + 8005cda: b088 sub sp, #32 + 8005cdc: af00 add r7, sp, #0 + 8005cde: 6078 str r0, [r7, #4] + 8005ce0: 6039 str r1, [r7, #0] + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = SDMMC_VOLTAGE_WINDOW_SD | Argument; + 8005ce2: 683b ldr r3, [r7, #0] + 8005ce4: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 + 8005ce8: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 + 8005cec: 60bb str r3, [r7, #8] + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND; + 8005cee: 2329 movs r3, #41 @ 0x29 + 8005cf0: 60fb str r3, [r7, #12] + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + 8005cf2: 2340 movs r3, #64 @ 0x40 + 8005cf4: 613b str r3, [r7, #16] + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + 8005cf6: 2300 movs r3, #0 + 8005cf8: 617b str r3, [r7, #20] + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + 8005cfa: f44f 6380 mov.w r3, #1024 @ 0x400 + 8005cfe: 61bb str r3, [r7, #24] + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + 8005d00: f107 0308 add.w r3, r7, #8 + 8005d04: 4619 mov r1, r3 + 8005d06: 6878 ldr r0, [r7, #4] + 8005d08: f7ff fdea bl 80058e0 + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp3(SDIOx); + 8005d0c: 6878 ldr r0, [r7, #4] + 8005d0e: f000 f9ff bl 8006110 + 8005d12: 61f8 str r0, [r7, #28] + + return errorstate; + 8005d14: 69fb ldr r3, [r7, #28] +} + 8005d16: 4618 mov r0, r3 + 8005d18: 3720 adds r7, #32 + 8005d1a: 46bd mov sp, r7 + 8005d1c: bd80 pop {r7, pc} + +08005d1e : + * @param SDIOx: Pointer to SDIO register base + * @param BusWidth: BusWidth + * @retval HAL status + */ +uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth) +{ + 8005d1e: b580 push {r7, lr} + 8005d20: b088 sub sp, #32 + 8005d22: af00 add r7, sp, #0 + 8005d24: 6078 str r0, [r7, #4] + 8005d26: 6039 str r1, [r7, #0] + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = (uint32_t)BusWidth; + 8005d28: 683b ldr r3, [r7, #0] + 8005d2a: 60bb str r3, [r7, #8] + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_SD_SET_BUSWIDTH; + 8005d2c: 2306 movs r3, #6 + 8005d2e: 60fb str r3, [r7, #12] + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + 8005d30: 2340 movs r3, #64 @ 0x40 + 8005d32: 613b str r3, [r7, #16] + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + 8005d34: 2300 movs r3, #0 + 8005d36: 617b str r3, [r7, #20] + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + 8005d38: f44f 6380 mov.w r3, #1024 @ 0x400 + 8005d3c: 61bb str r3, [r7, #24] + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + 8005d3e: f107 0308 add.w r3, r7, #8 + 8005d42: 4619 mov r1, r3 + 8005d44: 6878 ldr r0, [r7, #4] + 8005d46: f7ff fdcb bl 80058e0 + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDIO_CMDTIMEOUT); + 8005d4a: f241 3288 movw r2, #5000 @ 0x1388 + 8005d4e: 2106 movs r1, #6 + 8005d50: 6878 ldr r0, [r7, #4] + 8005d52: f000 f8a7 bl 8005ea4 + 8005d56: 61f8 str r0, [r7, #28] + + return errorstate; + 8005d58: 69fb ldr r3, [r7, #28] +} + 8005d5a: 4618 mov r0, r3 + 8005d5c: 3720 adds r7, #32 + 8005d5e: 46bd mov sp, r7 + 8005d60: bd80 pop {r7, pc} + +08005d62 : + * @brief Send the Send SCR command and check the response. + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx) +{ + 8005d62: b580 push {r7, lr} + 8005d64: b088 sub sp, #32 + 8005d66: af00 add r7, sp, #0 + 8005d68: 6078 str r0, [r7, #4] + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD51 SD_APP_SEND_SCR */ + sdmmc_cmdinit.Argument = 0U; + 8005d6a: 2300 movs r3, #0 + 8005d6c: 60bb str r3, [r7, #8] + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_SEND_SCR; + 8005d6e: 2333 movs r3, #51 @ 0x33 + 8005d70: 60fb str r3, [r7, #12] + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + 8005d72: 2340 movs r3, #64 @ 0x40 + 8005d74: 613b str r3, [r7, #16] + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + 8005d76: 2300 movs r3, #0 + 8005d78: 617b str r3, [r7, #20] + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + 8005d7a: f44f 6380 mov.w r3, #1024 @ 0x400 + 8005d7e: 61bb str r3, [r7, #24] + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + 8005d80: f107 0308 add.w r3, r7, #8 + 8005d84: 4619 mov r1, r3 + 8005d86: 6878 ldr r0, [r7, #4] + 8005d88: f7ff fdaa bl 80058e0 + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_SEND_SCR, SDIO_CMDTIMEOUT); + 8005d8c: f241 3288 movw r2, #5000 @ 0x1388 + 8005d90: 2133 movs r1, #51 @ 0x33 + 8005d92: 6878 ldr r0, [r7, #4] + 8005d94: f000 f886 bl 8005ea4 + 8005d98: 61f8 str r0, [r7, #28] + + return errorstate; + 8005d9a: 69fb ldr r3, [r7, #28] +} + 8005d9c: 4618 mov r0, r3 + 8005d9e: 3720 adds r7, #32 + 8005da0: 46bd mov sp, r7 + 8005da2: bd80 pop {r7, pc} + +08005da4 : + * @brief Send the Send CID command and check the response. + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx) +{ + 8005da4: b580 push {r7, lr} + 8005da6: b088 sub sp, #32 + 8005da8: af00 add r7, sp, #0 + 8005daa: 6078 str r0, [r7, #4] + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD2 ALL_SEND_CID */ + sdmmc_cmdinit.Argument = 0U; + 8005dac: 2300 movs r3, #0 + 8005dae: 60bb str r3, [r7, #8] + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ALL_SEND_CID; + 8005db0: 2302 movs r3, #2 + 8005db2: 60fb str r3, [r7, #12] + sdmmc_cmdinit.Response = SDIO_RESPONSE_LONG; + 8005db4: 23c0 movs r3, #192 @ 0xc0 + 8005db6: 613b str r3, [r7, #16] + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + 8005db8: 2300 movs r3, #0 + 8005dba: 617b str r3, [r7, #20] + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + 8005dbc: f44f 6380 mov.w r3, #1024 @ 0x400 + 8005dc0: 61bb str r3, [r7, #24] + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + 8005dc2: f107 0308 add.w r3, r7, #8 + 8005dc6: 4619 mov r1, r3 + 8005dc8: 6878 ldr r0, [r7, #4] + 8005dca: f7ff fd89 bl 80058e0 + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp2(SDIOx); + 8005dce: 6878 ldr r0, [r7, #4] + 8005dd0: f000 f956 bl 8006080 + 8005dd4: 61f8 str r0, [r7, #28] + + return errorstate; + 8005dd6: 69fb ldr r3, [r7, #28] +} + 8005dd8: 4618 mov r0, r3 + 8005dda: 3720 adds r7, #32 + 8005ddc: 46bd mov sp, r7 + 8005dde: bd80 pop {r7, pc} + +08005de0 : + * @param SDIOx: Pointer to SDIO register base + * @param Argument: Command Argument + * @retval HAL status + */ +uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument) +{ + 8005de0: b580 push {r7, lr} + 8005de2: b088 sub sp, #32 + 8005de4: af00 add r7, sp, #0 + 8005de6: 6078 str r0, [r7, #4] + 8005de8: 6039 str r1, [r7, #0] + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD9 SEND_CSD */ + sdmmc_cmdinit.Argument = Argument; + 8005dea: 683b ldr r3, [r7, #0] + 8005dec: 60bb str r3, [r7, #8] + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_CSD; + 8005dee: 2309 movs r3, #9 + 8005df0: 60fb str r3, [r7, #12] + sdmmc_cmdinit.Response = SDIO_RESPONSE_LONG; + 8005df2: 23c0 movs r3, #192 @ 0xc0 + 8005df4: 613b str r3, [r7, #16] + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + 8005df6: 2300 movs r3, #0 + 8005df8: 617b str r3, [r7, #20] + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + 8005dfa: f44f 6380 mov.w r3, #1024 @ 0x400 + 8005dfe: 61bb str r3, [r7, #24] + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + 8005e00: f107 0308 add.w r3, r7, #8 + 8005e04: 4619 mov r1, r3 + 8005e06: 6878 ldr r0, [r7, #4] + 8005e08: f7ff fd6a bl 80058e0 + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp2(SDIOx); + 8005e0c: 6878 ldr r0, [r7, #4] + 8005e0e: f000 f937 bl 8006080 + 8005e12: 61f8 str r0, [r7, #28] + + return errorstate; + 8005e14: 69fb ldr r3, [r7, #28] +} + 8005e16: 4618 mov r0, r3 + 8005e18: 3720 adds r7, #32 + 8005e1a: 46bd mov sp, r7 + 8005e1c: bd80 pop {r7, pc} + +08005e1e : + * @param SDIOx: Pointer to SDIO register base + * @param pRCA: Card RCA + * @retval HAL status + */ +uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA) +{ + 8005e1e: b580 push {r7, lr} + 8005e20: b088 sub sp, #32 + 8005e22: af00 add r7, sp, #0 + 8005e24: 6078 str r0, [r7, #4] + 8005e26: 6039 str r1, [r7, #0] + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD3 SD_CMD_SET_REL_ADDR */ + sdmmc_cmdinit.Argument = 0U; + 8005e28: 2300 movs r3, #0 + 8005e2a: 60bb str r3, [r7, #8] + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; + 8005e2c: 2303 movs r3, #3 + 8005e2e: 60fb str r3, [r7, #12] + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + 8005e30: 2340 movs r3, #64 @ 0x40 + 8005e32: 613b str r3, [r7, #16] + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + 8005e34: 2300 movs r3, #0 + 8005e36: 617b str r3, [r7, #20] + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + 8005e38: f44f 6380 mov.w r3, #1024 @ 0x400 + 8005e3c: 61bb str r3, [r7, #24] + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + 8005e3e: f107 0308 add.w r3, r7, #8 + 8005e42: 4619 mov r1, r3 + 8005e44: 6878 ldr r0, [r7, #4] + 8005e46: f7ff fd4b bl 80058e0 + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp6(SDIOx, SDMMC_CMD_SET_REL_ADDR, pRCA); + 8005e4a: 683a ldr r2, [r7, #0] + 8005e4c: 2103 movs r1, #3 + 8005e4e: 6878 ldr r0, [r7, #4] + 8005e50: f000 f99c bl 800618c + 8005e54: 61f8 str r0, [r7, #28] + + return errorstate; + 8005e56: 69fb ldr r3, [r7, #28] +} + 8005e58: 4618 mov r0, r3 + 8005e5a: 3720 adds r7, #32 + 8005e5c: 46bd mov sp, r7 + 8005e5e: bd80 pop {r7, pc} + +08005e60 : + * @param SDIOx: Pointer to SDIO register base + * @param Argument: Command Argument + * @retval HAL status + */ +uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument) +{ + 8005e60: b580 push {r7, lr} + 8005e62: b088 sub sp, #32 + 8005e64: af00 add r7, sp, #0 + 8005e66: 6078 str r0, [r7, #4] + 8005e68: 6039 str r1, [r7, #0] + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = Argument; + 8005e6a: 683b ldr r3, [r7, #0] + 8005e6c: 60bb str r3, [r7, #8] + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_STATUS; + 8005e6e: 230d movs r3, #13 + 8005e70: 60fb str r3, [r7, #12] + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + 8005e72: 2340 movs r3, #64 @ 0x40 + 8005e74: 613b str r3, [r7, #16] + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + 8005e76: 2300 movs r3, #0 + 8005e78: 617b str r3, [r7, #20] + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + 8005e7a: f44f 6380 mov.w r3, #1024 @ 0x400 + 8005e7e: 61bb str r3, [r7, #24] + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + 8005e80: f107 0308 add.w r3, r7, #8 + 8005e84: 4619 mov r1, r3 + 8005e86: 6878 ldr r0, [r7, #4] + 8005e88: f7ff fd2a bl 80058e0 + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEND_STATUS, SDIO_CMDTIMEOUT); + 8005e8c: f241 3288 movw r2, #5000 @ 0x1388 + 8005e90: 210d movs r1, #13 + 8005e92: 6878 ldr r0, [r7, #4] + 8005e94: f000 f806 bl 8005ea4 + 8005e98: 61f8 str r0, [r7, #28] + + return errorstate; + 8005e9a: 69fb ldr r3, [r7, #28] +} + 8005e9c: 4618 mov r0, r3 + 8005e9e: 3720 adds r7, #32 + 8005ea0: 46bd mov sp, r7 + 8005ea2: bd80 pop {r7, pc} + +08005ea4 : + * @param SDIOx Pointer to SDMMC register base + * @param SD_CMD: The sent command index + * @retval SD Card error state + */ +uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout) +{ + 8005ea4: b580 push {r7, lr} + 8005ea6: b088 sub sp, #32 + 8005ea8: af00 add r7, sp, #0 + 8005eaa: 60f8 str r0, [r7, #12] + 8005eac: 460b mov r3, r1 + 8005eae: 607a str r2, [r7, #4] + 8005eb0: 72fb strb r3, [r7, #11] + uint32_t response_r1; + uint32_t sta_reg; + + /* 8 is the number of required instructions cycles for the below loop statement. + The Timeout is expressed in ms */ + uint32_t count = Timeout * (SystemCoreClock / 8U /1000U); + 8005eb2: 4b70 ldr r3, [pc, #448] @ (8006074 ) + 8005eb4: 681b ldr r3, [r3, #0] + 8005eb6: 4a70 ldr r2, [pc, #448] @ (8006078 ) + 8005eb8: fba2 2303 umull r2, r3, r2, r3 + 8005ebc: 0a5a lsrs r2, r3, #9 + 8005ebe: 687b ldr r3, [r7, #4] + 8005ec0: fb02 f303 mul.w r3, r2, r3 + 8005ec4: 61fb str r3, [r7, #28] + + do + { + if (count-- == 0U) + 8005ec6: 69fb ldr r3, [r7, #28] + 8005ec8: 1e5a subs r2, r3, #1 + 8005eca: 61fa str r2, [r7, #28] + 8005ecc: 2b00 cmp r3, #0 + 8005ece: d102 bne.n 8005ed6 + { + return SDMMC_ERROR_TIMEOUT; + 8005ed0: f04f 4300 mov.w r3, #2147483648 @ 0x80000000 + 8005ed4: e0c9 b.n 800606a + } + sta_reg = SDIOx->STA; + 8005ed6: 68fb ldr r3, [r7, #12] + 8005ed8: 6b5b ldr r3, [r3, #52] @ 0x34 + 8005eda: 61bb str r3, [r7, #24] + }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || + 8005edc: 69bb ldr r3, [r7, #24] + 8005ede: f003 0345 and.w r3, r3, #69 @ 0x45 + 8005ee2: 2b00 cmp r3, #0 + 8005ee4: d0ef beq.n 8005ec6 + ((sta_reg & SDIO_FLAG_CMDACT) != 0U )); + 8005ee6: 69bb ldr r3, [r7, #24] + 8005ee8: f403 6300 and.w r3, r3, #2048 @ 0x800 + }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || + 8005eec: 2b00 cmp r3, #0 + 8005eee: d1ea bne.n 8005ec6 + + if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) + 8005ef0: 68fb ldr r3, [r7, #12] + 8005ef2: 6b5b ldr r3, [r3, #52] @ 0x34 + 8005ef4: f003 0304 and.w r3, r3, #4 + 8005ef8: 2b00 cmp r3, #0 + 8005efa: d004 beq.n 8005f06 + { + __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); + 8005efc: 68fb ldr r3, [r7, #12] + 8005efe: 2204 movs r2, #4 + 8005f00: 639a str r2, [r3, #56] @ 0x38 + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + 8005f02: 2304 movs r3, #4 + 8005f04: e0b1 b.n 800606a + } + else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL)) + 8005f06: 68fb ldr r3, [r7, #12] + 8005f08: 6b5b ldr r3, [r3, #52] @ 0x34 + 8005f0a: f003 0301 and.w r3, r3, #1 + 8005f0e: 2b00 cmp r3, #0 + 8005f10: d004 beq.n 8005f1c + { + __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL); + 8005f12: 68fb ldr r3, [r7, #12] + 8005f14: 2201 movs r2, #1 + 8005f16: 639a str r2, [r3, #56] @ 0x38 + + return SDMMC_ERROR_CMD_CRC_FAIL; + 8005f18: 2301 movs r3, #1 + 8005f1a: e0a6 b.n 800606a + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS); + 8005f1c: 68fb ldr r3, [r7, #12] + 8005f1e: 22c5 movs r2, #197 @ 0xc5 + 8005f20: 639a str r2, [r3, #56] @ 0x38 + + /* Check response received is of desired command */ + if(SDIO_GetCommandResponse(SDIOx) != SD_CMD) + 8005f22: 68f8 ldr r0, [r7, #12] + 8005f24: f7ff fd42 bl 80059ac + 8005f28: 4603 mov r3, r0 + 8005f2a: 461a mov r2, r3 + 8005f2c: 7afb ldrb r3, [r7, #11] + 8005f2e: 4293 cmp r3, r2 + 8005f30: d001 beq.n 8005f36 + { + return SDMMC_ERROR_CMD_CRC_FAIL; + 8005f32: 2301 movs r3, #1 + 8005f34: e099 b.n 800606a + } + + /* We have received response, retrieve it for analysis */ + response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1); + 8005f36: 2100 movs r1, #0 + 8005f38: 68f8 ldr r0, [r7, #12] + 8005f3a: f7ff fd45 bl 80059c8 + 8005f3e: 6178 str r0, [r7, #20] + + if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO) + 8005f40: 697a ldr r2, [r7, #20] + 8005f42: 4b4e ldr r3, [pc, #312] @ (800607c ) + 8005f44: 4013 ands r3, r2 + 8005f46: 2b00 cmp r3, #0 + 8005f48: d101 bne.n 8005f4e + { + return SDMMC_ERROR_NONE; + 8005f4a: 2300 movs r3, #0 + 8005f4c: e08d b.n 800606a + } + else if((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE) + 8005f4e: 697b ldr r3, [r7, #20] + 8005f50: 2b00 cmp r3, #0 + 8005f52: da02 bge.n 8005f5a + { + return SDMMC_ERROR_ADDR_OUT_OF_RANGE; + 8005f54: f04f 7300 mov.w r3, #33554432 @ 0x2000000 + 8005f58: e087 b.n 800606a + } + else if((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED) + 8005f5a: 697b ldr r3, [r7, #20] + 8005f5c: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 + 8005f60: 2b00 cmp r3, #0 + 8005f62: d001 beq.n 8005f68 + { + return SDMMC_ERROR_ADDR_MISALIGNED; + 8005f64: 2340 movs r3, #64 @ 0x40 + 8005f66: e080 b.n 800606a + } + else if((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR) + 8005f68: 697b ldr r3, [r7, #20] + 8005f6a: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 + 8005f6e: 2b00 cmp r3, #0 + 8005f70: d001 beq.n 8005f76 + { + return SDMMC_ERROR_BLOCK_LEN_ERR; + 8005f72: 2380 movs r3, #128 @ 0x80 + 8005f74: e079 b.n 800606a + } + else if((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR) + 8005f76: 697b ldr r3, [r7, #20] + 8005f78: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8005f7c: 2b00 cmp r3, #0 + 8005f7e: d002 beq.n 8005f86 + { + return SDMMC_ERROR_ERASE_SEQ_ERR; + 8005f80: f44f 7380 mov.w r3, #256 @ 0x100 + 8005f84: e071 b.n 800606a + } + else if((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM) + 8005f86: 697b ldr r3, [r7, #20] + 8005f88: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 + 8005f8c: 2b00 cmp r3, #0 + 8005f8e: d002 beq.n 8005f96 + { + return SDMMC_ERROR_BAD_ERASE_PARAM; + 8005f90: f44f 7300 mov.w r3, #512 @ 0x200 + 8005f94: e069 b.n 800606a + } + else if((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION) + 8005f96: 697b ldr r3, [r7, #20] + 8005f98: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 + 8005f9c: 2b00 cmp r3, #0 + 8005f9e: d002 beq.n 8005fa6 + { + return SDMMC_ERROR_WRITE_PROT_VIOLATION; + 8005fa0: f44f 6380 mov.w r3, #1024 @ 0x400 + 8005fa4: e061 b.n 800606a + } + else if((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED) + 8005fa6: 697b ldr r3, [r7, #20] + 8005fa8: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 + 8005fac: 2b00 cmp r3, #0 + 8005fae: d002 beq.n 8005fb6 + { + return SDMMC_ERROR_LOCK_UNLOCK_FAILED; + 8005fb0: f44f 6300 mov.w r3, #2048 @ 0x800 + 8005fb4: e059 b.n 800606a + } + else if((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED) + 8005fb6: 697b ldr r3, [r7, #20] + 8005fb8: f403 0300 and.w r3, r3, #8388608 @ 0x800000 + 8005fbc: 2b00 cmp r3, #0 + 8005fbe: d002 beq.n 8005fc6 + { + return SDMMC_ERROR_COM_CRC_FAILED; + 8005fc0: f44f 5380 mov.w r3, #4096 @ 0x1000 + 8005fc4: e051 b.n 800606a + } + else if((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD) + 8005fc6: 697b ldr r3, [r7, #20] + 8005fc8: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 8005fcc: 2b00 cmp r3, #0 + 8005fce: d002 beq.n 8005fd6 + { + return SDMMC_ERROR_ILLEGAL_CMD; + 8005fd0: f44f 5300 mov.w r3, #8192 @ 0x2000 + 8005fd4: e049 b.n 800606a + } + else if((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED) + 8005fd6: 697b ldr r3, [r7, #20] + 8005fd8: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 8005fdc: 2b00 cmp r3, #0 + 8005fde: d002 beq.n 8005fe6 + { + return SDMMC_ERROR_CARD_ECC_FAILED; + 8005fe0: f44f 4380 mov.w r3, #16384 @ 0x4000 + 8005fe4: e041 b.n 800606a + } + else if((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR) + 8005fe6: 697b ldr r3, [r7, #20] + 8005fe8: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 8005fec: 2b00 cmp r3, #0 + 8005fee: d002 beq.n 8005ff6 + { + return SDMMC_ERROR_CC_ERR; + 8005ff0: f44f 4300 mov.w r3, #32768 @ 0x8000 + 8005ff4: e039 b.n 800606a + } + else if((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN) + 8005ff6: 697b ldr r3, [r7, #20] + 8005ff8: f403 2380 and.w r3, r3, #262144 @ 0x40000 + 8005ffc: 2b00 cmp r3, #0 + 8005ffe: d002 beq.n 8006006 + { + return SDMMC_ERROR_STREAM_READ_UNDERRUN; + 8006000: f44f 3300 mov.w r3, #131072 @ 0x20000 + 8006004: e031 b.n 800606a + } + else if((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN) + 8006006: 697b ldr r3, [r7, #20] + 8006008: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 800600c: 2b00 cmp r3, #0 + 800600e: d002 beq.n 8006016 + { + return SDMMC_ERROR_STREAM_WRITE_OVERRUN; + 8006010: f44f 2380 mov.w r3, #262144 @ 0x40000 + 8006014: e029 b.n 800606a + } + else if((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE) + 8006016: 697b ldr r3, [r7, #20] + 8006018: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 800601c: 2b00 cmp r3, #0 + 800601e: d002 beq.n 8006026 + { + return SDMMC_ERROR_CID_CSD_OVERWRITE; + 8006020: f44f 2300 mov.w r3, #524288 @ 0x80000 + 8006024: e021 b.n 800606a + } + else if((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP) + 8006026: 697b ldr r3, [r7, #20] + 8006028: f403 4300 and.w r3, r3, #32768 @ 0x8000 + 800602c: 2b00 cmp r3, #0 + 800602e: d002 beq.n 8006036 + { + return SDMMC_ERROR_WP_ERASE_SKIP; + 8006030: f44f 1380 mov.w r3, #1048576 @ 0x100000 + 8006034: e019 b.n 800606a + } + else if((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED) + 8006036: 697b ldr r3, [r7, #20] + 8006038: f403 4380 and.w r3, r3, #16384 @ 0x4000 + 800603c: 2b00 cmp r3, #0 + 800603e: d002 beq.n 8006046 + { + return SDMMC_ERROR_CARD_ECC_DISABLED; + 8006040: f44f 1300 mov.w r3, #2097152 @ 0x200000 + 8006044: e011 b.n 800606a + } + else if((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET) + 8006046: 697b ldr r3, [r7, #20] + 8006048: f403 5300 and.w r3, r3, #8192 @ 0x2000 + 800604c: 2b00 cmp r3, #0 + 800604e: d002 beq.n 8006056 + { + return SDMMC_ERROR_ERASE_RESET; + 8006050: f44f 0380 mov.w r3, #4194304 @ 0x400000 + 8006054: e009 b.n 800606a + } + else if((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR) + 8006056: 697b ldr r3, [r7, #20] + 8006058: f003 0308 and.w r3, r3, #8 + 800605c: 2b00 cmp r3, #0 + 800605e: d002 beq.n 8006066 + { + return SDMMC_ERROR_AKE_SEQ_ERR; + 8006060: f44f 0300 mov.w r3, #8388608 @ 0x800000 + 8006064: e001 b.n 800606a + } + else + { + return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + 8006066: f44f 3380 mov.w r3, #65536 @ 0x10000 + } +} + 800606a: 4618 mov r0, r3 + 800606c: 3720 adds r7, #32 + 800606e: 46bd mov sp, r7 + 8006070: bd80 pop {r7, pc} + 8006072: bf00 nop + 8006074: 20000018 .word 0x20000018 + 8006078: 10624dd3 .word 0x10624dd3 + 800607c: fdffe008 .word 0xfdffe008 + +08006080 : + * @brief Checks for error conditions for R2 (CID or CSD) response. + * @param SDIOx Pointer to SDMMC register base + * @retval SD Card error state + */ +uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx) +{ + 8006080: b480 push {r7} + 8006082: b085 sub sp, #20 + 8006084: af00 add r7, sp, #0 + 8006086: 6078 str r0, [r7, #4] + uint32_t sta_reg; + /* 8 is the number of required instructions cycles for the below loop statement. + The SDIO_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + 8006088: 4b1f ldr r3, [pc, #124] @ (8006108 ) + 800608a: 681b ldr r3, [r3, #0] + 800608c: 4a1f ldr r2, [pc, #124] @ (800610c ) + 800608e: fba2 2303 umull r2, r3, r2, r3 + 8006092: 0a5b lsrs r3, r3, #9 + 8006094: f241 3288 movw r2, #5000 @ 0x1388 + 8006098: fb02 f303 mul.w r3, r2, r3 + 800609c: 60fb str r3, [r7, #12] + + do + { + if (count-- == 0U) + 800609e: 68fb ldr r3, [r7, #12] + 80060a0: 1e5a subs r2, r3, #1 + 80060a2: 60fa str r2, [r7, #12] + 80060a4: 2b00 cmp r3, #0 + 80060a6: d102 bne.n 80060ae + { + return SDMMC_ERROR_TIMEOUT; + 80060a8: f04f 4300 mov.w r3, #2147483648 @ 0x80000000 + 80060ac: e026 b.n 80060fc + } + sta_reg = SDIOx->STA; + 80060ae: 687b ldr r3, [r7, #4] + 80060b0: 6b5b ldr r3, [r3, #52] @ 0x34 + 80060b2: 60bb str r3, [r7, #8] + }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || + 80060b4: 68bb ldr r3, [r7, #8] + 80060b6: f003 0345 and.w r3, r3, #69 @ 0x45 + 80060ba: 2b00 cmp r3, #0 + 80060bc: d0ef beq.n 800609e + ((sta_reg & SDIO_FLAG_CMDACT) != 0U )); + 80060be: 68bb ldr r3, [r7, #8] + 80060c0: f403 6300 and.w r3, r3, #2048 @ 0x800 + }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || + 80060c4: 2b00 cmp r3, #0 + 80060c6: d1ea bne.n 800609e + + if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) + 80060c8: 687b ldr r3, [r7, #4] + 80060ca: 6b5b ldr r3, [r3, #52] @ 0x34 + 80060cc: f003 0304 and.w r3, r3, #4 + 80060d0: 2b00 cmp r3, #0 + 80060d2: d004 beq.n 80060de + { + __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); + 80060d4: 687b ldr r3, [r7, #4] + 80060d6: 2204 movs r2, #4 + 80060d8: 639a str r2, [r3, #56] @ 0x38 + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + 80060da: 2304 movs r3, #4 + 80060dc: e00e b.n 80060fc + } + else if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL)) + 80060de: 687b ldr r3, [r7, #4] + 80060e0: 6b5b ldr r3, [r3, #52] @ 0x34 + 80060e2: f003 0301 and.w r3, r3, #1 + 80060e6: 2b00 cmp r3, #0 + 80060e8: d004 beq.n 80060f4 + { + __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL); + 80060ea: 687b ldr r3, [r7, #4] + 80060ec: 2201 movs r2, #1 + 80060ee: 639a str r2, [r3, #56] @ 0x38 + + return SDMMC_ERROR_CMD_CRC_FAIL; + 80060f0: 2301 movs r3, #1 + 80060f2: e003 b.n 80060fc + } + else + { + /* No error flag set */ + /* Clear all the static flags */ + __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS); + 80060f4: 687b ldr r3, [r7, #4] + 80060f6: 22c5 movs r2, #197 @ 0xc5 + 80060f8: 639a str r2, [r3, #56] @ 0x38 + } + + return SDMMC_ERROR_NONE; + 80060fa: 2300 movs r3, #0 +} + 80060fc: 4618 mov r0, r3 + 80060fe: 3714 adds r7, #20 + 8006100: 46bd mov sp, r7 + 8006102: f85d 7b04 ldr.w r7, [sp], #4 + 8006106: 4770 bx lr + 8006108: 20000018 .word 0x20000018 + 800610c: 10624dd3 .word 0x10624dd3 + +08006110 : + * @brief Checks for error conditions for R3 (OCR) response. + * @param SDIOx Pointer to SDMMC register base + * @retval SD Card error state + */ +uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx) +{ + 8006110: b480 push {r7} + 8006112: b085 sub sp, #20 + 8006114: af00 add r7, sp, #0 + 8006116: 6078 str r0, [r7, #4] + uint32_t sta_reg; + /* 8 is the number of required instructions cycles for the below loop statement. + The SDIO_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + 8006118: 4b1a ldr r3, [pc, #104] @ (8006184 ) + 800611a: 681b ldr r3, [r3, #0] + 800611c: 4a1a ldr r2, [pc, #104] @ (8006188 ) + 800611e: fba2 2303 umull r2, r3, r2, r3 + 8006122: 0a5b lsrs r3, r3, #9 + 8006124: f241 3288 movw r2, #5000 @ 0x1388 + 8006128: fb02 f303 mul.w r3, r2, r3 + 800612c: 60fb str r3, [r7, #12] + + do + { + if (count-- == 0U) + 800612e: 68fb ldr r3, [r7, #12] + 8006130: 1e5a subs r2, r3, #1 + 8006132: 60fa str r2, [r7, #12] + 8006134: 2b00 cmp r3, #0 + 8006136: d102 bne.n 800613e + { + return SDMMC_ERROR_TIMEOUT; + 8006138: f04f 4300 mov.w r3, #2147483648 @ 0x80000000 + 800613c: e01b b.n 8006176 + } + sta_reg = SDIOx->STA; + 800613e: 687b ldr r3, [r7, #4] + 8006140: 6b5b ldr r3, [r3, #52] @ 0x34 + 8006142: 60bb str r3, [r7, #8] + }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || + 8006144: 68bb ldr r3, [r7, #8] + 8006146: f003 0345 and.w r3, r3, #69 @ 0x45 + 800614a: 2b00 cmp r3, #0 + 800614c: d0ef beq.n 800612e + ((sta_reg & SDIO_FLAG_CMDACT) != 0U )); + 800614e: 68bb ldr r3, [r7, #8] + 8006150: f403 6300 and.w r3, r3, #2048 @ 0x800 + }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || + 8006154: 2b00 cmp r3, #0 + 8006156: d1ea bne.n 800612e + + if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) + 8006158: 687b ldr r3, [r7, #4] + 800615a: 6b5b ldr r3, [r3, #52] @ 0x34 + 800615c: f003 0304 and.w r3, r3, #4 + 8006160: 2b00 cmp r3, #0 + 8006162: d004 beq.n 800616e + { + __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); + 8006164: 687b ldr r3, [r7, #4] + 8006166: 2204 movs r2, #4 + 8006168: 639a str r2, [r3, #56] @ 0x38 + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + 800616a: 2304 movs r3, #4 + 800616c: e003 b.n 8006176 + } + else + { + /* Clear all the static flags */ + __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS); + 800616e: 687b ldr r3, [r7, #4] + 8006170: 22c5 movs r2, #197 @ 0xc5 + 8006172: 639a str r2, [r3, #56] @ 0x38 + } + + return SDMMC_ERROR_NONE; + 8006174: 2300 movs r3, #0 +} + 8006176: 4618 mov r0, r3 + 8006178: 3714 adds r7, #20 + 800617a: 46bd mov sp, r7 + 800617c: f85d 7b04 ldr.w r7, [sp], #4 + 8006180: 4770 bx lr + 8006182: bf00 nop + 8006184: 20000018 .word 0x20000018 + 8006188: 10624dd3 .word 0x10624dd3 + +0800618c : + * @param pRCA: Pointer to the variable that will contain the SD card relative + * address RCA + * @retval SD Card error state + */ +uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA) +{ + 800618c: b580 push {r7, lr} + 800618e: b088 sub sp, #32 + 8006190: af00 add r7, sp, #0 + 8006192: 60f8 str r0, [r7, #12] + 8006194: 460b mov r3, r1 + 8006196: 607a str r2, [r7, #4] + 8006198: 72fb strb r3, [r7, #11] + uint32_t response_r1; + uint32_t sta_reg; + + /* 8 is the number of required instructions cycles for the below loop statement. + The SDIO_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + 800619a: 4b35 ldr r3, [pc, #212] @ (8006270 ) + 800619c: 681b ldr r3, [r3, #0] + 800619e: 4a35 ldr r2, [pc, #212] @ (8006274 ) + 80061a0: fba2 2303 umull r2, r3, r2, r3 + 80061a4: 0a5b lsrs r3, r3, #9 + 80061a6: f241 3288 movw r2, #5000 @ 0x1388 + 80061aa: fb02 f303 mul.w r3, r2, r3 + 80061ae: 61fb str r3, [r7, #28] + + do + { + if (count-- == 0U) + 80061b0: 69fb ldr r3, [r7, #28] + 80061b2: 1e5a subs r2, r3, #1 + 80061b4: 61fa str r2, [r7, #28] + 80061b6: 2b00 cmp r3, #0 + 80061b8: d102 bne.n 80061c0 + { + return SDMMC_ERROR_TIMEOUT; + 80061ba: f04f 4300 mov.w r3, #2147483648 @ 0x80000000 + 80061be: e052 b.n 8006266 + } + sta_reg = SDIOx->STA; + 80061c0: 68fb ldr r3, [r7, #12] + 80061c2: 6b5b ldr r3, [r3, #52] @ 0x34 + 80061c4: 61bb str r3, [r7, #24] + }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || + 80061c6: 69bb ldr r3, [r7, #24] + 80061c8: f003 0345 and.w r3, r3, #69 @ 0x45 + 80061cc: 2b00 cmp r3, #0 + 80061ce: d0ef beq.n 80061b0 + ((sta_reg & SDIO_FLAG_CMDACT) != 0U )); + 80061d0: 69bb ldr r3, [r7, #24] + 80061d2: f403 6300 and.w r3, r3, #2048 @ 0x800 + }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || + 80061d6: 2b00 cmp r3, #0 + 80061d8: d1ea bne.n 80061b0 + + if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) + 80061da: 68fb ldr r3, [r7, #12] + 80061dc: 6b5b ldr r3, [r3, #52] @ 0x34 + 80061de: f003 0304 and.w r3, r3, #4 + 80061e2: 2b00 cmp r3, #0 + 80061e4: d004 beq.n 80061f0 + { + __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); + 80061e6: 68fb ldr r3, [r7, #12] + 80061e8: 2204 movs r2, #4 + 80061ea: 639a str r2, [r3, #56] @ 0x38 + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + 80061ec: 2304 movs r3, #4 + 80061ee: e03a b.n 8006266 + } + else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL)) + 80061f0: 68fb ldr r3, [r7, #12] + 80061f2: 6b5b ldr r3, [r3, #52] @ 0x34 + 80061f4: f003 0301 and.w r3, r3, #1 + 80061f8: 2b00 cmp r3, #0 + 80061fa: d004 beq.n 8006206 + { + __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL); + 80061fc: 68fb ldr r3, [r7, #12] + 80061fe: 2201 movs r2, #1 + 8006200: 639a str r2, [r3, #56] @ 0x38 + + return SDMMC_ERROR_CMD_CRC_FAIL; + 8006202: 2301 movs r3, #1 + 8006204: e02f b.n 8006266 + { + /* Nothing to do */ + } + + /* Check response received is of desired command */ + if(SDIO_GetCommandResponse(SDIOx) != SD_CMD) + 8006206: 68f8 ldr r0, [r7, #12] + 8006208: f7ff fbd0 bl 80059ac + 800620c: 4603 mov r3, r0 + 800620e: 461a mov r2, r3 + 8006210: 7afb ldrb r3, [r7, #11] + 8006212: 4293 cmp r3, r2 + 8006214: d001 beq.n 800621a + { + return SDMMC_ERROR_CMD_CRC_FAIL; + 8006216: 2301 movs r3, #1 + 8006218: e025 b.n 8006266 + } + + /* Clear all the static flags */ + __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS); + 800621a: 68fb ldr r3, [r7, #12] + 800621c: 22c5 movs r2, #197 @ 0xc5 + 800621e: 639a str r2, [r3, #56] @ 0x38 + + /* We have received response, retrieve it. */ + response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1); + 8006220: 2100 movs r1, #0 + 8006222: 68f8 ldr r0, [r7, #12] + 8006224: f7ff fbd0 bl 80059c8 + 8006228: 6178 str r0, [r7, #20] + + if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO) + 800622a: 697b ldr r3, [r7, #20] + 800622c: f403 4360 and.w r3, r3, #57344 @ 0xe000 + 8006230: 2b00 cmp r3, #0 + 8006232: d106 bne.n 8006242 + { + *pRCA = (uint16_t) (response_r1 >> 16); + 8006234: 697b ldr r3, [r7, #20] + 8006236: 0c1b lsrs r3, r3, #16 + 8006238: b29a uxth r2, r3 + 800623a: 687b ldr r3, [r7, #4] + 800623c: 801a strh r2, [r3, #0] + + return SDMMC_ERROR_NONE; + 800623e: 2300 movs r3, #0 + 8006240: e011 b.n 8006266 + } + else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD) + 8006242: 697b ldr r3, [r7, #20] + 8006244: f403 4380 and.w r3, r3, #16384 @ 0x4000 + 8006248: 2b00 cmp r3, #0 + 800624a: d002 beq.n 8006252 + { + return SDMMC_ERROR_ILLEGAL_CMD; + 800624c: f44f 5300 mov.w r3, #8192 @ 0x2000 + 8006250: e009 b.n 8006266 + } + else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED) + 8006252: 697b ldr r3, [r7, #20] + 8006254: f403 4300 and.w r3, r3, #32768 @ 0x8000 + 8006258: 2b00 cmp r3, #0 + 800625a: d002 beq.n 8006262 + { + return SDMMC_ERROR_COM_CRC_FAILED; + 800625c: f44f 5380 mov.w r3, #4096 @ 0x1000 + 8006260: e001 b.n 8006266 + } + else + { + return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + 8006262: f44f 3380 mov.w r3, #65536 @ 0x10000 + } +} + 8006266: 4618 mov r0, r3 + 8006268: 3720 adds r7, #32 + 800626a: 46bd mov sp, r7 + 800626c: bd80 pop {r7, pc} + 800626e: bf00 nop + 8006270: 20000018 .word 0x20000018 + 8006274: 10624dd3 .word 0x10624dd3 + +08006278 : + * @brief Checks for error conditions for R7 response. + * @param SDIOx Pointer to SDMMC register base + * @retval SD Card error state + */ +uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx) +{ + 8006278: b480 push {r7} + 800627a: b085 sub sp, #20 + 800627c: af00 add r7, sp, #0 + 800627e: 6078 str r0, [r7, #4] + uint32_t sta_reg; + /* 8 is the number of required instructions cycles for the below loop statement. + The SDIO_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + 8006280: 4b22 ldr r3, [pc, #136] @ (800630c ) + 8006282: 681b ldr r3, [r3, #0] + 8006284: 4a22 ldr r2, [pc, #136] @ (8006310 ) + 8006286: fba2 2303 umull r2, r3, r2, r3 + 800628a: 0a5b lsrs r3, r3, #9 + 800628c: f241 3288 movw r2, #5000 @ 0x1388 + 8006290: fb02 f303 mul.w r3, r2, r3 + 8006294: 60fb str r3, [r7, #12] + + do + { + if (count-- == 0U) + 8006296: 68fb ldr r3, [r7, #12] + 8006298: 1e5a subs r2, r3, #1 + 800629a: 60fa str r2, [r7, #12] + 800629c: 2b00 cmp r3, #0 + 800629e: d102 bne.n 80062a6 + { + return SDMMC_ERROR_TIMEOUT; + 80062a0: f04f 4300 mov.w r3, #2147483648 @ 0x80000000 + 80062a4: e02c b.n 8006300 + } + sta_reg = SDIOx->STA; + 80062a6: 687b ldr r3, [r7, #4] + 80062a8: 6b5b ldr r3, [r3, #52] @ 0x34 + 80062aa: 60bb str r3, [r7, #8] + }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || + 80062ac: 68bb ldr r3, [r7, #8] + 80062ae: f003 0345 and.w r3, r3, #69 @ 0x45 + 80062b2: 2b00 cmp r3, #0 + 80062b4: d0ef beq.n 8006296 + ((sta_reg & SDIO_FLAG_CMDACT) != 0U )); + 80062b6: 68bb ldr r3, [r7, #8] + 80062b8: f403 6300 and.w r3, r3, #2048 @ 0x800 + }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || + 80062bc: 2b00 cmp r3, #0 + 80062be: d1ea bne.n 8006296 + + if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) + 80062c0: 687b ldr r3, [r7, #4] + 80062c2: 6b5b ldr r3, [r3, #52] @ 0x34 + 80062c4: f003 0304 and.w r3, r3, #4 + 80062c8: 2b00 cmp r3, #0 + 80062ca: d004 beq.n 80062d6 + { + /* Card is SD V2.0 compliant */ + __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); + 80062cc: 687b ldr r3, [r7, #4] + 80062ce: 2204 movs r2, #4 + 80062d0: 639a str r2, [r3, #56] @ 0x38 + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + 80062d2: 2304 movs r3, #4 + 80062d4: e014 b.n 8006300 + } + else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL)) + 80062d6: 687b ldr r3, [r7, #4] + 80062d8: 6b5b ldr r3, [r3, #52] @ 0x34 + 80062da: f003 0301 and.w r3, r3, #1 + 80062de: 2b00 cmp r3, #0 + 80062e0: d004 beq.n 80062ec + { + /* Card is SD V2.0 compliant */ + __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL); + 80062e2: 687b ldr r3, [r7, #4] + 80062e4: 2201 movs r2, #1 + 80062e6: 639a str r2, [r3, #56] @ 0x38 + + return SDMMC_ERROR_CMD_CRC_FAIL; + 80062e8: 2301 movs r3, #1 + 80062ea: e009 b.n 8006300 + else + { + /* Nothing to do */ + } + + if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDREND)) + 80062ec: 687b ldr r3, [r7, #4] + 80062ee: 6b5b ldr r3, [r3, #52] @ 0x34 + 80062f0: f003 0340 and.w r3, r3, #64 @ 0x40 + 80062f4: 2b00 cmp r3, #0 + 80062f6: d002 beq.n 80062fe + { + /* Card is SD V2.0 compliant */ + __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CMDREND); + 80062f8: 687b ldr r3, [r7, #4] + 80062fa: 2240 movs r2, #64 @ 0x40 + 80062fc: 639a str r2, [r3, #56] @ 0x38 + } + + return SDMMC_ERROR_NONE; + 80062fe: 2300 movs r3, #0 + +} + 8006300: 4618 mov r0, r3 + 8006302: 3714 adds r7, #20 + 8006304: 46bd mov sp, r7 + 8006306: f85d 7b04 ldr.w r7, [sp], #4 + 800630a: 4770 bx lr + 800630c: 20000018 .word 0x20000018 + 8006310: 10624dd3 .word 0x10624dd3 + +08006314 : + * @brief Checks for error conditions for CMD0. + * @param SDIOx Pointer to SDMMC register base + * @retval SD Card error state + */ +static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx) +{ + 8006314: b480 push {r7} + 8006316: b085 sub sp, #20 + 8006318: af00 add r7, sp, #0 + 800631a: 6078 str r0, [r7, #4] + /* 8 is the number of required instructions cycles for the below loop statement. + The SDIO_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + 800631c: 4b11 ldr r3, [pc, #68] @ (8006364 ) + 800631e: 681b ldr r3, [r3, #0] + 8006320: 4a11 ldr r2, [pc, #68] @ (8006368 ) + 8006322: fba2 2303 umull r2, r3, r2, r3 + 8006326: 0a5b lsrs r3, r3, #9 + 8006328: f241 3288 movw r2, #5000 @ 0x1388 + 800632c: fb02 f303 mul.w r3, r2, r3 + 8006330: 60fb str r3, [r7, #12] + + do + { + if (count-- == 0U) + 8006332: 68fb ldr r3, [r7, #12] + 8006334: 1e5a subs r2, r3, #1 + 8006336: 60fa str r2, [r7, #12] + 8006338: 2b00 cmp r3, #0 + 800633a: d102 bne.n 8006342 + { + return SDMMC_ERROR_TIMEOUT; + 800633c: f04f 4300 mov.w r3, #2147483648 @ 0x80000000 + 8006340: e009 b.n 8006356 + } + + }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDSENT)); + 8006342: 687b ldr r3, [r7, #4] + 8006344: 6b5b ldr r3, [r3, #52] @ 0x34 + 8006346: f003 0380 and.w r3, r3, #128 @ 0x80 + 800634a: 2b00 cmp r3, #0 + 800634c: d0f1 beq.n 8006332 + + /* Clear all the static flags */ + __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS); + 800634e: 687b ldr r3, [r7, #4] + 8006350: 22c5 movs r2, #197 @ 0xc5 + 8006352: 639a str r2, [r3, #56] @ 0x38 + + return SDMMC_ERROR_NONE; + 8006354: 2300 movs r3, #0 +} + 8006356: 4618 mov r0, r3 + 8006358: 3714 adds r7, #20 + 800635a: 46bd mov sp, r7 + 800635c: f85d 7b04 ldr.w r7, [sp], #4 + 8006360: 4770 bx lr + 8006362: bf00 nop + 8006364: 20000018 .word 0x20000018 + 8006368: 10624dd3 .word 0x10624dd3 + +0800636c <__NVIC_SetPriority>: +{ + 800636c: b480 push {r7} + 800636e: b083 sub sp, #12 + 8006370: af00 add r7, sp, #0 + 8006372: 4603 mov r3, r0 + 8006374: 6039 str r1, [r7, #0] + 8006376: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8006378: f997 3007 ldrsb.w r3, [r7, #7] + 800637c: 2b00 cmp r3, #0 + 800637e: db0a blt.n 8006396 <__NVIC_SetPriority+0x2a> + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8006380: 683b ldr r3, [r7, #0] + 8006382: b2da uxtb r2, r3 + 8006384: 490c ldr r1, [pc, #48] @ (80063b8 <__NVIC_SetPriority+0x4c>) + 8006386: f997 3007 ldrsb.w r3, [r7, #7] + 800638a: 0112 lsls r2, r2, #4 + 800638c: b2d2 uxtb r2, r2 + 800638e: 440b add r3, r1 + 8006390: f883 2300 strb.w r2, [r3, #768] @ 0x300 +} + 8006394: e00a b.n 80063ac <__NVIC_SetPriority+0x40> + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8006396: 683b ldr r3, [r7, #0] + 8006398: b2da uxtb r2, r3 + 800639a: 4908 ldr r1, [pc, #32] @ (80063bc <__NVIC_SetPriority+0x50>) + 800639c: 79fb ldrb r3, [r7, #7] + 800639e: f003 030f and.w r3, r3, #15 + 80063a2: 3b04 subs r3, #4 + 80063a4: 0112 lsls r2, r2, #4 + 80063a6: b2d2 uxtb r2, r2 + 80063a8: 440b add r3, r1 + 80063aa: 761a strb r2, [r3, #24] +} + 80063ac: bf00 nop + 80063ae: 370c adds r7, #12 + 80063b0: 46bd mov sp, r7 + 80063b2: f85d 7b04 ldr.w r7, [sp], #4 + 80063b6: 4770 bx lr + 80063b8: e000e100 .word 0xe000e100 + 80063bc: e000ed00 .word 0xe000ed00 + +080063c0 : /* SysTick handler implementation that also clears overflow flag. */ #if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0) void SysTick_Handler (void) { - 8002e5c: b580 push {r7, lr} - 8002e5e: af00 add r7, sp, #0 + 80063c0: b580 push {r7, lr} + 80063c2: af00 add r7, sp, #0 /* Clear overflow flag */ SysTick->CTRL; - 8002e60: 4b05 ldr r3, [pc, #20] @ (8002e78 ) - 8002e62: 681b ldr r3, [r3, #0] + 80063c4: 4b05 ldr r3, [pc, #20] @ (80063dc ) + 80063c6: 681b ldr r3, [r3, #0] if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { - 8002e64: f001 fd46 bl 80048f4 - 8002e68: 4603 mov r3, r0 - 8002e6a: 2b01 cmp r3, #1 - 8002e6c: d001 beq.n 8002e72 + 80063c8: f002 fb38 bl 8008a3c + 80063cc: 4603 mov r3, r0 + 80063ce: 2b01 cmp r3, #1 + 80063d0: d001 beq.n 80063d6 /* Call tick handler */ xPortSysTickHandler(); - 8002e6e: f002 fb3b bl 80054e8 + 80063d2: f003 faf1 bl 80099b8 } } - 8002e72: bf00 nop - 8002e74: bd80 pop {r7, pc} - 8002e76: bf00 nop - 8002e78: e000e010 .word 0xe000e010 + 80063d6: bf00 nop + 80063d8: bd80 pop {r7, pc} + 80063da: bf00 nop + 80063dc: e000e010 .word 0xe000e010 -08002e7c : +080063e0 : #endif /* SysTick */ /* Setup SVC to reset value. */ __STATIC_INLINE void SVC_Setup (void) { - 8002e7c: b580 push {r7, lr} - 8002e7e: af00 add r7, sp, #0 + 80063e0: b580 push {r7, lr} + 80063e2: af00 add r7, sp, #0 #if (__ARM_ARCH_7A__ == 0U) /* Service Call interrupt might be configured before kernel start */ /* and when its priority is lower or equal to BASEPRI, svc intruction */ /* causes a Hard Fault. */ NVIC_SetPriority (SVCall_IRQ_NBR, 0U); - 8002e80: 2100 movs r1, #0 - 8002e82: f06f 0004 mvn.w r0, #4 - 8002e86: f7ff ffbf bl 8002e08 <__NVIC_SetPriority> + 80063e4: 2100 movs r1, #0 + 80063e6: f06f 0004 mvn.w r0, #4 + 80063ea: f7ff ffbf bl 800636c <__NVIC_SetPriority> #endif } - 8002e8a: bf00 nop - 8002e8c: bd80 pop {r7, pc} + 80063ee: bf00 nop + 80063f0: bd80 pop {r7, pc} ... -08002e90 : +080063f4 : static uint32_t OS_Tick_GetOverflow (void); /* Get OS Tick interval */ static uint32_t OS_Tick_GetInterval (void); /*---------------------------------------------------------------------------*/ osStatus_t osKernelInitialize (void) { - 8002e90: b480 push {r7} - 8002e92: b083 sub sp, #12 - 8002e94: af00 add r7, sp, #0 + 80063f4: b480 push {r7} + 80063f6: b083 sub sp, #12 + 80063f8: af00 add r7, sp, #0 */ __STATIC_FORCEINLINE uint32_t __get_IPSR(void) { uint32_t result; __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - 8002e96: f3ef 8305 mrs r3, IPSR - 8002e9a: 603b str r3, [r7, #0] + 80063fa: f3ef 8305 mrs r3, IPSR + 80063fe: 603b str r3, [r7, #0] return(result); - 8002e9c: 683b ldr r3, [r7, #0] + 8006400: 683b ldr r3, [r7, #0] osStatus_t stat; if (IS_IRQ()) { - 8002e9e: 2b00 cmp r3, #0 - 8002ea0: d003 beq.n 8002eaa + 8006402: 2b00 cmp r3, #0 + 8006404: d003 beq.n 800640e stat = osErrorISR; - 8002ea2: f06f 0305 mvn.w r3, #5 - 8002ea6: 607b str r3, [r7, #4] - 8002ea8: e00c b.n 8002ec4 + 8006406: f06f 0305 mvn.w r3, #5 + 800640a: 607b str r3, [r7, #4] + 800640c: e00c b.n 8006428 } else { if (KernelState == osKernelInactive) { - 8002eaa: 4b0a ldr r3, [pc, #40] @ (8002ed4 ) - 8002eac: 681b ldr r3, [r3, #0] - 8002eae: 2b00 cmp r3, #0 - 8002eb0: d105 bne.n 8002ebe + 800640e: 4b0a ldr r3, [pc, #40] @ (8006438 ) + 8006410: 681b ldr r3, [r3, #0] + 8006412: 2b00 cmp r3, #0 + 8006414: d105 bne.n 8006422 EvrFreeRTOSSetup(0U); #endif #if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1) vPortDefineHeapRegions (configHEAP_5_REGIONS); #endif KernelState = osKernelReady; - 8002eb2: 4b08 ldr r3, [pc, #32] @ (8002ed4 ) - 8002eb4: 2201 movs r2, #1 - 8002eb6: 601a str r2, [r3, #0] + 8006416: 4b08 ldr r3, [pc, #32] @ (8006438 ) + 8006418: 2201 movs r2, #1 + 800641a: 601a str r2, [r3, #0] stat = osOK; - 8002eb8: 2300 movs r3, #0 - 8002eba: 607b str r3, [r7, #4] - 8002ebc: e002 b.n 8002ec4 + 800641c: 2300 movs r3, #0 + 800641e: 607b str r3, [r7, #4] + 8006420: e002 b.n 8006428 } else { stat = osError; - 8002ebe: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff - 8002ec2: 607b str r3, [r7, #4] + 8006422: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 8006426: 607b str r3, [r7, #4] } } return (stat); - 8002ec4: 687b ldr r3, [r7, #4] + 8006428: 687b ldr r3, [r7, #4] } - 8002ec6: 4618 mov r0, r3 - 8002ec8: 370c adds r7, #12 - 8002eca: 46bd mov sp, r7 - 8002ecc: f85d 7b04 ldr.w r7, [sp], #4 - 8002ed0: 4770 bx lr - 8002ed2: bf00 nop - 8002ed4: 200001a4 .word 0x200001a4 + 800642a: 4618 mov r0, r3 + 800642c: 370c adds r7, #12 + 800642e: 46bd mov sp, r7 + 8006430: f85d 7b04 ldr.w r7, [sp], #4 + 8006434: 4770 bx lr + 8006436: bf00 nop + 8006438: 2000032c .word 0x2000032c -08002ed8 : +0800643c : } return (state); } osStatus_t osKernelStart (void) { - 8002ed8: b580 push {r7, lr} - 8002eda: b082 sub sp, #8 - 8002edc: af00 add r7, sp, #0 + 800643c: b580 push {r7, lr} + 800643e: b082 sub sp, #8 + 8006440: af00 add r7, sp, #0 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - 8002ede: f3ef 8305 mrs r3, IPSR - 8002ee2: 603b str r3, [r7, #0] + 8006442: f3ef 8305 mrs r3, IPSR + 8006446: 603b str r3, [r7, #0] return(result); - 8002ee4: 683b ldr r3, [r7, #0] + 8006448: 683b ldr r3, [r7, #0] osStatus_t stat; if (IS_IRQ()) { - 8002ee6: 2b00 cmp r3, #0 - 8002ee8: d003 beq.n 8002ef2 + 800644a: 2b00 cmp r3, #0 + 800644c: d003 beq.n 8006456 stat = osErrorISR; - 8002eea: f06f 0305 mvn.w r3, #5 - 8002eee: 607b str r3, [r7, #4] - 8002ef0: e010 b.n 8002f14 + 800644e: f06f 0305 mvn.w r3, #5 + 8006452: 607b str r3, [r7, #4] + 8006454: e010 b.n 8006478 } else { if (KernelState == osKernelReady) { - 8002ef2: 4b0b ldr r3, [pc, #44] @ (8002f20 ) - 8002ef4: 681b ldr r3, [r3, #0] - 8002ef6: 2b01 cmp r3, #1 - 8002ef8: d109 bne.n 8002f0e + 8006456: 4b0b ldr r3, [pc, #44] @ (8006484 ) + 8006458: 681b ldr r3, [r3, #0] + 800645a: 2b01 cmp r3, #1 + 800645c: d109 bne.n 8006472 /* Ensure SVC priority is at the reset value */ SVC_Setup(); - 8002efa: f7ff ffbf bl 8002e7c + 800645e: f7ff ffbf bl 80063e0 /* Change state to enable IRQ masking check */ KernelState = osKernelRunning; - 8002efe: 4b08 ldr r3, [pc, #32] @ (8002f20 ) - 8002f00: 2202 movs r2, #2 - 8002f02: 601a str r2, [r3, #0] + 8006462: 4b08 ldr r3, [pc, #32] @ (8006484 ) + 8006464: 2202 movs r2, #2 + 8006466: 601a str r2, [r3, #0] /* Start the kernel scheduler */ vTaskStartScheduler(); - 8002f04: f001 f892 bl 800402c + 8006468: f001 fe84 bl 8008174 stat = osOK; - 8002f08: 2300 movs r3, #0 - 8002f0a: 607b str r3, [r7, #4] - 8002f0c: e002 b.n 8002f14 + 800646c: 2300 movs r3, #0 + 800646e: 607b str r3, [r7, #4] + 8006470: e002 b.n 8006478 } else { stat = osError; - 8002f0e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff - 8002f12: 607b str r3, [r7, #4] + 8006472: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 8006476: 607b str r3, [r7, #4] } } return (stat); - 8002f14: 687b ldr r3, [r7, #4] + 8006478: 687b ldr r3, [r7, #4] } - 8002f16: 4618 mov r0, r3 - 8002f18: 3708 adds r7, #8 - 8002f1a: 46bd mov sp, r7 - 8002f1c: bd80 pop {r7, pc} - 8002f1e: bf00 nop - 8002f20: 200001a4 .word 0x200001a4 + 800647a: 4618 mov r0, r3 + 800647c: 3708 adds r7, #8 + 800647e: 46bd mov sp, r7 + 8006480: bd80 pop {r7, pc} + 8006482: bf00 nop + 8006484: 2000032c .word 0x2000032c -08002f24 : +08006488 : return (configCPU_CLOCK_HZ); } /*---------------------------------------------------------------------------*/ osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) { - 8002f24: b580 push {r7, lr} - 8002f26: b08e sub sp, #56 @ 0x38 - 8002f28: af04 add r7, sp, #16 - 8002f2a: 60f8 str r0, [r7, #12] - 8002f2c: 60b9 str r1, [r7, #8] - 8002f2e: 607a str r2, [r7, #4] + 8006488: b580 push {r7, lr} + 800648a: b08e sub sp, #56 @ 0x38 + 800648c: af04 add r7, sp, #16 + 800648e: 60f8 str r0, [r7, #12] + 8006490: 60b9 str r1, [r7, #8] + 8006492: 607a str r2, [r7, #4] uint32_t stack; TaskHandle_t hTask; UBaseType_t prio; int32_t mem; hTask = NULL; - 8002f30: 2300 movs r3, #0 - 8002f32: 613b str r3, [r7, #16] + 8006494: 2300 movs r3, #0 + 8006496: 613b str r3, [r7, #16] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - 8002f34: f3ef 8305 mrs r3, IPSR - 8002f38: 617b str r3, [r7, #20] + 8006498: f3ef 8305 mrs r3, IPSR + 800649c: 617b str r3, [r7, #20] return(result); - 8002f3a: 697b ldr r3, [r7, #20] + 800649e: 697b ldr r3, [r7, #20] if (!IS_IRQ() && (func != NULL)) { - 8002f3c: 2b00 cmp r3, #0 - 8002f3e: d17e bne.n 800303e - 8002f40: 68fb ldr r3, [r7, #12] - 8002f42: 2b00 cmp r3, #0 - 8002f44: d07b beq.n 800303e + 80064a0: 2b00 cmp r3, #0 + 80064a2: d17e bne.n 80065a2 + 80064a4: 68fb ldr r3, [r7, #12] + 80064a6: 2b00 cmp r3, #0 + 80064a8: d07b beq.n 80065a2 stack = configMINIMAL_STACK_SIZE; - 8002f46: 2380 movs r3, #128 @ 0x80 - 8002f48: 623b str r3, [r7, #32] + 80064aa: 2380 movs r3, #128 @ 0x80 + 80064ac: 623b str r3, [r7, #32] prio = (UBaseType_t)osPriorityNormal; - 8002f4a: 2318 movs r3, #24 - 8002f4c: 61fb str r3, [r7, #28] + 80064ae: 2318 movs r3, #24 + 80064b0: 61fb str r3, [r7, #28] name = NULL; - 8002f4e: 2300 movs r3, #0 - 8002f50: 627b str r3, [r7, #36] @ 0x24 + 80064b2: 2300 movs r3, #0 + 80064b4: 627b str r3, [r7, #36] @ 0x24 mem = -1; - 8002f52: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff - 8002f56: 61bb str r3, [r7, #24] + 80064b6: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 80064ba: 61bb str r3, [r7, #24] if (attr != NULL) { - 8002f58: 687b ldr r3, [r7, #4] - 8002f5a: 2b00 cmp r3, #0 - 8002f5c: d045 beq.n 8002fea + 80064bc: 687b ldr r3, [r7, #4] + 80064be: 2b00 cmp r3, #0 + 80064c0: d045 beq.n 800654e if (attr->name != NULL) { - 8002f5e: 687b ldr r3, [r7, #4] - 8002f60: 681b ldr r3, [r3, #0] - 8002f62: 2b00 cmp r3, #0 - 8002f64: d002 beq.n 8002f6c + 80064c2: 687b ldr r3, [r7, #4] + 80064c4: 681b ldr r3, [r3, #0] + 80064c6: 2b00 cmp r3, #0 + 80064c8: d002 beq.n 80064d0 name = attr->name; - 8002f66: 687b ldr r3, [r7, #4] - 8002f68: 681b ldr r3, [r3, #0] - 8002f6a: 627b str r3, [r7, #36] @ 0x24 + 80064ca: 687b ldr r3, [r7, #4] + 80064cc: 681b ldr r3, [r3, #0] + 80064ce: 627b str r3, [r7, #36] @ 0x24 } if (attr->priority != osPriorityNone) { - 8002f6c: 687b ldr r3, [r7, #4] - 8002f6e: 699b ldr r3, [r3, #24] - 8002f70: 2b00 cmp r3, #0 - 8002f72: d002 beq.n 8002f7a + 80064d0: 687b ldr r3, [r7, #4] + 80064d2: 699b ldr r3, [r3, #24] + 80064d4: 2b00 cmp r3, #0 + 80064d6: d002 beq.n 80064de prio = (UBaseType_t)attr->priority; - 8002f74: 687b ldr r3, [r7, #4] - 8002f76: 699b ldr r3, [r3, #24] - 8002f78: 61fb str r3, [r7, #28] + 80064d8: 687b ldr r3, [r7, #4] + 80064da: 699b ldr r3, [r3, #24] + 80064dc: 61fb str r3, [r7, #28] } if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) { - 8002f7a: 69fb ldr r3, [r7, #28] - 8002f7c: 2b00 cmp r3, #0 - 8002f7e: d008 beq.n 8002f92 - 8002f80: 69fb ldr r3, [r7, #28] - 8002f82: 2b38 cmp r3, #56 @ 0x38 - 8002f84: d805 bhi.n 8002f92 - 8002f86: 687b ldr r3, [r7, #4] - 8002f88: 685b ldr r3, [r3, #4] - 8002f8a: f003 0301 and.w r3, r3, #1 - 8002f8e: 2b00 cmp r3, #0 - 8002f90: d001 beq.n 8002f96 + 80064de: 69fb ldr r3, [r7, #28] + 80064e0: 2b00 cmp r3, #0 + 80064e2: d008 beq.n 80064f6 + 80064e4: 69fb ldr r3, [r7, #28] + 80064e6: 2b38 cmp r3, #56 @ 0x38 + 80064e8: d805 bhi.n 80064f6 + 80064ea: 687b ldr r3, [r7, #4] + 80064ec: 685b ldr r3, [r3, #4] + 80064ee: f003 0301 and.w r3, r3, #1 + 80064f2: 2b00 cmp r3, #0 + 80064f4: d001 beq.n 80064fa return (NULL); - 8002f92: 2300 movs r3, #0 - 8002f94: e054 b.n 8003040 + 80064f6: 2300 movs r3, #0 + 80064f8: e054 b.n 80065a4 } if (attr->stack_size > 0U) { - 8002f96: 687b ldr r3, [r7, #4] - 8002f98: 695b ldr r3, [r3, #20] - 8002f9a: 2b00 cmp r3, #0 - 8002f9c: d003 beq.n 8002fa6 + 80064fa: 687b ldr r3, [r7, #4] + 80064fc: 695b ldr r3, [r3, #20] + 80064fe: 2b00 cmp r3, #0 + 8006500: d003 beq.n 800650a /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports. */ /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */ stack = attr->stack_size / sizeof(StackType_t); - 8002f9e: 687b ldr r3, [r7, #4] - 8002fa0: 695b ldr r3, [r3, #20] - 8002fa2: 089b lsrs r3, r3, #2 - 8002fa4: 623b str r3, [r7, #32] + 8006502: 687b ldr r3, [r7, #4] + 8006504: 695b ldr r3, [r3, #20] + 8006506: 089b lsrs r3, r3, #2 + 8006508: 623b str r3, [r7, #32] } if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && - 8002fa6: 687b ldr r3, [r7, #4] - 8002fa8: 689b ldr r3, [r3, #8] - 8002faa: 2b00 cmp r3, #0 - 8002fac: d00e beq.n 8002fcc - 8002fae: 687b ldr r3, [r7, #4] - 8002fb0: 68db ldr r3, [r3, #12] - 8002fb2: 2ba7 cmp r3, #167 @ 0xa7 - 8002fb4: d90a bls.n 8002fcc + 800650a: 687b ldr r3, [r7, #4] + 800650c: 689b ldr r3, [r3, #8] + 800650e: 2b00 cmp r3, #0 + 8006510: d00e beq.n 8006530 + 8006512: 687b ldr r3, [r7, #4] + 8006514: 68db ldr r3, [r3, #12] + 8006516: 2ba7 cmp r3, #167 @ 0xa7 + 8006518: d90a bls.n 8006530 (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { - 8002fb6: 687b ldr r3, [r7, #4] - 8002fb8: 691b ldr r3, [r3, #16] + 800651a: 687b ldr r3, [r7, #4] + 800651c: 691b ldr r3, [r3, #16] if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && - 8002fba: 2b00 cmp r3, #0 - 8002fbc: d006 beq.n 8002fcc + 800651e: 2b00 cmp r3, #0 + 8006520: d006 beq.n 8006530 (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { - 8002fbe: 687b ldr r3, [r7, #4] - 8002fc0: 695b ldr r3, [r3, #20] - 8002fc2: 2b00 cmp r3, #0 - 8002fc4: d002 beq.n 8002fcc + 8006522: 687b ldr r3, [r7, #4] + 8006524: 695b ldr r3, [r3, #20] + 8006526: 2b00 cmp r3, #0 + 8006528: d002 beq.n 8006530 mem = 1; - 8002fc6: 2301 movs r3, #1 - 8002fc8: 61bb str r3, [r7, #24] - 8002fca: e010 b.n 8002fee + 800652a: 2301 movs r3, #1 + 800652c: 61bb str r3, [r7, #24] + 800652e: e010 b.n 8006552 } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) { - 8002fcc: 687b ldr r3, [r7, #4] - 8002fce: 689b ldr r3, [r3, #8] - 8002fd0: 2b00 cmp r3, #0 - 8002fd2: d10c bne.n 8002fee - 8002fd4: 687b ldr r3, [r7, #4] - 8002fd6: 68db ldr r3, [r3, #12] - 8002fd8: 2b00 cmp r3, #0 - 8002fda: d108 bne.n 8002fee - 8002fdc: 687b ldr r3, [r7, #4] - 8002fde: 691b ldr r3, [r3, #16] - 8002fe0: 2b00 cmp r3, #0 - 8002fe2: d104 bne.n 8002fee + 8006530: 687b ldr r3, [r7, #4] + 8006532: 689b ldr r3, [r3, #8] + 8006534: 2b00 cmp r3, #0 + 8006536: d10c bne.n 8006552 + 8006538: 687b ldr r3, [r7, #4] + 800653a: 68db ldr r3, [r3, #12] + 800653c: 2b00 cmp r3, #0 + 800653e: d108 bne.n 8006552 + 8006540: 687b ldr r3, [r7, #4] + 8006542: 691b ldr r3, [r3, #16] + 8006544: 2b00 cmp r3, #0 + 8006546: d104 bne.n 8006552 mem = 0; - 8002fe4: 2300 movs r3, #0 - 8002fe6: 61bb str r3, [r7, #24] - 8002fe8: e001 b.n 8002fee + 8006548: 2300 movs r3, #0 + 800654a: 61bb str r3, [r7, #24] + 800654c: e001 b.n 8006552 } } } else { mem = 0; - 8002fea: 2300 movs r3, #0 - 8002fec: 61bb str r3, [r7, #24] + 800654e: 2300 movs r3, #0 + 8006550: 61bb str r3, [r7, #24] } if (mem == 1) { - 8002fee: 69bb ldr r3, [r7, #24] - 8002ff0: 2b01 cmp r3, #1 - 8002ff2: d110 bne.n 8003016 + 8006552: 69bb ldr r3, [r7, #24] + 8006554: 2b01 cmp r3, #1 + 8006556: d110 bne.n 800657a #if (configSUPPORT_STATIC_ALLOCATION == 1) hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, - 8002ff4: 687b ldr r3, [r7, #4] - 8002ff6: 691b ldr r3, [r3, #16] + 8006558: 687b ldr r3, [r7, #4] + 800655a: 691b ldr r3, [r3, #16] (StaticTask_t *)attr->cb_mem); - 8002ff8: 687a ldr r2, [r7, #4] - 8002ffa: 6892 ldr r2, [r2, #8] + 800655c: 687a ldr r2, [r7, #4] + 800655e: 6892 ldr r2, [r2, #8] hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, - 8002ffc: 9202 str r2, [sp, #8] - 8002ffe: 9301 str r3, [sp, #4] - 8003000: 69fb ldr r3, [r7, #28] - 8003002: 9300 str r3, [sp, #0] - 8003004: 68bb ldr r3, [r7, #8] - 8003006: 6a3a ldr r2, [r7, #32] - 8003008: 6a79 ldr r1, [r7, #36] @ 0x24 - 800300a: 68f8 ldr r0, [r7, #12] - 800300c: f000 fe1a bl 8003c44 - 8003010: 4603 mov r3, r0 - 8003012: 613b str r3, [r7, #16] - 8003014: e013 b.n 800303e + 8006560: 9202 str r2, [sp, #8] + 8006562: 9301 str r3, [sp, #4] + 8006564: 69fb ldr r3, [r7, #28] + 8006566: 9300 str r3, [sp, #0] + 8006568: 68bb ldr r3, [r7, #8] + 800656a: 6a3a ldr r2, [r7, #32] + 800656c: 6a79 ldr r1, [r7, #36] @ 0x24 + 800656e: 68f8 ldr r0, [r7, #12] + 8006570: f001 fc42 bl 8007df8 + 8006574: 4603 mov r3, r0 + 8006576: 613b str r3, [r7, #16] + 8006578: e013 b.n 80065a2 #endif } else { if (mem == 0) { - 8003016: 69bb ldr r3, [r7, #24] - 8003018: 2b00 cmp r3, #0 - 800301a: d110 bne.n 800303e + 800657a: 69bb ldr r3, [r7, #24] + 800657c: 2b00 cmp r3, #0 + 800657e: d110 bne.n 80065a2 #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) { - 800301c: 6a3b ldr r3, [r7, #32] - 800301e: b29a uxth r2, r3 - 8003020: f107 0310 add.w r3, r7, #16 - 8003024: 9301 str r3, [sp, #4] - 8003026: 69fb ldr r3, [r7, #28] - 8003028: 9300 str r3, [sp, #0] - 800302a: 68bb ldr r3, [r7, #8] - 800302c: 6a79 ldr r1, [r7, #36] @ 0x24 - 800302e: 68f8 ldr r0, [r7, #12] - 8003030: f000 fe68 bl 8003d04 - 8003034: 4603 mov r3, r0 - 8003036: 2b01 cmp r3, #1 - 8003038: d001 beq.n 800303e + 8006580: 6a3b ldr r3, [r7, #32] + 8006582: b29a uxth r2, r3 + 8006584: f107 0310 add.w r3, r7, #16 + 8006588: 9301 str r3, [sp, #4] + 800658a: 69fb ldr r3, [r7, #28] + 800658c: 9300 str r3, [sp, #0] + 800658e: 68bb ldr r3, [r7, #8] + 8006590: 6a79 ldr r1, [r7, #36] @ 0x24 + 8006592: 68f8 ldr r0, [r7, #12] + 8006594: f001 fc90 bl 8007eb8 + 8006598: 4603 mov r3, r0 + 800659a: 2b01 cmp r3, #1 + 800659c: d001 beq.n 80065a2 hTask = NULL; - 800303a: 2300 movs r3, #0 - 800303c: 613b str r3, [r7, #16] + 800659e: 2300 movs r3, #0 + 80065a0: 613b str r3, [r7, #16] #endif } } } return ((osThreadId_t)hTask); - 800303e: 693b ldr r3, [r7, #16] + 80065a2: 693b ldr r3, [r7, #16] } - 8003040: 4618 mov r0, r3 - 8003042: 3728 adds r7, #40 @ 0x28 - 8003044: 46bd mov sp, r7 - 8003046: bd80 pop {r7, pc} + 80065a4: 4618 mov r0, r3 + 80065a6: 3728 adds r7, #40 @ 0x28 + 80065a8: 46bd mov sp, r7 + 80065aa: bd80 pop {r7, pc} -08003048 : - /* Return flags before clearing */ - return (rflags); +080065ac : } -#endif /* (configUSE_OS2_THREAD_FLAGS == 1) */ -osStatus_t osDelay (uint32_t ticks) { - 8003048: b580 push {r7, lr} - 800304a: b084 sub sp, #16 - 800304c: af00 add r7, sp, #0 - 800304e: 6078 str r0, [r7, #4] +/*---------------------------------------------------------------------------*/ +#if (configUSE_OS2_TIMER == 1) + +static void TimerCallback (TimerHandle_t hTimer) { + 80065ac: b580 push {r7, lr} + 80065ae: b084 sub sp, #16 + 80065b0: af00 add r7, sp, #0 + 80065b2: 6078 str r0, [r7, #4] + TimerCallback_t *callb; + + callb = (TimerCallback_t *)pvTimerGetTimerID (hTimer); + 80065b4: 6878 ldr r0, [r7, #4] + 80065b6: f003 f81b bl 80095f0 + 80065ba: 60f8 str r0, [r7, #12] + + if (callb != NULL) { + 80065bc: 68fb ldr r3, [r7, #12] + 80065be: 2b00 cmp r3, #0 + 80065c0: d005 beq.n 80065ce + callb->func (callb->arg); + 80065c2: 68fb ldr r3, [r7, #12] + 80065c4: 681b ldr r3, [r3, #0] + 80065c6: 68fa ldr r2, [r7, #12] + 80065c8: 6852 ldr r2, [r2, #4] + 80065ca: 4610 mov r0, r2 + 80065cc: 4798 blx r3 + } +} + 80065ce: bf00 nop + 80065d0: 3710 adds r7, #16 + 80065d2: 46bd mov sp, r7 + 80065d4: bd80 pop {r7, pc} + ... + +080065d8 : + +osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) { + 80065d8: b580 push {r7, lr} + 80065da: b08c sub sp, #48 @ 0x30 + 80065dc: af02 add r7, sp, #8 + 80065de: 60f8 str r0, [r7, #12] + 80065e0: 607a str r2, [r7, #4] + 80065e2: 603b str r3, [r7, #0] + 80065e4: 460b mov r3, r1 + 80065e6: 72fb strb r3, [r7, #11] + TimerHandle_t hTimer; + TimerCallback_t *callb; + UBaseType_t reload; + int32_t mem; + + hTimer = NULL; + 80065e8: 2300 movs r3, #0 + 80065ea: 623b str r3, [r7, #32] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - 8003050: f3ef 8305 mrs r3, IPSR - 8003054: 60bb str r3, [r7, #8] + 80065ec: f3ef 8305 mrs r3, IPSR + 80065f0: 613b str r3, [r7, #16] return(result); - 8003056: 68bb ldr r3, [r7, #8] + 80065f2: 693b ldr r3, [r7, #16] + + if (!IS_IRQ() && (func != NULL)) { + 80065f4: 2b00 cmp r3, #0 + 80065f6: d163 bne.n 80066c0 + 80065f8: 68fb ldr r3, [r7, #12] + 80065fa: 2b00 cmp r3, #0 + 80065fc: d060 beq.n 80066c0 + /* Allocate memory to store callback function and argument */ + callb = pvPortMalloc (sizeof(TimerCallback_t)); + 80065fe: 2008 movs r0, #8 + 8006600: f003 fa6c bl 8009adc + 8006604: 6178 str r0, [r7, #20] + + if (callb != NULL) { + 8006606: 697b ldr r3, [r7, #20] + 8006608: 2b00 cmp r3, #0 + 800660a: d059 beq.n 80066c0 + callb->func = func; + 800660c: 697b ldr r3, [r7, #20] + 800660e: 68fa ldr r2, [r7, #12] + 8006610: 601a str r2, [r3, #0] + callb->arg = argument; + 8006612: 697b ldr r3, [r7, #20] + 8006614: 687a ldr r2, [r7, #4] + 8006616: 605a str r2, [r3, #4] + + if (type == osTimerOnce) { + 8006618: 7afb ldrb r3, [r7, #11] + 800661a: 2b00 cmp r3, #0 + 800661c: d102 bne.n 8006624 + reload = pdFALSE; + 800661e: 2300 movs r3, #0 + 8006620: 61fb str r3, [r7, #28] + 8006622: e001 b.n 8006628 + } else { + reload = pdTRUE; + 8006624: 2301 movs r3, #1 + 8006626: 61fb str r3, [r7, #28] + } + + mem = -1; + 8006628: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800662c: 61bb str r3, [r7, #24] + name = NULL; + 800662e: 2300 movs r3, #0 + 8006630: 627b str r3, [r7, #36] @ 0x24 + + if (attr != NULL) { + 8006632: 683b ldr r3, [r7, #0] + 8006634: 2b00 cmp r3, #0 + 8006636: d01c beq.n 8006672 + if (attr->name != NULL) { + 8006638: 683b ldr r3, [r7, #0] + 800663a: 681b ldr r3, [r3, #0] + 800663c: 2b00 cmp r3, #0 + 800663e: d002 beq.n 8006646 + name = attr->name; + 8006640: 683b ldr r3, [r7, #0] + 8006642: 681b ldr r3, [r3, #0] + 8006644: 627b str r3, [r7, #36] @ 0x24 + } + + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTimer_t))) { + 8006646: 683b ldr r3, [r7, #0] + 8006648: 689b ldr r3, [r3, #8] + 800664a: 2b00 cmp r3, #0 + 800664c: d006 beq.n 800665c + 800664e: 683b ldr r3, [r7, #0] + 8006650: 68db ldr r3, [r3, #12] + 8006652: 2b2b cmp r3, #43 @ 0x2b + 8006654: d902 bls.n 800665c + mem = 1; + 8006656: 2301 movs r3, #1 + 8006658: 61bb str r3, [r7, #24] + 800665a: e00c b.n 8006676 + } + else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { + 800665c: 683b ldr r3, [r7, #0] + 800665e: 689b ldr r3, [r3, #8] + 8006660: 2b00 cmp r3, #0 + 8006662: d108 bne.n 8006676 + 8006664: 683b ldr r3, [r7, #0] + 8006666: 68db ldr r3, [r3, #12] + 8006668: 2b00 cmp r3, #0 + 800666a: d104 bne.n 8006676 + mem = 0; + 800666c: 2300 movs r3, #0 + 800666e: 61bb str r3, [r7, #24] + 8006670: e001 b.n 8006676 + } + } + } + else { + mem = 0; + 8006672: 2300 movs r3, #0 + 8006674: 61bb str r3, [r7, #24] + } + + if (mem == 1) { + 8006676: 69bb ldr r3, [r7, #24] + 8006678: 2b01 cmp r3, #1 + 800667a: d10c bne.n 8006696 + #if (configSUPPORT_STATIC_ALLOCATION == 1) + hTimer = xTimerCreateStatic (name, 1, reload, callb, TimerCallback, (StaticTimer_t *)attr->cb_mem); + 800667c: 683b ldr r3, [r7, #0] + 800667e: 689b ldr r3, [r3, #8] + 8006680: 9301 str r3, [sp, #4] + 8006682: 4b12 ldr r3, [pc, #72] @ (80066cc ) + 8006684: 9300 str r3, [sp, #0] + 8006686: 697b ldr r3, [r7, #20] + 8006688: 69fa ldr r2, [r7, #28] + 800668a: 2101 movs r1, #1 + 800668c: 6a78 ldr r0, [r7, #36] @ 0x24 + 800668e: f002 fc22 bl 8008ed6 + 8006692: 6238 str r0, [r7, #32] + 8006694: e00b b.n 80066ae + #endif + } + else { + if (mem == 0) { + 8006696: 69bb ldr r3, [r7, #24] + 8006698: 2b00 cmp r3, #0 + 800669a: d108 bne.n 80066ae + #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + hTimer = xTimerCreate (name, 1, reload, callb, TimerCallback); + 800669c: 4b0b ldr r3, [pc, #44] @ (80066cc ) + 800669e: 9300 str r3, [sp, #0] + 80066a0: 697b ldr r3, [r7, #20] + 80066a2: 69fa ldr r2, [r7, #28] + 80066a4: 2101 movs r1, #1 + 80066a6: 6a78 ldr r0, [r7, #36] @ 0x24 + 80066a8: f002 fbf4 bl 8008e94 + 80066ac: 6238 str r0, [r7, #32] + #endif + } + } + + if ((hTimer == NULL) && (callb != NULL)) { + 80066ae: 6a3b ldr r3, [r7, #32] + 80066b0: 2b00 cmp r3, #0 + 80066b2: d105 bne.n 80066c0 + 80066b4: 697b ldr r3, [r7, #20] + 80066b6: 2b00 cmp r3, #0 + 80066b8: d002 beq.n 80066c0 + vPortFree (callb); + 80066ba: 6978 ldr r0, [r7, #20] + 80066bc: f003 fadc bl 8009c78 + } + } + } + + return ((osTimerId_t)hTimer); + 80066c0: 6a3b ldr r3, [r7, #32] +} + 80066c2: 4618 mov r0, r3 + 80066c4: 3728 adds r7, #40 @ 0x28 + 80066c6: 46bd mov sp, r7 + 80066c8: bd80 pop {r7, pc} + 80066ca: bf00 nop + 80066cc: 080065ad .word 0x080065ad + +080066d0 : + } + + return (p); +} + +osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks) { + 80066d0: b580 push {r7, lr} + 80066d2: b088 sub sp, #32 + 80066d4: af02 add r7, sp, #8 + 80066d6: 6078 str r0, [r7, #4] + 80066d8: 6039 str r1, [r7, #0] + TimerHandle_t hTimer = (TimerHandle_t)timer_id; + 80066da: 687b ldr r3, [r7, #4] + 80066dc: 613b str r3, [r7, #16] + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 80066de: f3ef 8305 mrs r3, IPSR + 80066e2: 60fb str r3, [r7, #12] + return(result); + 80066e4: 68fb ldr r3, [r7, #12] osStatus_t stat; if (IS_IRQ()) { - 8003058: 2b00 cmp r3, #0 - 800305a: d003 beq.n 8003064 + 80066e6: 2b00 cmp r3, #0 + 80066e8: d003 beq.n 80066f2 stat = osErrorISR; - 800305c: f06f 0305 mvn.w r3, #5 - 8003060: 60fb str r3, [r7, #12] - 8003062: e007 b.n 8003074 + 80066ea: f06f 0305 mvn.w r3, #5 + 80066ee: 617b str r3, [r7, #20] + 80066f0: e017 b.n 8006722 + } + else if (hTimer == NULL) { + 80066f2: 693b ldr r3, [r7, #16] + 80066f4: 2b00 cmp r3, #0 + 80066f6: d103 bne.n 8006700 + stat = osErrorParameter; + 80066f8: f06f 0303 mvn.w r3, #3 + 80066fc: 617b str r3, [r7, #20] + 80066fe: e010 b.n 8006722 } else { - stat = osOK; - 8003064: 2300 movs r3, #0 - 8003066: 60fb str r3, [r7, #12] - - if (ticks != 0U) { - 8003068: 687b ldr r3, [r7, #4] - 800306a: 2b00 cmp r3, #0 - 800306c: d002 beq.n 8003074 - vTaskDelay(ticks); - 800306e: 6878 ldr r0, [r7, #4] - 8003070: f000 ffa6 bl 8003fc0 + if (xTimerChangePeriod (hTimer, ticks, 0) == pdPASS) { + 8006700: 2300 movs r3, #0 + 8006702: 9300 str r3, [sp, #0] + 8006704: 2300 movs r3, #0 + 8006706: 683a ldr r2, [r7, #0] + 8006708: 2104 movs r1, #4 + 800670a: 6938 ldr r0, [r7, #16] + 800670c: f002 fc60 bl 8008fd0 + 8006710: 4603 mov r3, r0 + 8006712: 2b01 cmp r3, #1 + 8006714: d102 bne.n 800671c + stat = osOK; + 8006716: 2300 movs r3, #0 + 8006718: 617b str r3, [r7, #20] + 800671a: e002 b.n 8006722 + } else { + stat = osErrorResource; + 800671c: f06f 0302 mvn.w r3, #2 + 8006720: 617b str r3, [r7, #20] } } return (stat); - 8003074: 68fb ldr r3, [r7, #12] + 8006722: 697b ldr r3, [r7, #20] } - 8003076: 4618 mov r0, r3 - 8003078: 3710 adds r7, #16 - 800307a: 46bd mov sp, r7 - 800307c: bd80 pop {r7, pc} + 8006724: 4618 mov r0, r3 + 8006726: 3718 adds r7, #24 + 8006728: 46bd mov sp, r7 + 800672a: bd80 pop {r7, pc} + +0800672c : +} +#endif /* (configUSE_OS2_MUTEX == 1) */ + +/*---------------------------------------------------------------------------*/ + +osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) { + 800672c: b580 push {r7, lr} + 800672e: b08a sub sp, #40 @ 0x28 + 8006730: af02 add r7, sp, #8 + 8006732: 60f8 str r0, [r7, #12] + 8006734: 60b9 str r1, [r7, #8] + 8006736: 607a str r2, [r7, #4] + int32_t mem; + #if (configQUEUE_REGISTRY_SIZE > 0) + const char *name; + #endif + + hSemaphore = NULL; + 8006738: 2300 movs r3, #0 + 800673a: 61fb str r3, [r7, #28] + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 800673c: f3ef 8305 mrs r3, IPSR + 8006740: 613b str r3, [r7, #16] + return(result); + 8006742: 693b ldr r3, [r7, #16] + + if (!IS_IRQ() && (max_count > 0U) && (initial_count <= max_count)) { + 8006744: 2b00 cmp r3, #0 + 8006746: d175 bne.n 8006834 + 8006748: 68fb ldr r3, [r7, #12] + 800674a: 2b00 cmp r3, #0 + 800674c: d072 beq.n 8006834 + 800674e: 68ba ldr r2, [r7, #8] + 8006750: 68fb ldr r3, [r7, #12] + 8006752: 429a cmp r2, r3 + 8006754: d86e bhi.n 8006834 + mem = -1; + 8006756: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800675a: 61bb str r3, [r7, #24] + + if (attr != NULL) { + 800675c: 687b ldr r3, [r7, #4] + 800675e: 2b00 cmp r3, #0 + 8006760: d015 beq.n 800678e + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) { + 8006762: 687b ldr r3, [r7, #4] + 8006764: 689b ldr r3, [r3, #8] + 8006766: 2b00 cmp r3, #0 + 8006768: d006 beq.n 8006778 + 800676a: 687b ldr r3, [r7, #4] + 800676c: 68db ldr r3, [r3, #12] + 800676e: 2b4f cmp r3, #79 @ 0x4f + 8006770: d902 bls.n 8006778 + mem = 1; + 8006772: 2301 movs r3, #1 + 8006774: 61bb str r3, [r7, #24] + 8006776: e00c b.n 8006792 + } + else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { + 8006778: 687b ldr r3, [r7, #4] + 800677a: 689b ldr r3, [r3, #8] + 800677c: 2b00 cmp r3, #0 + 800677e: d108 bne.n 8006792 + 8006780: 687b ldr r3, [r7, #4] + 8006782: 68db ldr r3, [r3, #12] + 8006784: 2b00 cmp r3, #0 + 8006786: d104 bne.n 8006792 + mem = 0; + 8006788: 2300 movs r3, #0 + 800678a: 61bb str r3, [r7, #24] + 800678c: e001 b.n 8006792 + } + } + } + else { + mem = 0; + 800678e: 2300 movs r3, #0 + 8006790: 61bb str r3, [r7, #24] + } + + if (mem != -1) { + 8006792: 69bb ldr r3, [r7, #24] + 8006794: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8006798: d04c beq.n 8006834 + if (max_count == 1U) { + 800679a: 68fb ldr r3, [r7, #12] + 800679c: 2b01 cmp r3, #1 + 800679e: d128 bne.n 80067f2 + if (mem == 1) { + 80067a0: 69bb ldr r3, [r7, #24] + 80067a2: 2b01 cmp r3, #1 + 80067a4: d10a bne.n 80067bc + #if (configSUPPORT_STATIC_ALLOCATION == 1) + hSemaphore = xSemaphoreCreateBinaryStatic ((StaticSemaphore_t *)attr->cb_mem); + 80067a6: 687b ldr r3, [r7, #4] + 80067a8: 689b ldr r3, [r3, #8] + 80067aa: 2203 movs r2, #3 + 80067ac: 9200 str r2, [sp, #0] + 80067ae: 2200 movs r2, #0 + 80067b0: 2100 movs r1, #0 + 80067b2: 2001 movs r0, #1 + 80067b4: f000 fb5e bl 8006e74 + 80067b8: 61f8 str r0, [r7, #28] + 80067ba: e005 b.n 80067c8 + #endif + } + else { + #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + hSemaphore = xSemaphoreCreateBinary(); + 80067bc: 2203 movs r2, #3 + 80067be: 2100 movs r1, #0 + 80067c0: 2001 movs r0, #1 + 80067c2: f000 fbd4 bl 8006f6e + 80067c6: 61f8 str r0, [r7, #28] + #endif + } + + if ((hSemaphore != NULL) && (initial_count != 0U)) { + 80067c8: 69fb ldr r3, [r7, #28] + 80067ca: 2b00 cmp r3, #0 + 80067cc: d022 beq.n 8006814 + 80067ce: 68bb ldr r3, [r7, #8] + 80067d0: 2b00 cmp r3, #0 + 80067d2: d01f beq.n 8006814 + if (xSemaphoreGive (hSemaphore) != pdPASS) { + 80067d4: 2300 movs r3, #0 + 80067d6: 2200 movs r2, #0 + 80067d8: 2100 movs r1, #0 + 80067da: 69f8 ldr r0, [r7, #28] + 80067dc: f000 fc94 bl 8007108 + 80067e0: 4603 mov r3, r0 + 80067e2: 2b01 cmp r3, #1 + 80067e4: d016 beq.n 8006814 + vSemaphoreDelete (hSemaphore); + 80067e6: 69f8 ldr r0, [r7, #28] + 80067e8: f001 f932 bl 8007a50 + hSemaphore = NULL; + 80067ec: 2300 movs r3, #0 + 80067ee: 61fb str r3, [r7, #28] + 80067f0: e010 b.n 8006814 + } + } + } + else { + if (mem == 1) { + 80067f2: 69bb ldr r3, [r7, #24] + 80067f4: 2b01 cmp r3, #1 + 80067f6: d108 bne.n 800680a + #if (configSUPPORT_STATIC_ALLOCATION == 1) + hSemaphore = xSemaphoreCreateCountingStatic (max_count, initial_count, (StaticSemaphore_t *)attr->cb_mem); + 80067f8: 687b ldr r3, [r7, #4] + 80067fa: 689b ldr r3, [r3, #8] + 80067fc: 461a mov r2, r3 + 80067fe: 68b9 ldr r1, [r7, #8] + 8006800: 68f8 ldr r0, [r7, #12] + 8006802: f000 fc12 bl 800702a + 8006806: 61f8 str r0, [r7, #28] + 8006808: e004 b.n 8006814 + #endif + } + else { + #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + hSemaphore = xSemaphoreCreateCounting (max_count, initial_count); + 800680a: 68b9 ldr r1, [r7, #8] + 800680c: 68f8 ldr r0, [r7, #12] + 800680e: f000 fc45 bl 800709c + 8006812: 61f8 str r0, [r7, #28] + #endif + } + } + + #if (configQUEUE_REGISTRY_SIZE > 0) + if (hSemaphore != NULL) { + 8006814: 69fb ldr r3, [r7, #28] + 8006816: 2b00 cmp r3, #0 + 8006818: d00c beq.n 8006834 + if (attr != NULL) { + 800681a: 687b ldr r3, [r7, #4] + 800681c: 2b00 cmp r3, #0 + 800681e: d003 beq.n 8006828 + name = attr->name; + 8006820: 687b ldr r3, [r7, #4] + 8006822: 681b ldr r3, [r3, #0] + 8006824: 617b str r3, [r7, #20] + 8006826: e001 b.n 800682c + } else { + name = NULL; + 8006828: 2300 movs r3, #0 + 800682a: 617b str r3, [r7, #20] + } + vQueueAddToRegistry (hSemaphore, name); + 800682c: 6979 ldr r1, [r7, #20] + 800682e: 69f8 ldr r0, [r7, #28] + 8006830: f001 fa5a bl 8007ce8 + } + #endif + } + } + + return ((osSemaphoreId_t)hSemaphore); + 8006834: 69fb ldr r3, [r7, #28] +} + 8006836: 4618 mov r0, r3 + 8006838: 3720 adds r7, #32 + 800683a: 46bd mov sp, r7 + 800683c: bd80 pop {r7, pc} ... -08003080 : +08006840 : + +osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) { + 8006840: b580 push {r7, lr} + 8006842: b086 sub sp, #24 + 8006844: af00 add r7, sp, #0 + 8006846: 6078 str r0, [r7, #4] + 8006848: 6039 str r1, [r7, #0] + SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id; + 800684a: 687b ldr r3, [r7, #4] + 800684c: 613b str r3, [r7, #16] + osStatus_t stat; + BaseType_t yield; + + stat = osOK; + 800684e: 2300 movs r3, #0 + 8006850: 617b str r3, [r7, #20] + + if (hSemaphore == NULL) { + 8006852: 693b ldr r3, [r7, #16] + 8006854: 2b00 cmp r3, #0 + 8006856: d103 bne.n 8006860 + stat = osErrorParameter; + 8006858: f06f 0303 mvn.w r3, #3 + 800685c: 617b str r3, [r7, #20] + 800685e: e039 b.n 80068d4 + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 8006860: f3ef 8305 mrs r3, IPSR + 8006864: 60fb str r3, [r7, #12] + return(result); + 8006866: 68fb ldr r3, [r7, #12] + } + else if (IS_IRQ()) { + 8006868: 2b00 cmp r3, #0 + 800686a: d022 beq.n 80068b2 + if (timeout != 0U) { + 800686c: 683b ldr r3, [r7, #0] + 800686e: 2b00 cmp r3, #0 + 8006870: d003 beq.n 800687a + stat = osErrorParameter; + 8006872: f06f 0303 mvn.w r3, #3 + 8006876: 617b str r3, [r7, #20] + 8006878: e02c b.n 80068d4 + } + else { + yield = pdFALSE; + 800687a: 2300 movs r3, #0 + 800687c: 60bb str r3, [r7, #8] + + if (xSemaphoreTakeFromISR (hSemaphore, &yield) != pdPASS) { + 800687e: f107 0308 add.w r3, r7, #8 + 8006882: 461a mov r2, r3 + 8006884: 2100 movs r1, #0 + 8006886: 6938 ldr r0, [r7, #16] + 8006888: f001 f860 bl 800794c + 800688c: 4603 mov r3, r0 + 800688e: 2b01 cmp r3, #1 + 8006890: d003 beq.n 800689a + stat = osErrorResource; + 8006892: f06f 0302 mvn.w r3, #2 + 8006896: 617b str r3, [r7, #20] + 8006898: e01c b.n 80068d4 + } else { + portYIELD_FROM_ISR (yield); + 800689a: 68bb ldr r3, [r7, #8] + 800689c: 2b00 cmp r3, #0 + 800689e: d019 beq.n 80068d4 + 80068a0: 4b0f ldr r3, [pc, #60] @ (80068e0 ) + 80068a2: f04f 5280 mov.w r2, #268435456 @ 0x10000000 + 80068a6: 601a str r2, [r3, #0] + 80068a8: f3bf 8f4f dsb sy + 80068ac: f3bf 8f6f isb sy + 80068b0: e010 b.n 80068d4 + } + } + } + else { + if (xSemaphoreTake (hSemaphore, (TickType_t)timeout) != pdPASS) { + 80068b2: 6839 ldr r1, [r7, #0] + 80068b4: 6938 ldr r0, [r7, #16] + 80068b6: f000 ff39 bl 800772c + 80068ba: 4603 mov r3, r0 + 80068bc: 2b01 cmp r3, #1 + 80068be: d009 beq.n 80068d4 + if (timeout != 0U) { + 80068c0: 683b ldr r3, [r7, #0] + 80068c2: 2b00 cmp r3, #0 + 80068c4: d003 beq.n 80068ce + stat = osErrorTimeout; + 80068c6: f06f 0301 mvn.w r3, #1 + 80068ca: 617b str r3, [r7, #20] + 80068cc: e002 b.n 80068d4 + } else { + stat = osErrorResource; + 80068ce: f06f 0302 mvn.w r3, #2 + 80068d2: 617b str r3, [r7, #20] + } + } + } + + return (stat); + 80068d4: 697b ldr r3, [r7, #20] +} + 80068d6: 4618 mov r0, r3 + 80068d8: 3718 adds r7, #24 + 80068da: 46bd mov sp, r7 + 80068dc: bd80 pop {r7, pc} + 80068de: bf00 nop + 80068e0: e000ed04 .word 0xe000ed04 + +080068e4 : + +osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id) { + 80068e4: b580 push {r7, lr} + 80068e6: b086 sub sp, #24 + 80068e8: af00 add r7, sp, #0 + 80068ea: 6078 str r0, [r7, #4] + SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id; + 80068ec: 687b ldr r3, [r7, #4] + 80068ee: 613b str r3, [r7, #16] + osStatus_t stat; + BaseType_t yield; + + stat = osOK; + 80068f0: 2300 movs r3, #0 + 80068f2: 617b str r3, [r7, #20] + + if (hSemaphore == NULL) { + 80068f4: 693b ldr r3, [r7, #16] + 80068f6: 2b00 cmp r3, #0 + 80068f8: d103 bne.n 8006902 + stat = osErrorParameter; + 80068fa: f06f 0303 mvn.w r3, #3 + 80068fe: 617b str r3, [r7, #20] + 8006900: e02c b.n 800695c + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 8006902: f3ef 8305 mrs r3, IPSR + 8006906: 60fb str r3, [r7, #12] + return(result); + 8006908: 68fb ldr r3, [r7, #12] + } + else if (IS_IRQ()) { + 800690a: 2b00 cmp r3, #0 + 800690c: d01a beq.n 8006944 + yield = pdFALSE; + 800690e: 2300 movs r3, #0 + 8006910: 60bb str r3, [r7, #8] + + if (xSemaphoreGiveFromISR (hSemaphore, &yield) != pdTRUE) { + 8006912: f107 0308 add.w r3, r7, #8 + 8006916: 4619 mov r1, r3 + 8006918: 6938 ldr r0, [r7, #16] + 800691a: f000 fd95 bl 8007448 + 800691e: 4603 mov r3, r0 + 8006920: 2b01 cmp r3, #1 + 8006922: d003 beq.n 800692c + stat = osErrorResource; + 8006924: f06f 0302 mvn.w r3, #2 + 8006928: 617b str r3, [r7, #20] + 800692a: e017 b.n 800695c + } else { + portYIELD_FROM_ISR (yield); + 800692c: 68bb ldr r3, [r7, #8] + 800692e: 2b00 cmp r3, #0 + 8006930: d014 beq.n 800695c + 8006932: 4b0d ldr r3, [pc, #52] @ (8006968 ) + 8006934: f04f 5280 mov.w r2, #268435456 @ 0x10000000 + 8006938: 601a str r2, [r3, #0] + 800693a: f3bf 8f4f dsb sy + 800693e: f3bf 8f6f isb sy + 8006942: e00b b.n 800695c + } + } + else { + if (xSemaphoreGive (hSemaphore) != pdPASS) { + 8006944: 2300 movs r3, #0 + 8006946: 2200 movs r2, #0 + 8006948: 2100 movs r1, #0 + 800694a: 6938 ldr r0, [r7, #16] + 800694c: f000 fbdc bl 8007108 + 8006950: 4603 mov r3, r0 + 8006952: 2b01 cmp r3, #1 + 8006954: d002 beq.n 800695c + stat = osErrorResource; + 8006956: f06f 0302 mvn.w r3, #2 + 800695a: 617b str r3, [r7, #20] + } + } + + return (stat); + 800695c: 697b ldr r3, [r7, #20] +} + 800695e: 4618 mov r0, r3 + 8006960: 3718 adds r7, #24 + 8006962: 46bd mov sp, r7 + 8006964: bd80 pop {r7, pc} + 8006966: bf00 nop + 8006968: e000ed04 .word 0xe000ed04 + +0800696c : + return (stat); +} + +/*---------------------------------------------------------------------------*/ + +osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) { + 800696c: b580 push {r7, lr} + 800696e: b08a sub sp, #40 @ 0x28 + 8006970: af02 add r7, sp, #8 + 8006972: 60f8 str r0, [r7, #12] + 8006974: 60b9 str r1, [r7, #8] + 8006976: 607a str r2, [r7, #4] + int32_t mem; + #if (configQUEUE_REGISTRY_SIZE > 0) + const char *name; + #endif + + hQueue = NULL; + 8006978: 2300 movs r3, #0 + 800697a: 61fb str r3, [r7, #28] + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 800697c: f3ef 8305 mrs r3, IPSR + 8006980: 613b str r3, [r7, #16] + return(result); + 8006982: 693b ldr r3, [r7, #16] + + if (!IS_IRQ() && (msg_count > 0U) && (msg_size > 0U)) { + 8006984: 2b00 cmp r3, #0 + 8006986: d15f bne.n 8006a48 + 8006988: 68fb ldr r3, [r7, #12] + 800698a: 2b00 cmp r3, #0 + 800698c: d05c beq.n 8006a48 + 800698e: 68bb ldr r3, [r7, #8] + 8006990: 2b00 cmp r3, #0 + 8006992: d059 beq.n 8006a48 + mem = -1; + 8006994: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 8006998: 61bb str r3, [r7, #24] + + if (attr != NULL) { + 800699a: 687b ldr r3, [r7, #4] + 800699c: 2b00 cmp r3, #0 + 800699e: d029 beq.n 80069f4 + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) && + 80069a0: 687b ldr r3, [r7, #4] + 80069a2: 689b ldr r3, [r3, #8] + 80069a4: 2b00 cmp r3, #0 + 80069a6: d012 beq.n 80069ce + 80069a8: 687b ldr r3, [r7, #4] + 80069aa: 68db ldr r3, [r3, #12] + 80069ac: 2b4f cmp r3, #79 @ 0x4f + 80069ae: d90e bls.n 80069ce + (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) { + 80069b0: 687b ldr r3, [r7, #4] + 80069b2: 691b ldr r3, [r3, #16] + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) && + 80069b4: 2b00 cmp r3, #0 + 80069b6: d00a beq.n 80069ce + (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) { + 80069b8: 687b ldr r3, [r7, #4] + 80069ba: 695a ldr r2, [r3, #20] + 80069bc: 68fb ldr r3, [r7, #12] + 80069be: 68b9 ldr r1, [r7, #8] + 80069c0: fb01 f303 mul.w r3, r1, r3 + 80069c4: 429a cmp r2, r3 + 80069c6: d302 bcc.n 80069ce + mem = 1; + 80069c8: 2301 movs r3, #1 + 80069ca: 61bb str r3, [r7, #24] + 80069cc: e014 b.n 80069f8 + } + else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && + 80069ce: 687b ldr r3, [r7, #4] + 80069d0: 689b ldr r3, [r3, #8] + 80069d2: 2b00 cmp r3, #0 + 80069d4: d110 bne.n 80069f8 + 80069d6: 687b ldr r3, [r7, #4] + 80069d8: 68db ldr r3, [r3, #12] + 80069da: 2b00 cmp r3, #0 + 80069dc: d10c bne.n 80069f8 + (attr->mq_mem == NULL) && (attr->mq_size == 0U)) { + 80069de: 687b ldr r3, [r7, #4] + 80069e0: 691b ldr r3, [r3, #16] + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && + 80069e2: 2b00 cmp r3, #0 + 80069e4: d108 bne.n 80069f8 + (attr->mq_mem == NULL) && (attr->mq_size == 0U)) { + 80069e6: 687b ldr r3, [r7, #4] + 80069e8: 695b ldr r3, [r3, #20] + 80069ea: 2b00 cmp r3, #0 + 80069ec: d104 bne.n 80069f8 + mem = 0; + 80069ee: 2300 movs r3, #0 + 80069f0: 61bb str r3, [r7, #24] + 80069f2: e001 b.n 80069f8 + } + } + } + else { + mem = 0; + 80069f4: 2300 movs r3, #0 + 80069f6: 61bb str r3, [r7, #24] + } + + if (mem == 1) { + 80069f8: 69bb ldr r3, [r7, #24] + 80069fa: 2b01 cmp r3, #1 + 80069fc: d10b bne.n 8006a16 + #if (configSUPPORT_STATIC_ALLOCATION == 1) + hQueue = xQueueCreateStatic (msg_count, msg_size, attr->mq_mem, attr->cb_mem); + 80069fe: 687b ldr r3, [r7, #4] + 8006a00: 691a ldr r2, [r3, #16] + 8006a02: 687b ldr r3, [r7, #4] + 8006a04: 689b ldr r3, [r3, #8] + 8006a06: 2100 movs r1, #0 + 8006a08: 9100 str r1, [sp, #0] + 8006a0a: 68b9 ldr r1, [r7, #8] + 8006a0c: 68f8 ldr r0, [r7, #12] + 8006a0e: f000 fa31 bl 8006e74 + 8006a12: 61f8 str r0, [r7, #28] + 8006a14: e008 b.n 8006a28 + #endif + } + else { + if (mem == 0) { + 8006a16: 69bb ldr r3, [r7, #24] + 8006a18: 2b00 cmp r3, #0 + 8006a1a: d105 bne.n 8006a28 + #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + hQueue = xQueueCreate (msg_count, msg_size); + 8006a1c: 2200 movs r2, #0 + 8006a1e: 68b9 ldr r1, [r7, #8] + 8006a20: 68f8 ldr r0, [r7, #12] + 8006a22: f000 faa4 bl 8006f6e + 8006a26: 61f8 str r0, [r7, #28] + #endif + } + } + + #if (configQUEUE_REGISTRY_SIZE > 0) + if (hQueue != NULL) { + 8006a28: 69fb ldr r3, [r7, #28] + 8006a2a: 2b00 cmp r3, #0 + 8006a2c: d00c beq.n 8006a48 + if (attr != NULL) { + 8006a2e: 687b ldr r3, [r7, #4] + 8006a30: 2b00 cmp r3, #0 + 8006a32: d003 beq.n 8006a3c + name = attr->name; + 8006a34: 687b ldr r3, [r7, #4] + 8006a36: 681b ldr r3, [r3, #0] + 8006a38: 617b str r3, [r7, #20] + 8006a3a: e001 b.n 8006a40 + } else { + name = NULL; + 8006a3c: 2300 movs r3, #0 + 8006a3e: 617b str r3, [r7, #20] + } + vQueueAddToRegistry (hQueue, name); + 8006a40: 6979 ldr r1, [r7, #20] + 8006a42: 69f8 ldr r0, [r7, #28] + 8006a44: f001 f950 bl 8007ce8 + } + #endif + + } + + return ((osMessageQueueId_t)hQueue); + 8006a48: 69fb ldr r3, [r7, #28] +} + 8006a4a: 4618 mov r0, r3 + 8006a4c: 3720 adds r7, #32 + 8006a4e: 46bd mov sp, r7 + 8006a50: bd80 pop {r7, pc} + ... + +08006a54 : + +osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) { + 8006a54: b580 push {r7, lr} + 8006a56: b088 sub sp, #32 + 8006a58: af00 add r7, sp, #0 + 8006a5a: 60f8 str r0, [r7, #12] + 8006a5c: 60b9 str r1, [r7, #8] + 8006a5e: 603b str r3, [r7, #0] + 8006a60: 4613 mov r3, r2 + 8006a62: 71fb strb r3, [r7, #7] + QueueHandle_t hQueue = (QueueHandle_t)mq_id; + 8006a64: 68fb ldr r3, [r7, #12] + 8006a66: 61bb str r3, [r7, #24] + osStatus_t stat; + BaseType_t yield; + + (void)msg_prio; /* Message priority is ignored */ + + stat = osOK; + 8006a68: 2300 movs r3, #0 + 8006a6a: 61fb str r3, [r7, #28] + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 8006a6c: f3ef 8305 mrs r3, IPSR + 8006a70: 617b str r3, [r7, #20] + return(result); + 8006a72: 697b ldr r3, [r7, #20] + + if (IS_IRQ()) { + 8006a74: 2b00 cmp r3, #0 + 8006a76: d028 beq.n 8006aca + if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { + 8006a78: 69bb ldr r3, [r7, #24] + 8006a7a: 2b00 cmp r3, #0 + 8006a7c: d005 beq.n 8006a8a + 8006a7e: 68bb ldr r3, [r7, #8] + 8006a80: 2b00 cmp r3, #0 + 8006a82: d002 beq.n 8006a8a + 8006a84: 683b ldr r3, [r7, #0] + 8006a86: 2b00 cmp r3, #0 + 8006a88: d003 beq.n 8006a92 + stat = osErrorParameter; + 8006a8a: f06f 0303 mvn.w r3, #3 + 8006a8e: 61fb str r3, [r7, #28] + 8006a90: e038 b.n 8006b04 + } + else { + yield = pdFALSE; + 8006a92: 2300 movs r3, #0 + 8006a94: 613b str r3, [r7, #16] + + if (xQueueSendToBackFromISR (hQueue, msg_ptr, &yield) != pdTRUE) { + 8006a96: f107 0210 add.w r2, r7, #16 + 8006a9a: 2300 movs r3, #0 + 8006a9c: 68b9 ldr r1, [r7, #8] + 8006a9e: 69b8 ldr r0, [r7, #24] + 8006aa0: f000 fc34 bl 800730c + 8006aa4: 4603 mov r3, r0 + 8006aa6: 2b01 cmp r3, #1 + 8006aa8: d003 beq.n 8006ab2 + stat = osErrorResource; + 8006aaa: f06f 0302 mvn.w r3, #2 + 8006aae: 61fb str r3, [r7, #28] + 8006ab0: e028 b.n 8006b04 + } else { + portYIELD_FROM_ISR (yield); + 8006ab2: 693b ldr r3, [r7, #16] + 8006ab4: 2b00 cmp r3, #0 + 8006ab6: d025 beq.n 8006b04 + 8006ab8: 4b15 ldr r3, [pc, #84] @ (8006b10 ) + 8006aba: f04f 5280 mov.w r2, #268435456 @ 0x10000000 + 8006abe: 601a str r2, [r3, #0] + 8006ac0: f3bf 8f4f dsb sy + 8006ac4: f3bf 8f6f isb sy + 8006ac8: e01c b.n 8006b04 + } + } + } + else { + if ((hQueue == NULL) || (msg_ptr == NULL)) { + 8006aca: 69bb ldr r3, [r7, #24] + 8006acc: 2b00 cmp r3, #0 + 8006ace: d002 beq.n 8006ad6 + 8006ad0: 68bb ldr r3, [r7, #8] + 8006ad2: 2b00 cmp r3, #0 + 8006ad4: d103 bne.n 8006ade + stat = osErrorParameter; + 8006ad6: f06f 0303 mvn.w r3, #3 + 8006ada: 61fb str r3, [r7, #28] + 8006adc: e012 b.n 8006b04 + } + else { + if (xQueueSendToBack (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { + 8006ade: 2300 movs r3, #0 + 8006ae0: 683a ldr r2, [r7, #0] + 8006ae2: 68b9 ldr r1, [r7, #8] + 8006ae4: 69b8 ldr r0, [r7, #24] + 8006ae6: f000 fb0f bl 8007108 + 8006aea: 4603 mov r3, r0 + 8006aec: 2b01 cmp r3, #1 + 8006aee: d009 beq.n 8006b04 + if (timeout != 0U) { + 8006af0: 683b ldr r3, [r7, #0] + 8006af2: 2b00 cmp r3, #0 + 8006af4: d003 beq.n 8006afe + stat = osErrorTimeout; + 8006af6: f06f 0301 mvn.w r3, #1 + 8006afa: 61fb str r3, [r7, #28] + 8006afc: e002 b.n 8006b04 + } else { + stat = osErrorResource; + 8006afe: f06f 0302 mvn.w r3, #2 + 8006b02: 61fb str r3, [r7, #28] + } + } + } + } + + return (stat); + 8006b04: 69fb ldr r3, [r7, #28] +} + 8006b06: 4618 mov r0, r3 + 8006b08: 3720 adds r7, #32 + 8006b0a: 46bd mov sp, r7 + 8006b0c: bd80 pop {r7, pc} + 8006b0e: bf00 nop + 8006b10: e000ed04 .word 0xe000ed04 + +08006b14 : + +osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) { + 8006b14: b580 push {r7, lr} + 8006b16: b088 sub sp, #32 + 8006b18: af00 add r7, sp, #0 + 8006b1a: 60f8 str r0, [r7, #12] + 8006b1c: 60b9 str r1, [r7, #8] + 8006b1e: 607a str r2, [r7, #4] + 8006b20: 603b str r3, [r7, #0] + QueueHandle_t hQueue = (QueueHandle_t)mq_id; + 8006b22: 68fb ldr r3, [r7, #12] + 8006b24: 61bb str r3, [r7, #24] + osStatus_t stat; + BaseType_t yield; + + (void)msg_prio; /* Message priority is ignored */ + + stat = osOK; + 8006b26: 2300 movs r3, #0 + 8006b28: 61fb str r3, [r7, #28] + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 8006b2a: f3ef 8305 mrs r3, IPSR + 8006b2e: 617b str r3, [r7, #20] + return(result); + 8006b30: 697b ldr r3, [r7, #20] + + if (IS_IRQ()) { + 8006b32: 2b00 cmp r3, #0 + 8006b34: d028 beq.n 8006b88 + if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { + 8006b36: 69bb ldr r3, [r7, #24] + 8006b38: 2b00 cmp r3, #0 + 8006b3a: d005 beq.n 8006b48 + 8006b3c: 68bb ldr r3, [r7, #8] + 8006b3e: 2b00 cmp r3, #0 + 8006b40: d002 beq.n 8006b48 + 8006b42: 683b ldr r3, [r7, #0] + 8006b44: 2b00 cmp r3, #0 + 8006b46: d003 beq.n 8006b50 + stat = osErrorParameter; + 8006b48: f06f 0303 mvn.w r3, #3 + 8006b4c: 61fb str r3, [r7, #28] + 8006b4e: e037 b.n 8006bc0 + } + else { + yield = pdFALSE; + 8006b50: 2300 movs r3, #0 + 8006b52: 613b str r3, [r7, #16] + + if (xQueueReceiveFromISR (hQueue, msg_ptr, &yield) != pdPASS) { + 8006b54: f107 0310 add.w r3, r7, #16 + 8006b58: 461a mov r2, r3 + 8006b5a: 68b9 ldr r1, [r7, #8] + 8006b5c: 69b8 ldr r0, [r7, #24] + 8006b5e: f000 fef5 bl 800794c + 8006b62: 4603 mov r3, r0 + 8006b64: 2b01 cmp r3, #1 + 8006b66: d003 beq.n 8006b70 + stat = osErrorResource; + 8006b68: f06f 0302 mvn.w r3, #2 + 8006b6c: 61fb str r3, [r7, #28] + 8006b6e: e027 b.n 8006bc0 + } else { + portYIELD_FROM_ISR (yield); + 8006b70: 693b ldr r3, [r7, #16] + 8006b72: 2b00 cmp r3, #0 + 8006b74: d024 beq.n 8006bc0 + 8006b76: 4b15 ldr r3, [pc, #84] @ (8006bcc ) + 8006b78: f04f 5280 mov.w r2, #268435456 @ 0x10000000 + 8006b7c: 601a str r2, [r3, #0] + 8006b7e: f3bf 8f4f dsb sy + 8006b82: f3bf 8f6f isb sy + 8006b86: e01b b.n 8006bc0 + } + } + } + else { + if ((hQueue == NULL) || (msg_ptr == NULL)) { + 8006b88: 69bb ldr r3, [r7, #24] + 8006b8a: 2b00 cmp r3, #0 + 8006b8c: d002 beq.n 8006b94 + 8006b8e: 68bb ldr r3, [r7, #8] + 8006b90: 2b00 cmp r3, #0 + 8006b92: d103 bne.n 8006b9c + stat = osErrorParameter; + 8006b94: f06f 0303 mvn.w r3, #3 + 8006b98: 61fb str r3, [r7, #28] + 8006b9a: e011 b.n 8006bc0 + } + else { + if (xQueueReceive (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { + 8006b9c: 683a ldr r2, [r7, #0] + 8006b9e: 68b9 ldr r1, [r7, #8] + 8006ba0: 69b8 ldr r0, [r7, #24] + 8006ba2: f000 fce1 bl 8007568 + 8006ba6: 4603 mov r3, r0 + 8006ba8: 2b01 cmp r3, #1 + 8006baa: d009 beq.n 8006bc0 + if (timeout != 0U) { + 8006bac: 683b ldr r3, [r7, #0] + 8006bae: 2b00 cmp r3, #0 + 8006bb0: d003 beq.n 8006bba + stat = osErrorTimeout; + 8006bb2: f06f 0301 mvn.w r3, #1 + 8006bb6: 61fb str r3, [r7, #28] + 8006bb8: e002 b.n 8006bc0 + } else { + stat = osErrorResource; + 8006bba: f06f 0302 mvn.w r3, #2 + 8006bbe: 61fb str r3, [r7, #28] + } + } + } + } + + return (stat); + 8006bc0: 69fb ldr r3, [r7, #28] +} + 8006bc2: 4618 mov r0, r3 + 8006bc4: 3720 adds r7, #32 + 8006bc6: 46bd mov sp, r7 + 8006bc8: bd80 pop {r7, pc} + 8006bca: bf00 nop + 8006bcc: e000ed04 .word 0xe000ed04 + +08006bd0 : /* vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION equals to 1 and is required for static memory allocation support. */ __WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) { - 8003080: b480 push {r7} - 8003082: b085 sub sp, #20 - 8003084: af00 add r7, sp, #0 - 8003086: 60f8 str r0, [r7, #12] - 8003088: 60b9 str r1, [r7, #8] - 800308a: 607a str r2, [r7, #4] + 8006bd0: b480 push {r7} + 8006bd2: b085 sub sp, #20 + 8006bd4: af00 add r7, sp, #0 + 8006bd6: 60f8 str r0, [r7, #12] + 8006bd8: 60b9 str r1, [r7, #8] + 8006bda: 607a str r2, [r7, #4] /* Idle task control block and stack */ static StaticTask_t Idle_TCB; static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE]; *ppxIdleTaskTCBBuffer = &Idle_TCB; - 800308c: 68fb ldr r3, [r7, #12] - 800308e: 4a07 ldr r2, [pc, #28] @ (80030ac ) - 8003090: 601a str r2, [r3, #0] + 8006bdc: 68fb ldr r3, [r7, #12] + 8006bde: 4a07 ldr r2, [pc, #28] @ (8006bfc ) + 8006be0: 601a str r2, [r3, #0] *ppxIdleTaskStackBuffer = &Idle_Stack[0]; - 8003092: 68bb ldr r3, [r7, #8] - 8003094: 4a06 ldr r2, [pc, #24] @ (80030b0 ) - 8003096: 601a str r2, [r3, #0] + 8006be2: 68bb ldr r3, [r7, #8] + 8006be4: 4a06 ldr r2, [pc, #24] @ (8006c00 ) + 8006be6: 601a str r2, [r3, #0] *pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE; - 8003098: 687b ldr r3, [r7, #4] - 800309a: 2280 movs r2, #128 @ 0x80 - 800309c: 601a str r2, [r3, #0] + 8006be8: 687b ldr r3, [r7, #4] + 8006bea: 2280 movs r2, #128 @ 0x80 + 8006bec: 601a str r2, [r3, #0] } - 800309e: bf00 nop - 80030a0: 3714 adds r7, #20 - 80030a2: 46bd mov sp, r7 - 80030a4: f85d 7b04 ldr.w r7, [sp], #4 - 80030a8: 4770 bx lr - 80030aa: bf00 nop - 80030ac: 200001a8 .word 0x200001a8 - 80030b0: 20000250 .word 0x20000250 + 8006bee: bf00 nop + 8006bf0: 3714 adds r7, #20 + 8006bf2: 46bd mov sp, r7 + 8006bf4: f85d 7b04 ldr.w r7, [sp], #4 + 8006bf8: 4770 bx lr + 8006bfa: bf00 nop + 8006bfc: 20000330 .word 0x20000330 + 8006c00: 200003d8 .word 0x200003d8 -080030b4 : +08006c04 : /* vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION equals to 1 and is required for static memory allocation support. */ __WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) { - 80030b4: b480 push {r7} - 80030b6: b085 sub sp, #20 - 80030b8: af00 add r7, sp, #0 - 80030ba: 60f8 str r0, [r7, #12] - 80030bc: 60b9 str r1, [r7, #8] - 80030be: 607a str r2, [r7, #4] + 8006c04: b480 push {r7} + 8006c06: b085 sub sp, #20 + 8006c08: af00 add r7, sp, #0 + 8006c0a: 60f8 str r0, [r7, #12] + 8006c0c: 60b9 str r1, [r7, #8] + 8006c0e: 607a str r2, [r7, #4] /* Timer task control block and stack */ static StaticTask_t Timer_TCB; static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH]; *ppxTimerTaskTCBBuffer = &Timer_TCB; - 80030c0: 68fb ldr r3, [r7, #12] - 80030c2: 4a07 ldr r2, [pc, #28] @ (80030e0 ) - 80030c4: 601a str r2, [r3, #0] + 8006c10: 68fb ldr r3, [r7, #12] + 8006c12: 4a07 ldr r2, [pc, #28] @ (8006c30 ) + 8006c14: 601a str r2, [r3, #0] *ppxTimerTaskStackBuffer = &Timer_Stack[0]; - 80030c6: 68bb ldr r3, [r7, #8] - 80030c8: 4a06 ldr r2, [pc, #24] @ (80030e4 ) - 80030ca: 601a str r2, [r3, #0] + 8006c16: 68bb ldr r3, [r7, #8] + 8006c18: 4a06 ldr r2, [pc, #24] @ (8006c34 ) + 8006c1a: 601a str r2, [r3, #0] *pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH; - 80030cc: 687b ldr r3, [r7, #4] - 80030ce: f44f 7280 mov.w r2, #256 @ 0x100 - 80030d2: 601a str r2, [r3, #0] + 8006c1c: 687b ldr r3, [r7, #4] + 8006c1e: f44f 7280 mov.w r2, #256 @ 0x100 + 8006c22: 601a str r2, [r3, #0] } - 80030d4: bf00 nop - 80030d6: 3714 adds r7, #20 - 80030d8: 46bd mov sp, r7 - 80030da: f85d 7b04 ldr.w r7, [sp], #4 - 80030de: 4770 bx lr - 80030e0: 20000450 .word 0x20000450 - 80030e4: 200004f8 .word 0x200004f8 + 8006c24: bf00 nop + 8006c26: 3714 adds r7, #20 + 8006c28: 46bd mov sp, r7 + 8006c2a: f85d 7b04 ldr.w r7, [sp], #4 + 8006c2e: 4770 bx lr + 8006c30: 200005d8 .word 0x200005d8 + 8006c34: 20000680 .word 0x20000680 -080030e8 : +08006c38 : /*----------------------------------------------------------- * PUBLIC LIST API documented in list.h *----------------------------------------------------------*/ void vListInitialise( List_t * const pxList ) { - 80030e8: b480 push {r7} - 80030ea: b083 sub sp, #12 - 80030ec: af00 add r7, sp, #0 - 80030ee: 6078 str r0, [r7, #4] + 8006c38: b480 push {r7} + 8006c3a: b083 sub sp, #12 + 8006c3c: af00 add r7, sp, #0 + 8006c3e: 6078 str r0, [r7, #4] /* The list structure contains a list item which is used to mark the end of the list. To initialise the list the list end is inserted as the only list entry. */ pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ - 80030f0: 687b ldr r3, [r7, #4] - 80030f2: f103 0208 add.w r2, r3, #8 - 80030f6: 687b ldr r3, [r7, #4] - 80030f8: 605a str r2, [r3, #4] + 8006c40: 687b ldr r3, [r7, #4] + 8006c42: f103 0208 add.w r2, r3, #8 + 8006c46: 687b ldr r3, [r7, #4] + 8006c48: 605a str r2, [r3, #4] /* The list end value is the highest possible value in the list to ensure it remains at the end of the list. */ pxList->xListEnd.xItemValue = portMAX_DELAY; - 80030fa: 687b ldr r3, [r7, #4] - 80030fc: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff - 8003100: 609a str r2, [r3, #8] + 8006c4a: 687b ldr r3, [r7, #4] + 8006c4c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8006c50: 609a str r2, [r3, #8] /* The list end next and previous pointers point to itself so we know when the list is empty. */ pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ - 8003102: 687b ldr r3, [r7, #4] - 8003104: f103 0208 add.w r2, r3, #8 - 8003108: 687b ldr r3, [r7, #4] - 800310a: 60da str r2, [r3, #12] + 8006c52: 687b ldr r3, [r7, #4] + 8006c54: f103 0208 add.w r2, r3, #8 + 8006c58: 687b ldr r3, [r7, #4] + 8006c5a: 60da str r2, [r3, #12] pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ - 800310c: 687b ldr r3, [r7, #4] - 800310e: f103 0208 add.w r2, r3, #8 - 8003112: 687b ldr r3, [r7, #4] - 8003114: 611a str r2, [r3, #16] + 8006c5c: 687b ldr r3, [r7, #4] + 8006c5e: f103 0208 add.w r2, r3, #8 + 8006c62: 687b ldr r3, [r7, #4] + 8006c64: 611a str r2, [r3, #16] pxList->uxNumberOfItems = ( UBaseType_t ) 0U; - 8003116: 687b ldr r3, [r7, #4] - 8003118: 2200 movs r2, #0 - 800311a: 601a str r2, [r3, #0] + 8006c66: 687b ldr r3, [r7, #4] + 8006c68: 2200 movs r2, #0 + 8006c6a: 601a str r2, [r3, #0] /* Write known values into the list if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ); listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ); } - 800311c: bf00 nop - 800311e: 370c adds r7, #12 - 8003120: 46bd mov sp, r7 - 8003122: f85d 7b04 ldr.w r7, [sp], #4 - 8003126: 4770 bx lr + 8006c6c: bf00 nop + 8006c6e: 370c adds r7, #12 + 8006c70: 46bd mov sp, r7 + 8006c72: f85d 7b04 ldr.w r7, [sp], #4 + 8006c76: 4770 bx lr -08003128 : +08006c78 : /*-----------------------------------------------------------*/ void vListInitialiseItem( ListItem_t * const pxItem ) { - 8003128: b480 push {r7} - 800312a: b083 sub sp, #12 - 800312c: af00 add r7, sp, #0 - 800312e: 6078 str r0, [r7, #4] + 8006c78: b480 push {r7} + 8006c7a: b083 sub sp, #12 + 8006c7c: af00 add r7, sp, #0 + 8006c7e: 6078 str r0, [r7, #4] /* Make sure the list item is not recorded as being on a list. */ pxItem->pxContainer = NULL; - 8003130: 687b ldr r3, [r7, #4] - 8003132: 2200 movs r2, #0 - 8003134: 611a str r2, [r3, #16] + 8006c80: 687b ldr r3, [r7, #4] + 8006c82: 2200 movs r2, #0 + 8006c84: 611a str r2, [r3, #16] /* Write known values into the list item if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); } - 8003136: bf00 nop - 8003138: 370c adds r7, #12 - 800313a: 46bd mov sp, r7 - 800313c: f85d 7b04 ldr.w r7, [sp], #4 - 8003140: 4770 bx lr + 8006c86: bf00 nop + 8006c88: 370c adds r7, #12 + 8006c8a: 46bd mov sp, r7 + 8006c8c: f85d 7b04 ldr.w r7, [sp], #4 + 8006c90: 4770 bx lr -08003142 : +08006c92 : /*-----------------------------------------------------------*/ void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) { - 8003142: b480 push {r7} - 8003144: b085 sub sp, #20 - 8003146: af00 add r7, sp, #0 - 8003148: 6078 str r0, [r7, #4] - 800314a: 6039 str r1, [r7, #0] + 8006c92: b480 push {r7} + 8006c94: b085 sub sp, #20 + 8006c96: af00 add r7, sp, #0 + 8006c98: 6078 str r0, [r7, #4] + 8006c9a: 6039 str r1, [r7, #0] ListItem_t * const pxIndex = pxList->pxIndex; - 800314c: 687b ldr r3, [r7, #4] - 800314e: 685b ldr r3, [r3, #4] - 8003150: 60fb str r3, [r7, #12] + 8006c9c: 687b ldr r3, [r7, #4] + 8006c9e: 685b ldr r3, [r3, #4] + 8006ca0: 60fb str r3, [r7, #12] listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); /* Insert a new list item into pxList, but rather than sort the list, makes the new list item the last item to be removed by a call to listGET_OWNER_OF_NEXT_ENTRY(). */ pxNewListItem->pxNext = pxIndex; - 8003152: 683b ldr r3, [r7, #0] - 8003154: 68fa ldr r2, [r7, #12] - 8003156: 605a str r2, [r3, #4] + 8006ca2: 683b ldr r3, [r7, #0] + 8006ca4: 68fa ldr r2, [r7, #12] + 8006ca6: 605a str r2, [r3, #4] pxNewListItem->pxPrevious = pxIndex->pxPrevious; - 8003158: 68fb ldr r3, [r7, #12] - 800315a: 689a ldr r2, [r3, #8] - 800315c: 683b ldr r3, [r7, #0] - 800315e: 609a str r2, [r3, #8] + 8006ca8: 68fb ldr r3, [r7, #12] + 8006caa: 689a ldr r2, [r3, #8] + 8006cac: 683b ldr r3, [r7, #0] + 8006cae: 609a str r2, [r3, #8] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); pxIndex->pxPrevious->pxNext = pxNewListItem; - 8003160: 68fb ldr r3, [r7, #12] - 8003162: 689b ldr r3, [r3, #8] - 8003164: 683a ldr r2, [r7, #0] - 8003166: 605a str r2, [r3, #4] + 8006cb0: 68fb ldr r3, [r7, #12] + 8006cb2: 689b ldr r3, [r3, #8] + 8006cb4: 683a ldr r2, [r7, #0] + 8006cb6: 605a str r2, [r3, #4] pxIndex->pxPrevious = pxNewListItem; - 8003168: 68fb ldr r3, [r7, #12] - 800316a: 683a ldr r2, [r7, #0] - 800316c: 609a str r2, [r3, #8] + 8006cb8: 68fb ldr r3, [r7, #12] + 8006cba: 683a ldr r2, [r7, #0] + 8006cbc: 609a str r2, [r3, #8] /* Remember which list the item is in. */ pxNewListItem->pxContainer = pxList; - 800316e: 683b ldr r3, [r7, #0] - 8003170: 687a ldr r2, [r7, #4] - 8003172: 611a str r2, [r3, #16] + 8006cbe: 683b ldr r3, [r7, #0] + 8006cc0: 687a ldr r2, [r7, #4] + 8006cc2: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; - 8003174: 687b ldr r3, [r7, #4] - 8003176: 681b ldr r3, [r3, #0] - 8003178: 1c5a adds r2, r3, #1 - 800317a: 687b ldr r3, [r7, #4] - 800317c: 601a str r2, [r3, #0] + 8006cc4: 687b ldr r3, [r7, #4] + 8006cc6: 681b ldr r3, [r3, #0] + 8006cc8: 1c5a adds r2, r3, #1 + 8006cca: 687b ldr r3, [r7, #4] + 8006ccc: 601a str r2, [r3, #0] } - 800317e: bf00 nop - 8003180: 3714 adds r7, #20 - 8003182: 46bd mov sp, r7 - 8003184: f85d 7b04 ldr.w r7, [sp], #4 - 8003188: 4770 bx lr + 8006cce: bf00 nop + 8006cd0: 3714 adds r7, #20 + 8006cd2: 46bd mov sp, r7 + 8006cd4: f85d 7b04 ldr.w r7, [sp], #4 + 8006cd8: 4770 bx lr -0800318a : +08006cda : /*-----------------------------------------------------------*/ void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) { - 800318a: b480 push {r7} - 800318c: b085 sub sp, #20 - 800318e: af00 add r7, sp, #0 - 8003190: 6078 str r0, [r7, #4] - 8003192: 6039 str r1, [r7, #0] + 8006cda: b480 push {r7} + 8006cdc: b085 sub sp, #20 + 8006cde: af00 add r7, sp, #0 + 8006ce0: 6078 str r0, [r7, #4] + 8006ce2: 6039 str r1, [r7, #0] ListItem_t *pxIterator; const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; - 8003194: 683b ldr r3, [r7, #0] - 8003196: 681b ldr r3, [r3, #0] - 8003198: 60bb str r3, [r7, #8] + 8006ce4: 683b ldr r3, [r7, #0] + 8006ce6: 681b ldr r3, [r3, #0] + 8006ce8: 60bb str r3, [r7, #8] new list item should be placed after it. This ensures that TCBs which are stored in ready lists (all of which have the same xItemValue value) get a share of the CPU. However, if the xItemValue is the same as the back marker the iteration loop below will not end. Therefore the value is checked first, and the algorithm slightly modified if necessary. */ if( xValueOfInsertion == portMAX_DELAY ) - 800319a: 68bb ldr r3, [r7, #8] - 800319c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff - 80031a0: d103 bne.n 80031aa + 8006cea: 68bb ldr r3, [r7, #8] + 8006cec: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8006cf0: d103 bne.n 8006cfa { pxIterator = pxList->xListEnd.pxPrevious; - 80031a2: 687b ldr r3, [r7, #4] - 80031a4: 691b ldr r3, [r3, #16] - 80031a6: 60fb str r3, [r7, #12] - 80031a8: e00c b.n 80031c4 + 8006cf2: 687b ldr r3, [r7, #4] + 8006cf4: 691b ldr r3, [r3, #16] + 8006cf6: 60fb str r3, [r7, #12] + 8006cf8: e00c b.n 8006d14 4) Using a queue or semaphore before it has been initialised or before the scheduler has been started (are interrupts firing before vTaskStartScheduler() has been called?). **********************************************************************/ for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */ - 80031aa: 687b ldr r3, [r7, #4] - 80031ac: 3308 adds r3, #8 - 80031ae: 60fb str r3, [r7, #12] - 80031b0: e002 b.n 80031b8 - 80031b2: 68fb ldr r3, [r7, #12] - 80031b4: 685b ldr r3, [r3, #4] - 80031b6: 60fb str r3, [r7, #12] - 80031b8: 68fb ldr r3, [r7, #12] - 80031ba: 685b ldr r3, [r3, #4] - 80031bc: 681b ldr r3, [r3, #0] - 80031be: 68ba ldr r2, [r7, #8] - 80031c0: 429a cmp r2, r3 - 80031c2: d2f6 bcs.n 80031b2 + 8006cfa: 687b ldr r3, [r7, #4] + 8006cfc: 3308 adds r3, #8 + 8006cfe: 60fb str r3, [r7, #12] + 8006d00: e002 b.n 8006d08 + 8006d02: 68fb ldr r3, [r7, #12] + 8006d04: 685b ldr r3, [r3, #4] + 8006d06: 60fb str r3, [r7, #12] + 8006d08: 68fb ldr r3, [r7, #12] + 8006d0a: 685b ldr r3, [r3, #4] + 8006d0c: 681b ldr r3, [r3, #0] + 8006d0e: 68ba ldr r2, [r7, #8] + 8006d10: 429a cmp r2, r3 + 8006d12: d2f6 bcs.n 8006d02 /* There is nothing to do here, just iterating to the wanted insertion position. */ } } pxNewListItem->pxNext = pxIterator->pxNext; - 80031c4: 68fb ldr r3, [r7, #12] - 80031c6: 685a ldr r2, [r3, #4] - 80031c8: 683b ldr r3, [r7, #0] - 80031ca: 605a str r2, [r3, #4] + 8006d14: 68fb ldr r3, [r7, #12] + 8006d16: 685a ldr r2, [r3, #4] + 8006d18: 683b ldr r3, [r7, #0] + 8006d1a: 605a str r2, [r3, #4] pxNewListItem->pxNext->pxPrevious = pxNewListItem; - 80031cc: 683b ldr r3, [r7, #0] - 80031ce: 685b ldr r3, [r3, #4] - 80031d0: 683a ldr r2, [r7, #0] - 80031d2: 609a str r2, [r3, #8] + 8006d1c: 683b ldr r3, [r7, #0] + 8006d1e: 685b ldr r3, [r3, #4] + 8006d20: 683a ldr r2, [r7, #0] + 8006d22: 609a str r2, [r3, #8] pxNewListItem->pxPrevious = pxIterator; - 80031d4: 683b ldr r3, [r7, #0] - 80031d6: 68fa ldr r2, [r7, #12] - 80031d8: 609a str r2, [r3, #8] + 8006d24: 683b ldr r3, [r7, #0] + 8006d26: 68fa ldr r2, [r7, #12] + 8006d28: 609a str r2, [r3, #8] pxIterator->pxNext = pxNewListItem; - 80031da: 68fb ldr r3, [r7, #12] - 80031dc: 683a ldr r2, [r7, #0] - 80031de: 605a str r2, [r3, #4] + 8006d2a: 68fb ldr r3, [r7, #12] + 8006d2c: 683a ldr r2, [r7, #0] + 8006d2e: 605a str r2, [r3, #4] /* Remember which list the item is in. This allows fast removal of the item later. */ pxNewListItem->pxContainer = pxList; - 80031e0: 683b ldr r3, [r7, #0] - 80031e2: 687a ldr r2, [r7, #4] - 80031e4: 611a str r2, [r3, #16] + 8006d30: 683b ldr r3, [r7, #0] + 8006d32: 687a ldr r2, [r7, #4] + 8006d34: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; - 80031e6: 687b ldr r3, [r7, #4] - 80031e8: 681b ldr r3, [r3, #0] - 80031ea: 1c5a adds r2, r3, #1 - 80031ec: 687b ldr r3, [r7, #4] - 80031ee: 601a str r2, [r3, #0] + 8006d36: 687b ldr r3, [r7, #4] + 8006d38: 681b ldr r3, [r3, #0] + 8006d3a: 1c5a adds r2, r3, #1 + 8006d3c: 687b ldr r3, [r7, #4] + 8006d3e: 601a str r2, [r3, #0] } - 80031f0: bf00 nop - 80031f2: 3714 adds r7, #20 - 80031f4: 46bd mov sp, r7 - 80031f6: f85d 7b04 ldr.w r7, [sp], #4 - 80031fa: 4770 bx lr + 8006d40: bf00 nop + 8006d42: 3714 adds r7, #20 + 8006d44: 46bd mov sp, r7 + 8006d46: f85d 7b04 ldr.w r7, [sp], #4 + 8006d4a: 4770 bx lr -080031fc : +08006d4c : /*-----------------------------------------------------------*/ UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) { - 80031fc: b480 push {r7} - 80031fe: b085 sub sp, #20 - 8003200: af00 add r7, sp, #0 - 8003202: 6078 str r0, [r7, #4] + 8006d4c: b480 push {r7} + 8006d4e: b085 sub sp, #20 + 8006d50: af00 add r7, sp, #0 + 8006d52: 6078 str r0, [r7, #4] /* The list item knows which list it is in. Obtain the list from the list item. */ List_t * const pxList = pxItemToRemove->pxContainer; - 8003204: 687b ldr r3, [r7, #4] - 8003206: 691b ldr r3, [r3, #16] - 8003208: 60fb str r3, [r7, #12] + 8006d54: 687b ldr r3, [r7, #4] + 8006d56: 691b ldr r3, [r3, #16] + 8006d58: 60fb str r3, [r7, #12] pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; - 800320a: 687b ldr r3, [r7, #4] - 800320c: 685b ldr r3, [r3, #4] - 800320e: 687a ldr r2, [r7, #4] - 8003210: 6892 ldr r2, [r2, #8] - 8003212: 609a str r2, [r3, #8] + 8006d5a: 687b ldr r3, [r7, #4] + 8006d5c: 685b ldr r3, [r3, #4] + 8006d5e: 687a ldr r2, [r7, #4] + 8006d60: 6892 ldr r2, [r2, #8] + 8006d62: 609a str r2, [r3, #8] pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; - 8003214: 687b ldr r3, [r7, #4] - 8003216: 689b ldr r3, [r3, #8] - 8003218: 687a ldr r2, [r7, #4] - 800321a: 6852 ldr r2, [r2, #4] - 800321c: 605a str r2, [r3, #4] + 8006d64: 687b ldr r3, [r7, #4] + 8006d66: 689b ldr r3, [r3, #8] + 8006d68: 687a ldr r2, [r7, #4] + 8006d6a: 6852 ldr r2, [r2, #4] + 8006d6c: 605a str r2, [r3, #4] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); /* Make sure the index is left pointing to a valid item. */ if( pxList->pxIndex == pxItemToRemove ) - 800321e: 68fb ldr r3, [r7, #12] - 8003220: 685b ldr r3, [r3, #4] - 8003222: 687a ldr r2, [r7, #4] - 8003224: 429a cmp r2, r3 - 8003226: d103 bne.n 8003230 + 8006d6e: 68fb ldr r3, [r7, #12] + 8006d70: 685b ldr r3, [r3, #4] + 8006d72: 687a ldr r2, [r7, #4] + 8006d74: 429a cmp r2, r3 + 8006d76: d103 bne.n 8006d80 { pxList->pxIndex = pxItemToRemove->pxPrevious; - 8003228: 687b ldr r3, [r7, #4] - 800322a: 689a ldr r2, [r3, #8] - 800322c: 68fb ldr r3, [r7, #12] - 800322e: 605a str r2, [r3, #4] + 8006d78: 687b ldr r3, [r7, #4] + 8006d7a: 689a ldr r2, [r3, #8] + 8006d7c: 68fb ldr r3, [r7, #12] + 8006d7e: 605a str r2, [r3, #4] else { mtCOVERAGE_TEST_MARKER(); } pxItemToRemove->pxContainer = NULL; - 8003230: 687b ldr r3, [r7, #4] - 8003232: 2200 movs r2, #0 - 8003234: 611a str r2, [r3, #16] + 8006d80: 687b ldr r3, [r7, #4] + 8006d82: 2200 movs r2, #0 + 8006d84: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )--; - 8003236: 68fb ldr r3, [r7, #12] - 8003238: 681b ldr r3, [r3, #0] - 800323a: 1e5a subs r2, r3, #1 - 800323c: 68fb ldr r3, [r7, #12] - 800323e: 601a str r2, [r3, #0] + 8006d86: 68fb ldr r3, [r7, #12] + 8006d88: 681b ldr r3, [r3, #0] + 8006d8a: 1e5a subs r2, r3, #1 + 8006d8c: 68fb ldr r3, [r7, #12] + 8006d8e: 601a str r2, [r3, #0] return pxList->uxNumberOfItems; - 8003240: 68fb ldr r3, [r7, #12] - 8003242: 681b ldr r3, [r3, #0] + 8006d90: 68fb ldr r3, [r7, #12] + 8006d92: 681b ldr r3, [r3, #0] } - 8003244: 4618 mov r0, r3 - 8003246: 3714 adds r7, #20 - 8003248: 46bd mov sp, r7 - 800324a: f85d 7b04 ldr.w r7, [sp], #4 - 800324e: 4770 bx lr + 8006d94: 4618 mov r0, r3 + 8006d96: 3714 adds r7, #20 + 8006d98: 46bd mov sp, r7 + 8006d9a: f85d 7b04 ldr.w r7, [sp], #4 + 8006d9e: 4770 bx lr -08003250 : +08006da0 : } \ taskEXIT_CRITICAL() /*-----------------------------------------------------------*/ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) { - 8003250: b580 push {r7, lr} - 8003252: b084 sub sp, #16 - 8003254: af00 add r7, sp, #0 - 8003256: 6078 str r0, [r7, #4] - 8003258: 6039 str r1, [r7, #0] + 8006da0: b580 push {r7, lr} + 8006da2: b084 sub sp, #16 + 8006da4: af00 add r7, sp, #0 + 8006da6: 6078 str r0, [r7, #4] + 8006da8: 6039 str r1, [r7, #0] Queue_t * const pxQueue = xQueue; - 800325a: 687b ldr r3, [r7, #4] - 800325c: 60fb str r3, [r7, #12] + 8006daa: 687b ldr r3, [r7, #4] + 8006dac: 60fb str r3, [r7, #12] configASSERT( pxQueue ); - 800325e: 68fb ldr r3, [r7, #12] - 8003260: 2b00 cmp r3, #0 - 8003262: d10b bne.n 800327c + 8006dae: 68fb ldr r3, [r7, #12] + 8006db0: 2b00 cmp r3, #0 + 8006db2: d10b bne.n 8006dcc __asm volatile - 8003264: f04f 0350 mov.w r3, #80 @ 0x50 - 8003268: f383 8811 msr BASEPRI, r3 - 800326c: f3bf 8f6f isb sy - 8003270: f3bf 8f4f dsb sy - 8003274: 60bb str r3, [r7, #8] + 8006db4: f04f 0350 mov.w r3, #80 @ 0x50 + 8006db8: f383 8811 msr BASEPRI, r3 + 8006dbc: f3bf 8f6f isb sy + 8006dc0: f3bf 8f4f dsb sy + 8006dc4: 60bb str r3, [r7, #8] } - 8003276: bf00 nop - 8003278: bf00 nop - 800327a: e7fd b.n 8003278 + 8006dc6: bf00 nop + 8006dc8: bf00 nop + 8006dca: e7fd b.n 8006dc8 taskENTER_CRITICAL(); - 800327c: f002 f8a4 bl 80053c8 + 8006dcc: f002 fd64 bl 8009898 { pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ - 8003280: 68fb ldr r3, [r7, #12] - 8003282: 681a ldr r2, [r3, #0] - 8003284: 68fb ldr r3, [r7, #12] - 8003286: 6bdb ldr r3, [r3, #60] @ 0x3c - 8003288: 68f9 ldr r1, [r7, #12] - 800328a: 6c09 ldr r1, [r1, #64] @ 0x40 - 800328c: fb01 f303 mul.w r3, r1, r3 - 8003290: 441a add r2, r3 - 8003292: 68fb ldr r3, [r7, #12] - 8003294: 609a str r2, [r3, #8] + 8006dd0: 68fb ldr r3, [r7, #12] + 8006dd2: 681a ldr r2, [r3, #0] + 8006dd4: 68fb ldr r3, [r7, #12] + 8006dd6: 6bdb ldr r3, [r3, #60] @ 0x3c + 8006dd8: 68f9 ldr r1, [r7, #12] + 8006dda: 6c09 ldr r1, [r1, #64] @ 0x40 + 8006ddc: fb01 f303 mul.w r3, r1, r3 + 8006de0: 441a add r2, r3 + 8006de2: 68fb ldr r3, [r7, #12] + 8006de4: 609a str r2, [r3, #8] pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; - 8003296: 68fb ldr r3, [r7, #12] - 8003298: 2200 movs r2, #0 - 800329a: 639a str r2, [r3, #56] @ 0x38 + 8006de6: 68fb ldr r3, [r7, #12] + 8006de8: 2200 movs r2, #0 + 8006dea: 639a str r2, [r3, #56] @ 0x38 pxQueue->pcWriteTo = pxQueue->pcHead; - 800329c: 68fb ldr r3, [r7, #12] - 800329e: 681a ldr r2, [r3, #0] - 80032a0: 68fb ldr r3, [r7, #12] - 80032a2: 605a str r2, [r3, #4] + 8006dec: 68fb ldr r3, [r7, #12] + 8006dee: 681a ldr r2, [r3, #0] + 8006df0: 68fb ldr r3, [r7, #12] + 8006df2: 605a str r2, [r3, #4] pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ - 80032a4: 68fb ldr r3, [r7, #12] - 80032a6: 681a ldr r2, [r3, #0] - 80032a8: 68fb ldr r3, [r7, #12] - 80032aa: 6bdb ldr r3, [r3, #60] @ 0x3c - 80032ac: 3b01 subs r3, #1 - 80032ae: 68f9 ldr r1, [r7, #12] - 80032b0: 6c09 ldr r1, [r1, #64] @ 0x40 - 80032b2: fb01 f303 mul.w r3, r1, r3 - 80032b6: 441a add r2, r3 - 80032b8: 68fb ldr r3, [r7, #12] - 80032ba: 60da str r2, [r3, #12] + 8006df4: 68fb ldr r3, [r7, #12] + 8006df6: 681a ldr r2, [r3, #0] + 8006df8: 68fb ldr r3, [r7, #12] + 8006dfa: 6bdb ldr r3, [r3, #60] @ 0x3c + 8006dfc: 3b01 subs r3, #1 + 8006dfe: 68f9 ldr r1, [r7, #12] + 8006e00: 6c09 ldr r1, [r1, #64] @ 0x40 + 8006e02: fb01 f303 mul.w r3, r1, r3 + 8006e06: 441a add r2, r3 + 8006e08: 68fb ldr r3, [r7, #12] + 8006e0a: 60da str r2, [r3, #12] pxQueue->cRxLock = queueUNLOCKED; - 80032bc: 68fb ldr r3, [r7, #12] - 80032be: 22ff movs r2, #255 @ 0xff - 80032c0: f883 2044 strb.w r2, [r3, #68] @ 0x44 + 8006e0c: 68fb ldr r3, [r7, #12] + 8006e0e: 22ff movs r2, #255 @ 0xff + 8006e10: f883 2044 strb.w r2, [r3, #68] @ 0x44 pxQueue->cTxLock = queueUNLOCKED; - 80032c4: 68fb ldr r3, [r7, #12] - 80032c6: 22ff movs r2, #255 @ 0xff - 80032c8: f883 2045 strb.w r2, [r3, #69] @ 0x45 + 8006e14: 68fb ldr r3, [r7, #12] + 8006e16: 22ff movs r2, #255 @ 0xff + 8006e18: f883 2045 strb.w r2, [r3, #69] @ 0x45 if( xNewQueue == pdFALSE ) - 80032cc: 683b ldr r3, [r7, #0] - 80032ce: 2b00 cmp r3, #0 - 80032d0: d114 bne.n 80032fc + 8006e1c: 683b ldr r3, [r7, #0] + 8006e1e: 2b00 cmp r3, #0 + 8006e20: d114 bne.n 8006e4c /* If there are tasks blocked waiting to read from the queue, then the tasks will remain blocked as after this function exits the queue will still be empty. If there are tasks blocked waiting to write to the queue, then one should be unblocked as after this function exits it will be possible to write to it. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) - 80032d2: 68fb ldr r3, [r7, #12] - 80032d4: 691b ldr r3, [r3, #16] - 80032d6: 2b00 cmp r3, #0 - 80032d8: d01a beq.n 8003310 + 8006e22: 68fb ldr r3, [r7, #12] + 8006e24: 691b ldr r3, [r3, #16] + 8006e26: 2b00 cmp r3, #0 + 8006e28: d01a beq.n 8006e60 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - 80032da: 68fb ldr r3, [r7, #12] - 80032dc: 3310 adds r3, #16 - 80032de: 4618 mov r0, r3 - 80032e0: f001 f942 bl 8004568 - 80032e4: 4603 mov r3, r0 - 80032e6: 2b00 cmp r3, #0 - 80032e8: d012 beq.n 8003310 + 8006e2a: 68fb ldr r3, [r7, #12] + 8006e2c: 3310 adds r3, #16 + 8006e2e: 4618 mov r0, r3 + 8006e30: f001 fc3e bl 80086b0 + 8006e34: 4603 mov r3, r0 + 8006e36: 2b00 cmp r3, #0 + 8006e38: d012 beq.n 8006e60 { queueYIELD_IF_USING_PREEMPTION(); - 80032ea: 4b0d ldr r3, [pc, #52] @ (8003320 ) - 80032ec: f04f 5280 mov.w r2, #268435456 @ 0x10000000 - 80032f0: 601a str r2, [r3, #0] - 80032f2: f3bf 8f4f dsb sy - 80032f6: f3bf 8f6f isb sy - 80032fa: e009 b.n 8003310 + 8006e3a: 4b0d ldr r3, [pc, #52] @ (8006e70 ) + 8006e3c: f04f 5280 mov.w r2, #268435456 @ 0x10000000 + 8006e40: 601a str r2, [r3, #0] + 8006e42: f3bf 8f4f dsb sy + 8006e46: f3bf 8f6f isb sy + 8006e4a: e009 b.n 8006e60 } } else { /* Ensure the event queues start in the correct state. */ vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); - 80032fc: 68fb ldr r3, [r7, #12] - 80032fe: 3310 adds r3, #16 - 8003300: 4618 mov r0, r3 - 8003302: f7ff fef1 bl 80030e8 + 8006e4c: 68fb ldr r3, [r7, #12] + 8006e4e: 3310 adds r3, #16 + 8006e50: 4618 mov r0, r3 + 8006e52: f7ff fef1 bl 8006c38 vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); - 8003306: 68fb ldr r3, [r7, #12] - 8003308: 3324 adds r3, #36 @ 0x24 - 800330a: 4618 mov r0, r3 - 800330c: f7ff feec bl 80030e8 + 8006e56: 68fb ldr r3, [r7, #12] + 8006e58: 3324 adds r3, #36 @ 0x24 + 8006e5a: 4618 mov r0, r3 + 8006e5c: f7ff feec bl 8006c38 } } taskEXIT_CRITICAL(); - 8003310: f002 f88c bl 800542c + 8006e60: f002 fd4c bl 80098fc /* A value is returned for calling semantic consistency with previous versions. */ return pdPASS; - 8003314: 2301 movs r3, #1 + 8006e64: 2301 movs r3, #1 } - 8003316: 4618 mov r0, r3 - 8003318: 3710 adds r7, #16 - 800331a: 46bd mov sp, r7 - 800331c: bd80 pop {r7, pc} - 800331e: bf00 nop - 8003320: e000ed04 .word 0xe000ed04 + 8006e66: 4618 mov r0, r3 + 8006e68: 3710 adds r7, #16 + 8006e6a: 46bd mov sp, r7 + 8006e6c: bd80 pop {r7, pc} + 8006e6e: bf00 nop + 8006e70: e000ed04 .word 0xe000ed04 -08003324 : +08006e74 : /*-----------------------------------------------------------*/ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) { - 8003324: b580 push {r7, lr} - 8003326: b08e sub sp, #56 @ 0x38 - 8003328: af02 add r7, sp, #8 - 800332a: 60f8 str r0, [r7, #12] - 800332c: 60b9 str r1, [r7, #8] - 800332e: 607a str r2, [r7, #4] - 8003330: 603b str r3, [r7, #0] + 8006e74: b580 push {r7, lr} + 8006e76: b08e sub sp, #56 @ 0x38 + 8006e78: af02 add r7, sp, #8 + 8006e7a: 60f8 str r0, [r7, #12] + 8006e7c: 60b9 str r1, [r7, #8] + 8006e7e: 607a str r2, [r7, #4] + 8006e80: 603b str r3, [r7, #0] Queue_t *pxNewQueue; configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); - 8003332: 68fb ldr r3, [r7, #12] - 8003334: 2b00 cmp r3, #0 - 8003336: d10b bne.n 8003350 + 8006e82: 68fb ldr r3, [r7, #12] + 8006e84: 2b00 cmp r3, #0 + 8006e86: d10b bne.n 8006ea0 __asm volatile - 8003338: f04f 0350 mov.w r3, #80 @ 0x50 - 800333c: f383 8811 msr BASEPRI, r3 - 8003340: f3bf 8f6f isb sy - 8003344: f3bf 8f4f dsb sy - 8003348: 62bb str r3, [r7, #40] @ 0x28 + 8006e88: f04f 0350 mov.w r3, #80 @ 0x50 + 8006e8c: f383 8811 msr BASEPRI, r3 + 8006e90: f3bf 8f6f isb sy + 8006e94: f3bf 8f4f dsb sy + 8006e98: 62bb str r3, [r7, #40] @ 0x28 } - 800334a: bf00 nop - 800334c: bf00 nop - 800334e: e7fd b.n 800334c + 8006e9a: bf00 nop + 8006e9c: bf00 nop + 8006e9e: e7fd b.n 8006e9c /* The StaticQueue_t structure and the queue storage area must be supplied. */ configASSERT( pxStaticQueue != NULL ); - 8003350: 683b ldr r3, [r7, #0] - 8003352: 2b00 cmp r3, #0 - 8003354: d10b bne.n 800336e + 8006ea0: 683b ldr r3, [r7, #0] + 8006ea2: 2b00 cmp r3, #0 + 8006ea4: d10b bne.n 8006ebe __asm volatile - 8003356: f04f 0350 mov.w r3, #80 @ 0x50 - 800335a: f383 8811 msr BASEPRI, r3 - 800335e: f3bf 8f6f isb sy - 8003362: f3bf 8f4f dsb sy - 8003366: 627b str r3, [r7, #36] @ 0x24 + 8006ea6: f04f 0350 mov.w r3, #80 @ 0x50 + 8006eaa: f383 8811 msr BASEPRI, r3 + 8006eae: f3bf 8f6f isb sy + 8006eb2: f3bf 8f4f dsb sy + 8006eb6: 627b str r3, [r7, #36] @ 0x24 } - 8003368: bf00 nop - 800336a: bf00 nop - 800336c: e7fd b.n 800336a + 8006eb8: bf00 nop + 8006eba: bf00 nop + 8006ebc: e7fd b.n 8006eba /* A queue storage area should be provided if the item size is not 0, and should not be provided if the item size is 0. */ configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) ); - 800336e: 687b ldr r3, [r7, #4] - 8003370: 2b00 cmp r3, #0 - 8003372: d002 beq.n 800337a - 8003374: 68bb ldr r3, [r7, #8] - 8003376: 2b00 cmp r3, #0 - 8003378: d001 beq.n 800337e - 800337a: 2301 movs r3, #1 - 800337c: e000 b.n 8003380 - 800337e: 2300 movs r3, #0 - 8003380: 2b00 cmp r3, #0 - 8003382: d10b bne.n 800339c + 8006ebe: 687b ldr r3, [r7, #4] + 8006ec0: 2b00 cmp r3, #0 + 8006ec2: d002 beq.n 8006eca + 8006ec4: 68bb ldr r3, [r7, #8] + 8006ec6: 2b00 cmp r3, #0 + 8006ec8: d001 beq.n 8006ece + 8006eca: 2301 movs r3, #1 + 8006ecc: e000 b.n 8006ed0 + 8006ece: 2300 movs r3, #0 + 8006ed0: 2b00 cmp r3, #0 + 8006ed2: d10b bne.n 8006eec __asm volatile - 8003384: f04f 0350 mov.w r3, #80 @ 0x50 - 8003388: f383 8811 msr BASEPRI, r3 - 800338c: f3bf 8f6f isb sy - 8003390: f3bf 8f4f dsb sy - 8003394: 623b str r3, [r7, #32] + 8006ed4: f04f 0350 mov.w r3, #80 @ 0x50 + 8006ed8: f383 8811 msr BASEPRI, r3 + 8006edc: f3bf 8f6f isb sy + 8006ee0: f3bf 8f4f dsb sy + 8006ee4: 623b str r3, [r7, #32] } - 8003396: bf00 nop - 8003398: bf00 nop - 800339a: e7fd b.n 8003398 + 8006ee6: bf00 nop + 8006ee8: bf00 nop + 8006eea: e7fd b.n 8006ee8 configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ); - 800339c: 687b ldr r3, [r7, #4] - 800339e: 2b00 cmp r3, #0 - 80033a0: d102 bne.n 80033a8 - 80033a2: 68bb ldr r3, [r7, #8] - 80033a4: 2b00 cmp r3, #0 - 80033a6: d101 bne.n 80033ac - 80033a8: 2301 movs r3, #1 - 80033aa: e000 b.n 80033ae - 80033ac: 2300 movs r3, #0 - 80033ae: 2b00 cmp r3, #0 - 80033b0: d10b bne.n 80033ca + 8006eec: 687b ldr r3, [r7, #4] + 8006eee: 2b00 cmp r3, #0 + 8006ef0: d102 bne.n 8006ef8 + 8006ef2: 68bb ldr r3, [r7, #8] + 8006ef4: 2b00 cmp r3, #0 + 8006ef6: d101 bne.n 8006efc + 8006ef8: 2301 movs r3, #1 + 8006efa: e000 b.n 8006efe + 8006efc: 2300 movs r3, #0 + 8006efe: 2b00 cmp r3, #0 + 8006f00: d10b bne.n 8006f1a __asm volatile - 80033b2: f04f 0350 mov.w r3, #80 @ 0x50 - 80033b6: f383 8811 msr BASEPRI, r3 - 80033ba: f3bf 8f6f isb sy - 80033be: f3bf 8f4f dsb sy - 80033c2: 61fb str r3, [r7, #28] + 8006f02: f04f 0350 mov.w r3, #80 @ 0x50 + 8006f06: f383 8811 msr BASEPRI, r3 + 8006f0a: f3bf 8f6f isb sy + 8006f0e: f3bf 8f4f dsb sy + 8006f12: 61fb str r3, [r7, #28] } - 80033c4: bf00 nop - 80033c6: bf00 nop - 80033c8: e7fd b.n 80033c6 + 8006f14: bf00 nop + 8006f16: bf00 nop + 8006f18: e7fd b.n 8006f16 #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticQueue_t or StaticSemaphore_t equals the size of the real queue and semaphore structures. */ volatile size_t xSize = sizeof( StaticQueue_t ); - 80033ca: 2350 movs r3, #80 @ 0x50 - 80033cc: 617b str r3, [r7, #20] + 8006f1a: 2350 movs r3, #80 @ 0x50 + 8006f1c: 617b str r3, [r7, #20] configASSERT( xSize == sizeof( Queue_t ) ); - 80033ce: 697b ldr r3, [r7, #20] - 80033d0: 2b50 cmp r3, #80 @ 0x50 - 80033d2: d00b beq.n 80033ec + 8006f1e: 697b ldr r3, [r7, #20] + 8006f20: 2b50 cmp r3, #80 @ 0x50 + 8006f22: d00b beq.n 8006f3c __asm volatile - 80033d4: f04f 0350 mov.w r3, #80 @ 0x50 - 80033d8: f383 8811 msr BASEPRI, r3 - 80033dc: f3bf 8f6f isb sy - 80033e0: f3bf 8f4f dsb sy - 80033e4: 61bb str r3, [r7, #24] + 8006f24: f04f 0350 mov.w r3, #80 @ 0x50 + 8006f28: f383 8811 msr BASEPRI, r3 + 8006f2c: f3bf 8f6f isb sy + 8006f30: f3bf 8f4f dsb sy + 8006f34: 61bb str r3, [r7, #24] } - 80033e6: bf00 nop - 80033e8: bf00 nop - 80033ea: e7fd b.n 80033e8 + 8006f36: bf00 nop + 8006f38: bf00 nop + 8006f3a: e7fd b.n 8006f38 ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ - 80033ec: 697b ldr r3, [r7, #20] + 8006f3c: 697b ldr r3, [r7, #20] #endif /* configASSERT_DEFINED */ /* The address of a statically allocated queue was passed in, use it. The address of a statically allocated storage area was also passed in but is already set. */ pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ - 80033ee: 683b ldr r3, [r7, #0] - 80033f0: 62fb str r3, [r7, #44] @ 0x2c + 8006f3e: 683b ldr r3, [r7, #0] + 8006f40: 62fb str r3, [r7, #44] @ 0x2c if( pxNewQueue != NULL ) - 80033f2: 6afb ldr r3, [r7, #44] @ 0x2c - 80033f4: 2b00 cmp r3, #0 - 80033f6: d00d beq.n 8003414 + 8006f42: 6afb ldr r3, [r7, #44] @ 0x2c + 8006f44: 2b00 cmp r3, #0 + 8006f46: d00d beq.n 8006f64 #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* Queues can be allocated wither statically or dynamically, so note this queue was allocated statically in case the queue is later deleted. */ pxNewQueue->ucStaticallyAllocated = pdTRUE; - 80033f8: 6afb ldr r3, [r7, #44] @ 0x2c - 80033fa: 2201 movs r2, #1 - 80033fc: f883 2046 strb.w r2, [r3, #70] @ 0x46 + 8006f48: 6afb ldr r3, [r7, #44] @ 0x2c + 8006f4a: 2201 movs r2, #1 + 8006f4c: f883 2046 strb.w r2, [r3, #70] @ 0x46 } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); - 8003400: f897 2038 ldrb.w r2, [r7, #56] @ 0x38 - 8003404: 6afb ldr r3, [r7, #44] @ 0x2c - 8003406: 9300 str r3, [sp, #0] - 8003408: 4613 mov r3, r2 - 800340a: 687a ldr r2, [r7, #4] - 800340c: 68b9 ldr r1, [r7, #8] - 800340e: 68f8 ldr r0, [r7, #12] - 8003410: f000 f805 bl 800341e + 8006f50: f897 2038 ldrb.w r2, [r7, #56] @ 0x38 + 8006f54: 6afb ldr r3, [r7, #44] @ 0x2c + 8006f56: 9300 str r3, [sp, #0] + 8006f58: 4613 mov r3, r2 + 8006f5a: 687a ldr r2, [r7, #4] + 8006f5c: 68b9 ldr r1, [r7, #8] + 8006f5e: 68f8 ldr r0, [r7, #12] + 8006f60: f000 f840 bl 8006fe4 { traceQUEUE_CREATE_FAILED( ucQueueType ); mtCOVERAGE_TEST_MARKER(); } return pxNewQueue; - 8003414: 6afb ldr r3, [r7, #44] @ 0x2c + 8006f64: 6afb ldr r3, [r7, #44] @ 0x2c } - 8003416: 4618 mov r0, r3 - 8003418: 3730 adds r7, #48 @ 0x30 - 800341a: 46bd mov sp, r7 - 800341c: bd80 pop {r7, pc} + 8006f66: 4618 mov r0, r3 + 8006f68: 3730 adds r7, #48 @ 0x30 + 8006f6a: 46bd mov sp, r7 + 8006f6c: bd80 pop {r7, pc} -0800341e : +08006f6e : +/*-----------------------------------------------------------*/ + +#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) + { + 8006f6e: b580 push {r7, lr} + 8006f70: b08a sub sp, #40 @ 0x28 + 8006f72: af02 add r7, sp, #8 + 8006f74: 60f8 str r0, [r7, #12] + 8006f76: 60b9 str r1, [r7, #8] + 8006f78: 4613 mov r3, r2 + 8006f7a: 71fb strb r3, [r7, #7] + Queue_t *pxNewQueue; + size_t xQueueSizeInBytes; + uint8_t *pucQueueStorage; + + configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); + 8006f7c: 68fb ldr r3, [r7, #12] + 8006f7e: 2b00 cmp r3, #0 + 8006f80: d10b bne.n 8006f9a + __asm volatile + 8006f82: f04f 0350 mov.w r3, #80 @ 0x50 + 8006f86: f383 8811 msr BASEPRI, r3 + 8006f8a: f3bf 8f6f isb sy + 8006f8e: f3bf 8f4f dsb sy + 8006f92: 613b str r3, [r7, #16] +} + 8006f94: bf00 nop + 8006f96: bf00 nop + 8006f98: e7fd b.n 8006f96 + + /* Allocate enough space to hold the maximum number of items that + can be in the queue at any time. It is valid for uxItemSize to be + zero in the case the queue is used as a semaphore. */ + xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 8006f9a: 68fb ldr r3, [r7, #12] + 8006f9c: 68ba ldr r2, [r7, #8] + 8006f9e: fb02 f303 mul.w r3, r2, r3 + 8006fa2: 61fb str r3, [r7, #28] + alignment requirements of the Queue_t structure - which in this case + is an int8_t *. Therefore, whenever the stack alignment requirements + are greater than or equal to the pointer to char requirements the cast + is safe. In other cases alignment requirements are not strict (one or + two bytes). */ + pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */ + 8006fa4: 69fb ldr r3, [r7, #28] + 8006fa6: 3350 adds r3, #80 @ 0x50 + 8006fa8: 4618 mov r0, r3 + 8006faa: f002 fd97 bl 8009adc + 8006fae: 61b8 str r0, [r7, #24] + + if( pxNewQueue != NULL ) + 8006fb0: 69bb ldr r3, [r7, #24] + 8006fb2: 2b00 cmp r3, #0 + 8006fb4: d011 beq.n 8006fda + { + /* Jump past the queue structure to find the location of the queue + storage area. */ + pucQueueStorage = ( uint8_t * ) pxNewQueue; + 8006fb6: 69bb ldr r3, [r7, #24] + 8006fb8: 617b str r3, [r7, #20] + pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ + 8006fba: 697b ldr r3, [r7, #20] + 8006fbc: 3350 adds r3, #80 @ 0x50 + 8006fbe: 617b str r3, [r7, #20] + #if( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + /* Queues can be created either statically or dynamically, so + note this task was created dynamically in case it is later + deleted. */ + pxNewQueue->ucStaticallyAllocated = pdFALSE; + 8006fc0: 69bb ldr r3, [r7, #24] + 8006fc2: 2200 movs r2, #0 + 8006fc4: f883 2046 strb.w r2, [r3, #70] @ 0x46 + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); + 8006fc8: 79fa ldrb r2, [r7, #7] + 8006fca: 69bb ldr r3, [r7, #24] + 8006fcc: 9300 str r3, [sp, #0] + 8006fce: 4613 mov r3, r2 + 8006fd0: 697a ldr r2, [r7, #20] + 8006fd2: 68b9 ldr r1, [r7, #8] + 8006fd4: 68f8 ldr r0, [r7, #12] + 8006fd6: f000 f805 bl 8006fe4 + { + traceQUEUE_CREATE_FAILED( ucQueueType ); + mtCOVERAGE_TEST_MARKER(); + } + + return pxNewQueue; + 8006fda: 69bb ldr r3, [r7, #24] + } + 8006fdc: 4618 mov r0, r3 + 8006fde: 3720 adds r7, #32 + 8006fe0: 46bd mov sp, r7 + 8006fe2: bd80 pop {r7, pc} + +08006fe4 : #endif /* configSUPPORT_STATIC_ALLOCATION */ /*-----------------------------------------------------------*/ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) { - 800341e: b580 push {r7, lr} - 8003420: b084 sub sp, #16 - 8003422: af00 add r7, sp, #0 - 8003424: 60f8 str r0, [r7, #12] - 8003426: 60b9 str r1, [r7, #8] - 8003428: 607a str r2, [r7, #4] - 800342a: 70fb strb r3, [r7, #3] + 8006fe4: b580 push {r7, lr} + 8006fe6: b084 sub sp, #16 + 8006fe8: af00 add r7, sp, #0 + 8006fea: 60f8 str r0, [r7, #12] + 8006fec: 60b9 str r1, [r7, #8] + 8006fee: 607a str r2, [r7, #4] + 8006ff0: 70fb strb r3, [r7, #3] /* Remove compiler warnings about unused parameters should configUSE_TRACE_FACILITY not be set to 1. */ ( void ) ucQueueType; if( uxItemSize == ( UBaseType_t ) 0 ) - 800342c: 68bb ldr r3, [r7, #8] - 800342e: 2b00 cmp r3, #0 - 8003430: d103 bne.n 800343a + 8006ff2: 68bb ldr r3, [r7, #8] + 8006ff4: 2b00 cmp r3, #0 + 8006ff6: d103 bne.n 8007000 { /* No RAM was allocated for the queue storage area, but PC head cannot be set to NULL because NULL is used as a key to say the queue is used as a mutex. Therefore just set pcHead to point to the queue as a benign value that is known to be within the memory map. */ pxNewQueue->pcHead = ( int8_t * ) pxNewQueue; - 8003432: 69bb ldr r3, [r7, #24] - 8003434: 69ba ldr r2, [r7, #24] - 8003436: 601a str r2, [r3, #0] - 8003438: e002 b.n 8003440 + 8006ff8: 69bb ldr r3, [r7, #24] + 8006ffa: 69ba ldr r2, [r7, #24] + 8006ffc: 601a str r2, [r3, #0] + 8006ffe: e002 b.n 8007006 } else { /* Set the head to the start of the queue storage area. */ pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage; - 800343a: 69bb ldr r3, [r7, #24] - 800343c: 687a ldr r2, [r7, #4] - 800343e: 601a str r2, [r3, #0] + 8007000: 69bb ldr r3, [r7, #24] + 8007002: 687a ldr r2, [r7, #4] + 8007004: 601a str r2, [r3, #0] } /* Initialise the queue members as described where the queue type is defined. */ pxNewQueue->uxLength = uxQueueLength; - 8003440: 69bb ldr r3, [r7, #24] - 8003442: 68fa ldr r2, [r7, #12] - 8003444: 63da str r2, [r3, #60] @ 0x3c + 8007006: 69bb ldr r3, [r7, #24] + 8007008: 68fa ldr r2, [r7, #12] + 800700a: 63da str r2, [r3, #60] @ 0x3c pxNewQueue->uxItemSize = uxItemSize; - 8003446: 69bb ldr r3, [r7, #24] - 8003448: 68ba ldr r2, [r7, #8] - 800344a: 641a str r2, [r3, #64] @ 0x40 + 800700c: 69bb ldr r3, [r7, #24] + 800700e: 68ba ldr r2, [r7, #8] + 8007010: 641a str r2, [r3, #64] @ 0x40 ( void ) xQueueGenericReset( pxNewQueue, pdTRUE ); - 800344c: 2101 movs r1, #1 - 800344e: 69b8 ldr r0, [r7, #24] - 8003450: f7ff fefe bl 8003250 + 8007012: 2101 movs r1, #1 + 8007014: 69b8 ldr r0, [r7, #24] + 8007016: f7ff fec3 bl 8006da0 #if ( configUSE_TRACE_FACILITY == 1 ) { pxNewQueue->ucQueueType = ucQueueType; - 8003454: 69bb ldr r3, [r7, #24] - 8003456: 78fa ldrb r2, [r7, #3] - 8003458: f883 204c strb.w r2, [r3, #76] @ 0x4c + 800701a: 69bb ldr r3, [r7, #24] + 800701c: 78fa ldrb r2, [r7, #3] + 800701e: f883 204c strb.w r2, [r3, #76] @ 0x4c pxNewQueue->pxQueueSetContainer = NULL; } #endif /* configUSE_QUEUE_SETS */ traceQUEUE_CREATE( pxNewQueue ); } - 800345c: bf00 nop - 800345e: 3710 adds r7, #16 - 8003460: 46bd mov sp, r7 - 8003462: bd80 pop {r7, pc} + 8007022: bf00 nop + 8007024: 3710 adds r7, #16 + 8007026: 46bd mov sp, r7 + 8007028: bd80 pop {r7, pc} -08003464 : +0800702a : +/*-----------------------------------------------------------*/ + +#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + + QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) + { + 800702a: b580 push {r7, lr} + 800702c: b08a sub sp, #40 @ 0x28 + 800702e: af02 add r7, sp, #8 + 8007030: 60f8 str r0, [r7, #12] + 8007032: 60b9 str r1, [r7, #8] + 8007034: 607a str r2, [r7, #4] + QueueHandle_t xHandle; + + configASSERT( uxMaxCount != 0 ); + 8007036: 68fb ldr r3, [r7, #12] + 8007038: 2b00 cmp r3, #0 + 800703a: d10b bne.n 8007054 + __asm volatile + 800703c: f04f 0350 mov.w r3, #80 @ 0x50 + 8007040: f383 8811 msr BASEPRI, r3 + 8007044: f3bf 8f6f isb sy + 8007048: f3bf 8f4f dsb sy + 800704c: 61bb str r3, [r7, #24] +} + 800704e: bf00 nop + 8007050: bf00 nop + 8007052: e7fd b.n 8007050 + configASSERT( uxInitialCount <= uxMaxCount ); + 8007054: 68ba ldr r2, [r7, #8] + 8007056: 68fb ldr r3, [r7, #12] + 8007058: 429a cmp r2, r3 + 800705a: d90b bls.n 8007074 + __asm volatile + 800705c: f04f 0350 mov.w r3, #80 @ 0x50 + 8007060: f383 8811 msr BASEPRI, r3 + 8007064: f3bf 8f6f isb sy + 8007068: f3bf 8f4f dsb sy + 800706c: 617b str r3, [r7, #20] +} + 800706e: bf00 nop + 8007070: bf00 nop + 8007072: e7fd b.n 8007070 + + xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE ); + 8007074: 2302 movs r3, #2 + 8007076: 9300 str r3, [sp, #0] + 8007078: 687b ldr r3, [r7, #4] + 800707a: 2200 movs r2, #0 + 800707c: 2100 movs r1, #0 + 800707e: 68f8 ldr r0, [r7, #12] + 8007080: f7ff fef8 bl 8006e74 + 8007084: 61f8 str r0, [r7, #28] + + if( xHandle != NULL ) + 8007086: 69fb ldr r3, [r7, #28] + 8007088: 2b00 cmp r3, #0 + 800708a: d002 beq.n 8007092 + { + ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount; + 800708c: 69fb ldr r3, [r7, #28] + 800708e: 68ba ldr r2, [r7, #8] + 8007090: 639a str r2, [r3, #56] @ 0x38 + else + { + traceCREATE_COUNTING_SEMAPHORE_FAILED(); + } + + return xHandle; + 8007092: 69fb ldr r3, [r7, #28] + } + 8007094: 4618 mov r0, r3 + 8007096: 3720 adds r7, #32 + 8007098: 46bd mov sp, r7 + 800709a: bd80 pop {r7, pc} + +0800709c : +/*-----------------------------------------------------------*/ + +#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + + QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) + { + 800709c: b580 push {r7, lr} + 800709e: b086 sub sp, #24 + 80070a0: af00 add r7, sp, #0 + 80070a2: 6078 str r0, [r7, #4] + 80070a4: 6039 str r1, [r7, #0] + QueueHandle_t xHandle; + + configASSERT( uxMaxCount != 0 ); + 80070a6: 687b ldr r3, [r7, #4] + 80070a8: 2b00 cmp r3, #0 + 80070aa: d10b bne.n 80070c4 + __asm volatile + 80070ac: f04f 0350 mov.w r3, #80 @ 0x50 + 80070b0: f383 8811 msr BASEPRI, r3 + 80070b4: f3bf 8f6f isb sy + 80070b8: f3bf 8f4f dsb sy + 80070bc: 613b str r3, [r7, #16] +} + 80070be: bf00 nop + 80070c0: bf00 nop + 80070c2: e7fd b.n 80070c0 + configASSERT( uxInitialCount <= uxMaxCount ); + 80070c4: 683a ldr r2, [r7, #0] + 80070c6: 687b ldr r3, [r7, #4] + 80070c8: 429a cmp r2, r3 + 80070ca: d90b bls.n 80070e4 + __asm volatile + 80070cc: f04f 0350 mov.w r3, #80 @ 0x50 + 80070d0: f383 8811 msr BASEPRI, r3 + 80070d4: f3bf 8f6f isb sy + 80070d8: f3bf 8f4f dsb sy + 80070dc: 60fb str r3, [r7, #12] +} + 80070de: bf00 nop + 80070e0: bf00 nop + 80070e2: e7fd b.n 80070e0 + + xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE ); + 80070e4: 2202 movs r2, #2 + 80070e6: 2100 movs r1, #0 + 80070e8: 6878 ldr r0, [r7, #4] + 80070ea: f7ff ff40 bl 8006f6e + 80070ee: 6178 str r0, [r7, #20] + + if( xHandle != NULL ) + 80070f0: 697b ldr r3, [r7, #20] + 80070f2: 2b00 cmp r3, #0 + 80070f4: d002 beq.n 80070fc + { + ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount; + 80070f6: 697b ldr r3, [r7, #20] + 80070f8: 683a ldr r2, [r7, #0] + 80070fa: 639a str r2, [r3, #56] @ 0x38 + else + { + traceCREATE_COUNTING_SEMAPHORE_FAILED(); + } + + return xHandle; + 80070fc: 697b ldr r3, [r7, #20] + } + 80070fe: 4618 mov r0, r3 + 8007100: 3718 adds r7, #24 + 8007102: 46bd mov sp, r7 + 8007104: bd80 pop {r7, pc} + ... + +08007108 : #endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) { - 8003464: b580 push {r7, lr} - 8003466: b08e sub sp, #56 @ 0x38 - 8003468: af00 add r7, sp, #0 - 800346a: 60f8 str r0, [r7, #12] - 800346c: 60b9 str r1, [r7, #8] - 800346e: 607a str r2, [r7, #4] - 8003470: 603b str r3, [r7, #0] + 8007108: b580 push {r7, lr} + 800710a: b08e sub sp, #56 @ 0x38 + 800710c: af00 add r7, sp, #0 + 800710e: 60f8 str r0, [r7, #12] + 8007110: 60b9 str r1, [r7, #8] + 8007112: 607a str r2, [r7, #4] + 8007114: 603b str r3, [r7, #0] BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired; - 8003472: 2300 movs r3, #0 - 8003474: 637b str r3, [r7, #52] @ 0x34 + 8007116: 2300 movs r3, #0 + 8007118: 637b str r3, [r7, #52] @ 0x34 TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; - 8003476: 68fb ldr r3, [r7, #12] - 8003478: 633b str r3, [r7, #48] @ 0x30 + 800711a: 68fb ldr r3, [r7, #12] + 800711c: 633b str r3, [r7, #48] @ 0x30 configASSERT( pxQueue ); - 800347a: 6b3b ldr r3, [r7, #48] @ 0x30 - 800347c: 2b00 cmp r3, #0 - 800347e: d10b bne.n 8003498 + 800711e: 6b3b ldr r3, [r7, #48] @ 0x30 + 8007120: 2b00 cmp r3, #0 + 8007122: d10b bne.n 800713c __asm volatile - 8003480: f04f 0350 mov.w r3, #80 @ 0x50 - 8003484: f383 8811 msr BASEPRI, r3 - 8003488: f3bf 8f6f isb sy - 800348c: f3bf 8f4f dsb sy - 8003490: 62bb str r3, [r7, #40] @ 0x28 + 8007124: f04f 0350 mov.w r3, #80 @ 0x50 + 8007128: f383 8811 msr BASEPRI, r3 + 800712c: f3bf 8f6f isb sy + 8007130: f3bf 8f4f dsb sy + 8007134: 62bb str r3, [r7, #40] @ 0x28 } - 8003492: bf00 nop - 8003494: bf00 nop - 8003496: e7fd b.n 8003494 + 8007136: bf00 nop + 8007138: bf00 nop + 800713a: e7fd b.n 8007138 configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); - 8003498: 68bb ldr r3, [r7, #8] - 800349a: 2b00 cmp r3, #0 - 800349c: d103 bne.n 80034a6 - 800349e: 6b3b ldr r3, [r7, #48] @ 0x30 - 80034a0: 6c1b ldr r3, [r3, #64] @ 0x40 - 80034a2: 2b00 cmp r3, #0 - 80034a4: d101 bne.n 80034aa - 80034a6: 2301 movs r3, #1 - 80034a8: e000 b.n 80034ac - 80034aa: 2300 movs r3, #0 - 80034ac: 2b00 cmp r3, #0 - 80034ae: d10b bne.n 80034c8 + 800713c: 68bb ldr r3, [r7, #8] + 800713e: 2b00 cmp r3, #0 + 8007140: d103 bne.n 800714a + 8007142: 6b3b ldr r3, [r7, #48] @ 0x30 + 8007144: 6c1b ldr r3, [r3, #64] @ 0x40 + 8007146: 2b00 cmp r3, #0 + 8007148: d101 bne.n 800714e + 800714a: 2301 movs r3, #1 + 800714c: e000 b.n 8007150 + 800714e: 2300 movs r3, #0 + 8007150: 2b00 cmp r3, #0 + 8007152: d10b bne.n 800716c __asm volatile - 80034b0: f04f 0350 mov.w r3, #80 @ 0x50 - 80034b4: f383 8811 msr BASEPRI, r3 - 80034b8: f3bf 8f6f isb sy - 80034bc: f3bf 8f4f dsb sy - 80034c0: 627b str r3, [r7, #36] @ 0x24 + 8007154: f04f 0350 mov.w r3, #80 @ 0x50 + 8007158: f383 8811 msr BASEPRI, r3 + 800715c: f3bf 8f6f isb sy + 8007160: f3bf 8f4f dsb sy + 8007164: 627b str r3, [r7, #36] @ 0x24 } - 80034c2: bf00 nop - 80034c4: bf00 nop - 80034c6: e7fd b.n 80034c4 + 8007166: bf00 nop + 8007168: bf00 nop + 800716a: e7fd b.n 8007168 configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); - 80034c8: 683b ldr r3, [r7, #0] - 80034ca: 2b02 cmp r3, #2 - 80034cc: d103 bne.n 80034d6 - 80034ce: 6b3b ldr r3, [r7, #48] @ 0x30 - 80034d0: 6bdb ldr r3, [r3, #60] @ 0x3c - 80034d2: 2b01 cmp r3, #1 - 80034d4: d101 bne.n 80034da - 80034d6: 2301 movs r3, #1 - 80034d8: e000 b.n 80034dc - 80034da: 2300 movs r3, #0 - 80034dc: 2b00 cmp r3, #0 - 80034de: d10b bne.n 80034f8 + 800716c: 683b ldr r3, [r7, #0] + 800716e: 2b02 cmp r3, #2 + 8007170: d103 bne.n 800717a + 8007172: 6b3b ldr r3, [r7, #48] @ 0x30 + 8007174: 6bdb ldr r3, [r3, #60] @ 0x3c + 8007176: 2b01 cmp r3, #1 + 8007178: d101 bne.n 800717e + 800717a: 2301 movs r3, #1 + 800717c: e000 b.n 8007180 + 800717e: 2300 movs r3, #0 + 8007180: 2b00 cmp r3, #0 + 8007182: d10b bne.n 800719c __asm volatile - 80034e0: f04f 0350 mov.w r3, #80 @ 0x50 - 80034e4: f383 8811 msr BASEPRI, r3 - 80034e8: f3bf 8f6f isb sy - 80034ec: f3bf 8f4f dsb sy - 80034f0: 623b str r3, [r7, #32] + 8007184: f04f 0350 mov.w r3, #80 @ 0x50 + 8007188: f383 8811 msr BASEPRI, r3 + 800718c: f3bf 8f6f isb sy + 8007190: f3bf 8f4f dsb sy + 8007194: 623b str r3, [r7, #32] } - 80034f2: bf00 nop - 80034f4: bf00 nop - 80034f6: e7fd b.n 80034f4 + 8007196: bf00 nop + 8007198: bf00 nop + 800719a: e7fd b.n 8007198 #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); - 80034f8: f001 f9fc bl 80048f4 - 80034fc: 4603 mov r3, r0 - 80034fe: 2b00 cmp r3, #0 - 8003500: d102 bne.n 8003508 - 8003502: 687b ldr r3, [r7, #4] - 8003504: 2b00 cmp r3, #0 - 8003506: d101 bne.n 800350c - 8003508: 2301 movs r3, #1 - 800350a: e000 b.n 800350e - 800350c: 2300 movs r3, #0 - 800350e: 2b00 cmp r3, #0 - 8003510: d10b bne.n 800352a + 800719c: f001 fc4e bl 8008a3c + 80071a0: 4603 mov r3, r0 + 80071a2: 2b00 cmp r3, #0 + 80071a4: d102 bne.n 80071ac + 80071a6: 687b ldr r3, [r7, #4] + 80071a8: 2b00 cmp r3, #0 + 80071aa: d101 bne.n 80071b0 + 80071ac: 2301 movs r3, #1 + 80071ae: e000 b.n 80071b2 + 80071b0: 2300 movs r3, #0 + 80071b2: 2b00 cmp r3, #0 + 80071b4: d10b bne.n 80071ce __asm volatile - 8003512: f04f 0350 mov.w r3, #80 @ 0x50 - 8003516: f383 8811 msr BASEPRI, r3 - 800351a: f3bf 8f6f isb sy - 800351e: f3bf 8f4f dsb sy - 8003522: 61fb str r3, [r7, #28] + 80071b6: f04f 0350 mov.w r3, #80 @ 0x50 + 80071ba: f383 8811 msr BASEPRI, r3 + 80071be: f3bf 8f6f isb sy + 80071c2: f3bf 8f4f dsb sy + 80071c6: 61fb str r3, [r7, #28] } - 8003524: bf00 nop - 8003526: bf00 nop - 8003528: e7fd b.n 8003526 + 80071c8: bf00 nop + 80071ca: bf00 nop + 80071cc: e7fd b.n 80071ca /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); - 800352a: f001 ff4d bl 80053c8 + 80071ce: f002 fb63 bl 8009898 { /* Is there room on the queue now? The running task must be the highest priority task wanting to access the queue. If the head item in the queue is to be overwritten then it does not matter if the queue is full. */ if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) - 800352e: 6b3b ldr r3, [r7, #48] @ 0x30 - 8003530: 6b9a ldr r2, [r3, #56] @ 0x38 - 8003532: 6b3b ldr r3, [r7, #48] @ 0x30 - 8003534: 6bdb ldr r3, [r3, #60] @ 0x3c - 8003536: 429a cmp r2, r3 - 8003538: d302 bcc.n 8003540 - 800353a: 683b ldr r3, [r7, #0] - 800353c: 2b02 cmp r3, #2 - 800353e: d129 bne.n 8003594 + 80071d2: 6b3b ldr r3, [r7, #48] @ 0x30 + 80071d4: 6b9a ldr r2, [r3, #56] @ 0x38 + 80071d6: 6b3b ldr r3, [r7, #48] @ 0x30 + 80071d8: 6bdb ldr r3, [r3, #60] @ 0x3c + 80071da: 429a cmp r2, r3 + 80071dc: d302 bcc.n 80071e4 + 80071de: 683b ldr r3, [r7, #0] + 80071e0: 2b02 cmp r3, #2 + 80071e2: d129 bne.n 8007238 } } } #else /* configUSE_QUEUE_SETS */ { xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); - 8003540: 683a ldr r2, [r7, #0] - 8003542: 68b9 ldr r1, [r7, #8] - 8003544: 6b38 ldr r0, [r7, #48] @ 0x30 - 8003546: f000 fa0f bl 8003968 - 800354a: 62f8 str r0, [r7, #44] @ 0x2c + 80071e4: 683a ldr r2, [r7, #0] + 80071e6: 68b9 ldr r1, [r7, #8] + 80071e8: 6b38 ldr r0, [r7, #48] @ 0x30 + 80071ea: f000 fc6d bl 8007ac8 + 80071ee: 62f8 str r0, [r7, #44] @ 0x2c /* If there was a task waiting for data to arrive on the queue then unblock it now. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) - 800354c: 6b3b ldr r3, [r7, #48] @ 0x30 - 800354e: 6a5b ldr r3, [r3, #36] @ 0x24 - 8003550: 2b00 cmp r3, #0 - 8003552: d010 beq.n 8003576 + 80071f0: 6b3b ldr r3, [r7, #48] @ 0x30 + 80071f2: 6a5b ldr r3, [r3, #36] @ 0x24 + 80071f4: 2b00 cmp r3, #0 + 80071f6: d010 beq.n 800721a { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - 8003554: 6b3b ldr r3, [r7, #48] @ 0x30 - 8003556: 3324 adds r3, #36 @ 0x24 - 8003558: 4618 mov r0, r3 - 800355a: f001 f805 bl 8004568 - 800355e: 4603 mov r3, r0 - 8003560: 2b00 cmp r3, #0 - 8003562: d013 beq.n 800358c + 80071f8: 6b3b ldr r3, [r7, #48] @ 0x30 + 80071fa: 3324 adds r3, #36 @ 0x24 + 80071fc: 4618 mov r0, r3 + 80071fe: f001 fa57 bl 80086b0 + 8007202: 4603 mov r3, r0 + 8007204: 2b00 cmp r3, #0 + 8007206: d013 beq.n 8007230 { /* The unblocked task has a priority higher than our own so yield immediately. Yes it is ok to do this from within the critical section - the kernel takes care of that. */ queueYIELD_IF_USING_PREEMPTION(); - 8003564: 4b3f ldr r3, [pc, #252] @ (8003664 ) - 8003566: f04f 5280 mov.w r2, #268435456 @ 0x10000000 - 800356a: 601a str r2, [r3, #0] - 800356c: f3bf 8f4f dsb sy - 8003570: f3bf 8f6f isb sy - 8003574: e00a b.n 800358c + 8007208: 4b3f ldr r3, [pc, #252] @ (8007308 ) + 800720a: f04f 5280 mov.w r2, #268435456 @ 0x10000000 + 800720e: 601a str r2, [r3, #0] + 8007210: f3bf 8f4f dsb sy + 8007214: f3bf 8f6f isb sy + 8007218: e00a b.n 8007230 else { mtCOVERAGE_TEST_MARKER(); } } else if( xYieldRequired != pdFALSE ) - 8003576: 6afb ldr r3, [r7, #44] @ 0x2c - 8003578: 2b00 cmp r3, #0 - 800357a: d007 beq.n 800358c + 800721a: 6afb ldr r3, [r7, #44] @ 0x2c + 800721c: 2b00 cmp r3, #0 + 800721e: d007 beq.n 8007230 { /* This path is a special case that will only get executed if the task was holding multiple mutexes and the mutexes were given back in an order that is different to that in which they were taken. */ queueYIELD_IF_USING_PREEMPTION(); - 800357c: 4b39 ldr r3, [pc, #228] @ (8003664 ) - 800357e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 - 8003582: 601a str r2, [r3, #0] - 8003584: f3bf 8f4f dsb sy - 8003588: f3bf 8f6f isb sy + 8007220: 4b39 ldr r3, [pc, #228] @ (8007308 ) + 8007222: f04f 5280 mov.w r2, #268435456 @ 0x10000000 + 8007226: 601a str r2, [r3, #0] + 8007228: f3bf 8f4f dsb sy + 800722c: f3bf 8f6f isb sy mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_QUEUE_SETS */ taskEXIT_CRITICAL(); - 800358c: f001 ff4e bl 800542c + 8007230: f002 fb64 bl 80098fc return pdPASS; - 8003590: 2301 movs r3, #1 - 8003592: e063 b.n 800365c + 8007234: 2301 movs r3, #1 + 8007236: e063 b.n 8007300 } else { if( xTicksToWait == ( TickType_t ) 0 ) - 8003594: 687b ldr r3, [r7, #4] - 8003596: 2b00 cmp r3, #0 - 8003598: d103 bne.n 80035a2 + 8007238: 687b ldr r3, [r7, #4] + 800723a: 2b00 cmp r3, #0 + 800723c: d103 bne.n 8007246 { /* The queue was full and no block time is specified (or the block time has expired) so leave now. */ taskEXIT_CRITICAL(); - 800359a: f001 ff47 bl 800542c + 800723e: f002 fb5d bl 80098fc /* Return to the original privilege level before exiting the function. */ traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; - 800359e: 2300 movs r3, #0 - 80035a0: e05c b.n 800365c + 8007242: 2300 movs r3, #0 + 8007244: e05c b.n 8007300 } else if( xEntryTimeSet == pdFALSE ) - 80035a2: 6b7b ldr r3, [r7, #52] @ 0x34 - 80035a4: 2b00 cmp r3, #0 - 80035a6: d106 bne.n 80035b6 + 8007246: 6b7b ldr r3, [r7, #52] @ 0x34 + 8007248: 2b00 cmp r3, #0 + 800724a: d106 bne.n 800725a { /* The queue was full and a block time was specified so configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); - 80035a8: f107 0314 add.w r3, r7, #20 - 80035ac: 4618 mov r0, r3 - 80035ae: f001 f83f bl 8004630 + 800724c: f107 0314 add.w r3, r7, #20 + 8007250: 4618 mov r0, r3 + 8007252: f001 fa91 bl 8008778 xEntryTimeSet = pdTRUE; - 80035b2: 2301 movs r3, #1 - 80035b4: 637b str r3, [r7, #52] @ 0x34 + 8007256: 2301 movs r3, #1 + 8007258: 637b str r3, [r7, #52] @ 0x34 /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); - 80035b6: f001 ff39 bl 800542c + 800725a: f002 fb4f bl 80098fc /* Interrupts and other tasks can send to and receive from the queue now the critical section has been exited. */ vTaskSuspendAll(); - 80035ba: f000 fda7 bl 800410c + 800725e: f000 fff9 bl 8008254 prvLockQueue( pxQueue ); - 80035be: f001 ff03 bl 80053c8 - 80035c2: 6b3b ldr r3, [r7, #48] @ 0x30 - 80035c4: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 - 80035c8: b25b sxtb r3, r3 - 80035ca: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff - 80035ce: d103 bne.n 80035d8 - 80035d0: 6b3b ldr r3, [r7, #48] @ 0x30 - 80035d2: 2200 movs r2, #0 - 80035d4: f883 2044 strb.w r2, [r3, #68] @ 0x44 - 80035d8: 6b3b ldr r3, [r7, #48] @ 0x30 - 80035da: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 - 80035de: b25b sxtb r3, r3 - 80035e0: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff - 80035e4: d103 bne.n 80035ee - 80035e6: 6b3b ldr r3, [r7, #48] @ 0x30 - 80035e8: 2200 movs r2, #0 - 80035ea: f883 2045 strb.w r2, [r3, #69] @ 0x45 - 80035ee: f001 ff1d bl 800542c + 8007262: f002 fb19 bl 8009898 + 8007266: 6b3b ldr r3, [r7, #48] @ 0x30 + 8007268: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 + 800726c: b25b sxtb r3, r3 + 800726e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8007272: d103 bne.n 800727c + 8007274: 6b3b ldr r3, [r7, #48] @ 0x30 + 8007276: 2200 movs r2, #0 + 8007278: f883 2044 strb.w r2, [r3, #68] @ 0x44 + 800727c: 6b3b ldr r3, [r7, #48] @ 0x30 + 800727e: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 + 8007282: b25b sxtb r3, r3 + 8007284: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8007288: d103 bne.n 8007292 + 800728a: 6b3b ldr r3, [r7, #48] @ 0x30 + 800728c: 2200 movs r2, #0 + 800728e: f883 2045 strb.w r2, [r3, #69] @ 0x45 + 8007292: f002 fb33 bl 80098fc /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) - 80035f2: 1d3a adds r2, r7, #4 - 80035f4: f107 0314 add.w r3, r7, #20 - 80035f8: 4611 mov r1, r2 - 80035fa: 4618 mov r0, r3 - 80035fc: f001 f82e bl 800465c - 8003600: 4603 mov r3, r0 - 8003602: 2b00 cmp r3, #0 - 8003604: d124 bne.n 8003650 + 8007296: 1d3a adds r2, r7, #4 + 8007298: f107 0314 add.w r3, r7, #20 + 800729c: 4611 mov r1, r2 + 800729e: 4618 mov r0, r3 + 80072a0: f001 fa80 bl 80087a4 + 80072a4: 4603 mov r3, r0 + 80072a6: 2b00 cmp r3, #0 + 80072a8: d124 bne.n 80072f4 { if( prvIsQueueFull( pxQueue ) != pdFALSE ) - 8003606: 6b38 ldr r0, [r7, #48] @ 0x30 - 8003608: f000 faa6 bl 8003b58 - 800360c: 4603 mov r3, r0 - 800360e: 2b00 cmp r3, #0 - 8003610: d018 beq.n 8003644 + 80072aa: 6b38 ldr r0, [r7, #48] @ 0x30 + 80072ac: f000 fd04 bl 8007cb8 + 80072b0: 4603 mov r3, r0 + 80072b2: 2b00 cmp r3, #0 + 80072b4: d018 beq.n 80072e8 { traceBLOCKING_ON_QUEUE_SEND( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); - 8003612: 6b3b ldr r3, [r7, #48] @ 0x30 - 8003614: 3310 adds r3, #16 - 8003616: 687a ldr r2, [r7, #4] - 8003618: 4611 mov r1, r2 - 800361a: 4618 mov r0, r3 - 800361c: f000 ff52 bl 80044c4 + 80072b6: 6b3b ldr r3, [r7, #48] @ 0x30 + 80072b8: 3310 adds r3, #16 + 80072ba: 687a ldr r2, [r7, #4] + 80072bc: 4611 mov r1, r2 + 80072be: 4618 mov r0, r3 + 80072c0: f001 f9a4 bl 800860c /* Unlocking the queue means queue events can effect the event list. It is possible that interrupts occurring now remove this task from the event list again - but as the scheduler is suspended the task will go onto the pending ready last instead of the actual ready list. */ prvUnlockQueue( pxQueue ); - 8003620: 6b38 ldr r0, [r7, #48] @ 0x30 - 8003622: f000 fa31 bl 8003a88 + 80072c4: 6b38 ldr r0, [r7, #48] @ 0x30 + 80072c6: f000 fc8f bl 8007be8 /* Resuming the scheduler will move tasks from the pending ready list into the ready list - so it is feasible that this task is already in a ready list before it yields - in which case the yield will not cause a context switch unless there is also a higher priority task in the pending ready list. */ if( xTaskResumeAll() == pdFALSE ) - 8003626: f000 fd7f bl 8004128 - 800362a: 4603 mov r3, r0 - 800362c: 2b00 cmp r3, #0 - 800362e: f47f af7c bne.w 800352a + 80072ca: f000 ffd1 bl 8008270 + 80072ce: 4603 mov r3, r0 + 80072d0: 2b00 cmp r3, #0 + 80072d2: f47f af7c bne.w 80071ce { portYIELD_WITHIN_API(); - 8003632: 4b0c ldr r3, [pc, #48] @ (8003664 ) - 8003634: f04f 5280 mov.w r2, #268435456 @ 0x10000000 - 8003638: 601a str r2, [r3, #0] - 800363a: f3bf 8f4f dsb sy - 800363e: f3bf 8f6f isb sy - 8003642: e772 b.n 800352a + 80072d6: 4b0c ldr r3, [pc, #48] @ (8007308 ) + 80072d8: f04f 5280 mov.w r2, #268435456 @ 0x10000000 + 80072dc: 601a str r2, [r3, #0] + 80072de: f3bf 8f4f dsb sy + 80072e2: f3bf 8f6f isb sy + 80072e6: e772 b.n 80071ce } } else { /* Try again. */ prvUnlockQueue( pxQueue ); - 8003644: 6b38 ldr r0, [r7, #48] @ 0x30 - 8003646: f000 fa1f bl 8003a88 + 80072e8: 6b38 ldr r0, [r7, #48] @ 0x30 + 80072ea: f000 fc7d bl 8007be8 ( void ) xTaskResumeAll(); - 800364a: f000 fd6d bl 8004128 - 800364e: e76c b.n 800352a + 80072ee: f000 ffbf bl 8008270 + 80072f2: e76c b.n 80071ce } } else { /* The timeout has expired. */ prvUnlockQueue( pxQueue ); - 8003650: 6b38 ldr r0, [r7, #48] @ 0x30 - 8003652: f000 fa19 bl 8003a88 + 80072f4: 6b38 ldr r0, [r7, #48] @ 0x30 + 80072f6: f000 fc77 bl 8007be8 ( void ) xTaskResumeAll(); - 8003656: f000 fd67 bl 8004128 + 80072fa: f000 ffb9 bl 8008270 traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; - 800365a: 2300 movs r3, #0 + 80072fe: 2300 movs r3, #0 } } /*lint -restore */ } - 800365c: 4618 mov r0, r3 - 800365e: 3738 adds r7, #56 @ 0x38 - 8003660: 46bd mov sp, r7 - 8003662: bd80 pop {r7, pc} - 8003664: e000ed04 .word 0xe000ed04 + 8007300: 4618 mov r0, r3 + 8007302: 3738 adds r7, #56 @ 0x38 + 8007304: 46bd mov sp, r7 + 8007306: bd80 pop {r7, pc} + 8007308: e000ed04 .word 0xe000ed04 -08003668 : +0800730c : /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) { - 8003668: b580 push {r7, lr} - 800366a: b090 sub sp, #64 @ 0x40 - 800366c: af00 add r7, sp, #0 - 800366e: 60f8 str r0, [r7, #12] - 8003670: 60b9 str r1, [r7, #8] - 8003672: 607a str r2, [r7, #4] - 8003674: 603b str r3, [r7, #0] + 800730c: b580 push {r7, lr} + 800730e: b090 sub sp, #64 @ 0x40 + 8007310: af00 add r7, sp, #0 + 8007312: 60f8 str r0, [r7, #12] + 8007314: 60b9 str r1, [r7, #8] + 8007316: 607a str r2, [r7, #4] + 8007318: 603b str r3, [r7, #0] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; - 8003676: 68fb ldr r3, [r7, #12] - 8003678: 63bb str r3, [r7, #56] @ 0x38 + 800731a: 68fb ldr r3, [r7, #12] + 800731c: 63bb str r3, [r7, #56] @ 0x38 configASSERT( pxQueue ); - 800367a: 6bbb ldr r3, [r7, #56] @ 0x38 - 800367c: 2b00 cmp r3, #0 - 800367e: d10b bne.n 8003698 + 800731e: 6bbb ldr r3, [r7, #56] @ 0x38 + 8007320: 2b00 cmp r3, #0 + 8007322: d10b bne.n 800733c __asm volatile - 8003680: f04f 0350 mov.w r3, #80 @ 0x50 - 8003684: f383 8811 msr BASEPRI, r3 - 8003688: f3bf 8f6f isb sy - 800368c: f3bf 8f4f dsb sy - 8003690: 62bb str r3, [r7, #40] @ 0x28 + 8007324: f04f 0350 mov.w r3, #80 @ 0x50 + 8007328: f383 8811 msr BASEPRI, r3 + 800732c: f3bf 8f6f isb sy + 8007330: f3bf 8f4f dsb sy + 8007334: 62bb str r3, [r7, #40] @ 0x28 } - 8003692: bf00 nop - 8003694: bf00 nop - 8003696: e7fd b.n 8003694 + 8007336: bf00 nop + 8007338: bf00 nop + 800733a: e7fd b.n 8007338 configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); - 8003698: 68bb ldr r3, [r7, #8] - 800369a: 2b00 cmp r3, #0 - 800369c: d103 bne.n 80036a6 - 800369e: 6bbb ldr r3, [r7, #56] @ 0x38 - 80036a0: 6c1b ldr r3, [r3, #64] @ 0x40 - 80036a2: 2b00 cmp r3, #0 - 80036a4: d101 bne.n 80036aa - 80036a6: 2301 movs r3, #1 - 80036a8: e000 b.n 80036ac - 80036aa: 2300 movs r3, #0 - 80036ac: 2b00 cmp r3, #0 - 80036ae: d10b bne.n 80036c8 + 800733c: 68bb ldr r3, [r7, #8] + 800733e: 2b00 cmp r3, #0 + 8007340: d103 bne.n 800734a + 8007342: 6bbb ldr r3, [r7, #56] @ 0x38 + 8007344: 6c1b ldr r3, [r3, #64] @ 0x40 + 8007346: 2b00 cmp r3, #0 + 8007348: d101 bne.n 800734e + 800734a: 2301 movs r3, #1 + 800734c: e000 b.n 8007350 + 800734e: 2300 movs r3, #0 + 8007350: 2b00 cmp r3, #0 + 8007352: d10b bne.n 800736c __asm volatile - 80036b0: f04f 0350 mov.w r3, #80 @ 0x50 - 80036b4: f383 8811 msr BASEPRI, r3 - 80036b8: f3bf 8f6f isb sy - 80036bc: f3bf 8f4f dsb sy - 80036c0: 627b str r3, [r7, #36] @ 0x24 + 8007354: f04f 0350 mov.w r3, #80 @ 0x50 + 8007358: f383 8811 msr BASEPRI, r3 + 800735c: f3bf 8f6f isb sy + 8007360: f3bf 8f4f dsb sy + 8007364: 627b str r3, [r7, #36] @ 0x24 } - 80036c2: bf00 nop - 80036c4: bf00 nop - 80036c6: e7fd b.n 80036c4 + 8007366: bf00 nop + 8007368: bf00 nop + 800736a: e7fd b.n 8007368 configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); - 80036c8: 683b ldr r3, [r7, #0] - 80036ca: 2b02 cmp r3, #2 - 80036cc: d103 bne.n 80036d6 - 80036ce: 6bbb ldr r3, [r7, #56] @ 0x38 - 80036d0: 6bdb ldr r3, [r3, #60] @ 0x3c - 80036d2: 2b01 cmp r3, #1 - 80036d4: d101 bne.n 80036da - 80036d6: 2301 movs r3, #1 - 80036d8: e000 b.n 80036dc - 80036da: 2300 movs r3, #0 - 80036dc: 2b00 cmp r3, #0 - 80036de: d10b bne.n 80036f8 + 800736c: 683b ldr r3, [r7, #0] + 800736e: 2b02 cmp r3, #2 + 8007370: d103 bne.n 800737a + 8007372: 6bbb ldr r3, [r7, #56] @ 0x38 + 8007374: 6bdb ldr r3, [r3, #60] @ 0x3c + 8007376: 2b01 cmp r3, #1 + 8007378: d101 bne.n 800737e + 800737a: 2301 movs r3, #1 + 800737c: e000 b.n 8007380 + 800737e: 2300 movs r3, #0 + 8007380: 2b00 cmp r3, #0 + 8007382: d10b bne.n 800739c __asm volatile - 80036e0: f04f 0350 mov.w r3, #80 @ 0x50 - 80036e4: f383 8811 msr BASEPRI, r3 - 80036e8: f3bf 8f6f isb sy - 80036ec: f3bf 8f4f dsb sy - 80036f0: 623b str r3, [r7, #32] + 8007384: f04f 0350 mov.w r3, #80 @ 0x50 + 8007388: f383 8811 msr BASEPRI, r3 + 800738c: f3bf 8f6f isb sy + 8007390: f3bf 8f4f dsb sy + 8007394: 623b str r3, [r7, #32] } - 80036f2: bf00 nop - 80036f4: bf00 nop - 80036f6: e7fd b.n 80036f4 + 8007396: bf00 nop + 8007398: bf00 nop + 800739a: e7fd b.n 8007398 that have been assigned a priority at or (logically) below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); - 80036f8: f001 ff46 bl 8005588 + 800739c: f002 fb5c bl 8009a58 __asm volatile - 80036fc: f3ef 8211 mrs r2, BASEPRI - 8003700: f04f 0350 mov.w r3, #80 @ 0x50 - 8003704: f383 8811 msr BASEPRI, r3 - 8003708: f3bf 8f6f isb sy - 800370c: f3bf 8f4f dsb sy - 8003710: 61fa str r2, [r7, #28] - 8003712: 61bb str r3, [r7, #24] + 80073a0: f3ef 8211 mrs r2, BASEPRI + 80073a4: f04f 0350 mov.w r3, #80 @ 0x50 + 80073a8: f383 8811 msr BASEPRI, r3 + 80073ac: f3bf 8f6f isb sy + 80073b0: f3bf 8f4f dsb sy + 80073b4: 61fa str r2, [r7, #28] + 80073b6: 61bb str r3, [r7, #24] return ulOriginalBASEPRI; - 8003714: 69fb ldr r3, [r7, #28] + 80073b8: 69fb ldr r3, [r7, #28] /* Similar to xQueueGenericSend, except without blocking if there is no room in the queue. Also don't directly wake a task that was blocked on a queue read, instead return a flag to say whether a context switch is required or not (i.e. has a task with a higher priority than us been woken by this post). */ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); - 8003716: 637b str r3, [r7, #52] @ 0x34 + 80073ba: 637b str r3, [r7, #52] @ 0x34 { if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) - 8003718: 6bbb ldr r3, [r7, #56] @ 0x38 - 800371a: 6b9a ldr r2, [r3, #56] @ 0x38 - 800371c: 6bbb ldr r3, [r7, #56] @ 0x38 - 800371e: 6bdb ldr r3, [r3, #60] @ 0x3c - 8003720: 429a cmp r2, r3 - 8003722: d302 bcc.n 800372a - 8003724: 683b ldr r3, [r7, #0] - 8003726: 2b02 cmp r3, #2 - 8003728: d12f bne.n 800378a + 80073bc: 6bbb ldr r3, [r7, #56] @ 0x38 + 80073be: 6b9a ldr r2, [r3, #56] @ 0x38 + 80073c0: 6bbb ldr r3, [r7, #56] @ 0x38 + 80073c2: 6bdb ldr r3, [r3, #60] @ 0x3c + 80073c4: 429a cmp r2, r3 + 80073c6: d302 bcc.n 80073ce + 80073c8: 683b ldr r3, [r7, #0] + 80073ca: 2b02 cmp r3, #2 + 80073cc: d12f bne.n 800742e { const int8_t cTxLock = pxQueue->cTxLock; - 800372a: 6bbb ldr r3, [r7, #56] @ 0x38 - 800372c: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 - 8003730: f887 3033 strb.w r3, [r7, #51] @ 0x33 + 80073ce: 6bbb ldr r3, [r7, #56] @ 0x38 + 80073d0: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 + 80073d4: f887 3033 strb.w r3, [r7, #51] @ 0x33 const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; - 8003734: 6bbb ldr r3, [r7, #56] @ 0x38 - 8003736: 6b9b ldr r3, [r3, #56] @ 0x38 - 8003738: 62fb str r3, [r7, #44] @ 0x2c + 80073d8: 6bbb ldr r3, [r7, #56] @ 0x38 + 80073da: 6b9b ldr r3, [r3, #56] @ 0x38 + 80073dc: 62fb str r3, [r7, #44] @ 0x2c /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a semaphore or mutex. That means prvCopyDataToQueue() cannot result in a task disinheriting a priority and prvCopyDataToQueue() can be called here even though the disinherit function does not check if the scheduler is suspended before accessing the ready lists. */ ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); - 800373a: 683a ldr r2, [r7, #0] - 800373c: 68b9 ldr r1, [r7, #8] - 800373e: 6bb8 ldr r0, [r7, #56] @ 0x38 - 8003740: f000 f912 bl 8003968 + 80073de: 683a ldr r2, [r7, #0] + 80073e0: 68b9 ldr r1, [r7, #8] + 80073e2: 6bb8 ldr r0, [r7, #56] @ 0x38 + 80073e4: f000 fb70 bl 8007ac8 /* The event list is not altered if the queue is locked. This will be done when the queue is unlocked later. */ if( cTxLock == queueUNLOCKED ) - 8003744: f997 3033 ldrsb.w r3, [r7, #51] @ 0x33 - 8003748: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff - 800374c: d112 bne.n 8003774 + 80073e8: f997 3033 ldrsb.w r3, [r7, #51] @ 0x33 + 80073ec: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 80073f0: d112 bne.n 8007418 } } } #else /* configUSE_QUEUE_SETS */ { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) - 800374e: 6bbb ldr r3, [r7, #56] @ 0x38 - 8003750: 6a5b ldr r3, [r3, #36] @ 0x24 - 8003752: 2b00 cmp r3, #0 - 8003754: d016 beq.n 8003784 + 80073f2: 6bbb ldr r3, [r7, #56] @ 0x38 + 80073f4: 6a5b ldr r3, [r3, #36] @ 0x24 + 80073f6: 2b00 cmp r3, #0 + 80073f8: d016 beq.n 8007428 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - 8003756: 6bbb ldr r3, [r7, #56] @ 0x38 - 8003758: 3324 adds r3, #36 @ 0x24 - 800375a: 4618 mov r0, r3 - 800375c: f000 ff04 bl 8004568 - 8003760: 4603 mov r3, r0 - 8003762: 2b00 cmp r3, #0 - 8003764: d00e beq.n 8003784 + 80073fa: 6bbb ldr r3, [r7, #56] @ 0x38 + 80073fc: 3324 adds r3, #36 @ 0x24 + 80073fe: 4618 mov r0, r3 + 8007400: f001 f956 bl 80086b0 + 8007404: 4603 mov r3, r0 + 8007406: 2b00 cmp r3, #0 + 8007408: d00e beq.n 8007428 { /* The task waiting has a higher priority so record that a context switch is required. */ if( pxHigherPriorityTaskWoken != NULL ) - 8003766: 687b ldr r3, [r7, #4] - 8003768: 2b00 cmp r3, #0 - 800376a: d00b beq.n 8003784 + 800740a: 687b ldr r3, [r7, #4] + 800740c: 2b00 cmp r3, #0 + 800740e: d00b beq.n 8007428 { *pxHigherPriorityTaskWoken = pdTRUE; - 800376c: 687b ldr r3, [r7, #4] - 800376e: 2201 movs r2, #1 - 8003770: 601a str r2, [r3, #0] - 8003772: e007 b.n 8003784 + 8007410: 687b ldr r3, [r7, #4] + 8007412: 2201 movs r2, #1 + 8007414: 601a str r2, [r3, #0] + 8007416: e007 b.n 8007428 } else { /* Increment the lock count so the task that unlocks the queue knows that data was posted while it was locked. */ pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 ); - 8003774: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 - 8003778: 3301 adds r3, #1 - 800377a: b2db uxtb r3, r3 - 800377c: b25a sxtb r2, r3 - 800377e: 6bbb ldr r3, [r7, #56] @ 0x38 - 8003780: f883 2045 strb.w r2, [r3, #69] @ 0x45 + 8007418: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 + 800741c: 3301 adds r3, #1 + 800741e: b2db uxtb r3, r3 + 8007420: b25a sxtb r2, r3 + 8007422: 6bbb ldr r3, [r7, #56] @ 0x38 + 8007424: f883 2045 strb.w r2, [r3, #69] @ 0x45 } xReturn = pdPASS; - 8003784: 2301 movs r3, #1 - 8003786: 63fb str r3, [r7, #60] @ 0x3c + 8007428: 2301 movs r3, #1 + 800742a: 63fb str r3, [r7, #60] @ 0x3c { - 8003788: e001 b.n 800378e + 800742c: e001 b.n 8007432 } else { traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); xReturn = errQUEUE_FULL; - 800378a: 2300 movs r3, #0 - 800378c: 63fb str r3, [r7, #60] @ 0x3c - 800378e: 6b7b ldr r3, [r7, #52] @ 0x34 - 8003790: 617b str r3, [r7, #20] + 800742e: 2300 movs r3, #0 + 8007430: 63fb str r3, [r7, #60] @ 0x3c + 8007432: 6b7b ldr r3, [r7, #52] @ 0x34 + 8007434: 617b str r3, [r7, #20] __asm volatile - 8003792: 697b ldr r3, [r7, #20] - 8003794: f383 8811 msr BASEPRI, r3 + 8007436: 697b ldr r3, [r7, #20] + 8007438: f383 8811 msr BASEPRI, r3 } - 8003798: bf00 nop + 800743c: bf00 nop } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; - 800379a: 6bfb ldr r3, [r7, #60] @ 0x3c + 800743e: 6bfb ldr r3, [r7, #60] @ 0x3c } - 800379c: 4618 mov r0, r3 - 800379e: 3740 adds r7, #64 @ 0x40 - 80037a0: 46bd mov sp, r7 - 80037a2: bd80 pop {r7, pc} + 8007440: 4618 mov r0, r3 + 8007442: 3740 adds r7, #64 @ 0x40 + 8007444: 46bd mov sp, r7 + 8007446: bd80 pop {r7, pc} -080037a4 : - return xReturn; +08007448 : +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken ) +{ + 8007448: b580 push {r7, lr} + 800744a: b08e sub sp, #56 @ 0x38 + 800744c: af00 add r7, sp, #0 + 800744e: 6078 str r0, [r7, #4] + 8007450: 6039 str r1, [r7, #0] +BaseType_t xReturn; +UBaseType_t uxSavedInterruptStatus; +Queue_t * const pxQueue = xQueue; + 8007452: 687b ldr r3, [r7, #4] + 8007454: 633b str r3, [r7, #48] @ 0x30 + item size is 0. Don't directly wake a task that was blocked on a queue + read, instead return a flag to say whether a context switch is required or + not (i.e. has a task with a higher priority than us been woken by this + post). */ + + configASSERT( pxQueue ); + 8007456: 6b3b ldr r3, [r7, #48] @ 0x30 + 8007458: 2b00 cmp r3, #0 + 800745a: d10b bne.n 8007474 + __asm volatile + 800745c: f04f 0350 mov.w r3, #80 @ 0x50 + 8007460: f383 8811 msr BASEPRI, r3 + 8007464: f3bf 8f6f isb sy + 8007468: f3bf 8f4f dsb sy + 800746c: 623b str r3, [r7, #32] } + 800746e: bf00 nop + 8007470: bf00 nop + 8007472: e7fd b.n 8007470 + + /* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR() + if the item size is not 0. */ + configASSERT( pxQueue->uxItemSize == 0 ); + 8007474: 6b3b ldr r3, [r7, #48] @ 0x30 + 8007476: 6c1b ldr r3, [r3, #64] @ 0x40 + 8007478: 2b00 cmp r3, #0 + 800747a: d00b beq.n 8007494 + __asm volatile + 800747c: f04f 0350 mov.w r3, #80 @ 0x50 + 8007480: f383 8811 msr BASEPRI, r3 + 8007484: f3bf 8f6f isb sy + 8007488: f3bf 8f4f dsb sy + 800748c: 61fb str r3, [r7, #28] +} + 800748e: bf00 nop + 8007490: bf00 nop + 8007492: e7fd b.n 8007490 + + /* Normally a mutex would not be given from an interrupt, especially if + there is a mutex holder, as priority inheritance makes no sense for an + interrupts, only tasks. */ + configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) ); + 8007494: 6b3b ldr r3, [r7, #48] @ 0x30 + 8007496: 681b ldr r3, [r3, #0] + 8007498: 2b00 cmp r3, #0 + 800749a: d103 bne.n 80074a4 + 800749c: 6b3b ldr r3, [r7, #48] @ 0x30 + 800749e: 689b ldr r3, [r3, #8] + 80074a0: 2b00 cmp r3, #0 + 80074a2: d101 bne.n 80074a8 + 80074a4: 2301 movs r3, #1 + 80074a6: e000 b.n 80074aa + 80074a8: 2300 movs r3, #0 + 80074aa: 2b00 cmp r3, #0 + 80074ac: d10b bne.n 80074c6 + __asm volatile + 80074ae: f04f 0350 mov.w r3, #80 @ 0x50 + 80074b2: f383 8811 msr BASEPRI, r3 + 80074b6: f3bf 8f6f isb sy + 80074ba: f3bf 8f4f dsb sy + 80074be: 61bb str r3, [r7, #24] +} + 80074c0: bf00 nop + 80074c2: bf00 nop + 80074c4: e7fd b.n 80074c2 + that have been assigned a priority at or (logically) below the maximum + system call interrupt priority. FreeRTOS maintains a separate interrupt + safe API to ensure interrupt entry is as fast and as simple as possible. + More information (albeit Cortex-M specific) is provided on the following + link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + 80074c6: f002 fac7 bl 8009a58 + __asm volatile + 80074ca: f3ef 8211 mrs r2, BASEPRI + 80074ce: f04f 0350 mov.w r3, #80 @ 0x50 + 80074d2: f383 8811 msr BASEPRI, r3 + 80074d6: f3bf 8f6f isb sy + 80074da: f3bf 8f4f dsb sy + 80074de: 617a str r2, [r7, #20] + 80074e0: 613b str r3, [r7, #16] + return ulOriginalBASEPRI; + 80074e2: 697b ldr r3, [r7, #20] + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + 80074e4: 62fb str r3, [r7, #44] @ 0x2c + { + const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; + 80074e6: 6b3b ldr r3, [r7, #48] @ 0x30 + 80074e8: 6b9b ldr r3, [r3, #56] @ 0x38 + 80074ea: 62bb str r3, [r7, #40] @ 0x28 + + /* When the queue is used to implement a semaphore no data is ever + moved through the queue but it is still valid to see if the queue 'has + space'. */ + if( uxMessagesWaiting < pxQueue->uxLength ) + 80074ec: 6b3b ldr r3, [r7, #48] @ 0x30 + 80074ee: 6bdb ldr r3, [r3, #60] @ 0x3c + 80074f0: 6aba ldr r2, [r7, #40] @ 0x28 + 80074f2: 429a cmp r2, r3 + 80074f4: d22b bcs.n 800754e + { + const int8_t cTxLock = pxQueue->cTxLock; + 80074f6: 6b3b ldr r3, [r7, #48] @ 0x30 + 80074f8: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 + 80074fc: f887 3027 strb.w r3, [r7, #39] @ 0x27 + holder - and if there is a mutex holder then the mutex cannot be + given from an ISR. As this is the ISR version of the function it + can be assumed there is no mutex holder and no need to determine if + priority disinheritance is needed. Simply increase the count of + messages (semaphores) available. */ + pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; + 8007500: 6abb ldr r3, [r7, #40] @ 0x28 + 8007502: 1c5a adds r2, r3, #1 + 8007504: 6b3b ldr r3, [r7, #48] @ 0x30 + 8007506: 639a str r2, [r3, #56] @ 0x38 + + /* The event list is not altered if the queue is locked. This will + be done when the queue is unlocked later. */ + if( cTxLock == queueUNLOCKED ) + 8007508: f997 3027 ldrsb.w r3, [r7, #39] @ 0x27 + 800750c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8007510: d112 bne.n 8007538 + } + } + } + #else /* configUSE_QUEUE_SETS */ + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + 8007512: 6b3b ldr r3, [r7, #48] @ 0x30 + 8007514: 6a5b ldr r3, [r3, #36] @ 0x24 + 8007516: 2b00 cmp r3, #0 + 8007518: d016 beq.n 8007548 + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + 800751a: 6b3b ldr r3, [r7, #48] @ 0x30 + 800751c: 3324 adds r3, #36 @ 0x24 + 800751e: 4618 mov r0, r3 + 8007520: f001 f8c6 bl 80086b0 + 8007524: 4603 mov r3, r0 + 8007526: 2b00 cmp r3, #0 + 8007528: d00e beq.n 8007548 + { + /* The task waiting has a higher priority so record that a + context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + 800752a: 683b ldr r3, [r7, #0] + 800752c: 2b00 cmp r3, #0 + 800752e: d00b beq.n 8007548 + { + *pxHigherPriorityTaskWoken = pdTRUE; + 8007530: 683b ldr r3, [r7, #0] + 8007532: 2201 movs r2, #1 + 8007534: 601a str r2, [r3, #0] + 8007536: e007 b.n 8007548 + } + else + { + /* Increment the lock count so the task that unlocks the queue + knows that data was posted while it was locked. */ + pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 ); + 8007538: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 + 800753c: 3301 adds r3, #1 + 800753e: b2db uxtb r3, r3 + 8007540: b25a sxtb r2, r3 + 8007542: 6b3b ldr r3, [r7, #48] @ 0x30 + 8007544: f883 2045 strb.w r2, [r3, #69] @ 0x45 + } + + xReturn = pdPASS; + 8007548: 2301 movs r3, #1 + 800754a: 637b str r3, [r7, #52] @ 0x34 + 800754c: e001 b.n 8007552 + } + else + { + traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); + xReturn = errQUEUE_FULL; + 800754e: 2300 movs r3, #0 + 8007550: 637b str r3, [r7, #52] @ 0x34 + 8007552: 6afb ldr r3, [r7, #44] @ 0x2c + 8007554: 60fb str r3, [r7, #12] + __asm volatile + 8007556: 68fb ldr r3, [r7, #12] + 8007558: f383 8811 msr BASEPRI, r3 +} + 800755c: bf00 nop + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; + 800755e: 6b7b ldr r3, [r7, #52] @ 0x34 +} + 8007560: 4618 mov r0, r3 + 8007562: 3738 adds r7, #56 @ 0x38 + 8007564: 46bd mov sp, r7 + 8007566: bd80 pop {r7, pc} + +08007568 : /*-----------------------------------------------------------*/ BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) { - 80037a4: b580 push {r7, lr} - 80037a6: b08c sub sp, #48 @ 0x30 - 80037a8: af00 add r7, sp, #0 - 80037aa: 60f8 str r0, [r7, #12] - 80037ac: 60b9 str r1, [r7, #8] - 80037ae: 607a str r2, [r7, #4] + 8007568: b580 push {r7, lr} + 800756a: b08c sub sp, #48 @ 0x30 + 800756c: af00 add r7, sp, #0 + 800756e: 60f8 str r0, [r7, #12] + 8007570: 60b9 str r1, [r7, #8] + 8007572: 607a str r2, [r7, #4] BaseType_t xEntryTimeSet = pdFALSE; - 80037b0: 2300 movs r3, #0 - 80037b2: 62fb str r3, [r7, #44] @ 0x2c + 8007574: 2300 movs r3, #0 + 8007576: 62fb str r3, [r7, #44] @ 0x2c TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; - 80037b4: 68fb ldr r3, [r7, #12] - 80037b6: 62bb str r3, [r7, #40] @ 0x28 + 8007578: 68fb ldr r3, [r7, #12] + 800757a: 62bb str r3, [r7, #40] @ 0x28 /* Check the pointer is not NULL. */ configASSERT( ( pxQueue ) ); - 80037b8: 6abb ldr r3, [r7, #40] @ 0x28 - 80037ba: 2b00 cmp r3, #0 - 80037bc: d10b bne.n 80037d6 + 800757c: 6abb ldr r3, [r7, #40] @ 0x28 + 800757e: 2b00 cmp r3, #0 + 8007580: d10b bne.n 800759a __asm volatile - 80037be: f04f 0350 mov.w r3, #80 @ 0x50 - 80037c2: f383 8811 msr BASEPRI, r3 - 80037c6: f3bf 8f6f isb sy - 80037ca: f3bf 8f4f dsb sy - 80037ce: 623b str r3, [r7, #32] + 8007582: f04f 0350 mov.w r3, #80 @ 0x50 + 8007586: f383 8811 msr BASEPRI, r3 + 800758a: f3bf 8f6f isb sy + 800758e: f3bf 8f4f dsb sy + 8007592: 623b str r3, [r7, #32] } - 80037d0: bf00 nop - 80037d2: bf00 nop - 80037d4: e7fd b.n 80037d2 + 8007594: bf00 nop + 8007596: bf00 nop + 8007598: e7fd b.n 8007596 /* The buffer into which data is received can only be NULL if the data size is zero (so no data is copied into the buffer. */ configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); - 80037d6: 68bb ldr r3, [r7, #8] - 80037d8: 2b00 cmp r3, #0 - 80037da: d103 bne.n 80037e4 - 80037dc: 6abb ldr r3, [r7, #40] @ 0x28 - 80037de: 6c1b ldr r3, [r3, #64] @ 0x40 - 80037e0: 2b00 cmp r3, #0 - 80037e2: d101 bne.n 80037e8 - 80037e4: 2301 movs r3, #1 - 80037e6: e000 b.n 80037ea - 80037e8: 2300 movs r3, #0 - 80037ea: 2b00 cmp r3, #0 - 80037ec: d10b bne.n 8003806 + 800759a: 68bb ldr r3, [r7, #8] + 800759c: 2b00 cmp r3, #0 + 800759e: d103 bne.n 80075a8 + 80075a0: 6abb ldr r3, [r7, #40] @ 0x28 + 80075a2: 6c1b ldr r3, [r3, #64] @ 0x40 + 80075a4: 2b00 cmp r3, #0 + 80075a6: d101 bne.n 80075ac + 80075a8: 2301 movs r3, #1 + 80075aa: e000 b.n 80075ae + 80075ac: 2300 movs r3, #0 + 80075ae: 2b00 cmp r3, #0 + 80075b0: d10b bne.n 80075ca __asm volatile - 80037ee: f04f 0350 mov.w r3, #80 @ 0x50 - 80037f2: f383 8811 msr BASEPRI, r3 - 80037f6: f3bf 8f6f isb sy - 80037fa: f3bf 8f4f dsb sy - 80037fe: 61fb str r3, [r7, #28] + 80075b2: f04f 0350 mov.w r3, #80 @ 0x50 + 80075b6: f383 8811 msr BASEPRI, r3 + 80075ba: f3bf 8f6f isb sy + 80075be: f3bf 8f4f dsb sy + 80075c2: 61fb str r3, [r7, #28] } - 8003800: bf00 nop - 8003802: bf00 nop - 8003804: e7fd b.n 8003802 + 80075c4: bf00 nop + 80075c6: bf00 nop + 80075c8: e7fd b.n 80075c6 /* Cannot block if the scheduler is suspended. */ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); - 8003806: f001 f875 bl 80048f4 - 800380a: 4603 mov r3, r0 - 800380c: 2b00 cmp r3, #0 - 800380e: d102 bne.n 8003816 - 8003810: 687b ldr r3, [r7, #4] - 8003812: 2b00 cmp r3, #0 - 8003814: d101 bne.n 800381a - 8003816: 2301 movs r3, #1 - 8003818: e000 b.n 800381c - 800381a: 2300 movs r3, #0 - 800381c: 2b00 cmp r3, #0 - 800381e: d10b bne.n 8003838 + 80075ca: f001 fa37 bl 8008a3c + 80075ce: 4603 mov r3, r0 + 80075d0: 2b00 cmp r3, #0 + 80075d2: d102 bne.n 80075da + 80075d4: 687b ldr r3, [r7, #4] + 80075d6: 2b00 cmp r3, #0 + 80075d8: d101 bne.n 80075de + 80075da: 2301 movs r3, #1 + 80075dc: e000 b.n 80075e0 + 80075de: 2300 movs r3, #0 + 80075e0: 2b00 cmp r3, #0 + 80075e2: d10b bne.n 80075fc __asm volatile - 8003820: f04f 0350 mov.w r3, #80 @ 0x50 - 8003824: f383 8811 msr BASEPRI, r3 - 8003828: f3bf 8f6f isb sy - 800382c: f3bf 8f4f dsb sy - 8003830: 61bb str r3, [r7, #24] + 80075e4: f04f 0350 mov.w r3, #80 @ 0x50 + 80075e8: f383 8811 msr BASEPRI, r3 + 80075ec: f3bf 8f6f isb sy + 80075f0: f3bf 8f4f dsb sy + 80075f4: 61bb str r3, [r7, #24] } - 8003832: bf00 nop - 8003834: bf00 nop - 8003836: e7fd b.n 8003834 + 80075f6: bf00 nop + 80075f8: bf00 nop + 80075fa: e7fd b.n 80075f8 /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); - 8003838: f001 fdc6 bl 80053c8 + 80075fc: f002 f94c bl 8009898 { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; - 800383c: 6abb ldr r3, [r7, #40] @ 0x28 - 800383e: 6b9b ldr r3, [r3, #56] @ 0x38 - 8003840: 627b str r3, [r7, #36] @ 0x24 + 8007600: 6abb ldr r3, [r7, #40] @ 0x28 + 8007602: 6b9b ldr r3, [r3, #56] @ 0x38 + 8007604: 627b str r3, [r7, #36] @ 0x24 /* Is there data in the queue now? To be running the calling task must be the highest priority task wanting to access the queue. */ if( uxMessagesWaiting > ( UBaseType_t ) 0 ) - 8003842: 6a7b ldr r3, [r7, #36] @ 0x24 - 8003844: 2b00 cmp r3, #0 - 8003846: d01f beq.n 8003888 + 8007606: 6a7b ldr r3, [r7, #36] @ 0x24 + 8007608: 2b00 cmp r3, #0 + 800760a: d01f beq.n 800764c { /* Data available, remove one item. */ prvCopyDataFromQueue( pxQueue, pvBuffer ); - 8003848: 68b9 ldr r1, [r7, #8] - 800384a: 6ab8 ldr r0, [r7, #40] @ 0x28 - 800384c: f000 f8f6 bl 8003a3c + 800760c: 68b9 ldr r1, [r7, #8] + 800760e: 6ab8 ldr r0, [r7, #40] @ 0x28 + 8007610: f000 fac4 bl 8007b9c traceQUEUE_RECEIVE( pxQueue ); pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; - 8003850: 6a7b ldr r3, [r7, #36] @ 0x24 - 8003852: 1e5a subs r2, r3, #1 - 8003854: 6abb ldr r3, [r7, #40] @ 0x28 - 8003856: 639a str r2, [r3, #56] @ 0x38 + 8007614: 6a7b ldr r3, [r7, #36] @ 0x24 + 8007616: 1e5a subs r2, r3, #1 + 8007618: 6abb ldr r3, [r7, #40] @ 0x28 + 800761a: 639a str r2, [r3, #56] @ 0x38 /* There is now space in the queue, were any tasks waiting to post to the queue? If so, unblock the highest priority waiting task. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) - 8003858: 6abb ldr r3, [r7, #40] @ 0x28 - 800385a: 691b ldr r3, [r3, #16] - 800385c: 2b00 cmp r3, #0 - 800385e: d00f beq.n 8003880 + 800761c: 6abb ldr r3, [r7, #40] @ 0x28 + 800761e: 691b ldr r3, [r3, #16] + 8007620: 2b00 cmp r3, #0 + 8007622: d00f beq.n 8007644 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - 8003860: 6abb ldr r3, [r7, #40] @ 0x28 - 8003862: 3310 adds r3, #16 - 8003864: 4618 mov r0, r3 - 8003866: f000 fe7f bl 8004568 - 800386a: 4603 mov r3, r0 - 800386c: 2b00 cmp r3, #0 - 800386e: d007 beq.n 8003880 + 8007624: 6abb ldr r3, [r7, #40] @ 0x28 + 8007626: 3310 adds r3, #16 + 8007628: 4618 mov r0, r3 + 800762a: f001 f841 bl 80086b0 + 800762e: 4603 mov r3, r0 + 8007630: 2b00 cmp r3, #0 + 8007632: d007 beq.n 8007644 { queueYIELD_IF_USING_PREEMPTION(); - 8003870: 4b3c ldr r3, [pc, #240] @ (8003964 ) - 8003872: f04f 5280 mov.w r2, #268435456 @ 0x10000000 - 8003876: 601a str r2, [r3, #0] - 8003878: f3bf 8f4f dsb sy - 800387c: f3bf 8f6f isb sy + 8007634: 4b3c ldr r3, [pc, #240] @ (8007728 ) + 8007636: f04f 5280 mov.w r2, #268435456 @ 0x10000000 + 800763a: 601a str r2, [r3, #0] + 800763c: f3bf 8f4f dsb sy + 8007640: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } taskEXIT_CRITICAL(); - 8003880: f001 fdd4 bl 800542c + 8007644: f002 f95a bl 80098fc return pdPASS; - 8003884: 2301 movs r3, #1 - 8003886: e069 b.n 800395c + 8007648: 2301 movs r3, #1 + 800764a: e069 b.n 8007720 } else { if( xTicksToWait == ( TickType_t ) 0 ) - 8003888: 687b ldr r3, [r7, #4] - 800388a: 2b00 cmp r3, #0 - 800388c: d103 bne.n 8003896 + 800764c: 687b ldr r3, [r7, #4] + 800764e: 2b00 cmp r3, #0 + 8007650: d103 bne.n 800765a { /* The queue was empty and no block time is specified (or the block time has expired) so leave now. */ taskEXIT_CRITICAL(); - 800388e: f001 fdcd bl 800542c + 8007652: f002 f953 bl 80098fc traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; - 8003892: 2300 movs r3, #0 - 8003894: e062 b.n 800395c + 8007656: 2300 movs r3, #0 + 8007658: e062 b.n 8007720 } else if( xEntryTimeSet == pdFALSE ) - 8003896: 6afb ldr r3, [r7, #44] @ 0x2c - 8003898: 2b00 cmp r3, #0 - 800389a: d106 bne.n 80038aa + 800765a: 6afb ldr r3, [r7, #44] @ 0x2c + 800765c: 2b00 cmp r3, #0 + 800765e: d106 bne.n 800766e { /* The queue was empty and a block time was specified so configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); - 800389c: f107 0310 add.w r3, r7, #16 - 80038a0: 4618 mov r0, r3 - 80038a2: f000 fec5 bl 8004630 + 8007660: f107 0310 add.w r3, r7, #16 + 8007664: 4618 mov r0, r3 + 8007666: f001 f887 bl 8008778 xEntryTimeSet = pdTRUE; - 80038a6: 2301 movs r3, #1 - 80038a8: 62fb str r3, [r7, #44] @ 0x2c + 800766a: 2301 movs r3, #1 + 800766c: 62fb str r3, [r7, #44] @ 0x2c /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); - 80038aa: f001 fdbf bl 800542c + 800766e: f002 f945 bl 80098fc /* Interrupts and other tasks can send to and receive from the queue now the critical section has been exited. */ vTaskSuspendAll(); - 80038ae: f000 fc2d bl 800410c + 8007672: f000 fdef bl 8008254 prvLockQueue( pxQueue ); - 80038b2: f001 fd89 bl 80053c8 - 80038b6: 6abb ldr r3, [r7, #40] @ 0x28 - 80038b8: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 - 80038bc: b25b sxtb r3, r3 - 80038be: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff - 80038c2: d103 bne.n 80038cc - 80038c4: 6abb ldr r3, [r7, #40] @ 0x28 - 80038c6: 2200 movs r2, #0 - 80038c8: f883 2044 strb.w r2, [r3, #68] @ 0x44 - 80038cc: 6abb ldr r3, [r7, #40] @ 0x28 - 80038ce: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 - 80038d2: b25b sxtb r3, r3 - 80038d4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff - 80038d8: d103 bne.n 80038e2 - 80038da: 6abb ldr r3, [r7, #40] @ 0x28 - 80038dc: 2200 movs r2, #0 - 80038de: f883 2045 strb.w r2, [r3, #69] @ 0x45 - 80038e2: f001 fda3 bl 800542c + 8007676: f002 f90f bl 8009898 + 800767a: 6abb ldr r3, [r7, #40] @ 0x28 + 800767c: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 + 8007680: b25b sxtb r3, r3 + 8007682: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8007686: d103 bne.n 8007690 + 8007688: 6abb ldr r3, [r7, #40] @ 0x28 + 800768a: 2200 movs r2, #0 + 800768c: f883 2044 strb.w r2, [r3, #68] @ 0x44 + 8007690: 6abb ldr r3, [r7, #40] @ 0x28 + 8007692: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 + 8007696: b25b sxtb r3, r3 + 8007698: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 800769c: d103 bne.n 80076a6 + 800769e: 6abb ldr r3, [r7, #40] @ 0x28 + 80076a0: 2200 movs r2, #0 + 80076a2: f883 2045 strb.w r2, [r3, #69] @ 0x45 + 80076a6: f002 f929 bl 80098fc /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) - 80038e6: 1d3a adds r2, r7, #4 - 80038e8: f107 0310 add.w r3, r7, #16 - 80038ec: 4611 mov r1, r2 - 80038ee: 4618 mov r0, r3 - 80038f0: f000 feb4 bl 800465c - 80038f4: 4603 mov r3, r0 - 80038f6: 2b00 cmp r3, #0 - 80038f8: d123 bne.n 8003942 + 80076aa: 1d3a adds r2, r7, #4 + 80076ac: f107 0310 add.w r3, r7, #16 + 80076b0: 4611 mov r1, r2 + 80076b2: 4618 mov r0, r3 + 80076b4: f001 f876 bl 80087a4 + 80076b8: 4603 mov r3, r0 + 80076ba: 2b00 cmp r3, #0 + 80076bc: d123 bne.n 8007706 { /* The timeout has not expired. If the queue is still empty place the task on the list of tasks waiting to receive from the queue. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) - 80038fa: 6ab8 ldr r0, [r7, #40] @ 0x28 - 80038fc: f000 f916 bl 8003b2c - 8003900: 4603 mov r3, r0 - 8003902: 2b00 cmp r3, #0 - 8003904: d017 beq.n 8003936 + 80076be: 6ab8 ldr r0, [r7, #40] @ 0x28 + 80076c0: f000 fae4 bl 8007c8c + 80076c4: 4603 mov r3, r0 + 80076c6: 2b00 cmp r3, #0 + 80076c8: d017 beq.n 80076fa { traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); - 8003906: 6abb ldr r3, [r7, #40] @ 0x28 - 8003908: 3324 adds r3, #36 @ 0x24 - 800390a: 687a ldr r2, [r7, #4] - 800390c: 4611 mov r1, r2 - 800390e: 4618 mov r0, r3 - 8003910: f000 fdd8 bl 80044c4 + 80076ca: 6abb ldr r3, [r7, #40] @ 0x28 + 80076cc: 3324 adds r3, #36 @ 0x24 + 80076ce: 687a ldr r2, [r7, #4] + 80076d0: 4611 mov r1, r2 + 80076d2: 4618 mov r0, r3 + 80076d4: f000 ff9a bl 800860c prvUnlockQueue( pxQueue ); - 8003914: 6ab8 ldr r0, [r7, #40] @ 0x28 - 8003916: f000 f8b7 bl 8003a88 + 80076d8: 6ab8 ldr r0, [r7, #40] @ 0x28 + 80076da: f000 fa85 bl 8007be8 if( xTaskResumeAll() == pdFALSE ) - 800391a: f000 fc05 bl 8004128 - 800391e: 4603 mov r3, r0 - 8003920: 2b00 cmp r3, #0 - 8003922: d189 bne.n 8003838 + 80076de: f000 fdc7 bl 8008270 + 80076e2: 4603 mov r3, r0 + 80076e4: 2b00 cmp r3, #0 + 80076e6: d189 bne.n 80075fc { portYIELD_WITHIN_API(); - 8003924: 4b0f ldr r3, [pc, #60] @ (8003964 ) - 8003926: f04f 5280 mov.w r2, #268435456 @ 0x10000000 - 800392a: 601a str r2, [r3, #0] - 800392c: f3bf 8f4f dsb sy - 8003930: f3bf 8f6f isb sy - 8003934: e780 b.n 8003838 + 80076e8: 4b0f ldr r3, [pc, #60] @ (8007728 ) + 80076ea: f04f 5280 mov.w r2, #268435456 @ 0x10000000 + 80076ee: 601a str r2, [r3, #0] + 80076f0: f3bf 8f4f dsb sy + 80076f4: f3bf 8f6f isb sy + 80076f8: e780 b.n 80075fc } else { /* The queue contains data again. Loop back to try and read the data. */ prvUnlockQueue( pxQueue ); - 8003936: 6ab8 ldr r0, [r7, #40] @ 0x28 - 8003938: f000 f8a6 bl 8003a88 + 80076fa: 6ab8 ldr r0, [r7, #40] @ 0x28 + 80076fc: f000 fa74 bl 8007be8 ( void ) xTaskResumeAll(); - 800393c: f000 fbf4 bl 8004128 - 8003940: e77a b.n 8003838 + 8007700: f000 fdb6 bl 8008270 + 8007704: e77a b.n 80075fc } else { /* Timed out. If there is no data in the queue exit, otherwise loop back and attempt to read the data. */ prvUnlockQueue( pxQueue ); - 8003942: 6ab8 ldr r0, [r7, #40] @ 0x28 - 8003944: f000 f8a0 bl 8003a88 + 8007706: 6ab8 ldr r0, [r7, #40] @ 0x28 + 8007708: f000 fa6e bl 8007be8 ( void ) xTaskResumeAll(); - 8003948: f000 fbee bl 8004128 + 800770c: f000 fdb0 bl 8008270 if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) - 800394c: 6ab8 ldr r0, [r7, #40] @ 0x28 - 800394e: f000 f8ed bl 8003b2c - 8003952: 4603 mov r3, r0 - 8003954: 2b00 cmp r3, #0 - 8003956: f43f af6f beq.w 8003838 + 8007710: 6ab8 ldr r0, [r7, #40] @ 0x28 + 8007712: f000 fabb bl 8007c8c + 8007716: 4603 mov r3, r0 + 8007718: 2b00 cmp r3, #0 + 800771a: f43f af6f beq.w 80075fc { traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; - 800395a: 2300 movs r3, #0 + 800771e: 2300 movs r3, #0 { mtCOVERAGE_TEST_MARKER(); } } } /*lint -restore */ } - 800395c: 4618 mov r0, r3 - 800395e: 3730 adds r7, #48 @ 0x30 - 8003960: 46bd mov sp, r7 - 8003962: bd80 pop {r7, pc} - 8003964: e000ed04 .word 0xe000ed04 + 8007720: 4618 mov r0, r3 + 8007722: 3730 adds r7, #48 @ 0x30 + 8007724: 46bd mov sp, r7 + 8007726: bd80 pop {r7, pc} + 8007728: e000ed04 .word 0xe000ed04 -08003968 : +0800772c : +/*-----------------------------------------------------------*/ + +BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) +{ + 800772c: b580 push {r7, lr} + 800772e: b08e sub sp, #56 @ 0x38 + 8007730: af00 add r7, sp, #0 + 8007732: 6078 str r0, [r7, #4] + 8007734: 6039 str r1, [r7, #0] +BaseType_t xEntryTimeSet = pdFALSE; + 8007736: 2300 movs r3, #0 + 8007738: 637b str r3, [r7, #52] @ 0x34 +TimeOut_t xTimeOut; +Queue_t * const pxQueue = xQueue; + 800773a: 687b ldr r3, [r7, #4] + 800773c: 62fb str r3, [r7, #44] @ 0x2c + +#if( configUSE_MUTEXES == 1 ) + BaseType_t xInheritanceOccurred = pdFALSE; + 800773e: 2300 movs r3, #0 + 8007740: 633b str r3, [r7, #48] @ 0x30 +#endif + + /* Check the queue pointer is not NULL. */ + configASSERT( ( pxQueue ) ); + 8007742: 6afb ldr r3, [r7, #44] @ 0x2c + 8007744: 2b00 cmp r3, #0 + 8007746: d10b bne.n 8007760 + __asm volatile + 8007748: f04f 0350 mov.w r3, #80 @ 0x50 + 800774c: f383 8811 msr BASEPRI, r3 + 8007750: f3bf 8f6f isb sy + 8007754: f3bf 8f4f dsb sy + 8007758: 623b str r3, [r7, #32] +} + 800775a: bf00 nop + 800775c: bf00 nop + 800775e: e7fd b.n 800775c + + /* Check this really is a semaphore, in which case the item size will be + 0. */ + configASSERT( pxQueue->uxItemSize == 0 ); + 8007760: 6afb ldr r3, [r7, #44] @ 0x2c + 8007762: 6c1b ldr r3, [r3, #64] @ 0x40 + 8007764: 2b00 cmp r3, #0 + 8007766: d00b beq.n 8007780 + __asm volatile + 8007768: f04f 0350 mov.w r3, #80 @ 0x50 + 800776c: f383 8811 msr BASEPRI, r3 + 8007770: f3bf 8f6f isb sy + 8007774: f3bf 8f4f dsb sy + 8007778: 61fb str r3, [r7, #28] +} + 800777a: bf00 nop + 800777c: bf00 nop + 800777e: e7fd b.n 800777c + + /* Cannot block if the scheduler is suspended. */ + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + 8007780: f001 f95c bl 8008a3c + 8007784: 4603 mov r3, r0 + 8007786: 2b00 cmp r3, #0 + 8007788: d102 bne.n 8007790 + 800778a: 683b ldr r3, [r7, #0] + 800778c: 2b00 cmp r3, #0 + 800778e: d101 bne.n 8007794 + 8007790: 2301 movs r3, #1 + 8007792: e000 b.n 8007796 + 8007794: 2300 movs r3, #0 + 8007796: 2b00 cmp r3, #0 + 8007798: d10b bne.n 80077b2 + __asm volatile + 800779a: f04f 0350 mov.w r3, #80 @ 0x50 + 800779e: f383 8811 msr BASEPRI, r3 + 80077a2: f3bf 8f6f isb sy + 80077a6: f3bf 8f4f dsb sy + 80077aa: 61bb str r3, [r7, #24] +} + 80077ac: bf00 nop + 80077ae: bf00 nop + 80077b0: e7fd b.n 80077ae + /*lint -save -e904 This function relaxes the coding standard somewhat to allow return + statements within the function itself. This is done in the interest + of execution time efficiency. */ + for( ;; ) + { + taskENTER_CRITICAL(); + 80077b2: f002 f871 bl 8009898 + { + /* Semaphores are queues with an item size of 0, and where the + number of messages in the queue is the semaphore's count value. */ + const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting; + 80077b6: 6afb ldr r3, [r7, #44] @ 0x2c + 80077b8: 6b9b ldr r3, [r3, #56] @ 0x38 + 80077ba: 62bb str r3, [r7, #40] @ 0x28 + + /* Is there data in the queue now? To be running the calling task + must be the highest priority task wanting to access the queue. */ + if( uxSemaphoreCount > ( UBaseType_t ) 0 ) + 80077bc: 6abb ldr r3, [r7, #40] @ 0x28 + 80077be: 2b00 cmp r3, #0 + 80077c0: d024 beq.n 800780c + { + traceQUEUE_RECEIVE( pxQueue ); + + /* Semaphores are queues with a data size of zero and where the + messages waiting is the semaphore's count. Reduce the count. */ + pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1; + 80077c2: 6abb ldr r3, [r7, #40] @ 0x28 + 80077c4: 1e5a subs r2, r3, #1 + 80077c6: 6afb ldr r3, [r7, #44] @ 0x2c + 80077c8: 639a str r2, [r3, #56] @ 0x38 + + #if ( configUSE_MUTEXES == 1 ) + { + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + 80077ca: 6afb ldr r3, [r7, #44] @ 0x2c + 80077cc: 681b ldr r3, [r3, #0] + 80077ce: 2b00 cmp r3, #0 + 80077d0: d104 bne.n 80077dc + { + /* Record the information required to implement + priority inheritance should it become necessary. */ + pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount(); + 80077d2: f001 faad bl 8008d30 + 80077d6: 4602 mov r2, r0 + 80077d8: 6afb ldr r3, [r7, #44] @ 0x2c + 80077da: 609a str r2, [r3, #8] + } + #endif /* configUSE_MUTEXES */ + + /* Check to see if other tasks are blocked waiting to give the + semaphore, and if so, unblock the highest priority such task. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + 80077dc: 6afb ldr r3, [r7, #44] @ 0x2c + 80077de: 691b ldr r3, [r3, #16] + 80077e0: 2b00 cmp r3, #0 + 80077e2: d00f beq.n 8007804 + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + 80077e4: 6afb ldr r3, [r7, #44] @ 0x2c + 80077e6: 3310 adds r3, #16 + 80077e8: 4618 mov r0, r3 + 80077ea: f000 ff61 bl 80086b0 + 80077ee: 4603 mov r3, r0 + 80077f0: 2b00 cmp r3, #0 + 80077f2: d007 beq.n 8007804 + { + queueYIELD_IF_USING_PREEMPTION(); + 80077f4: 4b54 ldr r3, [pc, #336] @ (8007948 ) + 80077f6: f04f 5280 mov.w r2, #268435456 @ 0x10000000 + 80077fa: 601a str r2, [r3, #0] + 80077fc: f3bf 8f4f dsb sy + 8007800: f3bf 8f6f isb sy + else + { + mtCOVERAGE_TEST_MARKER(); + } + + taskEXIT_CRITICAL(); + 8007804: f002 f87a bl 80098fc + return pdPASS; + 8007808: 2301 movs r3, #1 + 800780a: e098 b.n 800793e + } + else + { + if( xTicksToWait == ( TickType_t ) 0 ) + 800780c: 683b ldr r3, [r7, #0] + 800780e: 2b00 cmp r3, #0 + 8007810: d112 bne.n 8007838 + /* For inheritance to have occurred there must have been an + initial timeout, and an adjusted timeout cannot become 0, as + if it were 0 the function would have exited. */ + #if( configUSE_MUTEXES == 1 ) + { + configASSERT( xInheritanceOccurred == pdFALSE ); + 8007812: 6b3b ldr r3, [r7, #48] @ 0x30 + 8007814: 2b00 cmp r3, #0 + 8007816: d00b beq.n 8007830 + __asm volatile + 8007818: f04f 0350 mov.w r3, #80 @ 0x50 + 800781c: f383 8811 msr BASEPRI, r3 + 8007820: f3bf 8f6f isb sy + 8007824: f3bf 8f4f dsb sy + 8007828: 617b str r3, [r7, #20] +} + 800782a: bf00 nop + 800782c: bf00 nop + 800782e: e7fd b.n 800782c + } + #endif /* configUSE_MUTEXES */ + + /* The semaphore count was 0 and no block time is specified + (or the block time has expired) so exit now. */ + taskEXIT_CRITICAL(); + 8007830: f002 f864 bl 80098fc + traceQUEUE_RECEIVE_FAILED( pxQueue ); + return errQUEUE_EMPTY; + 8007834: 2300 movs r3, #0 + 8007836: e082 b.n 800793e + } + else if( xEntryTimeSet == pdFALSE ) + 8007838: 6b7b ldr r3, [r7, #52] @ 0x34 + 800783a: 2b00 cmp r3, #0 + 800783c: d106 bne.n 800784c + { + /* The semaphore count was 0 and a block time was specified + so configure the timeout structure ready to block. */ + vTaskInternalSetTimeOutState( &xTimeOut ); + 800783e: f107 030c add.w r3, r7, #12 + 8007842: 4618 mov r0, r3 + 8007844: f000 ff98 bl 8008778 + xEntryTimeSet = pdTRUE; + 8007848: 2301 movs r3, #1 + 800784a: 637b str r3, [r7, #52] @ 0x34 + /* Entry time was already set. */ + mtCOVERAGE_TEST_MARKER(); + } + } + } + taskEXIT_CRITICAL(); + 800784c: f002 f856 bl 80098fc + + /* Interrupts and other tasks can give to and take from the semaphore + now the critical section has been exited. */ + + vTaskSuspendAll(); + 8007850: f000 fd00 bl 8008254 + prvLockQueue( pxQueue ); + 8007854: f002 f820 bl 8009898 + 8007858: 6afb ldr r3, [r7, #44] @ 0x2c + 800785a: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 + 800785e: b25b sxtb r3, r3 + 8007860: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8007864: d103 bne.n 800786e + 8007866: 6afb ldr r3, [r7, #44] @ 0x2c + 8007868: 2200 movs r2, #0 + 800786a: f883 2044 strb.w r2, [r3, #68] @ 0x44 + 800786e: 6afb ldr r3, [r7, #44] @ 0x2c + 8007870: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 + 8007874: b25b sxtb r3, r3 + 8007876: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 800787a: d103 bne.n 8007884 + 800787c: 6afb ldr r3, [r7, #44] @ 0x2c + 800787e: 2200 movs r2, #0 + 8007880: f883 2045 strb.w r2, [r3, #69] @ 0x45 + 8007884: f002 f83a bl 80098fc + + /* Update the timeout state to see if it has expired yet. */ + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + 8007888: 463a mov r2, r7 + 800788a: f107 030c add.w r3, r7, #12 + 800788e: 4611 mov r1, r2 + 8007890: 4618 mov r0, r3 + 8007892: f000 ff87 bl 80087a4 + 8007896: 4603 mov r3, r0 + 8007898: 2b00 cmp r3, #0 + 800789a: d132 bne.n 8007902 + { + /* A block time is specified and not expired. If the semaphore + count is 0 then enter the Blocked state to wait for a semaphore to + become available. As semaphores are implemented with queues the + queue being empty is equivalent to the semaphore count being 0. */ + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + 800789c: 6af8 ldr r0, [r7, #44] @ 0x2c + 800789e: f000 f9f5 bl 8007c8c + 80078a2: 4603 mov r3, r0 + 80078a4: 2b00 cmp r3, #0 + 80078a6: d026 beq.n 80078f6 + { + traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); + + #if ( configUSE_MUTEXES == 1 ) + { + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + 80078a8: 6afb ldr r3, [r7, #44] @ 0x2c + 80078aa: 681b ldr r3, [r3, #0] + 80078ac: 2b00 cmp r3, #0 + 80078ae: d109 bne.n 80078c4 + { + taskENTER_CRITICAL(); + 80078b0: f001 fff2 bl 8009898 + { + xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder ); + 80078b4: 6afb ldr r3, [r7, #44] @ 0x2c + 80078b6: 689b ldr r3, [r3, #8] + 80078b8: 4618 mov r0, r3 + 80078ba: f001 f8dd bl 8008a78 + 80078be: 6338 str r0, [r7, #48] @ 0x30 + } + taskEXIT_CRITICAL(); + 80078c0: f002 f81c bl 80098fc + mtCOVERAGE_TEST_MARKER(); + } + } + #endif + + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); + 80078c4: 6afb ldr r3, [r7, #44] @ 0x2c + 80078c6: 3324 adds r3, #36 @ 0x24 + 80078c8: 683a ldr r2, [r7, #0] + 80078ca: 4611 mov r1, r2 + 80078cc: 4618 mov r0, r3 + 80078ce: f000 fe9d bl 800860c + prvUnlockQueue( pxQueue ); + 80078d2: 6af8 ldr r0, [r7, #44] @ 0x2c + 80078d4: f000 f988 bl 8007be8 + if( xTaskResumeAll() == pdFALSE ) + 80078d8: f000 fcca bl 8008270 + 80078dc: 4603 mov r3, r0 + 80078de: 2b00 cmp r3, #0 + 80078e0: f47f af67 bne.w 80077b2 + { + portYIELD_WITHIN_API(); + 80078e4: 4b18 ldr r3, [pc, #96] @ (8007948 ) + 80078e6: f04f 5280 mov.w r2, #268435456 @ 0x10000000 + 80078ea: 601a str r2, [r3, #0] + 80078ec: f3bf 8f4f dsb sy + 80078f0: f3bf 8f6f isb sy + 80078f4: e75d b.n 80077b2 + } + else + { + /* There was no timeout and the semaphore count was not 0, so + attempt to take the semaphore again. */ + prvUnlockQueue( pxQueue ); + 80078f6: 6af8 ldr r0, [r7, #44] @ 0x2c + 80078f8: f000 f976 bl 8007be8 + ( void ) xTaskResumeAll(); + 80078fc: f000 fcb8 bl 8008270 + 8007900: e757 b.n 80077b2 + } + } + else + { + /* Timed out. */ + prvUnlockQueue( pxQueue ); + 8007902: 6af8 ldr r0, [r7, #44] @ 0x2c + 8007904: f000 f970 bl 8007be8 + ( void ) xTaskResumeAll(); + 8007908: f000 fcb2 bl 8008270 + + /* If the semaphore count is 0 exit now as the timeout has + expired. Otherwise return to attempt to take the semaphore that is + known to be available. As semaphores are implemented by queues the + queue being empty is equivalent to the semaphore count being 0. */ + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + 800790c: 6af8 ldr r0, [r7, #44] @ 0x2c + 800790e: f000 f9bd bl 8007c8c + 8007912: 4603 mov r3, r0 + 8007914: 2b00 cmp r3, #0 + 8007916: f43f af4c beq.w 80077b2 + #if ( configUSE_MUTEXES == 1 ) + { + /* xInheritanceOccurred could only have be set if + pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to + test the mutex type again to check it is actually a mutex. */ + if( xInheritanceOccurred != pdFALSE ) + 800791a: 6b3b ldr r3, [r7, #48] @ 0x30 + 800791c: 2b00 cmp r3, #0 + 800791e: d00d beq.n 800793c + { + taskENTER_CRITICAL(); + 8007920: f001 ffba bl 8009898 + /* This task blocking on the mutex caused another + task to inherit this task's priority. Now this task + has timed out the priority should be disinherited + again, but only as low as the next highest priority + task that is waiting for the same mutex. */ + uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue ); + 8007924: 6af8 ldr r0, [r7, #44] @ 0x2c + 8007926: f000 f8b7 bl 8007a98 + 800792a: 6278 str r0, [r7, #36] @ 0x24 + vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority ); + 800792c: 6afb ldr r3, [r7, #44] @ 0x2c + 800792e: 689b ldr r3, [r3, #8] + 8007930: 6a79 ldr r1, [r7, #36] @ 0x24 + 8007932: 4618 mov r0, r3 + 8007934: f001 f978 bl 8008c28 + } + taskEXIT_CRITICAL(); + 8007938: f001 ffe0 bl 80098fc + } + } + #endif /* configUSE_MUTEXES */ + + traceQUEUE_RECEIVE_FAILED( pxQueue ); + return errQUEUE_EMPTY; + 800793c: 2300 movs r3, #0 + { + mtCOVERAGE_TEST_MARKER(); + } + } + } /*lint -restore */ +} + 800793e: 4618 mov r0, r3 + 8007940: 3738 adds r7, #56 @ 0x38 + 8007942: 46bd mov sp, r7 + 8007944: bd80 pop {r7, pc} + 8007946: bf00 nop + 8007948: e000ed04 .word 0xe000ed04 + +0800794c : + } /*lint -restore */ +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) +{ + 800794c: b580 push {r7, lr} + 800794e: b08e sub sp, #56 @ 0x38 + 8007950: af00 add r7, sp, #0 + 8007952: 60f8 str r0, [r7, #12] + 8007954: 60b9 str r1, [r7, #8] + 8007956: 607a str r2, [r7, #4] +BaseType_t xReturn; +UBaseType_t uxSavedInterruptStatus; +Queue_t * const pxQueue = xQueue; + 8007958: 68fb ldr r3, [r7, #12] + 800795a: 633b str r3, [r7, #48] @ 0x30 + + configASSERT( pxQueue ); + 800795c: 6b3b ldr r3, [r7, #48] @ 0x30 + 800795e: 2b00 cmp r3, #0 + 8007960: d10b bne.n 800797a + __asm volatile + 8007962: f04f 0350 mov.w r3, #80 @ 0x50 + 8007966: f383 8811 msr BASEPRI, r3 + 800796a: f3bf 8f6f isb sy + 800796e: f3bf 8f4f dsb sy + 8007972: 623b str r3, [r7, #32] +} + 8007974: bf00 nop + 8007976: bf00 nop + 8007978: e7fd b.n 8007976 + configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + 800797a: 68bb ldr r3, [r7, #8] + 800797c: 2b00 cmp r3, #0 + 800797e: d103 bne.n 8007988 + 8007980: 6b3b ldr r3, [r7, #48] @ 0x30 + 8007982: 6c1b ldr r3, [r3, #64] @ 0x40 + 8007984: 2b00 cmp r3, #0 + 8007986: d101 bne.n 800798c + 8007988: 2301 movs r3, #1 + 800798a: e000 b.n 800798e + 800798c: 2300 movs r3, #0 + 800798e: 2b00 cmp r3, #0 + 8007990: d10b bne.n 80079aa + __asm volatile + 8007992: f04f 0350 mov.w r3, #80 @ 0x50 + 8007996: f383 8811 msr BASEPRI, r3 + 800799a: f3bf 8f6f isb sy + 800799e: f3bf 8f4f dsb sy + 80079a2: 61fb str r3, [r7, #28] +} + 80079a4: bf00 nop + 80079a6: bf00 nop + 80079a8: e7fd b.n 80079a6 + that have been assigned a priority at or (logically) below the maximum + system call interrupt priority. FreeRTOS maintains a separate interrupt + safe API to ensure interrupt entry is as fast and as simple as possible. + More information (albeit Cortex-M specific) is provided on the following + link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + 80079aa: f002 f855 bl 8009a58 + __asm volatile + 80079ae: f3ef 8211 mrs r2, BASEPRI + 80079b2: f04f 0350 mov.w r3, #80 @ 0x50 + 80079b6: f383 8811 msr BASEPRI, r3 + 80079ba: f3bf 8f6f isb sy + 80079be: f3bf 8f4f dsb sy + 80079c2: 61ba str r2, [r7, #24] + 80079c4: 617b str r3, [r7, #20] + return ulOriginalBASEPRI; + 80079c6: 69bb ldr r3, [r7, #24] + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + 80079c8: 62fb str r3, [r7, #44] @ 0x2c + { + const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; + 80079ca: 6b3b ldr r3, [r7, #48] @ 0x30 + 80079cc: 6b9b ldr r3, [r3, #56] @ 0x38 + 80079ce: 62bb str r3, [r7, #40] @ 0x28 + + /* Cannot block in an ISR, so check there is data available. */ + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + 80079d0: 6abb ldr r3, [r7, #40] @ 0x28 + 80079d2: 2b00 cmp r3, #0 + 80079d4: d02f beq.n 8007a36 + { + const int8_t cRxLock = pxQueue->cRxLock; + 80079d6: 6b3b ldr r3, [r7, #48] @ 0x30 + 80079d8: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 + 80079dc: f887 3027 strb.w r3, [r7, #39] @ 0x27 + + traceQUEUE_RECEIVE_FROM_ISR( pxQueue ); + + prvCopyDataFromQueue( pxQueue, pvBuffer ); + 80079e0: 68b9 ldr r1, [r7, #8] + 80079e2: 6b38 ldr r0, [r7, #48] @ 0x30 + 80079e4: f000 f8da bl 8007b9c + pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; + 80079e8: 6abb ldr r3, [r7, #40] @ 0x28 + 80079ea: 1e5a subs r2, r3, #1 + 80079ec: 6b3b ldr r3, [r7, #48] @ 0x30 + 80079ee: 639a str r2, [r3, #56] @ 0x38 + + /* If the queue is locked the event list will not be modified. + Instead update the lock count so the task that unlocks the queue + will know that an ISR has removed data while the queue was + locked. */ + if( cRxLock == queueUNLOCKED ) + 80079f0: f997 3027 ldrsb.w r3, [r7, #39] @ 0x27 + 80079f4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 80079f8: d112 bne.n 8007a20 + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + 80079fa: 6b3b ldr r3, [r7, #48] @ 0x30 + 80079fc: 691b ldr r3, [r3, #16] + 80079fe: 2b00 cmp r3, #0 + 8007a00: d016 beq.n 8007a30 + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + 8007a02: 6b3b ldr r3, [r7, #48] @ 0x30 + 8007a04: 3310 adds r3, #16 + 8007a06: 4618 mov r0, r3 + 8007a08: f000 fe52 bl 80086b0 + 8007a0c: 4603 mov r3, r0 + 8007a0e: 2b00 cmp r3, #0 + 8007a10: d00e beq.n 8007a30 + { + /* The task waiting has a higher priority than us so + force a context switch. */ + if( pxHigherPriorityTaskWoken != NULL ) + 8007a12: 687b ldr r3, [r7, #4] + 8007a14: 2b00 cmp r3, #0 + 8007a16: d00b beq.n 8007a30 + { + *pxHigherPriorityTaskWoken = pdTRUE; + 8007a18: 687b ldr r3, [r7, #4] + 8007a1a: 2201 movs r2, #1 + 8007a1c: 601a str r2, [r3, #0] + 8007a1e: e007 b.n 8007a30 + } + else + { + /* Increment the lock count so the task that unlocks the queue + knows that data was removed while it was locked. */ + pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 ); + 8007a20: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 + 8007a24: 3301 adds r3, #1 + 8007a26: b2db uxtb r3, r3 + 8007a28: b25a sxtb r2, r3 + 8007a2a: 6b3b ldr r3, [r7, #48] @ 0x30 + 8007a2c: f883 2044 strb.w r2, [r3, #68] @ 0x44 + } + + xReturn = pdPASS; + 8007a30: 2301 movs r3, #1 + 8007a32: 637b str r3, [r7, #52] @ 0x34 + 8007a34: e001 b.n 8007a3a + } + else + { + xReturn = pdFAIL; + 8007a36: 2300 movs r3, #0 + 8007a38: 637b str r3, [r7, #52] @ 0x34 + 8007a3a: 6afb ldr r3, [r7, #44] @ 0x2c + 8007a3c: 613b str r3, [r7, #16] + __asm volatile + 8007a3e: 693b ldr r3, [r7, #16] + 8007a40: f383 8811 msr BASEPRI, r3 +} + 8007a44: bf00 nop + traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; + 8007a46: 6b7b ldr r3, [r7, #52] @ 0x34 +} + 8007a48: 4618 mov r0, r3 + 8007a4a: 3738 adds r7, #56 @ 0x38 + 8007a4c: 46bd mov sp, r7 + 8007a4e: bd80 pop {r7, pc} + +08007a50 : + return uxReturn; +} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ +/*-----------------------------------------------------------*/ + +void vQueueDelete( QueueHandle_t xQueue ) +{ + 8007a50: b580 push {r7, lr} + 8007a52: b084 sub sp, #16 + 8007a54: af00 add r7, sp, #0 + 8007a56: 6078 str r0, [r7, #4] +Queue_t * const pxQueue = xQueue; + 8007a58: 687b ldr r3, [r7, #4] + 8007a5a: 60fb str r3, [r7, #12] + + configASSERT( pxQueue ); + 8007a5c: 68fb ldr r3, [r7, #12] + 8007a5e: 2b00 cmp r3, #0 + 8007a60: d10b bne.n 8007a7a + __asm volatile + 8007a62: f04f 0350 mov.w r3, #80 @ 0x50 + 8007a66: f383 8811 msr BASEPRI, r3 + 8007a6a: f3bf 8f6f isb sy + 8007a6e: f3bf 8f4f dsb sy + 8007a72: 60bb str r3, [r7, #8] +} + 8007a74: bf00 nop + 8007a76: bf00 nop + 8007a78: e7fd b.n 8007a76 + traceQUEUE_DELETE( pxQueue ); + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + { + vQueueUnregisterQueue( pxQueue ); + 8007a7a: 68f8 ldr r0, [r7, #12] + 8007a7c: f000 f95e bl 8007d3c + } + #elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + { + /* The queue could have been allocated statically or dynamically, so + check before attempting to free the memory. */ + if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE ) + 8007a80: 68fb ldr r3, [r7, #12] + 8007a82: f893 3046 ldrb.w r3, [r3, #70] @ 0x46 + 8007a86: 2b00 cmp r3, #0 + 8007a88: d102 bne.n 8007a90 + { + vPortFree( pxQueue ); + 8007a8a: 68f8 ldr r0, [r7, #12] + 8007a8c: f002 f8f4 bl 8009c78 + /* The queue must have been statically allocated, so is not going to be + deleted. Avoid compiler warnings about the unused parameter. */ + ( void ) pxQueue; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +} + 8007a90: bf00 nop + 8007a92: 3710 adds r7, #16 + 8007a94: 46bd mov sp, r7 + 8007a96: bd80 pop {r7, pc} + +08007a98 : +/*-----------------------------------------------------------*/ + +#if( configUSE_MUTEXES == 1 ) + + static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) + { + 8007a98: b480 push {r7} + 8007a9a: b085 sub sp, #20 + 8007a9c: af00 add r7, sp, #0 + 8007a9e: 6078 str r0, [r7, #4] + priority, but the waiting task times out, then the holder should + disinherit the priority - but only down to the highest priority of any + other tasks that are waiting for the same mutex. For this purpose, + return the priority of the highest priority task that is waiting for the + mutex. */ + if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U ) + 8007aa0: 687b ldr r3, [r7, #4] + 8007aa2: 6a5b ldr r3, [r3, #36] @ 0x24 + 8007aa4: 2b00 cmp r3, #0 + 8007aa6: d006 beq.n 8007ab6 + { + uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) ); + 8007aa8: 687b ldr r3, [r7, #4] + 8007aaa: 6b1b ldr r3, [r3, #48] @ 0x30 + 8007aac: 681b ldr r3, [r3, #0] + 8007aae: f1c3 0338 rsb r3, r3, #56 @ 0x38 + 8007ab2: 60fb str r3, [r7, #12] + 8007ab4: e001 b.n 8007aba + } + else + { + uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY; + 8007ab6: 2300 movs r3, #0 + 8007ab8: 60fb str r3, [r7, #12] + } + + return uxHighestPriorityOfWaitingTasks; + 8007aba: 68fb ldr r3, [r7, #12] + } + 8007abc: 4618 mov r0, r3 + 8007abe: 3714 adds r7, #20 + 8007ac0: 46bd mov sp, r7 + 8007ac2: f85d 7b04 ldr.w r7, [sp], #4 + 8007ac6: 4770 bx lr + +08007ac8 : #endif /* configUSE_MUTEXES */ /*-----------------------------------------------------------*/ static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) { - 8003968: b580 push {r7, lr} - 800396a: b086 sub sp, #24 - 800396c: af00 add r7, sp, #0 - 800396e: 60f8 str r0, [r7, #12] - 8003970: 60b9 str r1, [r7, #8] - 8003972: 607a str r2, [r7, #4] + 8007ac8: b580 push {r7, lr} + 8007aca: b086 sub sp, #24 + 8007acc: af00 add r7, sp, #0 + 8007ace: 60f8 str r0, [r7, #12] + 8007ad0: 60b9 str r1, [r7, #8] + 8007ad2: 607a str r2, [r7, #4] BaseType_t xReturn = pdFALSE; - 8003974: 2300 movs r3, #0 - 8003976: 617b str r3, [r7, #20] + 8007ad4: 2300 movs r3, #0 + 8007ad6: 617b str r3, [r7, #20] UBaseType_t uxMessagesWaiting; /* This function is called from a critical section. */ uxMessagesWaiting = pxQueue->uxMessagesWaiting; - 8003978: 68fb ldr r3, [r7, #12] - 800397a: 6b9b ldr r3, [r3, #56] @ 0x38 - 800397c: 613b str r3, [r7, #16] + 8007ad8: 68fb ldr r3, [r7, #12] + 8007ada: 6b9b ldr r3, [r3, #56] @ 0x38 + 8007adc: 613b str r3, [r7, #16] if( pxQueue->uxItemSize == ( UBaseType_t ) 0 ) - 800397e: 68fb ldr r3, [r7, #12] - 8003980: 6c1b ldr r3, [r3, #64] @ 0x40 - 8003982: 2b00 cmp r3, #0 - 8003984: d10d bne.n 80039a2 + 8007ade: 68fb ldr r3, [r7, #12] + 8007ae0: 6c1b ldr r3, [r3, #64] @ 0x40 + 8007ae2: 2b00 cmp r3, #0 + 8007ae4: d10d bne.n 8007b02 { #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) - 8003986: 68fb ldr r3, [r7, #12] - 8003988: 681b ldr r3, [r3, #0] - 800398a: 2b00 cmp r3, #0 - 800398c: d14d bne.n 8003a2a + 8007ae6: 68fb ldr r3, [r7, #12] + 8007ae8: 681b ldr r3, [r3, #0] + 8007aea: 2b00 cmp r3, #0 + 8007aec: d14d bne.n 8007b8a { /* The mutex is no longer being held. */ xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder ); - 800398e: 68fb ldr r3, [r7, #12] - 8003990: 689b ldr r3, [r3, #8] - 8003992: 4618 mov r0, r3 - 8003994: f000 ffcc bl 8004930 - 8003998: 6178 str r0, [r7, #20] + 8007aee: 68fb ldr r3, [r7, #12] + 8007af0: 689b ldr r3, [r3, #8] + 8007af2: 4618 mov r0, r3 + 8007af4: f001 f828 bl 8008b48 + 8007af8: 6178 str r0, [r7, #20] pxQueue->u.xSemaphore.xMutexHolder = NULL; - 800399a: 68fb ldr r3, [r7, #12] - 800399c: 2200 movs r2, #0 - 800399e: 609a str r2, [r3, #8] - 80039a0: e043 b.n 8003a2a + 8007afa: 68fb ldr r3, [r7, #12] + 8007afc: 2200 movs r2, #0 + 8007afe: 609a str r2, [r3, #8] + 8007b00: e043 b.n 8007b8a mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_MUTEXES */ } else if( xPosition == queueSEND_TO_BACK ) - 80039a2: 687b ldr r3, [r7, #4] - 80039a4: 2b00 cmp r3, #0 - 80039a6: d119 bne.n 80039dc + 8007b02: 687b ldr r3, [r7, #4] + 8007b04: 2b00 cmp r3, #0 + 8007b06: d119 bne.n 8007b3c { ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ - 80039a8: 68fb ldr r3, [r7, #12] - 80039aa: 6858 ldr r0, [r3, #4] - 80039ac: 68fb ldr r3, [r7, #12] - 80039ae: 6c1b ldr r3, [r3, #64] @ 0x40 - 80039b0: 461a mov r2, r3 - 80039b2: 68b9 ldr r1, [r7, #8] - 80039b4: f002 f8ae bl 8005b14 + 8007b08: 68fb ldr r3, [r7, #12] + 8007b0a: 6858 ldr r0, [r3, #4] + 8007b0c: 68fb ldr r3, [r7, #12] + 8007b0e: 6c1b ldr r3, [r3, #64] @ 0x40 + 8007b10: 461a mov r2, r3 + 8007b12: 68b9 ldr r1, [r7, #8] + 8007b14: f002 fa66 bl 8009fe4 pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ - 80039b8: 68fb ldr r3, [r7, #12] - 80039ba: 685a ldr r2, [r3, #4] - 80039bc: 68fb ldr r3, [r7, #12] - 80039be: 6c1b ldr r3, [r3, #64] @ 0x40 - 80039c0: 441a add r2, r3 - 80039c2: 68fb ldr r3, [r7, #12] - 80039c4: 605a str r2, [r3, #4] + 8007b18: 68fb ldr r3, [r7, #12] + 8007b1a: 685a ldr r2, [r3, #4] + 8007b1c: 68fb ldr r3, [r7, #12] + 8007b1e: 6c1b ldr r3, [r3, #64] @ 0x40 + 8007b20: 441a add r2, r3 + 8007b22: 68fb ldr r3, [r7, #12] + 8007b24: 605a str r2, [r3, #4] if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ - 80039c6: 68fb ldr r3, [r7, #12] - 80039c8: 685a ldr r2, [r3, #4] - 80039ca: 68fb ldr r3, [r7, #12] - 80039cc: 689b ldr r3, [r3, #8] - 80039ce: 429a cmp r2, r3 - 80039d0: d32b bcc.n 8003a2a + 8007b26: 68fb ldr r3, [r7, #12] + 8007b28: 685a ldr r2, [r3, #4] + 8007b2a: 68fb ldr r3, [r7, #12] + 8007b2c: 689b ldr r3, [r3, #8] + 8007b2e: 429a cmp r2, r3 + 8007b30: d32b bcc.n 8007b8a { pxQueue->pcWriteTo = pxQueue->pcHead; - 80039d2: 68fb ldr r3, [r7, #12] - 80039d4: 681a ldr r2, [r3, #0] - 80039d6: 68fb ldr r3, [r7, #12] - 80039d8: 605a str r2, [r3, #4] - 80039da: e026 b.n 8003a2a + 8007b32: 68fb ldr r3, [r7, #12] + 8007b34: 681a ldr r2, [r3, #0] + 8007b36: 68fb ldr r3, [r7, #12] + 8007b38: 605a str r2, [r3, #4] + 8007b3a: e026 b.n 8007b8a mtCOVERAGE_TEST_MARKER(); } } else { ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */ - 80039dc: 68fb ldr r3, [r7, #12] - 80039de: 68d8 ldr r0, [r3, #12] - 80039e0: 68fb ldr r3, [r7, #12] - 80039e2: 6c1b ldr r3, [r3, #64] @ 0x40 - 80039e4: 461a mov r2, r3 - 80039e6: 68b9 ldr r1, [r7, #8] - 80039e8: f002 f894 bl 8005b14 + 8007b3c: 68fb ldr r3, [r7, #12] + 8007b3e: 68d8 ldr r0, [r3, #12] + 8007b40: 68fb ldr r3, [r7, #12] + 8007b42: 6c1b ldr r3, [r3, #64] @ 0x40 + 8007b44: 461a mov r2, r3 + 8007b46: 68b9 ldr r1, [r7, #8] + 8007b48: f002 fa4c bl 8009fe4 pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize; - 80039ec: 68fb ldr r3, [r7, #12] - 80039ee: 68da ldr r2, [r3, #12] - 80039f0: 68fb ldr r3, [r7, #12] - 80039f2: 6c1b ldr r3, [r3, #64] @ 0x40 - 80039f4: 425b negs r3, r3 - 80039f6: 441a add r2, r3 - 80039f8: 68fb ldr r3, [r7, #12] - 80039fa: 60da str r2, [r3, #12] + 8007b4c: 68fb ldr r3, [r7, #12] + 8007b4e: 68da ldr r2, [r3, #12] + 8007b50: 68fb ldr r3, [r7, #12] + 8007b52: 6c1b ldr r3, [r3, #64] @ 0x40 + 8007b54: 425b negs r3, r3 + 8007b56: 441a add r2, r3 + 8007b58: 68fb ldr r3, [r7, #12] + 8007b5a: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ - 80039fc: 68fb ldr r3, [r7, #12] - 80039fe: 68da ldr r2, [r3, #12] - 8003a00: 68fb ldr r3, [r7, #12] - 8003a02: 681b ldr r3, [r3, #0] - 8003a04: 429a cmp r2, r3 - 8003a06: d207 bcs.n 8003a18 + 8007b5c: 68fb ldr r3, [r7, #12] + 8007b5e: 68da ldr r2, [r3, #12] + 8007b60: 68fb ldr r3, [r7, #12] + 8007b62: 681b ldr r3, [r3, #0] + 8007b64: 429a cmp r2, r3 + 8007b66: d207 bcs.n 8007b78 { pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize ); - 8003a08: 68fb ldr r3, [r7, #12] - 8003a0a: 689a ldr r2, [r3, #8] - 8003a0c: 68fb ldr r3, [r7, #12] - 8003a0e: 6c1b ldr r3, [r3, #64] @ 0x40 - 8003a10: 425b negs r3, r3 - 8003a12: 441a add r2, r3 - 8003a14: 68fb ldr r3, [r7, #12] - 8003a16: 60da str r2, [r3, #12] + 8007b68: 68fb ldr r3, [r7, #12] + 8007b6a: 689a ldr r2, [r3, #8] + 8007b6c: 68fb ldr r3, [r7, #12] + 8007b6e: 6c1b ldr r3, [r3, #64] @ 0x40 + 8007b70: 425b negs r3, r3 + 8007b72: 441a add r2, r3 + 8007b74: 68fb ldr r3, [r7, #12] + 8007b76: 60da str r2, [r3, #12] else { mtCOVERAGE_TEST_MARKER(); } if( xPosition == queueOVERWRITE ) - 8003a18: 687b ldr r3, [r7, #4] - 8003a1a: 2b02 cmp r3, #2 - 8003a1c: d105 bne.n 8003a2a + 8007b78: 687b ldr r3, [r7, #4] + 8007b7a: 2b02 cmp r3, #2 + 8007b7c: d105 bne.n 8007b8a { if( uxMessagesWaiting > ( UBaseType_t ) 0 ) - 8003a1e: 693b ldr r3, [r7, #16] - 8003a20: 2b00 cmp r3, #0 - 8003a22: d002 beq.n 8003a2a + 8007b7e: 693b ldr r3, [r7, #16] + 8007b80: 2b00 cmp r3, #0 + 8007b82: d002 beq.n 8007b8a { /* An item is not being added but overwritten, so subtract one from the recorded number of items in the queue so when one is added again below the number of recorded items remains correct. */ --uxMessagesWaiting; - 8003a24: 693b ldr r3, [r7, #16] - 8003a26: 3b01 subs r3, #1 - 8003a28: 613b str r3, [r7, #16] + 8007b84: 693b ldr r3, [r7, #16] + 8007b86: 3b01 subs r3, #1 + 8007b88: 613b str r3, [r7, #16] { mtCOVERAGE_TEST_MARKER(); } } pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; - 8003a2a: 693b ldr r3, [r7, #16] - 8003a2c: 1c5a adds r2, r3, #1 - 8003a2e: 68fb ldr r3, [r7, #12] - 8003a30: 639a str r2, [r3, #56] @ 0x38 + 8007b8a: 693b ldr r3, [r7, #16] + 8007b8c: 1c5a adds r2, r3, #1 + 8007b8e: 68fb ldr r3, [r7, #12] + 8007b90: 639a str r2, [r3, #56] @ 0x38 return xReturn; - 8003a32: 697b ldr r3, [r7, #20] + 8007b92: 697b ldr r3, [r7, #20] } - 8003a34: 4618 mov r0, r3 - 8003a36: 3718 adds r7, #24 - 8003a38: 46bd mov sp, r7 - 8003a3a: bd80 pop {r7, pc} + 8007b94: 4618 mov r0, r3 + 8007b96: 3718 adds r7, #24 + 8007b98: 46bd mov sp, r7 + 8007b9a: bd80 pop {r7, pc} -08003a3c : +08007b9c : /*-----------------------------------------------------------*/ static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) { - 8003a3c: b580 push {r7, lr} - 8003a3e: b082 sub sp, #8 - 8003a40: af00 add r7, sp, #0 - 8003a42: 6078 str r0, [r7, #4] - 8003a44: 6039 str r1, [r7, #0] + 8007b9c: b580 push {r7, lr} + 8007b9e: b082 sub sp, #8 + 8007ba0: af00 add r7, sp, #0 + 8007ba2: 6078 str r0, [r7, #4] + 8007ba4: 6039 str r1, [r7, #0] if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) - 8003a46: 687b ldr r3, [r7, #4] - 8003a48: 6c1b ldr r3, [r3, #64] @ 0x40 - 8003a4a: 2b00 cmp r3, #0 - 8003a4c: d018 beq.n 8003a80 + 8007ba6: 687b ldr r3, [r7, #4] + 8007ba8: 6c1b ldr r3, [r3, #64] @ 0x40 + 8007baa: 2b00 cmp r3, #0 + 8007bac: d018 beq.n 8007be0 { pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ - 8003a4e: 687b ldr r3, [r7, #4] - 8003a50: 68da ldr r2, [r3, #12] - 8003a52: 687b ldr r3, [r7, #4] - 8003a54: 6c1b ldr r3, [r3, #64] @ 0x40 - 8003a56: 441a add r2, r3 - 8003a58: 687b ldr r3, [r7, #4] - 8003a5a: 60da str r2, [r3, #12] + 8007bae: 687b ldr r3, [r7, #4] + 8007bb0: 68da ldr r2, [r3, #12] + 8007bb2: 687b ldr r3, [r7, #4] + 8007bb4: 6c1b ldr r3, [r3, #64] @ 0x40 + 8007bb6: 441a add r2, r3 + 8007bb8: 687b ldr r3, [r7, #4] + 8007bba: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ - 8003a5c: 687b ldr r3, [r7, #4] - 8003a5e: 68da ldr r2, [r3, #12] - 8003a60: 687b ldr r3, [r7, #4] - 8003a62: 689b ldr r3, [r3, #8] - 8003a64: 429a cmp r2, r3 - 8003a66: d303 bcc.n 8003a70 + 8007bbc: 687b ldr r3, [r7, #4] + 8007bbe: 68da ldr r2, [r3, #12] + 8007bc0: 687b ldr r3, [r7, #4] + 8007bc2: 689b ldr r3, [r3, #8] + 8007bc4: 429a cmp r2, r3 + 8007bc6: d303 bcc.n 8007bd0 { pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; - 8003a68: 687b ldr r3, [r7, #4] - 8003a6a: 681a ldr r2, [r3, #0] - 8003a6c: 687b ldr r3, [r7, #4] - 8003a6e: 60da str r2, [r3, #12] + 8007bc8: 687b ldr r3, [r7, #4] + 8007bca: 681a ldr r2, [r3, #0] + 8007bcc: 687b ldr r3, [r7, #4] + 8007bce: 60da str r2, [r3, #12] } else { mtCOVERAGE_TEST_MARKER(); } ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ - 8003a70: 687b ldr r3, [r7, #4] - 8003a72: 68d9 ldr r1, [r3, #12] - 8003a74: 687b ldr r3, [r7, #4] - 8003a76: 6c1b ldr r3, [r3, #64] @ 0x40 - 8003a78: 461a mov r2, r3 - 8003a7a: 6838 ldr r0, [r7, #0] - 8003a7c: f002 f84a bl 8005b14 + 8007bd0: 687b ldr r3, [r7, #4] + 8007bd2: 68d9 ldr r1, [r3, #12] + 8007bd4: 687b ldr r3, [r7, #4] + 8007bd6: 6c1b ldr r3, [r3, #64] @ 0x40 + 8007bd8: 461a mov r2, r3 + 8007bda: 6838 ldr r0, [r7, #0] + 8007bdc: f002 fa02 bl 8009fe4 } } - 8003a80: bf00 nop - 8003a82: 3708 adds r7, #8 - 8003a84: 46bd mov sp, r7 - 8003a86: bd80 pop {r7, pc} + 8007be0: bf00 nop + 8007be2: 3708 adds r7, #8 + 8007be4: 46bd mov sp, r7 + 8007be6: bd80 pop {r7, pc} -08003a88 : +08007be8 : /*-----------------------------------------------------------*/ static void prvUnlockQueue( Queue_t * const pxQueue ) { - 8003a88: b580 push {r7, lr} - 8003a8a: b084 sub sp, #16 - 8003a8c: af00 add r7, sp, #0 - 8003a8e: 6078 str r0, [r7, #4] + 8007be8: b580 push {r7, lr} + 8007bea: b084 sub sp, #16 + 8007bec: af00 add r7, sp, #0 + 8007bee: 6078 str r0, [r7, #4] /* The lock counts contains the number of extra data items placed or removed from the queue while the queue was locked. When a queue is locked items can be added or removed, but the event lists cannot be updated. */ taskENTER_CRITICAL(); - 8003a90: f001 fc9a bl 80053c8 + 8007bf0: f001 fe52 bl 8009898 { int8_t cTxLock = pxQueue->cTxLock; - 8003a94: 687b ldr r3, [r7, #4] - 8003a96: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 - 8003a9a: 73fb strb r3, [r7, #15] + 8007bf4: 687b ldr r3, [r7, #4] + 8007bf6: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 + 8007bfa: 73fb strb r3, [r7, #15] /* See if data was added to the queue while it was locked. */ while( cTxLock > queueLOCKED_UNMODIFIED ) - 8003a9c: e011 b.n 8003ac2 + 8007bfc: e011 b.n 8007c22 } #else /* configUSE_QUEUE_SETS */ { /* Tasks that are removed from the event list will get added to the pending ready list as the scheduler is still suspended. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) - 8003a9e: 687b ldr r3, [r7, #4] - 8003aa0: 6a5b ldr r3, [r3, #36] @ 0x24 - 8003aa2: 2b00 cmp r3, #0 - 8003aa4: d012 beq.n 8003acc + 8007bfe: 687b ldr r3, [r7, #4] + 8007c00: 6a5b ldr r3, [r3, #36] @ 0x24 + 8007c02: 2b00 cmp r3, #0 + 8007c04: d012 beq.n 8007c2c { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - 8003aa6: 687b ldr r3, [r7, #4] - 8003aa8: 3324 adds r3, #36 @ 0x24 - 8003aaa: 4618 mov r0, r3 - 8003aac: f000 fd5c bl 8004568 - 8003ab0: 4603 mov r3, r0 - 8003ab2: 2b00 cmp r3, #0 - 8003ab4: d001 beq.n 8003aba + 8007c06: 687b ldr r3, [r7, #4] + 8007c08: 3324 adds r3, #36 @ 0x24 + 8007c0a: 4618 mov r0, r3 + 8007c0c: f000 fd50 bl 80086b0 + 8007c10: 4603 mov r3, r0 + 8007c12: 2b00 cmp r3, #0 + 8007c14: d001 beq.n 8007c1a { /* The task waiting has a higher priority so record that a context switch is required. */ vTaskMissedYield(); - 8003ab6: f000 fe35 bl 8004724 + 8007c16: f000 fe29 bl 800886c break; } } #endif /* configUSE_QUEUE_SETS */ --cTxLock; - 8003aba: 7bfb ldrb r3, [r7, #15] - 8003abc: 3b01 subs r3, #1 - 8003abe: b2db uxtb r3, r3 - 8003ac0: 73fb strb r3, [r7, #15] + 8007c1a: 7bfb ldrb r3, [r7, #15] + 8007c1c: 3b01 subs r3, #1 + 8007c1e: b2db uxtb r3, r3 + 8007c20: 73fb strb r3, [r7, #15] while( cTxLock > queueLOCKED_UNMODIFIED ) - 8003ac2: f997 300f ldrsb.w r3, [r7, #15] - 8003ac6: 2b00 cmp r3, #0 - 8003ac8: dce9 bgt.n 8003a9e - 8003aca: e000 b.n 8003ace + 8007c22: f997 300f ldrsb.w r3, [r7, #15] + 8007c26: 2b00 cmp r3, #0 + 8007c28: dce9 bgt.n 8007bfe + 8007c2a: e000 b.n 8007c2e break; - 8003acc: bf00 nop + 8007c2c: bf00 nop } pxQueue->cTxLock = queueUNLOCKED; - 8003ace: 687b ldr r3, [r7, #4] - 8003ad0: 22ff movs r2, #255 @ 0xff - 8003ad2: f883 2045 strb.w r2, [r3, #69] @ 0x45 + 8007c2e: 687b ldr r3, [r7, #4] + 8007c30: 22ff movs r2, #255 @ 0xff + 8007c32: f883 2045 strb.w r2, [r3, #69] @ 0x45 } taskEXIT_CRITICAL(); - 8003ad6: f001 fca9 bl 800542c + 8007c36: f001 fe61 bl 80098fc /* Do the same for the Rx lock. */ taskENTER_CRITICAL(); - 8003ada: f001 fc75 bl 80053c8 + 8007c3a: f001 fe2d bl 8009898 { int8_t cRxLock = pxQueue->cRxLock; - 8003ade: 687b ldr r3, [r7, #4] - 8003ae0: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 - 8003ae4: 73bb strb r3, [r7, #14] + 8007c3e: 687b ldr r3, [r7, #4] + 8007c40: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 + 8007c44: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) - 8003ae6: e011 b.n 8003b0c + 8007c46: e011 b.n 8007c6c { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) - 8003ae8: 687b ldr r3, [r7, #4] - 8003aea: 691b ldr r3, [r3, #16] - 8003aec: 2b00 cmp r3, #0 - 8003aee: d012 beq.n 8003b16 + 8007c48: 687b ldr r3, [r7, #4] + 8007c4a: 691b ldr r3, [r3, #16] + 8007c4c: 2b00 cmp r3, #0 + 8007c4e: d012 beq.n 8007c76 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - 8003af0: 687b ldr r3, [r7, #4] - 8003af2: 3310 adds r3, #16 - 8003af4: 4618 mov r0, r3 - 8003af6: f000 fd37 bl 8004568 - 8003afa: 4603 mov r3, r0 - 8003afc: 2b00 cmp r3, #0 - 8003afe: d001 beq.n 8003b04 + 8007c50: 687b ldr r3, [r7, #4] + 8007c52: 3310 adds r3, #16 + 8007c54: 4618 mov r0, r3 + 8007c56: f000 fd2b bl 80086b0 + 8007c5a: 4603 mov r3, r0 + 8007c5c: 2b00 cmp r3, #0 + 8007c5e: d001 beq.n 8007c64 { vTaskMissedYield(); - 8003b00: f000 fe10 bl 8004724 + 8007c60: f000 fe04 bl 800886c else { mtCOVERAGE_TEST_MARKER(); } --cRxLock; - 8003b04: 7bbb ldrb r3, [r7, #14] - 8003b06: 3b01 subs r3, #1 - 8003b08: b2db uxtb r3, r3 - 8003b0a: 73bb strb r3, [r7, #14] + 8007c64: 7bbb ldrb r3, [r7, #14] + 8007c66: 3b01 subs r3, #1 + 8007c68: b2db uxtb r3, r3 + 8007c6a: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) - 8003b0c: f997 300e ldrsb.w r3, [r7, #14] - 8003b10: 2b00 cmp r3, #0 - 8003b12: dce9 bgt.n 8003ae8 - 8003b14: e000 b.n 8003b18 + 8007c6c: f997 300e ldrsb.w r3, [r7, #14] + 8007c70: 2b00 cmp r3, #0 + 8007c72: dce9 bgt.n 8007c48 + 8007c74: e000 b.n 8007c78 } else { break; - 8003b16: bf00 nop + 8007c76: bf00 nop } } pxQueue->cRxLock = queueUNLOCKED; - 8003b18: 687b ldr r3, [r7, #4] - 8003b1a: 22ff movs r2, #255 @ 0xff - 8003b1c: f883 2044 strb.w r2, [r3, #68] @ 0x44 + 8007c78: 687b ldr r3, [r7, #4] + 8007c7a: 22ff movs r2, #255 @ 0xff + 8007c7c: f883 2044 strb.w r2, [r3, #68] @ 0x44 } taskEXIT_CRITICAL(); - 8003b20: f001 fc84 bl 800542c + 8007c80: f001 fe3c bl 80098fc } - 8003b24: bf00 nop - 8003b26: 3710 adds r7, #16 - 8003b28: 46bd mov sp, r7 - 8003b2a: bd80 pop {r7, pc} + 8007c84: bf00 nop + 8007c86: 3710 adds r7, #16 + 8007c88: 46bd mov sp, r7 + 8007c8a: bd80 pop {r7, pc} -08003b2c : +08007c8c : /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) { - 8003b2c: b580 push {r7, lr} - 8003b2e: b084 sub sp, #16 - 8003b30: af00 add r7, sp, #0 - 8003b32: 6078 str r0, [r7, #4] + 8007c8c: b580 push {r7, lr} + 8007c8e: b084 sub sp, #16 + 8007c90: af00 add r7, sp, #0 + 8007c92: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); - 8003b34: f001 fc48 bl 80053c8 + 8007c94: f001 fe00 bl 8009898 { if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) - 8003b38: 687b ldr r3, [r7, #4] - 8003b3a: 6b9b ldr r3, [r3, #56] @ 0x38 - 8003b3c: 2b00 cmp r3, #0 - 8003b3e: d102 bne.n 8003b46 + 8007c98: 687b ldr r3, [r7, #4] + 8007c9a: 6b9b ldr r3, [r3, #56] @ 0x38 + 8007c9c: 2b00 cmp r3, #0 + 8007c9e: d102 bne.n 8007ca6 { xReturn = pdTRUE; - 8003b40: 2301 movs r3, #1 - 8003b42: 60fb str r3, [r7, #12] - 8003b44: e001 b.n 8003b4a + 8007ca0: 2301 movs r3, #1 + 8007ca2: 60fb str r3, [r7, #12] + 8007ca4: e001 b.n 8007caa } else { xReturn = pdFALSE; - 8003b46: 2300 movs r3, #0 - 8003b48: 60fb str r3, [r7, #12] + 8007ca6: 2300 movs r3, #0 + 8007ca8: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); - 8003b4a: f001 fc6f bl 800542c + 8007caa: f001 fe27 bl 80098fc return xReturn; - 8003b4e: 68fb ldr r3, [r7, #12] + 8007cae: 68fb ldr r3, [r7, #12] } - 8003b50: 4618 mov r0, r3 - 8003b52: 3710 adds r7, #16 - 8003b54: 46bd mov sp, r7 - 8003b56: bd80 pop {r7, pc} + 8007cb0: 4618 mov r0, r3 + 8007cb2: 3710 adds r7, #16 + 8007cb4: 46bd mov sp, r7 + 8007cb6: bd80 pop {r7, pc} -08003b58 : +08007cb8 : return xReturn; } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) { - 8003b58: b580 push {r7, lr} - 8003b5a: b084 sub sp, #16 - 8003b5c: af00 add r7, sp, #0 - 8003b5e: 6078 str r0, [r7, #4] + 8007cb8: b580 push {r7, lr} + 8007cba: b084 sub sp, #16 + 8007cbc: af00 add r7, sp, #0 + 8007cbe: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); - 8003b60: f001 fc32 bl 80053c8 + 8007cc0: f001 fdea bl 8009898 { if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) - 8003b64: 687b ldr r3, [r7, #4] - 8003b66: 6b9a ldr r2, [r3, #56] @ 0x38 - 8003b68: 687b ldr r3, [r7, #4] - 8003b6a: 6bdb ldr r3, [r3, #60] @ 0x3c - 8003b6c: 429a cmp r2, r3 - 8003b6e: d102 bne.n 8003b76 + 8007cc4: 687b ldr r3, [r7, #4] + 8007cc6: 6b9a ldr r2, [r3, #56] @ 0x38 + 8007cc8: 687b ldr r3, [r7, #4] + 8007cca: 6bdb ldr r3, [r3, #60] @ 0x3c + 8007ccc: 429a cmp r2, r3 + 8007cce: d102 bne.n 8007cd6 { xReturn = pdTRUE; - 8003b70: 2301 movs r3, #1 - 8003b72: 60fb str r3, [r7, #12] - 8003b74: e001 b.n 8003b7a + 8007cd0: 2301 movs r3, #1 + 8007cd2: 60fb str r3, [r7, #12] + 8007cd4: e001 b.n 8007cda } else { xReturn = pdFALSE; - 8003b76: 2300 movs r3, #0 - 8003b78: 60fb str r3, [r7, #12] + 8007cd6: 2300 movs r3, #0 + 8007cd8: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); - 8003b7a: f001 fc57 bl 800542c + 8007cda: f001 fe0f bl 80098fc return xReturn; - 8003b7e: 68fb ldr r3, [r7, #12] + 8007cde: 68fb ldr r3, [r7, #12] } - 8003b80: 4618 mov r0, r3 - 8003b82: 3710 adds r7, #16 - 8003b84: 46bd mov sp, r7 - 8003b86: bd80 pop {r7, pc} + 8007ce0: 4618 mov r0, r3 + 8007ce2: 3710 adds r7, #16 + 8007ce4: 46bd mov sp, r7 + 8007ce6: bd80 pop {r7, pc} -08003b88 : +08007ce8 : /*-----------------------------------------------------------*/ #if ( configQUEUE_REGISTRY_SIZE > 0 ) void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ { - 8003b88: b480 push {r7} - 8003b8a: b085 sub sp, #20 - 8003b8c: af00 add r7, sp, #0 - 8003b8e: 6078 str r0, [r7, #4] - 8003b90: 6039 str r1, [r7, #0] + 8007ce8: b480 push {r7} + 8007cea: b085 sub sp, #20 + 8007cec: af00 add r7, sp, #0 + 8007cee: 6078 str r0, [r7, #4] + 8007cf0: 6039 str r1, [r7, #0] UBaseType_t ux; /* See if there is an empty space in the registry. A NULL name denotes a free slot. */ for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) - 8003b92: 2300 movs r3, #0 - 8003b94: 60fb str r3, [r7, #12] - 8003b96: e014 b.n 8003bc2 + 8007cf2: 2300 movs r3, #0 + 8007cf4: 60fb str r3, [r7, #12] + 8007cf6: e014 b.n 8007d22 { if( xQueueRegistry[ ux ].pcQueueName == NULL ) - 8003b98: 4a0f ldr r2, [pc, #60] @ (8003bd8 ) - 8003b9a: 68fb ldr r3, [r7, #12] - 8003b9c: f852 3033 ldr.w r3, [r2, r3, lsl #3] - 8003ba0: 2b00 cmp r3, #0 - 8003ba2: d10b bne.n 8003bbc + 8007cf8: 4a0f ldr r2, [pc, #60] @ (8007d38 ) + 8007cfa: 68fb ldr r3, [r7, #12] + 8007cfc: f852 3033 ldr.w r3, [r2, r3, lsl #3] + 8007d00: 2b00 cmp r3, #0 + 8007d02: d10b bne.n 8007d1c { /* Store the information on this queue. */ xQueueRegistry[ ux ].pcQueueName = pcQueueName; - 8003ba4: 490c ldr r1, [pc, #48] @ (8003bd8 ) - 8003ba6: 68fb ldr r3, [r7, #12] - 8003ba8: 683a ldr r2, [r7, #0] - 8003baa: f841 2033 str.w r2, [r1, r3, lsl #3] + 8007d04: 490c ldr r1, [pc, #48] @ (8007d38 ) + 8007d06: 68fb ldr r3, [r7, #12] + 8007d08: 683a ldr r2, [r7, #0] + 8007d0a: f841 2033 str.w r2, [r1, r3, lsl #3] xQueueRegistry[ ux ].xHandle = xQueue; - 8003bae: 4a0a ldr r2, [pc, #40] @ (8003bd8 ) - 8003bb0: 68fb ldr r3, [r7, #12] - 8003bb2: 00db lsls r3, r3, #3 - 8003bb4: 4413 add r3, r2 - 8003bb6: 687a ldr r2, [r7, #4] - 8003bb8: 605a str r2, [r3, #4] + 8007d0e: 4a0a ldr r2, [pc, #40] @ (8007d38 ) + 8007d10: 68fb ldr r3, [r7, #12] + 8007d12: 00db lsls r3, r3, #3 + 8007d14: 4413 add r3, r2 + 8007d16: 687a ldr r2, [r7, #4] + 8007d18: 605a str r2, [r3, #4] traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ); break; - 8003bba: e006 b.n 8003bca + 8007d1a: e006 b.n 8007d2a for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) - 8003bbc: 68fb ldr r3, [r7, #12] - 8003bbe: 3301 adds r3, #1 - 8003bc0: 60fb str r3, [r7, #12] - 8003bc2: 68fb ldr r3, [r7, #12] - 8003bc4: 2b07 cmp r3, #7 - 8003bc6: d9e7 bls.n 8003b98 + 8007d1c: 68fb ldr r3, [r7, #12] + 8007d1e: 3301 adds r3, #1 + 8007d20: 60fb str r3, [r7, #12] + 8007d22: 68fb ldr r3, [r7, #12] + 8007d24: 2b07 cmp r3, #7 + 8007d26: d9e7 bls.n 8007cf8 else { mtCOVERAGE_TEST_MARKER(); } } } - 8003bc8: bf00 nop - 8003bca: bf00 nop - 8003bcc: 3714 adds r7, #20 - 8003bce: 46bd mov sp, r7 - 8003bd0: f85d 7b04 ldr.w r7, [sp], #4 - 8003bd4: 4770 bx lr - 8003bd6: bf00 nop - 8003bd8: 200008f8 .word 0x200008f8 + 8007d28: bf00 nop + 8007d2a: bf00 nop + 8007d2c: 3714 adds r7, #20 + 8007d2e: 46bd mov sp, r7 + 8007d30: f85d 7b04 ldr.w r7, [sp], #4 + 8007d34: 4770 bx lr + 8007d36: bf00 nop + 8007d38: 20000a80 .word 0x20000a80 -08003bdc : +08007d3c : +/*-----------------------------------------------------------*/ + +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void vQueueUnregisterQueue( QueueHandle_t xQueue ) + { + 8007d3c: b480 push {r7} + 8007d3e: b085 sub sp, #20 + 8007d40: af00 add r7, sp, #0 + 8007d42: 6078 str r0, [r7, #4] + UBaseType_t ux; + + /* See if the handle of the queue being unregistered in actually in the + registry. */ + for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) + 8007d44: 2300 movs r3, #0 + 8007d46: 60fb str r3, [r7, #12] + 8007d48: e016 b.n 8007d78 + { + if( xQueueRegistry[ ux ].xHandle == xQueue ) + 8007d4a: 4a10 ldr r2, [pc, #64] @ (8007d8c ) + 8007d4c: 68fb ldr r3, [r7, #12] + 8007d4e: 00db lsls r3, r3, #3 + 8007d50: 4413 add r3, r2 + 8007d52: 685b ldr r3, [r3, #4] + 8007d54: 687a ldr r2, [r7, #4] + 8007d56: 429a cmp r2, r3 + 8007d58: d10b bne.n 8007d72 + { + /* Set the name to NULL to show that this slot if free again. */ + xQueueRegistry[ ux ].pcQueueName = NULL; + 8007d5a: 4a0c ldr r2, [pc, #48] @ (8007d8c ) + 8007d5c: 68fb ldr r3, [r7, #12] + 8007d5e: 2100 movs r1, #0 + 8007d60: f842 1033 str.w r1, [r2, r3, lsl #3] + + /* Set the handle to NULL to ensure the same queue handle cannot + appear in the registry twice if it is added, removed, then + added again. */ + xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0; + 8007d64: 4a09 ldr r2, [pc, #36] @ (8007d8c ) + 8007d66: 68fb ldr r3, [r7, #12] + 8007d68: 00db lsls r3, r3, #3 + 8007d6a: 4413 add r3, r2 + 8007d6c: 2200 movs r2, #0 + 8007d6e: 605a str r2, [r3, #4] + break; + 8007d70: e006 b.n 8007d80 + for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) + 8007d72: 68fb ldr r3, [r7, #12] + 8007d74: 3301 adds r3, #1 + 8007d76: 60fb str r3, [r7, #12] + 8007d78: 68fb ldr r3, [r7, #12] + 8007d7a: 2b07 cmp r3, #7 + 8007d7c: d9e5 bls.n 8007d4a + { + mtCOVERAGE_TEST_MARKER(); + } + } + + } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ + 8007d7e: bf00 nop + 8007d80: bf00 nop + 8007d82: 3714 adds r7, #20 + 8007d84: 46bd mov sp, r7 + 8007d86: f85d 7b04 ldr.w r7, [sp], #4 + 8007d8a: 4770 bx lr + 8007d8c: 20000a80 .word 0x20000a80 + +08007d90 : /*-----------------------------------------------------------*/ #if ( configUSE_TIMERS == 1 ) void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { - 8003bdc: b580 push {r7, lr} - 8003bde: b086 sub sp, #24 - 8003be0: af00 add r7, sp, #0 - 8003be2: 60f8 str r0, [r7, #12] - 8003be4: 60b9 str r1, [r7, #8] - 8003be6: 607a str r2, [r7, #4] + 8007d90: b580 push {r7, lr} + 8007d92: b086 sub sp, #24 + 8007d94: af00 add r7, sp, #0 + 8007d96: 60f8 str r0, [r7, #12] + 8007d98: 60b9 str r1, [r7, #8] + 8007d9a: 607a str r2, [r7, #4] Queue_t * const pxQueue = xQueue; - 8003be8: 68fb ldr r3, [r7, #12] - 8003bea: 617b str r3, [r7, #20] + 8007d9c: 68fb ldr r3, [r7, #12] + 8007d9e: 617b str r3, [r7, #20] will not actually cause the task to block, just place it on a blocked list. It will not block until the scheduler is unlocked - at which time a yield will be performed. If an item is added to the queue while the queue is locked, and the calling task blocks on the queue, then the calling task will be immediately unblocked when the queue is unlocked. */ prvLockQueue( pxQueue ); - 8003bec: f001 fbec bl 80053c8 - 8003bf0: 697b ldr r3, [r7, #20] - 8003bf2: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 - 8003bf6: b25b sxtb r3, r3 - 8003bf8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff - 8003bfc: d103 bne.n 8003c06 - 8003bfe: 697b ldr r3, [r7, #20] - 8003c00: 2200 movs r2, #0 - 8003c02: f883 2044 strb.w r2, [r3, #68] @ 0x44 - 8003c06: 697b ldr r3, [r7, #20] - 8003c08: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 - 8003c0c: b25b sxtb r3, r3 - 8003c0e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff - 8003c12: d103 bne.n 8003c1c - 8003c14: 697b ldr r3, [r7, #20] - 8003c16: 2200 movs r2, #0 - 8003c18: f883 2045 strb.w r2, [r3, #69] @ 0x45 - 8003c1c: f001 fc06 bl 800542c + 8007da0: f001 fd7a bl 8009898 + 8007da4: 697b ldr r3, [r7, #20] + 8007da6: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 + 8007daa: b25b sxtb r3, r3 + 8007dac: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8007db0: d103 bne.n 8007dba + 8007db2: 697b ldr r3, [r7, #20] + 8007db4: 2200 movs r2, #0 + 8007db6: f883 2044 strb.w r2, [r3, #68] @ 0x44 + 8007dba: 697b ldr r3, [r7, #20] + 8007dbc: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 + 8007dc0: b25b sxtb r3, r3 + 8007dc2: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8007dc6: d103 bne.n 8007dd0 + 8007dc8: 697b ldr r3, [r7, #20] + 8007dca: 2200 movs r2, #0 + 8007dcc: f883 2045 strb.w r2, [r3, #69] @ 0x45 + 8007dd0: f001 fd94 bl 80098fc if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U ) - 8003c20: 697b ldr r3, [r7, #20] - 8003c22: 6b9b ldr r3, [r3, #56] @ 0x38 - 8003c24: 2b00 cmp r3, #0 - 8003c26: d106 bne.n 8003c36 + 8007dd4: 697b ldr r3, [r7, #20] + 8007dd6: 6b9b ldr r3, [r3, #56] @ 0x38 + 8007dd8: 2b00 cmp r3, #0 + 8007dda: d106 bne.n 8007dea { /* There is nothing in the queue, block for the specified period. */ vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely ); - 8003c28: 697b ldr r3, [r7, #20] - 8003c2a: 3324 adds r3, #36 @ 0x24 - 8003c2c: 687a ldr r2, [r7, #4] - 8003c2e: 68b9 ldr r1, [r7, #8] - 8003c30: 4618 mov r0, r3 - 8003c32: f000 fc6d bl 8004510 + 8007ddc: 697b ldr r3, [r7, #20] + 8007dde: 3324 adds r3, #36 @ 0x24 + 8007de0: 687a ldr r2, [r7, #4] + 8007de2: 68b9 ldr r1, [r7, #8] + 8007de4: 4618 mov r0, r3 + 8007de6: f000 fc37 bl 8008658 } else { mtCOVERAGE_TEST_MARKER(); } prvUnlockQueue( pxQueue ); - 8003c36: 6978 ldr r0, [r7, #20] - 8003c38: f7ff ff26 bl 8003a88 + 8007dea: 6978 ldr r0, [r7, #20] + 8007dec: f7ff fefc bl 8007be8 } - 8003c3c: bf00 nop - 8003c3e: 3718 adds r7, #24 - 8003c40: 46bd mov sp, r7 - 8003c42: bd80 pop {r7, pc} + 8007df0: bf00 nop + 8007df2: 3718 adds r7, #24 + 8007df4: 46bd mov sp, r7 + 8007df6: bd80 pop {r7, pc} -08003c44 : +08007df8 : const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) { - 8003c44: b580 push {r7, lr} - 8003c46: b08e sub sp, #56 @ 0x38 - 8003c48: af04 add r7, sp, #16 - 8003c4a: 60f8 str r0, [r7, #12] - 8003c4c: 60b9 str r1, [r7, #8] - 8003c4e: 607a str r2, [r7, #4] - 8003c50: 603b str r3, [r7, #0] + 8007df8: b580 push {r7, lr} + 8007dfa: b08e sub sp, #56 @ 0x38 + 8007dfc: af04 add r7, sp, #16 + 8007dfe: 60f8 str r0, [r7, #12] + 8007e00: 60b9 str r1, [r7, #8] + 8007e02: 607a str r2, [r7, #4] + 8007e04: 603b str r3, [r7, #0] TCB_t *pxNewTCB; TaskHandle_t xReturn; configASSERT( puxStackBuffer != NULL ); - 8003c52: 6b7b ldr r3, [r7, #52] @ 0x34 - 8003c54: 2b00 cmp r3, #0 - 8003c56: d10b bne.n 8003c70 + 8007e06: 6b7b ldr r3, [r7, #52] @ 0x34 + 8007e08: 2b00 cmp r3, #0 + 8007e0a: d10b bne.n 8007e24 __asm volatile - 8003c58: f04f 0350 mov.w r3, #80 @ 0x50 - 8003c5c: f383 8811 msr BASEPRI, r3 - 8003c60: f3bf 8f6f isb sy - 8003c64: f3bf 8f4f dsb sy - 8003c68: 623b str r3, [r7, #32] + 8007e0c: f04f 0350 mov.w r3, #80 @ 0x50 + 8007e10: f383 8811 msr BASEPRI, r3 + 8007e14: f3bf 8f6f isb sy + 8007e18: f3bf 8f4f dsb sy + 8007e1c: 623b str r3, [r7, #32] } - 8003c6a: bf00 nop - 8003c6c: bf00 nop - 8003c6e: e7fd b.n 8003c6c + 8007e1e: bf00 nop + 8007e20: bf00 nop + 8007e22: e7fd b.n 8007e20 configASSERT( pxTaskBuffer != NULL ); - 8003c70: 6bbb ldr r3, [r7, #56] @ 0x38 - 8003c72: 2b00 cmp r3, #0 - 8003c74: d10b bne.n 8003c8e + 8007e24: 6bbb ldr r3, [r7, #56] @ 0x38 + 8007e26: 2b00 cmp r3, #0 + 8007e28: d10b bne.n 8007e42 __asm volatile - 8003c76: f04f 0350 mov.w r3, #80 @ 0x50 - 8003c7a: f383 8811 msr BASEPRI, r3 - 8003c7e: f3bf 8f6f isb sy - 8003c82: f3bf 8f4f dsb sy - 8003c86: 61fb str r3, [r7, #28] + 8007e2a: f04f 0350 mov.w r3, #80 @ 0x50 + 8007e2e: f383 8811 msr BASEPRI, r3 + 8007e32: f3bf 8f6f isb sy + 8007e36: f3bf 8f4f dsb sy + 8007e3a: 61fb str r3, [r7, #28] } - 8003c88: bf00 nop - 8003c8a: bf00 nop - 8003c8c: e7fd b.n 8003c8a + 8007e3c: bf00 nop + 8007e3e: bf00 nop + 8007e40: e7fd b.n 8007e3e #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticTask_t equals the size of the real task structure. */ volatile size_t xSize = sizeof( StaticTask_t ); - 8003c8e: 23a8 movs r3, #168 @ 0xa8 - 8003c90: 613b str r3, [r7, #16] + 8007e42: 23a8 movs r3, #168 @ 0xa8 + 8007e44: 613b str r3, [r7, #16] configASSERT( xSize == sizeof( TCB_t ) ); - 8003c92: 693b ldr r3, [r7, #16] - 8003c94: 2ba8 cmp r3, #168 @ 0xa8 - 8003c96: d00b beq.n 8003cb0 + 8007e46: 693b ldr r3, [r7, #16] + 8007e48: 2ba8 cmp r3, #168 @ 0xa8 + 8007e4a: d00b beq.n 8007e64 __asm volatile - 8003c98: f04f 0350 mov.w r3, #80 @ 0x50 - 8003c9c: f383 8811 msr BASEPRI, r3 - 8003ca0: f3bf 8f6f isb sy - 8003ca4: f3bf 8f4f dsb sy - 8003ca8: 61bb str r3, [r7, #24] + 8007e4c: f04f 0350 mov.w r3, #80 @ 0x50 + 8007e50: f383 8811 msr BASEPRI, r3 + 8007e54: f3bf 8f6f isb sy + 8007e58: f3bf 8f4f dsb sy + 8007e5c: 61bb str r3, [r7, #24] } - 8003caa: bf00 nop - 8003cac: bf00 nop - 8003cae: e7fd b.n 8003cac + 8007e5e: bf00 nop + 8007e60: bf00 nop + 8007e62: e7fd b.n 8007e60 ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */ - 8003cb0: 693b ldr r3, [r7, #16] + 8007e64: 693b ldr r3, [r7, #16] } #endif /* configASSERT_DEFINED */ if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) ) - 8003cb2: 6bbb ldr r3, [r7, #56] @ 0x38 - 8003cb4: 2b00 cmp r3, #0 - 8003cb6: d01e beq.n 8003cf6 - 8003cb8: 6b7b ldr r3, [r7, #52] @ 0x34 - 8003cba: 2b00 cmp r3, #0 - 8003cbc: d01b beq.n 8003cf6 + 8007e66: 6bbb ldr r3, [r7, #56] @ 0x38 + 8007e68: 2b00 cmp r3, #0 + 8007e6a: d01e beq.n 8007eaa + 8007e6c: 6b7b ldr r3, [r7, #52] @ 0x34 + 8007e6e: 2b00 cmp r3, #0 + 8007e70: d01b beq.n 8007eaa { /* The memory used for the task's TCB and stack are passed into this function - use them. */ pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ - 8003cbe: 6bbb ldr r3, [r7, #56] @ 0x38 - 8003cc0: 627b str r3, [r7, #36] @ 0x24 + 8007e72: 6bbb ldr r3, [r7, #56] @ 0x38 + 8007e74: 627b str r3, [r7, #36] @ 0x24 pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer; - 8003cc2: 6a7b ldr r3, [r7, #36] @ 0x24 - 8003cc4: 6b7a ldr r2, [r7, #52] @ 0x34 - 8003cc6: 631a str r2, [r3, #48] @ 0x30 + 8007e76: 6a7b ldr r3, [r7, #36] @ 0x24 + 8007e78: 6b7a ldr r2, [r7, #52] @ 0x34 + 8007e7a: 631a str r2, [r3, #48] @ 0x30 #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this task was created statically in case the task is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; - 8003cc8: 6a7b ldr r3, [r7, #36] @ 0x24 - 8003cca: 2202 movs r2, #2 - 8003ccc: f883 20a5 strb.w r2, [r3, #165] @ 0xa5 + 8007e7c: 6a7b ldr r3, [r7, #36] @ 0x24 + 8007e7e: 2202 movs r2, #2 + 8007e80: f883 20a5 strb.w r2, [r3, #165] @ 0xa5 } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); - 8003cd0: 2300 movs r3, #0 - 8003cd2: 9303 str r3, [sp, #12] - 8003cd4: 6a7b ldr r3, [r7, #36] @ 0x24 - 8003cd6: 9302 str r3, [sp, #8] - 8003cd8: f107 0314 add.w r3, r7, #20 - 8003cdc: 9301 str r3, [sp, #4] - 8003cde: 6b3b ldr r3, [r7, #48] @ 0x30 - 8003ce0: 9300 str r3, [sp, #0] - 8003ce2: 683b ldr r3, [r7, #0] - 8003ce4: 687a ldr r2, [r7, #4] - 8003ce6: 68b9 ldr r1, [r7, #8] - 8003ce8: 68f8 ldr r0, [r7, #12] - 8003cea: f000 f851 bl 8003d90 + 8007e84: 2300 movs r3, #0 + 8007e86: 9303 str r3, [sp, #12] + 8007e88: 6a7b ldr r3, [r7, #36] @ 0x24 + 8007e8a: 9302 str r3, [sp, #8] + 8007e8c: f107 0314 add.w r3, r7, #20 + 8007e90: 9301 str r3, [sp, #4] + 8007e92: 6b3b ldr r3, [r7, #48] @ 0x30 + 8007e94: 9300 str r3, [sp, #0] + 8007e96: 683b ldr r3, [r7, #0] + 8007e98: 687a ldr r2, [r7, #4] + 8007e9a: 68b9 ldr r1, [r7, #8] + 8007e9c: 68f8 ldr r0, [r7, #12] + 8007e9e: f000 f851 bl 8007f44 prvAddNewTaskToReadyList( pxNewTCB ); - 8003cee: 6a78 ldr r0, [r7, #36] @ 0x24 - 8003cf0: f000 f8f6 bl 8003ee0 - 8003cf4: e001 b.n 8003cfa + 8007ea2: 6a78 ldr r0, [r7, #36] @ 0x24 + 8007ea4: f000 f8f6 bl 8008094 + 8007ea8: e001 b.n 8007eae } else { xReturn = NULL; - 8003cf6: 2300 movs r3, #0 - 8003cf8: 617b str r3, [r7, #20] + 8007eaa: 2300 movs r3, #0 + 8007eac: 617b str r3, [r7, #20] } return xReturn; - 8003cfa: 697b ldr r3, [r7, #20] + 8007eae: 697b ldr r3, [r7, #20] } - 8003cfc: 4618 mov r0, r3 - 8003cfe: 3728 adds r7, #40 @ 0x28 - 8003d00: 46bd mov sp, r7 - 8003d02: bd80 pop {r7, pc} + 8007eb0: 4618 mov r0, r3 + 8007eb2: 3728 adds r7, #40 @ 0x28 + 8007eb4: 46bd mov sp, r7 + 8007eb6: bd80 pop {r7, pc} -08003d04 : +08007eb8 : const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const configSTACK_DEPTH_TYPE usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) { - 8003d04: b580 push {r7, lr} - 8003d06: b08c sub sp, #48 @ 0x30 - 8003d08: af04 add r7, sp, #16 - 8003d0a: 60f8 str r0, [r7, #12] - 8003d0c: 60b9 str r1, [r7, #8] - 8003d0e: 603b str r3, [r7, #0] - 8003d10: 4613 mov r3, r2 - 8003d12: 80fb strh r3, [r7, #6] + 8007eb8: b580 push {r7, lr} + 8007eba: b08c sub sp, #48 @ 0x30 + 8007ebc: af04 add r7, sp, #16 + 8007ebe: 60f8 str r0, [r7, #12] + 8007ec0: 60b9 str r1, [r7, #8] + 8007ec2: 603b str r3, [r7, #0] + 8007ec4: 4613 mov r3, r2 + 8007ec6: 80fb strh r3, [r7, #6] #else /* portSTACK_GROWTH */ { StackType_t *pxStack; /* Allocate space for the stack used by the task being created. */ pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */ - 8003d14: 88fb ldrh r3, [r7, #6] - 8003d16: 009b lsls r3, r3, #2 - 8003d18: 4618 mov r0, r3 - 8003d1a: f001 fc77 bl 800560c - 8003d1e: 6178 str r0, [r7, #20] + 8007ec8: 88fb ldrh r3, [r7, #6] + 8007eca: 009b lsls r3, r3, #2 + 8007ecc: 4618 mov r0, r3 + 8007ece: f001 fe05 bl 8009adc + 8007ed2: 6178 str r0, [r7, #20] if( pxStack != NULL ) - 8003d20: 697b ldr r3, [r7, #20] - 8003d22: 2b00 cmp r3, #0 - 8003d24: d00e beq.n 8003d44 + 8007ed4: 697b ldr r3, [r7, #20] + 8007ed6: 2b00 cmp r3, #0 + 8007ed8: d00e beq.n 8007ef8 { /* Allocate space for the TCB. */ pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */ - 8003d26: 20a8 movs r0, #168 @ 0xa8 - 8003d28: f001 fc70 bl 800560c - 8003d2c: 61f8 str r0, [r7, #28] + 8007eda: 20a8 movs r0, #168 @ 0xa8 + 8007edc: f001 fdfe bl 8009adc + 8007ee0: 61f8 str r0, [r7, #28] if( pxNewTCB != NULL ) - 8003d2e: 69fb ldr r3, [r7, #28] - 8003d30: 2b00 cmp r3, #0 - 8003d32: d003 beq.n 8003d3c + 8007ee2: 69fb ldr r3, [r7, #28] + 8007ee4: 2b00 cmp r3, #0 + 8007ee6: d003 beq.n 8007ef0 { /* Store the stack location in the TCB. */ pxNewTCB->pxStack = pxStack; - 8003d34: 69fb ldr r3, [r7, #28] - 8003d36: 697a ldr r2, [r7, #20] - 8003d38: 631a str r2, [r3, #48] @ 0x30 - 8003d3a: e005 b.n 8003d48 + 8007ee8: 69fb ldr r3, [r7, #28] + 8007eea: 697a ldr r2, [r7, #20] + 8007eec: 631a str r2, [r3, #48] @ 0x30 + 8007eee: e005 b.n 8007efc } else { /* The stack cannot be used as the TCB was not created. Free it again. */ vPortFree( pxStack ); - 8003d3c: 6978 ldr r0, [r7, #20] - 8003d3e: f001 fd33 bl 80057a8 - 8003d42: e001 b.n 8003d48 + 8007ef0: 6978 ldr r0, [r7, #20] + 8007ef2: f001 fec1 bl 8009c78 + 8007ef6: e001 b.n 8007efc } } else { pxNewTCB = NULL; - 8003d44: 2300 movs r3, #0 - 8003d46: 61fb str r3, [r7, #28] + 8007ef8: 2300 movs r3, #0 + 8007efa: 61fb str r3, [r7, #28] } } #endif /* portSTACK_GROWTH */ if( pxNewTCB != NULL ) - 8003d48: 69fb ldr r3, [r7, #28] - 8003d4a: 2b00 cmp r3, #0 - 8003d4c: d017 beq.n 8003d7e + 8007efc: 69fb ldr r3, [r7, #28] + 8007efe: 2b00 cmp r3, #0 + 8007f00: d017 beq.n 8007f32 { #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this task was created dynamically in case it is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB; - 8003d4e: 69fb ldr r3, [r7, #28] - 8003d50: 2200 movs r2, #0 - 8003d52: f883 20a5 strb.w r2, [r3, #165] @ 0xa5 + 8007f02: 69fb ldr r3, [r7, #28] + 8007f04: 2200 movs r2, #0 + 8007f06: f883 20a5 strb.w r2, [r3, #165] @ 0xa5 } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); - 8003d56: 88fa ldrh r2, [r7, #6] - 8003d58: 2300 movs r3, #0 - 8003d5a: 9303 str r3, [sp, #12] - 8003d5c: 69fb ldr r3, [r7, #28] - 8003d5e: 9302 str r3, [sp, #8] - 8003d60: 6afb ldr r3, [r7, #44] @ 0x2c - 8003d62: 9301 str r3, [sp, #4] - 8003d64: 6abb ldr r3, [r7, #40] @ 0x28 - 8003d66: 9300 str r3, [sp, #0] - 8003d68: 683b ldr r3, [r7, #0] - 8003d6a: 68b9 ldr r1, [r7, #8] - 8003d6c: 68f8 ldr r0, [r7, #12] - 8003d6e: f000 f80f bl 8003d90 + 8007f0a: 88fa ldrh r2, [r7, #6] + 8007f0c: 2300 movs r3, #0 + 8007f0e: 9303 str r3, [sp, #12] + 8007f10: 69fb ldr r3, [r7, #28] + 8007f12: 9302 str r3, [sp, #8] + 8007f14: 6afb ldr r3, [r7, #44] @ 0x2c + 8007f16: 9301 str r3, [sp, #4] + 8007f18: 6abb ldr r3, [r7, #40] @ 0x28 + 8007f1a: 9300 str r3, [sp, #0] + 8007f1c: 683b ldr r3, [r7, #0] + 8007f1e: 68b9 ldr r1, [r7, #8] + 8007f20: 68f8 ldr r0, [r7, #12] + 8007f22: f000 f80f bl 8007f44 prvAddNewTaskToReadyList( pxNewTCB ); - 8003d72: 69f8 ldr r0, [r7, #28] - 8003d74: f000 f8b4 bl 8003ee0 + 8007f26: 69f8 ldr r0, [r7, #28] + 8007f28: f000 f8b4 bl 8008094 xReturn = pdPASS; - 8003d78: 2301 movs r3, #1 - 8003d7a: 61bb str r3, [r7, #24] - 8003d7c: e002 b.n 8003d84 + 8007f2c: 2301 movs r3, #1 + 8007f2e: 61bb str r3, [r7, #24] + 8007f30: e002 b.n 8007f38 } else { xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; - 8003d7e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff - 8003d82: 61bb str r3, [r7, #24] + 8007f32: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 8007f36: 61bb str r3, [r7, #24] } return xReturn; - 8003d84: 69bb ldr r3, [r7, #24] + 8007f38: 69bb ldr r3, [r7, #24] } - 8003d86: 4618 mov r0, r3 - 8003d88: 3720 adds r7, #32 - 8003d8a: 46bd mov sp, r7 - 8003d8c: bd80 pop {r7, pc} + 8007f3a: 4618 mov r0, r3 + 8007f3c: 3720 adds r7, #32 + 8007f3e: 46bd mov sp, r7 + 8007f40: bd80 pop {r7, pc} ... -08003d90 : +08007f44 : void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask, TCB_t *pxNewTCB, const MemoryRegion_t * const xRegions ) { - 8003d90: b580 push {r7, lr} - 8003d92: b088 sub sp, #32 - 8003d94: af00 add r7, sp, #0 - 8003d96: 60f8 str r0, [r7, #12] - 8003d98: 60b9 str r1, [r7, #8] - 8003d9a: 607a str r2, [r7, #4] - 8003d9c: 603b str r3, [r7, #0] + 8007f44: b580 push {r7, lr} + 8007f46: b088 sub sp, #32 + 8007f48: af00 add r7, sp, #0 + 8007f4a: 60f8 str r0, [r7, #12] + 8007f4c: 60b9 str r1, [r7, #8] + 8007f4e: 607a str r2, [r7, #4] + 8007f50: 603b str r3, [r7, #0] /* Avoid dependency on memset() if it is not required. */ #if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 ) { /* Fill the stack with a known value to assist debugging. */ ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) ); - 8003d9e: 6b3b ldr r3, [r7, #48] @ 0x30 - 8003da0: 6b18 ldr r0, [r3, #48] @ 0x30 - 8003da2: 687b ldr r3, [r7, #4] - 8003da4: 009b lsls r3, r3, #2 - 8003da6: 461a mov r2, r3 - 8003da8: 21a5 movs r1, #165 @ 0xa5 - 8003daa: f001 fe29 bl 8005a00 + 8007f52: 6b3b ldr r3, [r7, #48] @ 0x30 + 8007f54: 6b18 ldr r0, [r3, #48] @ 0x30 + 8007f56: 687b ldr r3, [r7, #4] + 8007f58: 009b lsls r3, r3, #2 + 8007f5a: 461a mov r2, r3 + 8007f5c: 21a5 movs r1, #165 @ 0xa5 + 8007f5e: f001 ffb7 bl 8009ed0 grows from high memory to low (as per the 80x86) or vice versa. portSTACK_GROWTH is used to make the result positive or negative as required by the port. */ #if( portSTACK_GROWTH < 0 ) { pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] ); - 8003dae: 6b3b ldr r3, [r7, #48] @ 0x30 - 8003db0: 6b1a ldr r2, [r3, #48] @ 0x30 - 8003db2: 687b ldr r3, [r7, #4] - 8003db4: f103 4380 add.w r3, r3, #1073741824 @ 0x40000000 - 8003db8: 3b01 subs r3, #1 - 8003dba: 009b lsls r3, r3, #2 - 8003dbc: 4413 add r3, r2 - 8003dbe: 61bb str r3, [r7, #24] + 8007f62: 6b3b ldr r3, [r7, #48] @ 0x30 + 8007f64: 6b1a ldr r2, [r3, #48] @ 0x30 + 8007f66: 687b ldr r3, [r7, #4] + 8007f68: f103 4380 add.w r3, r3, #1073741824 @ 0x40000000 + 8007f6c: 3b01 subs r3, #1 + 8007f6e: 009b lsls r3, r3, #2 + 8007f70: 4413 add r3, r2 + 8007f72: 61bb str r3, [r7, #24] pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */ - 8003dc0: 69bb ldr r3, [r7, #24] - 8003dc2: f023 0307 bic.w r3, r3, #7 - 8003dc6: 61bb str r3, [r7, #24] + 8007f74: 69bb ldr r3, [r7, #24] + 8007f76: f023 0307 bic.w r3, r3, #7 + 8007f7a: 61bb str r3, [r7, #24] /* Check the alignment of the calculated top of stack is correct. */ configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); - 8003dc8: 69bb ldr r3, [r7, #24] - 8003dca: f003 0307 and.w r3, r3, #7 - 8003dce: 2b00 cmp r3, #0 - 8003dd0: d00b beq.n 8003dea + 8007f7c: 69bb ldr r3, [r7, #24] + 8007f7e: f003 0307 and.w r3, r3, #7 + 8007f82: 2b00 cmp r3, #0 + 8007f84: d00b beq.n 8007f9e __asm volatile - 8003dd2: f04f 0350 mov.w r3, #80 @ 0x50 - 8003dd6: f383 8811 msr BASEPRI, r3 - 8003dda: f3bf 8f6f isb sy - 8003dde: f3bf 8f4f dsb sy - 8003de2: 617b str r3, [r7, #20] + 8007f86: f04f 0350 mov.w r3, #80 @ 0x50 + 8007f8a: f383 8811 msr BASEPRI, r3 + 8007f8e: f3bf 8f6f isb sy + 8007f92: f3bf 8f4f dsb sy + 8007f96: 617b str r3, [r7, #20] } - 8003de4: bf00 nop - 8003de6: bf00 nop - 8003de8: e7fd b.n 8003de6 + 8007f98: bf00 nop + 8007f9a: bf00 nop + 8007f9c: e7fd b.n 8007f9a pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 ); } #endif /* portSTACK_GROWTH */ /* Store the task name in the TCB. */ if( pcName != NULL ) - 8003dea: 68bb ldr r3, [r7, #8] - 8003dec: 2b00 cmp r3, #0 - 8003dee: d01f beq.n 8003e30 + 8007f9e: 68bb ldr r3, [r7, #8] + 8007fa0: 2b00 cmp r3, #0 + 8007fa2: d01f beq.n 8007fe4 { for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) - 8003df0: 2300 movs r3, #0 - 8003df2: 61fb str r3, [r7, #28] - 8003df4: e012 b.n 8003e1c + 8007fa4: 2300 movs r3, #0 + 8007fa6: 61fb str r3, [r7, #28] + 8007fa8: e012 b.n 8007fd0 { pxNewTCB->pcTaskName[ x ] = pcName[ x ]; - 8003df6: 68ba ldr r2, [r7, #8] - 8003df8: 69fb ldr r3, [r7, #28] - 8003dfa: 4413 add r3, r2 - 8003dfc: 7819 ldrb r1, [r3, #0] - 8003dfe: 6b3a ldr r2, [r7, #48] @ 0x30 - 8003e00: 69fb ldr r3, [r7, #28] - 8003e02: 4413 add r3, r2 - 8003e04: 3334 adds r3, #52 @ 0x34 - 8003e06: 460a mov r2, r1 - 8003e08: 701a strb r2, [r3, #0] + 8007faa: 68ba ldr r2, [r7, #8] + 8007fac: 69fb ldr r3, [r7, #28] + 8007fae: 4413 add r3, r2 + 8007fb0: 7819 ldrb r1, [r3, #0] + 8007fb2: 6b3a ldr r2, [r7, #48] @ 0x30 + 8007fb4: 69fb ldr r3, [r7, #28] + 8007fb6: 4413 add r3, r2 + 8007fb8: 3334 adds r3, #52 @ 0x34 + 8007fba: 460a mov r2, r1 + 8007fbc: 701a strb r2, [r3, #0] /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than configMAX_TASK_NAME_LEN characters just in case the memory after the string is not accessible (extremely unlikely). */ if( pcName[ x ] == ( char ) 0x00 ) - 8003e0a: 68ba ldr r2, [r7, #8] - 8003e0c: 69fb ldr r3, [r7, #28] - 8003e0e: 4413 add r3, r2 - 8003e10: 781b ldrb r3, [r3, #0] - 8003e12: 2b00 cmp r3, #0 - 8003e14: d006 beq.n 8003e24 + 8007fbe: 68ba ldr r2, [r7, #8] + 8007fc0: 69fb ldr r3, [r7, #28] + 8007fc2: 4413 add r3, r2 + 8007fc4: 781b ldrb r3, [r3, #0] + 8007fc6: 2b00 cmp r3, #0 + 8007fc8: d006 beq.n 8007fd8 for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) - 8003e16: 69fb ldr r3, [r7, #28] - 8003e18: 3301 adds r3, #1 - 8003e1a: 61fb str r3, [r7, #28] - 8003e1c: 69fb ldr r3, [r7, #28] - 8003e1e: 2b0f cmp r3, #15 - 8003e20: d9e9 bls.n 8003df6 - 8003e22: e000 b.n 8003e26 + 8007fca: 69fb ldr r3, [r7, #28] + 8007fcc: 3301 adds r3, #1 + 8007fce: 61fb str r3, [r7, #28] + 8007fd0: 69fb ldr r3, [r7, #28] + 8007fd2: 2b0f cmp r3, #15 + 8007fd4: d9e9 bls.n 8007faa + 8007fd6: e000 b.n 8007fda { break; - 8003e24: bf00 nop + 8007fd8: bf00 nop } } /* Ensure the name string is terminated in the case that the string length was greater or equal to configMAX_TASK_NAME_LEN. */ pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0'; - 8003e26: 6b3b ldr r3, [r7, #48] @ 0x30 - 8003e28: 2200 movs r2, #0 - 8003e2a: f883 2043 strb.w r2, [r3, #67] @ 0x43 - 8003e2e: e003 b.n 8003e38 + 8007fda: 6b3b ldr r3, [r7, #48] @ 0x30 + 8007fdc: 2200 movs r2, #0 + 8007fde: f883 2043 strb.w r2, [r3, #67] @ 0x43 + 8007fe2: e003 b.n 8007fec } else { /* The task has not been given a name, so just ensure there is a NULL terminator when it is read out. */ pxNewTCB->pcTaskName[ 0 ] = 0x00; - 8003e30: 6b3b ldr r3, [r7, #48] @ 0x30 - 8003e32: 2200 movs r2, #0 - 8003e34: f883 2034 strb.w r2, [r3, #52] @ 0x34 + 8007fe4: 6b3b ldr r3, [r7, #48] @ 0x30 + 8007fe6: 2200 movs r2, #0 + 8007fe8: f883 2034 strb.w r2, [r3, #52] @ 0x34 } /* This is used as an array index so must ensure it's not too large. First remove the privilege bit if one is present. */ if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) - 8003e38: 6abb ldr r3, [r7, #40] @ 0x28 - 8003e3a: 2b37 cmp r3, #55 @ 0x37 - 8003e3c: d901 bls.n 8003e42 + 8007fec: 6abb ldr r3, [r7, #40] @ 0x28 + 8007fee: 2b37 cmp r3, #55 @ 0x37 + 8007ff0: d901 bls.n 8007ff6 { uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U; - 8003e3e: 2337 movs r3, #55 @ 0x37 - 8003e40: 62bb str r3, [r7, #40] @ 0x28 + 8007ff2: 2337 movs r3, #55 @ 0x37 + 8007ff4: 62bb str r3, [r7, #40] @ 0x28 else { mtCOVERAGE_TEST_MARKER(); } pxNewTCB->uxPriority = uxPriority; - 8003e42: 6b3b ldr r3, [r7, #48] @ 0x30 - 8003e44: 6aba ldr r2, [r7, #40] @ 0x28 - 8003e46: 62da str r2, [r3, #44] @ 0x2c + 8007ff6: 6b3b ldr r3, [r7, #48] @ 0x30 + 8007ff8: 6aba ldr r2, [r7, #40] @ 0x28 + 8007ffa: 62da str r2, [r3, #44] @ 0x2c #if ( configUSE_MUTEXES == 1 ) { pxNewTCB->uxBasePriority = uxPriority; - 8003e48: 6b3b ldr r3, [r7, #48] @ 0x30 - 8003e4a: 6aba ldr r2, [r7, #40] @ 0x28 - 8003e4c: 64da str r2, [r3, #76] @ 0x4c + 8007ffc: 6b3b ldr r3, [r7, #48] @ 0x30 + 8007ffe: 6aba ldr r2, [r7, #40] @ 0x28 + 8008000: 64da str r2, [r3, #76] @ 0x4c pxNewTCB->uxMutexesHeld = 0; - 8003e4e: 6b3b ldr r3, [r7, #48] @ 0x30 - 8003e50: 2200 movs r2, #0 - 8003e52: 651a str r2, [r3, #80] @ 0x50 + 8008002: 6b3b ldr r3, [r7, #48] @ 0x30 + 8008004: 2200 movs r2, #0 + 8008006: 651a str r2, [r3, #80] @ 0x50 } #endif /* configUSE_MUTEXES */ vListInitialiseItem( &( pxNewTCB->xStateListItem ) ); - 8003e54: 6b3b ldr r3, [r7, #48] @ 0x30 - 8003e56: 3304 adds r3, #4 - 8003e58: 4618 mov r0, r3 - 8003e5a: f7ff f965 bl 8003128 + 8008008: 6b3b ldr r3, [r7, #48] @ 0x30 + 800800a: 3304 adds r3, #4 + 800800c: 4618 mov r0, r3 + 800800e: f7fe fe33 bl 8006c78 vListInitialiseItem( &( pxNewTCB->xEventListItem ) ); - 8003e5e: 6b3b ldr r3, [r7, #48] @ 0x30 - 8003e60: 3318 adds r3, #24 - 8003e62: 4618 mov r0, r3 - 8003e64: f7ff f960 bl 8003128 + 8008012: 6b3b ldr r3, [r7, #48] @ 0x30 + 8008014: 3318 adds r3, #24 + 8008016: 4618 mov r0, r3 + 8008018: f7fe fe2e bl 8006c78 /* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get back to the containing TCB from a generic item in a list. */ listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB ); - 8003e68: 6b3b ldr r3, [r7, #48] @ 0x30 - 8003e6a: 6b3a ldr r2, [r7, #48] @ 0x30 - 8003e6c: 611a str r2, [r3, #16] + 800801c: 6b3b ldr r3, [r7, #48] @ 0x30 + 800801e: 6b3a ldr r2, [r7, #48] @ 0x30 + 8008020: 611a str r2, [r3, #16] /* Event lists are always in priority order. */ listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ - 8003e6e: 6abb ldr r3, [r7, #40] @ 0x28 - 8003e70: f1c3 0238 rsb r2, r3, #56 @ 0x38 - 8003e74: 6b3b ldr r3, [r7, #48] @ 0x30 - 8003e76: 619a str r2, [r3, #24] + 8008022: 6abb ldr r3, [r7, #40] @ 0x28 + 8008024: f1c3 0238 rsb r2, r3, #56 @ 0x38 + 8008028: 6b3b ldr r3, [r7, #48] @ 0x30 + 800802a: 619a str r2, [r3, #24] listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB ); - 8003e78: 6b3b ldr r3, [r7, #48] @ 0x30 - 8003e7a: 6b3a ldr r2, [r7, #48] @ 0x30 - 8003e7c: 625a str r2, [r3, #36] @ 0x24 + 800802c: 6b3b ldr r3, [r7, #48] @ 0x30 + 800802e: 6b3a ldr r2, [r7, #48] @ 0x30 + 8008030: 625a str r2, [r3, #36] @ 0x24 } #endif #if ( configUSE_TASK_NOTIFICATIONS == 1 ) { pxNewTCB->ulNotifiedValue = 0; - 8003e7e: 6b3b ldr r3, [r7, #48] @ 0x30 - 8003e80: 2200 movs r2, #0 - 8003e82: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 + 8008032: 6b3b ldr r3, [r7, #48] @ 0x30 + 8008034: 2200 movs r2, #0 + 8008036: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; - 8003e86: 6b3b ldr r3, [r7, #48] @ 0x30 - 8003e88: 2200 movs r2, #0 - 8003e8a: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 + 800803a: 6b3b ldr r3, [r7, #48] @ 0x30 + 800803c: 2200 movs r2, #0 + 800803e: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 #if ( configUSE_NEWLIB_REENTRANT == 1 ) { /* Initialise this task's Newlib reent structure. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) ); - 8003e8e: 6b3b ldr r3, [r7, #48] @ 0x30 - 8003e90: 3354 adds r3, #84 @ 0x54 - 8003e92: 224c movs r2, #76 @ 0x4c - 8003e94: 2100 movs r1, #0 - 8003e96: 4618 mov r0, r3 - 8003e98: f001 fdb2 bl 8005a00 - 8003e9c: 6b3b ldr r3, [r7, #48] @ 0x30 - 8003e9e: 4a0d ldr r2, [pc, #52] @ (8003ed4 ) - 8003ea0: 659a str r2, [r3, #88] @ 0x58 - 8003ea2: 6b3b ldr r3, [r7, #48] @ 0x30 - 8003ea4: 4a0c ldr r2, [pc, #48] @ (8003ed8 ) - 8003ea6: 65da str r2, [r3, #92] @ 0x5c - 8003ea8: 6b3b ldr r3, [r7, #48] @ 0x30 - 8003eaa: 4a0c ldr r2, [pc, #48] @ (8003edc ) - 8003eac: 661a str r2, [r3, #96] @ 0x60 + 8008042: 6b3b ldr r3, [r7, #48] @ 0x30 + 8008044: 3354 adds r3, #84 @ 0x54 + 8008046: 224c movs r2, #76 @ 0x4c + 8008048: 2100 movs r1, #0 + 800804a: 4618 mov r0, r3 + 800804c: f001 ff40 bl 8009ed0 + 8008050: 6b3b ldr r3, [r7, #48] @ 0x30 + 8008052: 4a0d ldr r2, [pc, #52] @ (8008088 ) + 8008054: 659a str r2, [r3, #88] @ 0x58 + 8008056: 6b3b ldr r3, [r7, #48] @ 0x30 + 8008058: 4a0c ldr r2, [pc, #48] @ (800808c ) + 800805a: 65da str r2, [r3, #92] @ 0x5c + 800805c: 6b3b ldr r3, [r7, #48] @ 0x30 + 800805e: 4a0c ldr r2, [pc, #48] @ (8008090 ) + 8008060: 661a str r2, [r3, #96] @ 0x60 } #endif /* portSTACK_GROWTH */ } #else /* portHAS_STACK_OVERFLOW_CHECKING */ { pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); - 8003eae: 683a ldr r2, [r7, #0] - 8003eb0: 68f9 ldr r1, [r7, #12] - 8003eb2: 69b8 ldr r0, [r7, #24] - 8003eb4: f001 f95a bl 800516c - 8003eb8: 4602 mov r2, r0 - 8003eba: 6b3b ldr r3, [r7, #48] @ 0x30 - 8003ebc: 601a str r2, [r3, #0] + 8008062: 683a ldr r2, [r7, #0] + 8008064: 68f9 ldr r1, [r7, #12] + 8008066: 69b8 ldr r0, [r7, #24] + 8008068: f001 fae4 bl 8009634 + 800806c: 4602 mov r2, r0 + 800806e: 6b3b ldr r3, [r7, #48] @ 0x30 + 8008070: 601a str r2, [r3, #0] } #endif /* portHAS_STACK_OVERFLOW_CHECKING */ } #endif /* portUSING_MPU_WRAPPERS */ if( pxCreatedTask != NULL ) - 8003ebe: 6afb ldr r3, [r7, #44] @ 0x2c - 8003ec0: 2b00 cmp r3, #0 - 8003ec2: d002 beq.n 8003eca + 8008072: 6afb ldr r3, [r7, #44] @ 0x2c + 8008074: 2b00 cmp r3, #0 + 8008076: d002 beq.n 800807e { /* Pass the handle out in an anonymous way. The handle can be used to change the created task's priority, delete the created task, etc.*/ *pxCreatedTask = ( TaskHandle_t ) pxNewTCB; - 8003ec4: 6afb ldr r3, [r7, #44] @ 0x2c - 8003ec6: 6b3a ldr r2, [r7, #48] @ 0x30 - 8003ec8: 601a str r2, [r3, #0] + 8008078: 6afb ldr r3, [r7, #44] @ 0x2c + 800807a: 6b3a ldr r2, [r7, #48] @ 0x30 + 800807c: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } - 8003eca: bf00 nop - 8003ecc: 3720 adds r7, #32 - 8003ece: 46bd mov sp, r7 - 8003ed0: bd80 pop {r7, pc} - 8003ed2: bf00 nop - 8003ed4: 20004b90 .word 0x20004b90 - 8003ed8: 20004bf8 .word 0x20004bf8 - 8003edc: 20004c60 .word 0x20004c60 + 800807e: bf00 nop + 8008080: 3720 adds r7, #32 + 8008082: 46bd mov sp, r7 + 8008084: bd80 pop {r7, pc} + 8008086: bf00 nop + 8008088: 20004d18 .word 0x20004d18 + 800808c: 20004d80 .word 0x20004d80 + 8008090: 20004de8 .word 0x20004de8 -08003ee0 : +08008094 : /*-----------------------------------------------------------*/ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) { - 8003ee0: b580 push {r7, lr} - 8003ee2: b082 sub sp, #8 - 8003ee4: af00 add r7, sp, #0 - 8003ee6: 6078 str r0, [r7, #4] + 8008094: b580 push {r7, lr} + 8008096: b082 sub sp, #8 + 8008098: af00 add r7, sp, #0 + 800809a: 6078 str r0, [r7, #4] /* Ensure interrupts don't access the task lists while the lists are being updated. */ taskENTER_CRITICAL(); - 8003ee8: f001 fa6e bl 80053c8 + 800809c: f001 fbfc bl 8009898 { uxCurrentNumberOfTasks++; - 8003eec: 4b2d ldr r3, [pc, #180] @ (8003fa4 ) - 8003eee: 681b ldr r3, [r3, #0] - 8003ef0: 3301 adds r3, #1 - 8003ef2: 4a2c ldr r2, [pc, #176] @ (8003fa4 ) - 8003ef4: 6013 str r3, [r2, #0] + 80080a0: 4b2d ldr r3, [pc, #180] @ (8008158 ) + 80080a2: 681b ldr r3, [r3, #0] + 80080a4: 3301 adds r3, #1 + 80080a6: 4a2c ldr r2, [pc, #176] @ (8008158 ) + 80080a8: 6013 str r3, [r2, #0] if( pxCurrentTCB == NULL ) - 8003ef6: 4b2c ldr r3, [pc, #176] @ (8003fa8 ) - 8003ef8: 681b ldr r3, [r3, #0] - 8003efa: 2b00 cmp r3, #0 - 8003efc: d109 bne.n 8003f12 + 80080aa: 4b2c ldr r3, [pc, #176] @ (800815c ) + 80080ac: 681b ldr r3, [r3, #0] + 80080ae: 2b00 cmp r3, #0 + 80080b0: d109 bne.n 80080c6 { /* There are no other tasks, or all the other tasks are in the suspended state - make this the current task. */ pxCurrentTCB = pxNewTCB; - 8003efe: 4a2a ldr r2, [pc, #168] @ (8003fa8 ) - 8003f00: 687b ldr r3, [r7, #4] - 8003f02: 6013 str r3, [r2, #0] + 80080b2: 4a2a ldr r2, [pc, #168] @ (800815c ) + 80080b4: 687b ldr r3, [r7, #4] + 80080b6: 6013 str r3, [r2, #0] if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) - 8003f04: 4b27 ldr r3, [pc, #156] @ (8003fa4 ) - 8003f06: 681b ldr r3, [r3, #0] - 8003f08: 2b01 cmp r3, #1 - 8003f0a: d110 bne.n 8003f2e + 80080b8: 4b27 ldr r3, [pc, #156] @ (8008158 ) + 80080ba: 681b ldr r3, [r3, #0] + 80080bc: 2b01 cmp r3, #1 + 80080be: d110 bne.n 80080e2 { /* This is the first task to be created so do the preliminary initialisation required. We will not recover if this call fails, but we will report the failure. */ prvInitialiseTaskLists(); - 8003f0c: f000 fc2e bl 800476c - 8003f10: e00d b.n 8003f2e + 80080c0: f000 fbf8 bl 80088b4 + 80080c4: e00d b.n 80080e2 else { /* If the scheduler is not already running, make this task the current task if it is the highest priority task to be created so far. */ if( xSchedulerRunning == pdFALSE ) - 8003f12: 4b26 ldr r3, [pc, #152] @ (8003fac ) - 8003f14: 681b ldr r3, [r3, #0] - 8003f16: 2b00 cmp r3, #0 - 8003f18: d109 bne.n 8003f2e + 80080c6: 4b26 ldr r3, [pc, #152] @ (8008160 ) + 80080c8: 681b ldr r3, [r3, #0] + 80080ca: 2b00 cmp r3, #0 + 80080cc: d109 bne.n 80080e2 { if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) - 8003f1a: 4b23 ldr r3, [pc, #140] @ (8003fa8 ) - 8003f1c: 681b ldr r3, [r3, #0] - 8003f1e: 6ada ldr r2, [r3, #44] @ 0x2c - 8003f20: 687b ldr r3, [r7, #4] - 8003f22: 6adb ldr r3, [r3, #44] @ 0x2c - 8003f24: 429a cmp r2, r3 - 8003f26: d802 bhi.n 8003f2e + 80080ce: 4b23 ldr r3, [pc, #140] @ (800815c ) + 80080d0: 681b ldr r3, [r3, #0] + 80080d2: 6ada ldr r2, [r3, #44] @ 0x2c + 80080d4: 687b ldr r3, [r7, #4] + 80080d6: 6adb ldr r3, [r3, #44] @ 0x2c + 80080d8: 429a cmp r2, r3 + 80080da: d802 bhi.n 80080e2 { pxCurrentTCB = pxNewTCB; - 8003f28: 4a1f ldr r2, [pc, #124] @ (8003fa8 ) - 8003f2a: 687b ldr r3, [r7, #4] - 8003f2c: 6013 str r3, [r2, #0] + 80080dc: 4a1f ldr r2, [pc, #124] @ (800815c ) + 80080de: 687b ldr r3, [r7, #4] + 80080e0: 6013 str r3, [r2, #0] { mtCOVERAGE_TEST_MARKER(); } } uxTaskNumber++; - 8003f2e: 4b20 ldr r3, [pc, #128] @ (8003fb0 ) - 8003f30: 681b ldr r3, [r3, #0] - 8003f32: 3301 adds r3, #1 - 8003f34: 4a1e ldr r2, [pc, #120] @ (8003fb0 ) - 8003f36: 6013 str r3, [r2, #0] + 80080e2: 4b20 ldr r3, [pc, #128] @ (8008164 ) + 80080e4: 681b ldr r3, [r3, #0] + 80080e6: 3301 adds r3, #1 + 80080e8: 4a1e ldr r2, [pc, #120] @ (8008164 ) + 80080ea: 6013 str r3, [r2, #0] #if ( configUSE_TRACE_FACILITY == 1 ) { /* Add a counter into the TCB for tracing only. */ pxNewTCB->uxTCBNumber = uxTaskNumber; - 8003f38: 4b1d ldr r3, [pc, #116] @ (8003fb0 ) - 8003f3a: 681a ldr r2, [r3, #0] - 8003f3c: 687b ldr r3, [r7, #4] - 8003f3e: 645a str r2, [r3, #68] @ 0x44 + 80080ec: 4b1d ldr r3, [pc, #116] @ (8008164 ) + 80080ee: 681a ldr r2, [r3, #0] + 80080f0: 687b ldr r3, [r7, #4] + 80080f2: 645a str r2, [r3, #68] @ 0x44 } #endif /* configUSE_TRACE_FACILITY */ traceTASK_CREATE( pxNewTCB ); prvAddTaskToReadyList( pxNewTCB ); - 8003f40: 687b ldr r3, [r7, #4] - 8003f42: 6ada ldr r2, [r3, #44] @ 0x2c - 8003f44: 4b1b ldr r3, [pc, #108] @ (8003fb4 ) - 8003f46: 681b ldr r3, [r3, #0] - 8003f48: 429a cmp r2, r3 - 8003f4a: d903 bls.n 8003f54 - 8003f4c: 687b ldr r3, [r7, #4] - 8003f4e: 6adb ldr r3, [r3, #44] @ 0x2c - 8003f50: 4a18 ldr r2, [pc, #96] @ (8003fb4 ) - 8003f52: 6013 str r3, [r2, #0] - 8003f54: 687b ldr r3, [r7, #4] - 8003f56: 6ada ldr r2, [r3, #44] @ 0x2c - 8003f58: 4613 mov r3, r2 - 8003f5a: 009b lsls r3, r3, #2 - 8003f5c: 4413 add r3, r2 - 8003f5e: 009b lsls r3, r3, #2 - 8003f60: 4a15 ldr r2, [pc, #84] @ (8003fb8 ) - 8003f62: 441a add r2, r3 - 8003f64: 687b ldr r3, [r7, #4] - 8003f66: 3304 adds r3, #4 - 8003f68: 4619 mov r1, r3 - 8003f6a: 4610 mov r0, r2 - 8003f6c: f7ff f8e9 bl 8003142 + 80080f4: 687b ldr r3, [r7, #4] + 80080f6: 6ada ldr r2, [r3, #44] @ 0x2c + 80080f8: 4b1b ldr r3, [pc, #108] @ (8008168 ) + 80080fa: 681b ldr r3, [r3, #0] + 80080fc: 429a cmp r2, r3 + 80080fe: d903 bls.n 8008108 + 8008100: 687b ldr r3, [r7, #4] + 8008102: 6adb ldr r3, [r3, #44] @ 0x2c + 8008104: 4a18 ldr r2, [pc, #96] @ (8008168 ) + 8008106: 6013 str r3, [r2, #0] + 8008108: 687b ldr r3, [r7, #4] + 800810a: 6ada ldr r2, [r3, #44] @ 0x2c + 800810c: 4613 mov r3, r2 + 800810e: 009b lsls r3, r3, #2 + 8008110: 4413 add r3, r2 + 8008112: 009b lsls r3, r3, #2 + 8008114: 4a15 ldr r2, [pc, #84] @ (800816c ) + 8008116: 441a add r2, r3 + 8008118: 687b ldr r3, [r7, #4] + 800811a: 3304 adds r3, #4 + 800811c: 4619 mov r1, r3 + 800811e: 4610 mov r0, r2 + 8008120: f7fe fdb7 bl 8006c92 portSETUP_TCB( pxNewTCB ); } taskEXIT_CRITICAL(); - 8003f70: f001 fa5c bl 800542c + 8008124: f001 fbea bl 80098fc if( xSchedulerRunning != pdFALSE ) - 8003f74: 4b0d ldr r3, [pc, #52] @ (8003fac ) - 8003f76: 681b ldr r3, [r3, #0] - 8003f78: 2b00 cmp r3, #0 - 8003f7a: d00e beq.n 8003f9a + 8008128: 4b0d ldr r3, [pc, #52] @ (8008160 ) + 800812a: 681b ldr r3, [r3, #0] + 800812c: 2b00 cmp r3, #0 + 800812e: d00e beq.n 800814e { /* If the created task is of a higher priority than the current task then it should run now. */ if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority ) - 8003f7c: 4b0a ldr r3, [pc, #40] @ (8003fa8 ) - 8003f7e: 681b ldr r3, [r3, #0] - 8003f80: 6ada ldr r2, [r3, #44] @ 0x2c - 8003f82: 687b ldr r3, [r7, #4] - 8003f84: 6adb ldr r3, [r3, #44] @ 0x2c - 8003f86: 429a cmp r2, r3 - 8003f88: d207 bcs.n 8003f9a + 8008130: 4b0a ldr r3, [pc, #40] @ (800815c ) + 8008132: 681b ldr r3, [r3, #0] + 8008134: 6ada ldr r2, [r3, #44] @ 0x2c + 8008136: 687b ldr r3, [r7, #4] + 8008138: 6adb ldr r3, [r3, #44] @ 0x2c + 800813a: 429a cmp r2, r3 + 800813c: d207 bcs.n 800814e { taskYIELD_IF_USING_PREEMPTION(); - 8003f8a: 4b0c ldr r3, [pc, #48] @ (8003fbc ) - 8003f8c: f04f 5280 mov.w r2, #268435456 @ 0x10000000 - 8003f90: 601a str r2, [r3, #0] - 8003f92: f3bf 8f4f dsb sy - 8003f96: f3bf 8f6f isb sy + 800813e: 4b0c ldr r3, [pc, #48] @ (8008170 ) + 8008140: f04f 5280 mov.w r2, #268435456 @ 0x10000000 + 8008144: 601a str r2, [r3, #0] + 8008146: f3bf 8f4f dsb sy + 800814a: f3bf 8f6f isb sy } else { mtCOVERAGE_TEST_MARKER(); } } - 8003f9a: bf00 nop - 8003f9c: 3708 adds r7, #8 - 8003f9e: 46bd mov sp, r7 - 8003fa0: bd80 pop {r7, pc} - 8003fa2: bf00 nop - 8003fa4: 20000e0c .word 0x20000e0c - 8003fa8: 20000938 .word 0x20000938 - 8003fac: 20000e18 .word 0x20000e18 - 8003fb0: 20000e28 .word 0x20000e28 - 8003fb4: 20000e14 .word 0x20000e14 - 8003fb8: 2000093c .word 0x2000093c - 8003fbc: e000ed04 .word 0xe000ed04 + 800814e: bf00 nop + 8008150: 3708 adds r7, #8 + 8008152: 46bd mov sp, r7 + 8008154: bd80 pop {r7, pc} + 8008156: bf00 nop + 8008158: 20000f94 .word 0x20000f94 + 800815c: 20000ac0 .word 0x20000ac0 + 8008160: 20000fa0 .word 0x20000fa0 + 8008164: 20000fb0 .word 0x20000fb0 + 8008168: 20000f9c .word 0x20000f9c + 800816c: 20000ac4 .word 0x20000ac4 + 8008170: e000ed04 .word 0xe000ed04 -08003fc0 : -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelay == 1 ) - - void vTaskDelay( const TickType_t xTicksToDelay ) - { - 8003fc0: b580 push {r7, lr} - 8003fc2: b084 sub sp, #16 - 8003fc4: af00 add r7, sp, #0 - 8003fc6: 6078 str r0, [r7, #4] - BaseType_t xAlreadyYielded = pdFALSE; - 8003fc8: 2300 movs r3, #0 - 8003fca: 60fb str r3, [r7, #12] - - /* A delay time of zero just forces a reschedule. */ - if( xTicksToDelay > ( TickType_t ) 0U ) - 8003fcc: 687b ldr r3, [r7, #4] - 8003fce: 2b00 cmp r3, #0 - 8003fd0: d018 beq.n 8004004 - { - configASSERT( uxSchedulerSuspended == 0 ); - 8003fd2: 4b14 ldr r3, [pc, #80] @ (8004024 ) - 8003fd4: 681b ldr r3, [r3, #0] - 8003fd6: 2b00 cmp r3, #0 - 8003fd8: d00b beq.n 8003ff2 - __asm volatile - 8003fda: f04f 0350 mov.w r3, #80 @ 0x50 - 8003fde: f383 8811 msr BASEPRI, r3 - 8003fe2: f3bf 8f6f isb sy - 8003fe6: f3bf 8f4f dsb sy - 8003fea: 60bb str r3, [r7, #8] -} - 8003fec: bf00 nop - 8003fee: bf00 nop - 8003ff0: e7fd b.n 8003fee - vTaskSuspendAll(); - 8003ff2: f000 f88b bl 800410c - list or removed from the blocked list until the scheduler - is resumed. - - This task cannot be in an event list as it is the currently - executing task. */ - prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE ); - 8003ff6: 2100 movs r1, #0 - 8003ff8: 6878 ldr r0, [r7, #4] - 8003ffa: f000 fd09 bl 8004a10 - } - xAlreadyYielded = xTaskResumeAll(); - 8003ffe: f000 f893 bl 8004128 - 8004002: 60f8 str r0, [r7, #12] - mtCOVERAGE_TEST_MARKER(); - } - - /* Force a reschedule if xTaskResumeAll has not already done so, we may - have put ourselves to sleep. */ - if( xAlreadyYielded == pdFALSE ) - 8004004: 68fb ldr r3, [r7, #12] - 8004006: 2b00 cmp r3, #0 - 8004008: d107 bne.n 800401a - { - portYIELD_WITHIN_API(); - 800400a: 4b07 ldr r3, [pc, #28] @ (8004028 ) - 800400c: f04f 5280 mov.w r2, #268435456 @ 0x10000000 - 8004010: 601a str r2, [r3, #0] - 8004012: f3bf 8f4f dsb sy - 8004016: f3bf 8f6f isb sy - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - } - 800401a: bf00 nop - 800401c: 3710 adds r7, #16 - 800401e: 46bd mov sp, r7 - 8004020: bd80 pop {r7, pc} - 8004022: bf00 nop - 8004024: 20000e34 .word 0x20000e34 - 8004028: e000ed04 .word 0xe000ed04 - -0800402c : +08008174 : #endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */ /*-----------------------------------------------------------*/ void vTaskStartScheduler( void ) { - 800402c: b580 push {r7, lr} - 800402e: b08a sub sp, #40 @ 0x28 - 8004030: af04 add r7, sp, #16 + 8008174: b580 push {r7, lr} + 8008176: b08a sub sp, #40 @ 0x28 + 8008178: af04 add r7, sp, #16 BaseType_t xReturn; /* Add the idle task at the lowest priority. */ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t *pxIdleTaskTCBBuffer = NULL; - 8004032: 2300 movs r3, #0 - 8004034: 60bb str r3, [r7, #8] + 800817a: 2300 movs r3, #0 + 800817c: 60bb str r3, [r7, #8] StackType_t *pxIdleTaskStackBuffer = NULL; - 8004036: 2300 movs r3, #0 - 8004038: 607b str r3, [r7, #4] + 800817e: 2300 movs r3, #0 + 8008180: 607b str r3, [r7, #4] uint32_t ulIdleTaskStackSize; /* The Idle task is created using user provided RAM - obtain the address of the RAM then create the idle task. */ vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize ); - 800403a: 463a mov r2, r7 - 800403c: 1d39 adds r1, r7, #4 - 800403e: f107 0308 add.w r3, r7, #8 - 8004042: 4618 mov r0, r3 - 8004044: f7ff f81c bl 8003080 + 8008182: 463a mov r2, r7 + 8008184: 1d39 adds r1, r7, #4 + 8008186: f107 0308 add.w r3, r7, #8 + 800818a: 4618 mov r0, r3 + 800818c: f7fe fd20 bl 8006bd0 xIdleTaskHandle = xTaskCreateStatic( prvIdleTask, - 8004048: 6839 ldr r1, [r7, #0] - 800404a: 687b ldr r3, [r7, #4] - 800404c: 68ba ldr r2, [r7, #8] - 800404e: 9202 str r2, [sp, #8] - 8004050: 9301 str r3, [sp, #4] - 8004052: 2300 movs r3, #0 - 8004054: 9300 str r3, [sp, #0] - 8004056: 2300 movs r3, #0 - 8004058: 460a mov r2, r1 - 800405a: 4924 ldr r1, [pc, #144] @ (80040ec ) - 800405c: 4824 ldr r0, [pc, #144] @ (80040f0 ) - 800405e: f7ff fdf1 bl 8003c44 - 8004062: 4603 mov r3, r0 - 8004064: 4a23 ldr r2, [pc, #140] @ (80040f4 ) - 8004066: 6013 str r3, [r2, #0] + 8008190: 6839 ldr r1, [r7, #0] + 8008192: 687b ldr r3, [r7, #4] + 8008194: 68ba ldr r2, [r7, #8] + 8008196: 9202 str r2, [sp, #8] + 8008198: 9301 str r3, [sp, #4] + 800819a: 2300 movs r3, #0 + 800819c: 9300 str r3, [sp, #0] + 800819e: 2300 movs r3, #0 + 80081a0: 460a mov r2, r1 + 80081a2: 4924 ldr r1, [pc, #144] @ (8008234 ) + 80081a4: 4824 ldr r0, [pc, #144] @ (8008238 ) + 80081a6: f7ff fe27 bl 8007df8 + 80081aa: 4603 mov r3, r0 + 80081ac: 4a23 ldr r2, [pc, #140] @ (800823c ) + 80081ae: 6013 str r3, [r2, #0] ( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */ portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ pxIdleTaskStackBuffer, pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ if( xIdleTaskHandle != NULL ) - 8004068: 4b22 ldr r3, [pc, #136] @ (80040f4 ) - 800406a: 681b ldr r3, [r3, #0] - 800406c: 2b00 cmp r3, #0 - 800406e: d002 beq.n 8004076 + 80081b0: 4b22 ldr r3, [pc, #136] @ (800823c ) + 80081b2: 681b ldr r3, [r3, #0] + 80081b4: 2b00 cmp r3, #0 + 80081b6: d002 beq.n 80081be { xReturn = pdPASS; - 8004070: 2301 movs r3, #1 - 8004072: 617b str r3, [r7, #20] - 8004074: e001 b.n 800407a + 80081b8: 2301 movs r3, #1 + 80081ba: 617b str r3, [r7, #20] + 80081bc: e001 b.n 80081c2 } else { xReturn = pdFAIL; - 8004076: 2300 movs r3, #0 - 8004078: 617b str r3, [r7, #20] + 80081be: 2300 movs r3, #0 + 80081c0: 617b str r3, [r7, #20] } #endif /* configSUPPORT_STATIC_ALLOCATION */ #if ( configUSE_TIMERS == 1 ) { if( xReturn == pdPASS ) - 800407a: 697b ldr r3, [r7, #20] - 800407c: 2b01 cmp r3, #1 - 800407e: d102 bne.n 8004086 + 80081c2: 697b ldr r3, [r7, #20] + 80081c4: 2b01 cmp r3, #1 + 80081c6: d102 bne.n 80081ce { xReturn = xTimerCreateTimerTask(); - 8004080: f000 fd1a bl 8004ab8 - 8004084: 6178 str r0, [r7, #20] + 80081c8: f000 fe1a bl 8008e00 + 80081cc: 6178 str r0, [r7, #20] mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_TIMERS */ if( xReturn == pdPASS ) - 8004086: 697b ldr r3, [r7, #20] - 8004088: 2b01 cmp r3, #1 - 800408a: d11b bne.n 80040c4 + 80081ce: 697b ldr r3, [r7, #20] + 80081d0: 2b01 cmp r3, #1 + 80081d2: d11b bne.n 800820c __asm volatile - 800408c: f04f 0350 mov.w r3, #80 @ 0x50 - 8004090: f383 8811 msr BASEPRI, r3 - 8004094: f3bf 8f6f isb sy - 8004098: f3bf 8f4f dsb sy - 800409c: 613b str r3, [r7, #16] + 80081d4: f04f 0350 mov.w r3, #80 @ 0x50 + 80081d8: f383 8811 msr BASEPRI, r3 + 80081dc: f3bf 8f6f isb sy + 80081e0: f3bf 8f4f dsb sy + 80081e4: 613b str r3, [r7, #16] } - 800409e: bf00 nop + 80081e6: bf00 nop { /* Switch Newlib's _impure_ptr variable to point to the _reent structure specific to the task that will run first. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); - 80040a0: 4b15 ldr r3, [pc, #84] @ (80040f8 ) - 80040a2: 681b ldr r3, [r3, #0] - 80040a4: 3354 adds r3, #84 @ 0x54 - 80040a6: 4a15 ldr r2, [pc, #84] @ (80040fc ) - 80040a8: 6013 str r3, [r2, #0] + 80081e8: 4b15 ldr r3, [pc, #84] @ (8008240 ) + 80081ea: 681b ldr r3, [r3, #0] + 80081ec: 3354 adds r3, #84 @ 0x54 + 80081ee: 4a15 ldr r2, [pc, #84] @ (8008244 ) + 80081f0: 6013 str r3, [r2, #0] } #endif /* configUSE_NEWLIB_REENTRANT */ xNextTaskUnblockTime = portMAX_DELAY; - 80040aa: 4b15 ldr r3, [pc, #84] @ (8004100 ) - 80040ac: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff - 80040b0: 601a str r2, [r3, #0] + 80081f2: 4b15 ldr r3, [pc, #84] @ (8008248 ) + 80081f4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 80081f8: 601a str r2, [r3, #0] xSchedulerRunning = pdTRUE; - 80040b2: 4b14 ldr r3, [pc, #80] @ (8004104 ) - 80040b4: 2201 movs r2, #1 - 80040b6: 601a str r2, [r3, #0] + 80081fa: 4b14 ldr r3, [pc, #80] @ (800824c ) + 80081fc: 2201 movs r2, #1 + 80081fe: 601a str r2, [r3, #0] xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; - 80040b8: 4b13 ldr r3, [pc, #76] @ (8004108 ) - 80040ba: 2200 movs r2, #0 - 80040bc: 601a str r2, [r3, #0] + 8008200: 4b13 ldr r3, [pc, #76] @ (8008250 ) + 8008202: 2200 movs r2, #0 + 8008204: 601a str r2, [r3, #0] traceTASK_SWITCHED_IN(); /* Setting up the timer tick is hardware specific and thus in the portable interface. */ if( xPortStartScheduler() != pdFALSE ) - 80040be: f001 f8df bl 8005280 + 8008206: f001 faa3 bl 8009750 } /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0, meaning xIdleTaskHandle is not used anywhere else. */ ( void ) xIdleTaskHandle; } - 80040c2: e00f b.n 80040e4 + 800820a: e00f b.n 800822c configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ); - 80040c4: 697b ldr r3, [r7, #20] - 80040c6: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff - 80040ca: d10b bne.n 80040e4 + 800820c: 697b ldr r3, [r7, #20] + 800820e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8008212: d10b bne.n 800822c __asm volatile - 80040cc: f04f 0350 mov.w r3, #80 @ 0x50 - 80040d0: f383 8811 msr BASEPRI, r3 - 80040d4: f3bf 8f6f isb sy - 80040d8: f3bf 8f4f dsb sy - 80040dc: 60fb str r3, [r7, #12] + 8008214: f04f 0350 mov.w r3, #80 @ 0x50 + 8008218: f383 8811 msr BASEPRI, r3 + 800821c: f3bf 8f6f isb sy + 8008220: f3bf 8f4f dsb sy + 8008224: 60fb str r3, [r7, #12] } - 80040de: bf00 nop - 80040e0: bf00 nop - 80040e2: e7fd b.n 80040e0 + 8008226: bf00 nop + 8008228: bf00 nop + 800822a: e7fd b.n 8008228 } - 80040e4: bf00 nop - 80040e6: 3718 adds r7, #24 - 80040e8: 46bd mov sp, r7 - 80040ea: bd80 pop {r7, pc} - 80040ec: 08005d08 .word 0x08005d08 - 80040f0: 0800473d .word 0x0800473d - 80040f4: 20000e30 .word 0x20000e30 - 80040f8: 20000938 .word 0x20000938 - 80040fc: 20000010 .word 0x20000010 - 8004100: 20000e2c .word 0x20000e2c - 8004104: 20000e18 .word 0x20000e18 - 8004108: 20000e10 .word 0x20000e10 + 800822c: bf00 nop + 800822e: 3718 adds r7, #24 + 8008230: 46bd mov sp, r7 + 8008232: bd80 pop {r7, pc} + 8008234: 0800a288 .word 0x0800a288 + 8008238: 08008885 .word 0x08008885 + 800823c: 20000fb8 .word 0x20000fb8 + 8008240: 20000ac0 .word 0x20000ac0 + 8008244: 20000028 .word 0x20000028 + 8008248: 20000fb4 .word 0x20000fb4 + 800824c: 20000fa0 .word 0x20000fa0 + 8008250: 20000f98 .word 0x20000f98 -0800410c : +08008254 : vPortEndScheduler(); } /*----------------------------------------------------------*/ void vTaskSuspendAll( void ) { - 800410c: b480 push {r7} - 800410e: af00 add r7, sp, #0 + 8008254: b480 push {r7} + 8008256: af00 add r7, sp, #0 do not otherwise exhibit real time behaviour. */ portSOFTWARE_BARRIER(); /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment is used to allow calls to vTaskSuspendAll() to nest. */ ++uxSchedulerSuspended; - 8004110: 4b04 ldr r3, [pc, #16] @ (8004124 ) - 8004112: 681b ldr r3, [r3, #0] - 8004114: 3301 adds r3, #1 - 8004116: 4a03 ldr r2, [pc, #12] @ (8004124 ) - 8004118: 6013 str r3, [r2, #0] + 8008258: 4b04 ldr r3, [pc, #16] @ (800826c ) + 800825a: 681b ldr r3, [r3, #0] + 800825c: 3301 adds r3, #1 + 800825e: 4a03 ldr r2, [pc, #12] @ (800826c ) + 8008260: 6013 str r3, [r2, #0] /* Enforces ordering for ports and optimised compilers that may otherwise place the above increment elsewhere. */ portMEMORY_BARRIER(); } - 800411a: bf00 nop - 800411c: 46bd mov sp, r7 - 800411e: f85d 7b04 ldr.w r7, [sp], #4 - 8004122: 4770 bx lr - 8004124: 20000e34 .word 0x20000e34 + 8008262: bf00 nop + 8008264: 46bd mov sp, r7 + 8008266: f85d 7b04 ldr.w r7, [sp], #4 + 800826a: 4770 bx lr + 800826c: 20000fbc .word 0x20000fbc -08004128 : +08008270 : #endif /* configUSE_TICKLESS_IDLE */ /*----------------------------------------------------------*/ BaseType_t xTaskResumeAll( void ) { - 8004128: b580 push {r7, lr} - 800412a: b084 sub sp, #16 - 800412c: af00 add r7, sp, #0 + 8008270: b580 push {r7, lr} + 8008272: b084 sub sp, #16 + 8008274: af00 add r7, sp, #0 TCB_t *pxTCB = NULL; - 800412e: 2300 movs r3, #0 - 8004130: 60fb str r3, [r7, #12] + 8008276: 2300 movs r3, #0 + 8008278: 60fb str r3, [r7, #12] BaseType_t xAlreadyYielded = pdFALSE; - 8004132: 2300 movs r3, #0 - 8004134: 60bb str r3, [r7, #8] + 800827a: 2300 movs r3, #0 + 800827c: 60bb str r3, [r7, #8] /* If uxSchedulerSuspended is zero then this function does not match a previous call to vTaskSuspendAll(). */ configASSERT( uxSchedulerSuspended ); - 8004136: 4b42 ldr r3, [pc, #264] @ (8004240 ) - 8004138: 681b ldr r3, [r3, #0] - 800413a: 2b00 cmp r3, #0 - 800413c: d10b bne.n 8004156 + 800827e: 4b42 ldr r3, [pc, #264] @ (8008388 ) + 8008280: 681b ldr r3, [r3, #0] + 8008282: 2b00 cmp r3, #0 + 8008284: d10b bne.n 800829e __asm volatile - 800413e: f04f 0350 mov.w r3, #80 @ 0x50 - 8004142: f383 8811 msr BASEPRI, r3 - 8004146: f3bf 8f6f isb sy - 800414a: f3bf 8f4f dsb sy - 800414e: 603b str r3, [r7, #0] + 8008286: f04f 0350 mov.w r3, #80 @ 0x50 + 800828a: f383 8811 msr BASEPRI, r3 + 800828e: f3bf 8f6f isb sy + 8008292: f3bf 8f4f dsb sy + 8008296: 603b str r3, [r7, #0] } - 8004150: bf00 nop - 8004152: bf00 nop - 8004154: e7fd b.n 8004152 + 8008298: bf00 nop + 800829a: bf00 nop + 800829c: e7fd b.n 800829a /* It is possible that an ISR caused a task to be removed from an event list while the scheduler was suspended. If this was the case then the removed task will have been added to the xPendingReadyList. Once the scheduler has been resumed it is safe to move all the pending ready tasks from this list into their appropriate ready list. */ taskENTER_CRITICAL(); - 8004156: f001 f937 bl 80053c8 + 800829e: f001 fafb bl 8009898 { --uxSchedulerSuspended; - 800415a: 4b39 ldr r3, [pc, #228] @ (8004240 ) - 800415c: 681b ldr r3, [r3, #0] - 800415e: 3b01 subs r3, #1 - 8004160: 4a37 ldr r2, [pc, #220] @ (8004240 ) - 8004162: 6013 str r3, [r2, #0] + 80082a2: 4b39 ldr r3, [pc, #228] @ (8008388 ) + 80082a4: 681b ldr r3, [r3, #0] + 80082a6: 3b01 subs r3, #1 + 80082a8: 4a37 ldr r2, [pc, #220] @ (8008388 ) + 80082aa: 6013 str r3, [r2, #0] if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) - 8004164: 4b36 ldr r3, [pc, #216] @ (8004240 ) - 8004166: 681b ldr r3, [r3, #0] - 8004168: 2b00 cmp r3, #0 - 800416a: d162 bne.n 8004232 + 80082ac: 4b36 ldr r3, [pc, #216] @ (8008388 ) + 80082ae: 681b ldr r3, [r3, #0] + 80082b0: 2b00 cmp r3, #0 + 80082b2: d162 bne.n 800837a { if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) - 800416c: 4b35 ldr r3, [pc, #212] @ (8004244 ) - 800416e: 681b ldr r3, [r3, #0] - 8004170: 2b00 cmp r3, #0 - 8004172: d05e beq.n 8004232 + 80082b4: 4b35 ldr r3, [pc, #212] @ (800838c ) + 80082b6: 681b ldr r3, [r3, #0] + 80082b8: 2b00 cmp r3, #0 + 80082ba: d05e beq.n 800837a { /* Move any readied tasks from the pending list into the appropriate ready list. */ while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) - 8004174: e02f b.n 80041d6 + 80082bc: e02f b.n 800831e { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ - 8004176: 4b34 ldr r3, [pc, #208] @ (8004248 ) - 8004178: 68db ldr r3, [r3, #12] - 800417a: 68db ldr r3, [r3, #12] - 800417c: 60fb str r3, [r7, #12] + 80082be: 4b34 ldr r3, [pc, #208] @ (8008390 ) + 80082c0: 68db ldr r3, [r3, #12] + 80082c2: 68db ldr r3, [r3, #12] + 80082c4: 60fb str r3, [r7, #12] ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); - 800417e: 68fb ldr r3, [r7, #12] - 8004180: 3318 adds r3, #24 - 8004182: 4618 mov r0, r3 - 8004184: f7ff f83a bl 80031fc + 80082c6: 68fb ldr r3, [r7, #12] + 80082c8: 3318 adds r3, #24 + 80082ca: 4618 mov r0, r3 + 80082cc: f7fe fd3e bl 8006d4c ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); - 8004188: 68fb ldr r3, [r7, #12] - 800418a: 3304 adds r3, #4 - 800418c: 4618 mov r0, r3 - 800418e: f7ff f835 bl 80031fc + 80082d0: 68fb ldr r3, [r7, #12] + 80082d2: 3304 adds r3, #4 + 80082d4: 4618 mov r0, r3 + 80082d6: f7fe fd39 bl 8006d4c prvAddTaskToReadyList( pxTCB ); - 8004192: 68fb ldr r3, [r7, #12] - 8004194: 6ada ldr r2, [r3, #44] @ 0x2c - 8004196: 4b2d ldr r3, [pc, #180] @ (800424c ) - 8004198: 681b ldr r3, [r3, #0] - 800419a: 429a cmp r2, r3 - 800419c: d903 bls.n 80041a6 - 800419e: 68fb ldr r3, [r7, #12] - 80041a0: 6adb ldr r3, [r3, #44] @ 0x2c - 80041a2: 4a2a ldr r2, [pc, #168] @ (800424c ) - 80041a4: 6013 str r3, [r2, #0] - 80041a6: 68fb ldr r3, [r7, #12] - 80041a8: 6ada ldr r2, [r3, #44] @ 0x2c - 80041aa: 4613 mov r3, r2 - 80041ac: 009b lsls r3, r3, #2 - 80041ae: 4413 add r3, r2 - 80041b0: 009b lsls r3, r3, #2 - 80041b2: 4a27 ldr r2, [pc, #156] @ (8004250 ) - 80041b4: 441a add r2, r3 - 80041b6: 68fb ldr r3, [r7, #12] - 80041b8: 3304 adds r3, #4 - 80041ba: 4619 mov r1, r3 - 80041bc: 4610 mov r0, r2 - 80041be: f7fe ffc0 bl 8003142 + 80082da: 68fb ldr r3, [r7, #12] + 80082dc: 6ada ldr r2, [r3, #44] @ 0x2c + 80082de: 4b2d ldr r3, [pc, #180] @ (8008394 ) + 80082e0: 681b ldr r3, [r3, #0] + 80082e2: 429a cmp r2, r3 + 80082e4: d903 bls.n 80082ee + 80082e6: 68fb ldr r3, [r7, #12] + 80082e8: 6adb ldr r3, [r3, #44] @ 0x2c + 80082ea: 4a2a ldr r2, [pc, #168] @ (8008394 ) + 80082ec: 6013 str r3, [r2, #0] + 80082ee: 68fb ldr r3, [r7, #12] + 80082f0: 6ada ldr r2, [r3, #44] @ 0x2c + 80082f2: 4613 mov r3, r2 + 80082f4: 009b lsls r3, r3, #2 + 80082f6: 4413 add r3, r2 + 80082f8: 009b lsls r3, r3, #2 + 80082fa: 4a27 ldr r2, [pc, #156] @ (8008398 ) + 80082fc: 441a add r2, r3 + 80082fe: 68fb ldr r3, [r7, #12] + 8008300: 3304 adds r3, #4 + 8008302: 4619 mov r1, r3 + 8008304: 4610 mov r0, r2 + 8008306: f7fe fcc4 bl 8006c92 /* If the moved task has a priority higher than the current task then a yield must be performed. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) - 80041c2: 68fb ldr r3, [r7, #12] - 80041c4: 6ada ldr r2, [r3, #44] @ 0x2c - 80041c6: 4b23 ldr r3, [pc, #140] @ (8004254 ) - 80041c8: 681b ldr r3, [r3, #0] - 80041ca: 6adb ldr r3, [r3, #44] @ 0x2c - 80041cc: 429a cmp r2, r3 - 80041ce: d302 bcc.n 80041d6 + 800830a: 68fb ldr r3, [r7, #12] + 800830c: 6ada ldr r2, [r3, #44] @ 0x2c + 800830e: 4b23 ldr r3, [pc, #140] @ (800839c ) + 8008310: 681b ldr r3, [r3, #0] + 8008312: 6adb ldr r3, [r3, #44] @ 0x2c + 8008314: 429a cmp r2, r3 + 8008316: d302 bcc.n 800831e { xYieldPending = pdTRUE; - 80041d0: 4b21 ldr r3, [pc, #132] @ (8004258 ) - 80041d2: 2201 movs r2, #1 - 80041d4: 601a str r2, [r3, #0] + 8008318: 4b21 ldr r3, [pc, #132] @ (80083a0 ) + 800831a: 2201 movs r2, #1 + 800831c: 601a str r2, [r3, #0] while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) - 80041d6: 4b1c ldr r3, [pc, #112] @ (8004248 ) - 80041d8: 681b ldr r3, [r3, #0] - 80041da: 2b00 cmp r3, #0 - 80041dc: d1cb bne.n 8004176 + 800831e: 4b1c ldr r3, [pc, #112] @ (8008390 ) + 8008320: 681b ldr r3, [r3, #0] + 8008322: 2b00 cmp r3, #0 + 8008324: d1cb bne.n 80082be { mtCOVERAGE_TEST_MARKER(); } } if( pxTCB != NULL ) - 80041de: 68fb ldr r3, [r7, #12] - 80041e0: 2b00 cmp r3, #0 - 80041e2: d001 beq.n 80041e8 + 8008326: 68fb ldr r3, [r7, #12] + 8008328: 2b00 cmp r3, #0 + 800832a: d001 beq.n 8008330 which may have prevented the next unblock time from being re-calculated, in which case re-calculate it now. Mainly important for low power tickless implementations, where this can prevent an unnecessary exit from low power state. */ prvResetNextTaskUnblockTime(); - 80041e4: f000 fb66 bl 80048b4 + 800832c: f000 fb66 bl 80089fc /* If any ticks occurred while the scheduler was suspended then they should be processed now. This ensures the tick count does not slip, and that any delayed tasks are resumed at the correct time. */ { TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */ - 80041e8: 4b1c ldr r3, [pc, #112] @ (800425c ) - 80041ea: 681b ldr r3, [r3, #0] - 80041ec: 607b str r3, [r7, #4] + 8008330: 4b1c ldr r3, [pc, #112] @ (80083a4 ) + 8008332: 681b ldr r3, [r3, #0] + 8008334: 607b str r3, [r7, #4] if( xPendedCounts > ( TickType_t ) 0U ) - 80041ee: 687b ldr r3, [r7, #4] - 80041f0: 2b00 cmp r3, #0 - 80041f2: d010 beq.n 8004216 + 8008336: 687b ldr r3, [r7, #4] + 8008338: 2b00 cmp r3, #0 + 800833a: d010 beq.n 800835e { do { if( xTaskIncrementTick() != pdFALSE ) - 80041f4: f000 f846 bl 8004284 - 80041f8: 4603 mov r3, r0 - 80041fa: 2b00 cmp r3, #0 - 80041fc: d002 beq.n 8004204 + 800833c: f000 f846 bl 80083cc + 8008340: 4603 mov r3, r0 + 8008342: 2b00 cmp r3, #0 + 8008344: d002 beq.n 800834c { xYieldPending = pdTRUE; - 80041fe: 4b16 ldr r3, [pc, #88] @ (8004258 ) - 8004200: 2201 movs r2, #1 - 8004202: 601a str r2, [r3, #0] + 8008346: 4b16 ldr r3, [pc, #88] @ (80083a0 ) + 8008348: 2201 movs r2, #1 + 800834a: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } --xPendedCounts; - 8004204: 687b ldr r3, [r7, #4] - 8004206: 3b01 subs r3, #1 - 8004208: 607b str r3, [r7, #4] + 800834c: 687b ldr r3, [r7, #4] + 800834e: 3b01 subs r3, #1 + 8008350: 607b str r3, [r7, #4] } while( xPendedCounts > ( TickType_t ) 0U ); - 800420a: 687b ldr r3, [r7, #4] - 800420c: 2b00 cmp r3, #0 - 800420e: d1f1 bne.n 80041f4 + 8008352: 687b ldr r3, [r7, #4] + 8008354: 2b00 cmp r3, #0 + 8008356: d1f1 bne.n 800833c xPendedTicks = 0; - 8004210: 4b12 ldr r3, [pc, #72] @ (800425c ) - 8004212: 2200 movs r2, #0 - 8004214: 601a str r2, [r3, #0] + 8008358: 4b12 ldr r3, [pc, #72] @ (80083a4 ) + 800835a: 2200 movs r2, #0 + 800835c: 601a str r2, [r3, #0] { mtCOVERAGE_TEST_MARKER(); } } if( xYieldPending != pdFALSE ) - 8004216: 4b10 ldr r3, [pc, #64] @ (8004258 ) - 8004218: 681b ldr r3, [r3, #0] - 800421a: 2b00 cmp r3, #0 - 800421c: d009 beq.n 8004232 + 800835e: 4b10 ldr r3, [pc, #64] @ (80083a0 ) + 8008360: 681b ldr r3, [r3, #0] + 8008362: 2b00 cmp r3, #0 + 8008364: d009 beq.n 800837a { #if( configUSE_PREEMPTION != 0 ) { xAlreadyYielded = pdTRUE; - 800421e: 2301 movs r3, #1 - 8004220: 60bb str r3, [r7, #8] + 8008366: 2301 movs r3, #1 + 8008368: 60bb str r3, [r7, #8] } #endif taskYIELD_IF_USING_PREEMPTION(); - 8004222: 4b0f ldr r3, [pc, #60] @ (8004260 ) - 8004224: f04f 5280 mov.w r2, #268435456 @ 0x10000000 - 8004228: 601a str r2, [r3, #0] - 800422a: f3bf 8f4f dsb sy - 800422e: f3bf 8f6f isb sy + 800836a: 4b0f ldr r3, [pc, #60] @ (80083a8 ) + 800836c: f04f 5280 mov.w r2, #268435456 @ 0x10000000 + 8008370: 601a str r2, [r3, #0] + 8008372: f3bf 8f4f dsb sy + 8008376: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); - 8004232: f001 f8fb bl 800542c + 800837a: f001 fabf bl 80098fc return xAlreadyYielded; - 8004236: 68bb ldr r3, [r7, #8] + 800837e: 68bb ldr r3, [r7, #8] } - 8004238: 4618 mov r0, r3 - 800423a: 3710 adds r7, #16 - 800423c: 46bd mov sp, r7 - 800423e: bd80 pop {r7, pc} - 8004240: 20000e34 .word 0x20000e34 - 8004244: 20000e0c .word 0x20000e0c - 8004248: 20000dcc .word 0x20000dcc - 800424c: 20000e14 .word 0x20000e14 - 8004250: 2000093c .word 0x2000093c - 8004254: 20000938 .word 0x20000938 - 8004258: 20000e20 .word 0x20000e20 - 800425c: 20000e1c .word 0x20000e1c - 8004260: e000ed04 .word 0xe000ed04 + 8008380: 4618 mov r0, r3 + 8008382: 3710 adds r7, #16 + 8008384: 46bd mov sp, r7 + 8008386: bd80 pop {r7, pc} + 8008388: 20000fbc .word 0x20000fbc + 800838c: 20000f94 .word 0x20000f94 + 8008390: 20000f54 .word 0x20000f54 + 8008394: 20000f9c .word 0x20000f9c + 8008398: 20000ac4 .word 0x20000ac4 + 800839c: 20000ac0 .word 0x20000ac0 + 80083a0: 20000fa8 .word 0x20000fa8 + 80083a4: 20000fa4 .word 0x20000fa4 + 80083a8: e000ed04 .word 0xe000ed04 -08004264 : +080083ac : /*-----------------------------------------------------------*/ TickType_t xTaskGetTickCount( void ) { - 8004264: b480 push {r7} - 8004266: b083 sub sp, #12 - 8004268: af00 add r7, sp, #0 + 80083ac: b480 push {r7} + 80083ae: b083 sub sp, #12 + 80083b0: af00 add r7, sp, #0 TickType_t xTicks; /* Critical section required if running on a 16 bit processor. */ portTICK_TYPE_ENTER_CRITICAL(); { xTicks = xTickCount; - 800426a: 4b05 ldr r3, [pc, #20] @ (8004280 ) - 800426c: 681b ldr r3, [r3, #0] - 800426e: 607b str r3, [r7, #4] + 80083b2: 4b05 ldr r3, [pc, #20] @ (80083c8 ) + 80083b4: 681b ldr r3, [r3, #0] + 80083b6: 607b str r3, [r7, #4] } portTICK_TYPE_EXIT_CRITICAL(); return xTicks; - 8004270: 687b ldr r3, [r7, #4] + 80083b8: 687b ldr r3, [r7, #4] } - 8004272: 4618 mov r0, r3 - 8004274: 370c adds r7, #12 - 8004276: 46bd mov sp, r7 - 8004278: f85d 7b04 ldr.w r7, [sp], #4 - 800427c: 4770 bx lr - 800427e: bf00 nop - 8004280: 20000e10 .word 0x20000e10 + 80083ba: 4618 mov r0, r3 + 80083bc: 370c adds r7, #12 + 80083be: 46bd mov sp, r7 + 80083c0: f85d 7b04 ldr.w r7, [sp], #4 + 80083c4: 4770 bx lr + 80083c6: bf00 nop + 80083c8: 20000f98 .word 0x20000f98 -08004284 : +080083cc : #endif /* INCLUDE_xTaskAbortDelay */ /*----------------------------------------------------------*/ BaseType_t xTaskIncrementTick( void ) { - 8004284: b580 push {r7, lr} - 8004286: b086 sub sp, #24 - 8004288: af00 add r7, sp, #0 + 80083cc: b580 push {r7, lr} + 80083ce: b086 sub sp, #24 + 80083d0: af00 add r7, sp, #0 TCB_t * pxTCB; TickType_t xItemValue; BaseType_t xSwitchRequired = pdFALSE; - 800428a: 2300 movs r3, #0 - 800428c: 617b str r3, [r7, #20] + 80083d2: 2300 movs r3, #0 + 80083d4: 617b str r3, [r7, #20] /* Called by the portable layer each time a tick interrupt occurs. Increments the tick then checks to see if the new tick value will cause any tasks to be unblocked. */ traceTASK_INCREMENT_TICK( xTickCount ); if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) - 800428e: 4b4f ldr r3, [pc, #316] @ (80043cc ) - 8004290: 681b ldr r3, [r3, #0] - 8004292: 2b00 cmp r3, #0 - 8004294: f040 8090 bne.w 80043b8 + 80083d6: 4b4f ldr r3, [pc, #316] @ (8008514 ) + 80083d8: 681b ldr r3, [r3, #0] + 80083da: 2b00 cmp r3, #0 + 80083dc: f040 8090 bne.w 8008500 { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; - 8004298: 4b4d ldr r3, [pc, #308] @ (80043d0 ) - 800429a: 681b ldr r3, [r3, #0] - 800429c: 3301 adds r3, #1 - 800429e: 613b str r3, [r7, #16] + 80083e0: 4b4d ldr r3, [pc, #308] @ (8008518 ) + 80083e2: 681b ldr r3, [r3, #0] + 80083e4: 3301 adds r3, #1 + 80083e6: 613b str r3, [r7, #16] /* Increment the RTOS tick, switching the delayed and overflowed delayed lists if it wraps to 0. */ xTickCount = xConstTickCount; - 80042a0: 4a4b ldr r2, [pc, #300] @ (80043d0 ) - 80042a2: 693b ldr r3, [r7, #16] - 80042a4: 6013 str r3, [r2, #0] + 80083e8: 4a4b ldr r2, [pc, #300] @ (8008518 ) + 80083ea: 693b ldr r3, [r7, #16] + 80083ec: 6013 str r3, [r2, #0] if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */ - 80042a6: 693b ldr r3, [r7, #16] - 80042a8: 2b00 cmp r3, #0 - 80042aa: d121 bne.n 80042f0 + 80083ee: 693b ldr r3, [r7, #16] + 80083f0: 2b00 cmp r3, #0 + 80083f2: d121 bne.n 8008438 { taskSWITCH_DELAYED_LISTS(); - 80042ac: 4b49 ldr r3, [pc, #292] @ (80043d4 ) - 80042ae: 681b ldr r3, [r3, #0] - 80042b0: 681b ldr r3, [r3, #0] - 80042b2: 2b00 cmp r3, #0 - 80042b4: d00b beq.n 80042ce + 80083f4: 4b49 ldr r3, [pc, #292] @ (800851c ) + 80083f6: 681b ldr r3, [r3, #0] + 80083f8: 681b ldr r3, [r3, #0] + 80083fa: 2b00 cmp r3, #0 + 80083fc: d00b beq.n 8008416 __asm volatile - 80042b6: f04f 0350 mov.w r3, #80 @ 0x50 - 80042ba: f383 8811 msr BASEPRI, r3 - 80042be: f3bf 8f6f isb sy - 80042c2: f3bf 8f4f dsb sy - 80042c6: 603b str r3, [r7, #0] + 80083fe: f04f 0350 mov.w r3, #80 @ 0x50 + 8008402: f383 8811 msr BASEPRI, r3 + 8008406: f3bf 8f6f isb sy + 800840a: f3bf 8f4f dsb sy + 800840e: 603b str r3, [r7, #0] } - 80042c8: bf00 nop - 80042ca: bf00 nop - 80042cc: e7fd b.n 80042ca - 80042ce: 4b41 ldr r3, [pc, #260] @ (80043d4 ) - 80042d0: 681b ldr r3, [r3, #0] - 80042d2: 60fb str r3, [r7, #12] - 80042d4: 4b40 ldr r3, [pc, #256] @ (80043d8 ) - 80042d6: 681b ldr r3, [r3, #0] - 80042d8: 4a3e ldr r2, [pc, #248] @ (80043d4 ) - 80042da: 6013 str r3, [r2, #0] - 80042dc: 4a3e ldr r2, [pc, #248] @ (80043d8 ) - 80042de: 68fb ldr r3, [r7, #12] - 80042e0: 6013 str r3, [r2, #0] - 80042e2: 4b3e ldr r3, [pc, #248] @ (80043dc ) - 80042e4: 681b ldr r3, [r3, #0] - 80042e6: 3301 adds r3, #1 - 80042e8: 4a3c ldr r2, [pc, #240] @ (80043dc ) - 80042ea: 6013 str r3, [r2, #0] - 80042ec: f000 fae2 bl 80048b4 + 8008410: bf00 nop + 8008412: bf00 nop + 8008414: e7fd b.n 8008412 + 8008416: 4b41 ldr r3, [pc, #260] @ (800851c ) + 8008418: 681b ldr r3, [r3, #0] + 800841a: 60fb str r3, [r7, #12] + 800841c: 4b40 ldr r3, [pc, #256] @ (8008520 ) + 800841e: 681b ldr r3, [r3, #0] + 8008420: 4a3e ldr r2, [pc, #248] @ (800851c ) + 8008422: 6013 str r3, [r2, #0] + 8008424: 4a3e ldr r2, [pc, #248] @ (8008520 ) + 8008426: 68fb ldr r3, [r7, #12] + 8008428: 6013 str r3, [r2, #0] + 800842a: 4b3e ldr r3, [pc, #248] @ (8008524 ) + 800842c: 681b ldr r3, [r3, #0] + 800842e: 3301 adds r3, #1 + 8008430: 4a3c ldr r2, [pc, #240] @ (8008524 ) + 8008432: 6013 str r3, [r2, #0] + 8008434: f000 fae2 bl 80089fc /* See if this tick has made a timeout expire. Tasks are stored in the queue in the order of their wake time - meaning once one task has been found whose block time has not expired there is no need to look any further down the list. */ if( xConstTickCount >= xNextTaskUnblockTime ) - 80042f0: 4b3b ldr r3, [pc, #236] @ (80043e0 ) - 80042f2: 681b ldr r3, [r3, #0] - 80042f4: 693a ldr r2, [r7, #16] - 80042f6: 429a cmp r2, r3 - 80042f8: d349 bcc.n 800438e + 8008438: 4b3b ldr r3, [pc, #236] @ (8008528 ) + 800843a: 681b ldr r3, [r3, #0] + 800843c: 693a ldr r2, [r7, #16] + 800843e: 429a cmp r2, r3 + 8008440: d349 bcc.n 80084d6 { for( ;; ) { if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) - 80042fa: 4b36 ldr r3, [pc, #216] @ (80043d4 ) - 80042fc: 681b ldr r3, [r3, #0] - 80042fe: 681b ldr r3, [r3, #0] - 8004300: 2b00 cmp r3, #0 - 8004302: d104 bne.n 800430e + 8008442: 4b36 ldr r3, [pc, #216] @ (800851c ) + 8008444: 681b ldr r3, [r3, #0] + 8008446: 681b ldr r3, [r3, #0] + 8008448: 2b00 cmp r3, #0 + 800844a: d104 bne.n 8008456 /* The delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass next time through. */ xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ - 8004304: 4b36 ldr r3, [pc, #216] @ (80043e0 ) - 8004306: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff - 800430a: 601a str r2, [r3, #0] + 800844c: 4b36 ldr r3, [pc, #216] @ (8008528 ) + 800844e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8008452: 601a str r2, [r3, #0] break; - 800430c: e03f b.n 800438e + 8008454: e03f b.n 80084d6 { /* The delayed list is not empty, get the value of the item at the head of the delayed list. This is the time at which the task at the head of the delayed list must be removed from the Blocked state. */ pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ - 800430e: 4b31 ldr r3, [pc, #196] @ (80043d4 ) - 8004310: 681b ldr r3, [r3, #0] - 8004312: 68db ldr r3, [r3, #12] - 8004314: 68db ldr r3, [r3, #12] - 8004316: 60bb str r3, [r7, #8] + 8008456: 4b31 ldr r3, [pc, #196] @ (800851c ) + 8008458: 681b ldr r3, [r3, #0] + 800845a: 68db ldr r3, [r3, #12] + 800845c: 68db ldr r3, [r3, #12] + 800845e: 60bb str r3, [r7, #8] xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); - 8004318: 68bb ldr r3, [r7, #8] - 800431a: 685b ldr r3, [r3, #4] - 800431c: 607b str r3, [r7, #4] + 8008460: 68bb ldr r3, [r7, #8] + 8008462: 685b ldr r3, [r3, #4] + 8008464: 607b str r3, [r7, #4] if( xConstTickCount < xItemValue ) - 800431e: 693a ldr r2, [r7, #16] - 8004320: 687b ldr r3, [r7, #4] - 8004322: 429a cmp r2, r3 - 8004324: d203 bcs.n 800432e + 8008466: 693a ldr r2, [r7, #16] + 8008468: 687b ldr r3, [r7, #4] + 800846a: 429a cmp r2, r3 + 800846c: d203 bcs.n 8008476 /* It is not time to unblock this item yet, but the item value is the time at which the task at the head of the blocked list must be removed from the Blocked state - so record the item value in xNextTaskUnblockTime. */ xNextTaskUnblockTime = xItemValue; - 8004326: 4a2e ldr r2, [pc, #184] @ (80043e0 ) - 8004328: 687b ldr r3, [r7, #4] - 800432a: 6013 str r3, [r2, #0] + 800846e: 4a2e ldr r2, [pc, #184] @ (8008528 ) + 8008470: 687b ldr r3, [r7, #4] + 8008472: 6013 str r3, [r2, #0] break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */ - 800432c: e02f b.n 800438e + 8008474: e02f b.n 80084d6 { mtCOVERAGE_TEST_MARKER(); } /* It is time to remove the item from the Blocked state. */ ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); - 800432e: 68bb ldr r3, [r7, #8] - 8004330: 3304 adds r3, #4 - 8004332: 4618 mov r0, r3 - 8004334: f7fe ff62 bl 80031fc + 8008476: 68bb ldr r3, [r7, #8] + 8008478: 3304 adds r3, #4 + 800847a: 4618 mov r0, r3 + 800847c: f7fe fc66 bl 8006d4c /* Is the task waiting on an event also? If so remove it from the event list. */ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) - 8004338: 68bb ldr r3, [r7, #8] - 800433a: 6a9b ldr r3, [r3, #40] @ 0x28 - 800433c: 2b00 cmp r3, #0 - 800433e: d004 beq.n 800434a + 8008480: 68bb ldr r3, [r7, #8] + 8008482: 6a9b ldr r3, [r3, #40] @ 0x28 + 8008484: 2b00 cmp r3, #0 + 8008486: d004 beq.n 8008492 { ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); - 8004340: 68bb ldr r3, [r7, #8] - 8004342: 3318 adds r3, #24 - 8004344: 4618 mov r0, r3 - 8004346: f7fe ff59 bl 80031fc + 8008488: 68bb ldr r3, [r7, #8] + 800848a: 3318 adds r3, #24 + 800848c: 4618 mov r0, r3 + 800848e: f7fe fc5d bl 8006d4c mtCOVERAGE_TEST_MARKER(); } /* Place the unblocked task into the appropriate ready list. */ prvAddTaskToReadyList( pxTCB ); - 800434a: 68bb ldr r3, [r7, #8] - 800434c: 6ada ldr r2, [r3, #44] @ 0x2c - 800434e: 4b25 ldr r3, [pc, #148] @ (80043e4 ) - 8004350: 681b ldr r3, [r3, #0] - 8004352: 429a cmp r2, r3 - 8004354: d903 bls.n 800435e - 8004356: 68bb ldr r3, [r7, #8] - 8004358: 6adb ldr r3, [r3, #44] @ 0x2c - 800435a: 4a22 ldr r2, [pc, #136] @ (80043e4 ) - 800435c: 6013 str r3, [r2, #0] - 800435e: 68bb ldr r3, [r7, #8] - 8004360: 6ada ldr r2, [r3, #44] @ 0x2c - 8004362: 4613 mov r3, r2 - 8004364: 009b lsls r3, r3, #2 - 8004366: 4413 add r3, r2 - 8004368: 009b lsls r3, r3, #2 - 800436a: 4a1f ldr r2, [pc, #124] @ (80043e8 ) - 800436c: 441a add r2, r3 - 800436e: 68bb ldr r3, [r7, #8] - 8004370: 3304 adds r3, #4 - 8004372: 4619 mov r1, r3 - 8004374: 4610 mov r0, r2 - 8004376: f7fe fee4 bl 8003142 + 8008492: 68bb ldr r3, [r7, #8] + 8008494: 6ada ldr r2, [r3, #44] @ 0x2c + 8008496: 4b25 ldr r3, [pc, #148] @ (800852c ) + 8008498: 681b ldr r3, [r3, #0] + 800849a: 429a cmp r2, r3 + 800849c: d903 bls.n 80084a6 + 800849e: 68bb ldr r3, [r7, #8] + 80084a0: 6adb ldr r3, [r3, #44] @ 0x2c + 80084a2: 4a22 ldr r2, [pc, #136] @ (800852c ) + 80084a4: 6013 str r3, [r2, #0] + 80084a6: 68bb ldr r3, [r7, #8] + 80084a8: 6ada ldr r2, [r3, #44] @ 0x2c + 80084aa: 4613 mov r3, r2 + 80084ac: 009b lsls r3, r3, #2 + 80084ae: 4413 add r3, r2 + 80084b0: 009b lsls r3, r3, #2 + 80084b2: 4a1f ldr r2, [pc, #124] @ (8008530 ) + 80084b4: 441a add r2, r3 + 80084b6: 68bb ldr r3, [r7, #8] + 80084b8: 3304 adds r3, #4 + 80084ba: 4619 mov r1, r3 + 80084bc: 4610 mov r0, r2 + 80084be: f7fe fbe8 bl 8006c92 { /* Preemption is on, but a context switch should only be performed if the unblocked task has a priority that is equal to or higher than the currently executing task. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) - 800437a: 68bb ldr r3, [r7, #8] - 800437c: 6ada ldr r2, [r3, #44] @ 0x2c - 800437e: 4b1b ldr r3, [pc, #108] @ (80043ec ) - 8004380: 681b ldr r3, [r3, #0] - 8004382: 6adb ldr r3, [r3, #44] @ 0x2c - 8004384: 429a cmp r2, r3 - 8004386: d3b8 bcc.n 80042fa + 80084c2: 68bb ldr r3, [r7, #8] + 80084c4: 6ada ldr r2, [r3, #44] @ 0x2c + 80084c6: 4b1b ldr r3, [pc, #108] @ (8008534 ) + 80084c8: 681b ldr r3, [r3, #0] + 80084ca: 6adb ldr r3, [r3, #44] @ 0x2c + 80084cc: 429a cmp r2, r3 + 80084ce: d3b8 bcc.n 8008442 { xSwitchRequired = pdTRUE; - 8004388: 2301 movs r3, #1 - 800438a: 617b str r3, [r7, #20] + 80084d0: 2301 movs r3, #1 + 80084d2: 617b str r3, [r7, #20] if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) - 800438c: e7b5 b.n 80042fa + 80084d4: e7b5 b.n 8008442 /* Tasks of equal priority to the currently running task will share processing time (time slice) if preemption is on, and the application writer has not explicitly turned time slicing off. */ #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) { if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) - 800438e: 4b17 ldr r3, [pc, #92] @ (80043ec ) - 8004390: 681b ldr r3, [r3, #0] - 8004392: 6ada ldr r2, [r3, #44] @ 0x2c - 8004394: 4914 ldr r1, [pc, #80] @ (80043e8 ) - 8004396: 4613 mov r3, r2 - 8004398: 009b lsls r3, r3, #2 - 800439a: 4413 add r3, r2 - 800439c: 009b lsls r3, r3, #2 - 800439e: 440b add r3, r1 - 80043a0: 681b ldr r3, [r3, #0] - 80043a2: 2b01 cmp r3, #1 - 80043a4: d901 bls.n 80043aa + 80084d6: 4b17 ldr r3, [pc, #92] @ (8008534 ) + 80084d8: 681b ldr r3, [r3, #0] + 80084da: 6ada ldr r2, [r3, #44] @ 0x2c + 80084dc: 4914 ldr r1, [pc, #80] @ (8008530 ) + 80084de: 4613 mov r3, r2 + 80084e0: 009b lsls r3, r3, #2 + 80084e2: 4413 add r3, r2 + 80084e4: 009b lsls r3, r3, #2 + 80084e6: 440b add r3, r1 + 80084e8: 681b ldr r3, [r3, #0] + 80084ea: 2b01 cmp r3, #1 + 80084ec: d901 bls.n 80084f2 { xSwitchRequired = pdTRUE; - 80043a6: 2301 movs r3, #1 - 80043a8: 617b str r3, [r7, #20] + 80084ee: 2301 movs r3, #1 + 80084f0: 617b str r3, [r7, #20] } #endif /* configUSE_TICK_HOOK */ #if ( configUSE_PREEMPTION == 1 ) { if( xYieldPending != pdFALSE ) - 80043aa: 4b11 ldr r3, [pc, #68] @ (80043f0 ) - 80043ac: 681b ldr r3, [r3, #0] - 80043ae: 2b00 cmp r3, #0 - 80043b0: d007 beq.n 80043c2 + 80084f2: 4b11 ldr r3, [pc, #68] @ (8008538 ) + 80084f4: 681b ldr r3, [r3, #0] + 80084f6: 2b00 cmp r3, #0 + 80084f8: d007 beq.n 800850a { xSwitchRequired = pdTRUE; - 80043b2: 2301 movs r3, #1 - 80043b4: 617b str r3, [r7, #20] - 80043b6: e004 b.n 80043c2 + 80084fa: 2301 movs r3, #1 + 80084fc: 617b str r3, [r7, #20] + 80084fe: e004 b.n 800850a } #endif /* configUSE_PREEMPTION */ } else { ++xPendedTicks; - 80043b8: 4b0e ldr r3, [pc, #56] @ (80043f4 ) - 80043ba: 681b ldr r3, [r3, #0] - 80043bc: 3301 adds r3, #1 - 80043be: 4a0d ldr r2, [pc, #52] @ (80043f4 ) - 80043c0: 6013 str r3, [r2, #0] + 8008500: 4b0e ldr r3, [pc, #56] @ (800853c ) + 8008502: 681b ldr r3, [r3, #0] + 8008504: 3301 adds r3, #1 + 8008506: 4a0d ldr r2, [pc, #52] @ (800853c ) + 8008508: 6013 str r3, [r2, #0] vApplicationTickHook(); } #endif } return xSwitchRequired; - 80043c2: 697b ldr r3, [r7, #20] + 800850a: 697b ldr r3, [r7, #20] } - 80043c4: 4618 mov r0, r3 - 80043c6: 3718 adds r7, #24 - 80043c8: 46bd mov sp, r7 - 80043ca: bd80 pop {r7, pc} - 80043cc: 20000e34 .word 0x20000e34 - 80043d0: 20000e10 .word 0x20000e10 - 80043d4: 20000dc4 .word 0x20000dc4 - 80043d8: 20000dc8 .word 0x20000dc8 - 80043dc: 20000e24 .word 0x20000e24 - 80043e0: 20000e2c .word 0x20000e2c - 80043e4: 20000e14 .word 0x20000e14 - 80043e8: 2000093c .word 0x2000093c - 80043ec: 20000938 .word 0x20000938 - 80043f0: 20000e20 .word 0x20000e20 - 80043f4: 20000e1c .word 0x20000e1c + 800850c: 4618 mov r0, r3 + 800850e: 3718 adds r7, #24 + 8008510: 46bd mov sp, r7 + 8008512: bd80 pop {r7, pc} + 8008514: 20000fbc .word 0x20000fbc + 8008518: 20000f98 .word 0x20000f98 + 800851c: 20000f4c .word 0x20000f4c + 8008520: 20000f50 .word 0x20000f50 + 8008524: 20000fac .word 0x20000fac + 8008528: 20000fb4 .word 0x20000fb4 + 800852c: 20000f9c .word 0x20000f9c + 8008530: 20000ac4 .word 0x20000ac4 + 8008534: 20000ac0 .word 0x20000ac0 + 8008538: 20000fa8 .word 0x20000fa8 + 800853c: 20000fa4 .word 0x20000fa4 -080043f8 : +08008540 : #endif /* configUSE_APPLICATION_TASK_TAG */ /*-----------------------------------------------------------*/ void vTaskSwitchContext( void ) { - 80043f8: b480 push {r7} - 80043fa: b085 sub sp, #20 - 80043fc: af00 add r7, sp, #0 + 8008540: b480 push {r7} + 8008542: b085 sub sp, #20 + 8008544: af00 add r7, sp, #0 if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE ) - 80043fe: 4b2b ldr r3, [pc, #172] @ (80044ac ) - 8004400: 681b ldr r3, [r3, #0] - 8004402: 2b00 cmp r3, #0 - 8004404: d003 beq.n 800440e + 8008546: 4b2b ldr r3, [pc, #172] @ (80085f4 ) + 8008548: 681b ldr r3, [r3, #0] + 800854a: 2b00 cmp r3, #0 + 800854c: d003 beq.n 8008556 { /* The scheduler is currently suspended - do not allow a context switch. */ xYieldPending = pdTRUE; - 8004406: 4b2a ldr r3, [pc, #168] @ (80044b0 ) - 8004408: 2201 movs r2, #1 - 800440a: 601a str r2, [r3, #0] + 800854e: 4b2a ldr r3, [pc, #168] @ (80085f8 ) + 8008550: 2201 movs r2, #1 + 8008552: 601a str r2, [r3, #0] for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); } #endif /* configUSE_NEWLIB_REENTRANT */ } } - 800440c: e047 b.n 800449e + 8008554: e047 b.n 80085e6 xYieldPending = pdFALSE; - 800440e: 4b28 ldr r3, [pc, #160] @ (80044b0 ) - 8004410: 2200 movs r2, #0 - 8004412: 601a str r2, [r3, #0] + 8008556: 4b28 ldr r3, [pc, #160] @ (80085f8 ) + 8008558: 2200 movs r2, #0 + 800855a: 601a str r2, [r3, #0] taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ - 8004414: 4b27 ldr r3, [pc, #156] @ (80044b4 ) - 8004416: 681b ldr r3, [r3, #0] - 8004418: 60fb str r3, [r7, #12] - 800441a: e011 b.n 8004440 - 800441c: 68fb ldr r3, [r7, #12] - 800441e: 2b00 cmp r3, #0 - 8004420: d10b bne.n 800443a + 800855c: 4b27 ldr r3, [pc, #156] @ (80085fc ) + 800855e: 681b ldr r3, [r3, #0] + 8008560: 60fb str r3, [r7, #12] + 8008562: e011 b.n 8008588 + 8008564: 68fb ldr r3, [r7, #12] + 8008566: 2b00 cmp r3, #0 + 8008568: d10b bne.n 8008582 __asm volatile - 8004422: f04f 0350 mov.w r3, #80 @ 0x50 - 8004426: f383 8811 msr BASEPRI, r3 - 800442a: f3bf 8f6f isb sy - 800442e: f3bf 8f4f dsb sy - 8004432: 607b str r3, [r7, #4] + 800856a: f04f 0350 mov.w r3, #80 @ 0x50 + 800856e: f383 8811 msr BASEPRI, r3 + 8008572: f3bf 8f6f isb sy + 8008576: f3bf 8f4f dsb sy + 800857a: 607b str r3, [r7, #4] } - 8004434: bf00 nop - 8004436: bf00 nop - 8004438: e7fd b.n 8004436 - 800443a: 68fb ldr r3, [r7, #12] - 800443c: 3b01 subs r3, #1 - 800443e: 60fb str r3, [r7, #12] - 8004440: 491d ldr r1, [pc, #116] @ (80044b8 ) - 8004442: 68fa ldr r2, [r7, #12] - 8004444: 4613 mov r3, r2 - 8004446: 009b lsls r3, r3, #2 - 8004448: 4413 add r3, r2 - 800444a: 009b lsls r3, r3, #2 - 800444c: 440b add r3, r1 - 800444e: 681b ldr r3, [r3, #0] - 8004450: 2b00 cmp r3, #0 - 8004452: d0e3 beq.n 800441c - 8004454: 68fa ldr r2, [r7, #12] - 8004456: 4613 mov r3, r2 - 8004458: 009b lsls r3, r3, #2 - 800445a: 4413 add r3, r2 - 800445c: 009b lsls r3, r3, #2 - 800445e: 4a16 ldr r2, [pc, #88] @ (80044b8 ) - 8004460: 4413 add r3, r2 - 8004462: 60bb str r3, [r7, #8] - 8004464: 68bb ldr r3, [r7, #8] - 8004466: 685b ldr r3, [r3, #4] - 8004468: 685a ldr r2, [r3, #4] - 800446a: 68bb ldr r3, [r7, #8] - 800446c: 605a str r2, [r3, #4] - 800446e: 68bb ldr r3, [r7, #8] - 8004470: 685a ldr r2, [r3, #4] - 8004472: 68bb ldr r3, [r7, #8] - 8004474: 3308 adds r3, #8 - 8004476: 429a cmp r2, r3 - 8004478: d104 bne.n 8004484 - 800447a: 68bb ldr r3, [r7, #8] - 800447c: 685b ldr r3, [r3, #4] - 800447e: 685a ldr r2, [r3, #4] - 8004480: 68bb ldr r3, [r7, #8] - 8004482: 605a str r2, [r3, #4] - 8004484: 68bb ldr r3, [r7, #8] - 8004486: 685b ldr r3, [r3, #4] - 8004488: 68db ldr r3, [r3, #12] - 800448a: 4a0c ldr r2, [pc, #48] @ (80044bc ) - 800448c: 6013 str r3, [r2, #0] - 800448e: 4a09 ldr r2, [pc, #36] @ (80044b4 ) - 8004490: 68fb ldr r3, [r7, #12] - 8004492: 6013 str r3, [r2, #0] + 800857c: bf00 nop + 800857e: bf00 nop + 8008580: e7fd b.n 800857e + 8008582: 68fb ldr r3, [r7, #12] + 8008584: 3b01 subs r3, #1 + 8008586: 60fb str r3, [r7, #12] + 8008588: 491d ldr r1, [pc, #116] @ (8008600 ) + 800858a: 68fa ldr r2, [r7, #12] + 800858c: 4613 mov r3, r2 + 800858e: 009b lsls r3, r3, #2 + 8008590: 4413 add r3, r2 + 8008592: 009b lsls r3, r3, #2 + 8008594: 440b add r3, r1 + 8008596: 681b ldr r3, [r3, #0] + 8008598: 2b00 cmp r3, #0 + 800859a: d0e3 beq.n 8008564 + 800859c: 68fa ldr r2, [r7, #12] + 800859e: 4613 mov r3, r2 + 80085a0: 009b lsls r3, r3, #2 + 80085a2: 4413 add r3, r2 + 80085a4: 009b lsls r3, r3, #2 + 80085a6: 4a16 ldr r2, [pc, #88] @ (8008600 ) + 80085a8: 4413 add r3, r2 + 80085aa: 60bb str r3, [r7, #8] + 80085ac: 68bb ldr r3, [r7, #8] + 80085ae: 685b ldr r3, [r3, #4] + 80085b0: 685a ldr r2, [r3, #4] + 80085b2: 68bb ldr r3, [r7, #8] + 80085b4: 605a str r2, [r3, #4] + 80085b6: 68bb ldr r3, [r7, #8] + 80085b8: 685a ldr r2, [r3, #4] + 80085ba: 68bb ldr r3, [r7, #8] + 80085bc: 3308 adds r3, #8 + 80085be: 429a cmp r2, r3 + 80085c0: d104 bne.n 80085cc + 80085c2: 68bb ldr r3, [r7, #8] + 80085c4: 685b ldr r3, [r3, #4] + 80085c6: 685a ldr r2, [r3, #4] + 80085c8: 68bb ldr r3, [r7, #8] + 80085ca: 605a str r2, [r3, #4] + 80085cc: 68bb ldr r3, [r7, #8] + 80085ce: 685b ldr r3, [r3, #4] + 80085d0: 68db ldr r3, [r3, #12] + 80085d2: 4a0c ldr r2, [pc, #48] @ (8008604 ) + 80085d4: 6013 str r3, [r2, #0] + 80085d6: 4a09 ldr r2, [pc, #36] @ (80085fc ) + 80085d8: 68fb ldr r3, [r7, #12] + 80085da: 6013 str r3, [r2, #0] _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); - 8004494: 4b09 ldr r3, [pc, #36] @ (80044bc ) - 8004496: 681b ldr r3, [r3, #0] - 8004498: 3354 adds r3, #84 @ 0x54 - 800449a: 4a09 ldr r2, [pc, #36] @ (80044c0 ) - 800449c: 6013 str r3, [r2, #0] + 80085dc: 4b09 ldr r3, [pc, #36] @ (8008604 ) + 80085de: 681b ldr r3, [r3, #0] + 80085e0: 3354 adds r3, #84 @ 0x54 + 80085e2: 4a09 ldr r2, [pc, #36] @ (8008608 ) + 80085e4: 6013 str r3, [r2, #0] } - 800449e: bf00 nop - 80044a0: 3714 adds r7, #20 - 80044a2: 46bd mov sp, r7 - 80044a4: f85d 7b04 ldr.w r7, [sp], #4 - 80044a8: 4770 bx lr - 80044aa: bf00 nop - 80044ac: 20000e34 .word 0x20000e34 - 80044b0: 20000e20 .word 0x20000e20 - 80044b4: 20000e14 .word 0x20000e14 - 80044b8: 2000093c .word 0x2000093c - 80044bc: 20000938 .word 0x20000938 - 80044c0: 20000010 .word 0x20000010 + 80085e6: bf00 nop + 80085e8: 3714 adds r7, #20 + 80085ea: 46bd mov sp, r7 + 80085ec: f85d 7b04 ldr.w r7, [sp], #4 + 80085f0: 4770 bx lr + 80085f2: bf00 nop + 80085f4: 20000fbc .word 0x20000fbc + 80085f8: 20000fa8 .word 0x20000fa8 + 80085fc: 20000f9c .word 0x20000f9c + 8008600: 20000ac4 .word 0x20000ac4 + 8008604: 20000ac0 .word 0x20000ac0 + 8008608: 20000028 .word 0x20000028 -080044c4 : +0800860c : /*-----------------------------------------------------------*/ void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) { - 80044c4: b580 push {r7, lr} - 80044c6: b084 sub sp, #16 - 80044c8: af00 add r7, sp, #0 - 80044ca: 6078 str r0, [r7, #4] - 80044cc: 6039 str r1, [r7, #0] + 800860c: b580 push {r7, lr} + 800860e: b084 sub sp, #16 + 8008610: af00 add r7, sp, #0 + 8008612: 6078 str r0, [r7, #4] + 8008614: 6039 str r1, [r7, #0] configASSERT( pxEventList ); - 80044ce: 687b ldr r3, [r7, #4] - 80044d0: 2b00 cmp r3, #0 - 80044d2: d10b bne.n 80044ec + 8008616: 687b ldr r3, [r7, #4] + 8008618: 2b00 cmp r3, #0 + 800861a: d10b bne.n 8008634 __asm volatile - 80044d4: f04f 0350 mov.w r3, #80 @ 0x50 - 80044d8: f383 8811 msr BASEPRI, r3 - 80044dc: f3bf 8f6f isb sy - 80044e0: f3bf 8f4f dsb sy - 80044e4: 60fb str r3, [r7, #12] + 800861c: f04f 0350 mov.w r3, #80 @ 0x50 + 8008620: f383 8811 msr BASEPRI, r3 + 8008624: f3bf 8f6f isb sy + 8008628: f3bf 8f4f dsb sy + 800862c: 60fb str r3, [r7, #12] } - 80044e6: bf00 nop - 80044e8: bf00 nop - 80044ea: e7fd b.n 80044e8 + 800862e: bf00 nop + 8008630: bf00 nop + 8008632: e7fd b.n 8008630 /* Place the event list item of the TCB in the appropriate event list. This is placed in the list in priority order so the highest priority task is the first to be woken by the event. The queue that contains the event list is locked, preventing simultaneous access from interrupts. */ vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) ); - 80044ec: 4b07 ldr r3, [pc, #28] @ (800450c ) - 80044ee: 681b ldr r3, [r3, #0] - 80044f0: 3318 adds r3, #24 - 80044f2: 4619 mov r1, r3 - 80044f4: 6878 ldr r0, [r7, #4] - 80044f6: f7fe fe48 bl 800318a + 8008634: 4b07 ldr r3, [pc, #28] @ (8008654 ) + 8008636: 681b ldr r3, [r3, #0] + 8008638: 3318 adds r3, #24 + 800863a: 4619 mov r1, r3 + 800863c: 6878 ldr r0, [r7, #4] + 800863e: f7fe fb4c bl 8006cda prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); - 80044fa: 2101 movs r1, #1 - 80044fc: 6838 ldr r0, [r7, #0] - 80044fe: f000 fa87 bl 8004a10 + 8008642: 2101 movs r1, #1 + 8008644: 6838 ldr r0, [r7, #0] + 8008646: f000 fb87 bl 8008d58 } - 8004502: bf00 nop - 8004504: 3710 adds r7, #16 - 8004506: 46bd mov sp, r7 - 8004508: bd80 pop {r7, pc} - 800450a: bf00 nop - 800450c: 20000938 .word 0x20000938 + 800864a: bf00 nop + 800864c: 3710 adds r7, #16 + 800864e: 46bd mov sp, r7 + 8008650: bd80 pop {r7, pc} + 8008652: bf00 nop + 8008654: 20000ac0 .word 0x20000ac0 -08004510 : +08008658 : /*-----------------------------------------------------------*/ #if( configUSE_TIMERS == 1 ) void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { - 8004510: b580 push {r7, lr} - 8004512: b086 sub sp, #24 - 8004514: af00 add r7, sp, #0 - 8004516: 60f8 str r0, [r7, #12] - 8004518: 60b9 str r1, [r7, #8] - 800451a: 607a str r2, [r7, #4] + 8008658: b580 push {r7, lr} + 800865a: b086 sub sp, #24 + 800865c: af00 add r7, sp, #0 + 800865e: 60f8 str r0, [r7, #12] + 8008660: 60b9 str r1, [r7, #8] + 8008662: 607a str r2, [r7, #4] configASSERT( pxEventList ); - 800451c: 68fb ldr r3, [r7, #12] - 800451e: 2b00 cmp r3, #0 - 8004520: d10b bne.n 800453a + 8008664: 68fb ldr r3, [r7, #12] + 8008666: 2b00 cmp r3, #0 + 8008668: d10b bne.n 8008682 __asm volatile - 8004522: f04f 0350 mov.w r3, #80 @ 0x50 - 8004526: f383 8811 msr BASEPRI, r3 - 800452a: f3bf 8f6f isb sy - 800452e: f3bf 8f4f dsb sy - 8004532: 617b str r3, [r7, #20] + 800866a: f04f 0350 mov.w r3, #80 @ 0x50 + 800866e: f383 8811 msr BASEPRI, r3 + 8008672: f3bf 8f6f isb sy + 8008676: f3bf 8f4f dsb sy + 800867a: 617b str r3, [r7, #20] } - 8004534: bf00 nop - 8004536: bf00 nop - 8004538: e7fd b.n 8004536 + 800867c: bf00 nop + 800867e: bf00 nop + 8008680: e7fd b.n 800867e /* Place the event list item of the TCB in the appropriate event list. In this case it is assume that this is the only task that is going to be waiting on this event list, so the faster vListInsertEnd() function can be used in place of vListInsert. */ vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) ); - 800453a: 4b0a ldr r3, [pc, #40] @ (8004564 ) - 800453c: 681b ldr r3, [r3, #0] - 800453e: 3318 adds r3, #24 - 8004540: 4619 mov r1, r3 - 8004542: 68f8 ldr r0, [r7, #12] - 8004544: f7fe fdfd bl 8003142 + 8008682: 4b0a ldr r3, [pc, #40] @ (80086ac ) + 8008684: 681b ldr r3, [r3, #0] + 8008686: 3318 adds r3, #24 + 8008688: 4619 mov r1, r3 + 800868a: 68f8 ldr r0, [r7, #12] + 800868c: f7fe fb01 bl 8006c92 /* If the task should block indefinitely then set the block time to a value that will be recognised as an indefinite delay inside the prvAddCurrentTaskToDelayedList() function. */ if( xWaitIndefinitely != pdFALSE ) - 8004548: 687b ldr r3, [r7, #4] - 800454a: 2b00 cmp r3, #0 - 800454c: d002 beq.n 8004554 + 8008690: 687b ldr r3, [r7, #4] + 8008692: 2b00 cmp r3, #0 + 8008694: d002 beq.n 800869c { xTicksToWait = portMAX_DELAY; - 800454e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff - 8004552: 60bb str r3, [r7, #8] + 8008696: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800869a: 60bb str r3, [r7, #8] } traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) ); prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely ); - 8004554: 6879 ldr r1, [r7, #4] - 8004556: 68b8 ldr r0, [r7, #8] - 8004558: f000 fa5a bl 8004a10 + 800869c: 6879 ldr r1, [r7, #4] + 800869e: 68b8 ldr r0, [r7, #8] + 80086a0: f000 fb5a bl 8008d58 } - 800455c: bf00 nop - 800455e: 3718 adds r7, #24 - 8004560: 46bd mov sp, r7 - 8004562: bd80 pop {r7, pc} - 8004564: 20000938 .word 0x20000938 + 80086a4: bf00 nop + 80086a6: 3718 adds r7, #24 + 80086a8: 46bd mov sp, r7 + 80086aa: bd80 pop {r7, pc} + 80086ac: 20000ac0 .word 0x20000ac0 -08004568 : +080086b0 : #endif /* configUSE_TIMERS */ /*-----------------------------------------------------------*/ BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) { - 8004568: b580 push {r7, lr} - 800456a: b086 sub sp, #24 - 800456c: af00 add r7, sp, #0 - 800456e: 6078 str r0, [r7, #4] + 80086b0: b580 push {r7, lr} + 80086b2: b086 sub sp, #24 + 80086b4: af00 add r7, sp, #0 + 80086b6: 6078 str r0, [r7, #4] get called - the lock count on the queue will get modified instead. This means exclusive access to the event list is guaranteed here. This function assumes that a check has already been made to ensure that pxEventList is not empty. */ pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ - 8004570: 687b ldr r3, [r7, #4] - 8004572: 68db ldr r3, [r3, #12] - 8004574: 68db ldr r3, [r3, #12] - 8004576: 613b str r3, [r7, #16] + 80086b8: 687b ldr r3, [r7, #4] + 80086ba: 68db ldr r3, [r3, #12] + 80086bc: 68db ldr r3, [r3, #12] + 80086be: 613b str r3, [r7, #16] configASSERT( pxUnblockedTCB ); - 8004578: 693b ldr r3, [r7, #16] - 800457a: 2b00 cmp r3, #0 - 800457c: d10b bne.n 8004596 + 80086c0: 693b ldr r3, [r7, #16] + 80086c2: 2b00 cmp r3, #0 + 80086c4: d10b bne.n 80086de __asm volatile - 800457e: f04f 0350 mov.w r3, #80 @ 0x50 - 8004582: f383 8811 msr BASEPRI, r3 - 8004586: f3bf 8f6f isb sy - 800458a: f3bf 8f4f dsb sy - 800458e: 60fb str r3, [r7, #12] + 80086c6: f04f 0350 mov.w r3, #80 @ 0x50 + 80086ca: f383 8811 msr BASEPRI, r3 + 80086ce: f3bf 8f6f isb sy + 80086d2: f3bf 8f4f dsb sy + 80086d6: 60fb str r3, [r7, #12] } - 8004590: bf00 nop - 8004592: bf00 nop - 8004594: e7fd b.n 8004592 + 80086d8: bf00 nop + 80086da: bf00 nop + 80086dc: e7fd b.n 80086da ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) ); - 8004596: 693b ldr r3, [r7, #16] - 8004598: 3318 adds r3, #24 - 800459a: 4618 mov r0, r3 - 800459c: f7fe fe2e bl 80031fc + 80086de: 693b ldr r3, [r7, #16] + 80086e0: 3318 adds r3, #24 + 80086e2: 4618 mov r0, r3 + 80086e4: f7fe fb32 bl 8006d4c if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) - 80045a0: 4b1d ldr r3, [pc, #116] @ (8004618 ) - 80045a2: 681b ldr r3, [r3, #0] - 80045a4: 2b00 cmp r3, #0 - 80045a6: d11d bne.n 80045e4 + 80086e8: 4b1d ldr r3, [pc, #116] @ (8008760 ) + 80086ea: 681b ldr r3, [r3, #0] + 80086ec: 2b00 cmp r3, #0 + 80086ee: d11d bne.n 800872c { ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) ); - 80045a8: 693b ldr r3, [r7, #16] - 80045aa: 3304 adds r3, #4 - 80045ac: 4618 mov r0, r3 - 80045ae: f7fe fe25 bl 80031fc + 80086f0: 693b ldr r3, [r7, #16] + 80086f2: 3304 adds r3, #4 + 80086f4: 4618 mov r0, r3 + 80086f6: f7fe fb29 bl 8006d4c prvAddTaskToReadyList( pxUnblockedTCB ); - 80045b2: 693b ldr r3, [r7, #16] - 80045b4: 6ada ldr r2, [r3, #44] @ 0x2c - 80045b6: 4b19 ldr r3, [pc, #100] @ (800461c ) - 80045b8: 681b ldr r3, [r3, #0] - 80045ba: 429a cmp r2, r3 - 80045bc: d903 bls.n 80045c6 - 80045be: 693b ldr r3, [r7, #16] - 80045c0: 6adb ldr r3, [r3, #44] @ 0x2c - 80045c2: 4a16 ldr r2, [pc, #88] @ (800461c ) - 80045c4: 6013 str r3, [r2, #0] - 80045c6: 693b ldr r3, [r7, #16] - 80045c8: 6ada ldr r2, [r3, #44] @ 0x2c - 80045ca: 4613 mov r3, r2 - 80045cc: 009b lsls r3, r3, #2 - 80045ce: 4413 add r3, r2 - 80045d0: 009b lsls r3, r3, #2 - 80045d2: 4a13 ldr r2, [pc, #76] @ (8004620 ) - 80045d4: 441a add r2, r3 - 80045d6: 693b ldr r3, [r7, #16] - 80045d8: 3304 adds r3, #4 - 80045da: 4619 mov r1, r3 - 80045dc: 4610 mov r0, r2 - 80045de: f7fe fdb0 bl 8003142 - 80045e2: e005 b.n 80045f0 + 80086fa: 693b ldr r3, [r7, #16] + 80086fc: 6ada ldr r2, [r3, #44] @ 0x2c + 80086fe: 4b19 ldr r3, [pc, #100] @ (8008764 ) + 8008700: 681b ldr r3, [r3, #0] + 8008702: 429a cmp r2, r3 + 8008704: d903 bls.n 800870e + 8008706: 693b ldr r3, [r7, #16] + 8008708: 6adb ldr r3, [r3, #44] @ 0x2c + 800870a: 4a16 ldr r2, [pc, #88] @ (8008764 ) + 800870c: 6013 str r3, [r2, #0] + 800870e: 693b ldr r3, [r7, #16] + 8008710: 6ada ldr r2, [r3, #44] @ 0x2c + 8008712: 4613 mov r3, r2 + 8008714: 009b lsls r3, r3, #2 + 8008716: 4413 add r3, r2 + 8008718: 009b lsls r3, r3, #2 + 800871a: 4a13 ldr r2, [pc, #76] @ (8008768 ) + 800871c: 441a add r2, r3 + 800871e: 693b ldr r3, [r7, #16] + 8008720: 3304 adds r3, #4 + 8008722: 4619 mov r1, r3 + 8008724: 4610 mov r0, r2 + 8008726: f7fe fab4 bl 8006c92 + 800872a: e005 b.n 8008738 } else { /* The delayed and ready lists cannot be accessed, so hold this task pending until the scheduler is resumed. */ vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); - 80045e4: 693b ldr r3, [r7, #16] - 80045e6: 3318 adds r3, #24 - 80045e8: 4619 mov r1, r3 - 80045ea: 480e ldr r0, [pc, #56] @ (8004624 ) - 80045ec: f7fe fda9 bl 8003142 + 800872c: 693b ldr r3, [r7, #16] + 800872e: 3318 adds r3, #24 + 8008730: 4619 mov r1, r3 + 8008732: 480e ldr r0, [pc, #56] @ (800876c ) + 8008734: f7fe faad bl 8006c92 } if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) - 80045f0: 693b ldr r3, [r7, #16] - 80045f2: 6ada ldr r2, [r3, #44] @ 0x2c - 80045f4: 4b0c ldr r3, [pc, #48] @ (8004628 ) - 80045f6: 681b ldr r3, [r3, #0] - 80045f8: 6adb ldr r3, [r3, #44] @ 0x2c - 80045fa: 429a cmp r2, r3 - 80045fc: d905 bls.n 800460a + 8008738: 693b ldr r3, [r7, #16] + 800873a: 6ada ldr r2, [r3, #44] @ 0x2c + 800873c: 4b0c ldr r3, [pc, #48] @ (8008770 ) + 800873e: 681b ldr r3, [r3, #0] + 8008740: 6adb ldr r3, [r3, #44] @ 0x2c + 8008742: 429a cmp r2, r3 + 8008744: d905 bls.n 8008752 { /* Return true if the task removed from the event list has a higher priority than the calling task. This allows the calling task to know if it should force a context switch now. */ xReturn = pdTRUE; - 80045fe: 2301 movs r3, #1 - 8004600: 617b str r3, [r7, #20] + 8008746: 2301 movs r3, #1 + 8008748: 617b str r3, [r7, #20] /* Mark that a yield is pending in case the user is not using the "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ xYieldPending = pdTRUE; - 8004602: 4b0a ldr r3, [pc, #40] @ (800462c ) - 8004604: 2201 movs r2, #1 - 8004606: 601a str r2, [r3, #0] - 8004608: e001 b.n 800460e + 800874a: 4b0a ldr r3, [pc, #40] @ (8008774 ) + 800874c: 2201 movs r2, #1 + 800874e: 601a str r2, [r3, #0] + 8008750: e001 b.n 8008756 } else { xReturn = pdFALSE; - 800460a: 2300 movs r3, #0 - 800460c: 617b str r3, [r7, #20] + 8008752: 2300 movs r3, #0 + 8008754: 617b str r3, [r7, #20] } return xReturn; - 800460e: 697b ldr r3, [r7, #20] + 8008756: 697b ldr r3, [r7, #20] } - 8004610: 4618 mov r0, r3 - 8004612: 3718 adds r7, #24 - 8004614: 46bd mov sp, r7 - 8004616: bd80 pop {r7, pc} - 8004618: 20000e34 .word 0x20000e34 - 800461c: 20000e14 .word 0x20000e14 - 8004620: 2000093c .word 0x2000093c - 8004624: 20000dcc .word 0x20000dcc - 8004628: 20000938 .word 0x20000938 - 800462c: 20000e20 .word 0x20000e20 + 8008758: 4618 mov r0, r3 + 800875a: 3718 adds r7, #24 + 800875c: 46bd mov sp, r7 + 800875e: bd80 pop {r7, pc} + 8008760: 20000fbc .word 0x20000fbc + 8008764: 20000f9c .word 0x20000f9c + 8008768: 20000ac4 .word 0x20000ac4 + 800876c: 20000f54 .word 0x20000f54 + 8008770: 20000ac0 .word 0x20000ac0 + 8008774: 20000fa8 .word 0x20000fa8 -08004630 : +08008778 : taskEXIT_CRITICAL(); } /*-----------------------------------------------------------*/ void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) { - 8004630: b480 push {r7} - 8004632: b083 sub sp, #12 - 8004634: af00 add r7, sp, #0 - 8004636: 6078 str r0, [r7, #4] + 8008778: b480 push {r7} + 800877a: b083 sub sp, #12 + 800877c: af00 add r7, sp, #0 + 800877e: 6078 str r0, [r7, #4] /* For internal use only as it does not use a critical section. */ pxTimeOut->xOverflowCount = xNumOfOverflows; - 8004638: 4b06 ldr r3, [pc, #24] @ (8004654 ) - 800463a: 681a ldr r2, [r3, #0] - 800463c: 687b ldr r3, [r7, #4] - 800463e: 601a str r2, [r3, #0] + 8008780: 4b06 ldr r3, [pc, #24] @ (800879c ) + 8008782: 681a ldr r2, [r3, #0] + 8008784: 687b ldr r3, [r7, #4] + 8008786: 601a str r2, [r3, #0] pxTimeOut->xTimeOnEntering = xTickCount; - 8004640: 4b05 ldr r3, [pc, #20] @ (8004658 ) - 8004642: 681a ldr r2, [r3, #0] - 8004644: 687b ldr r3, [r7, #4] - 8004646: 605a str r2, [r3, #4] + 8008788: 4b05 ldr r3, [pc, #20] @ (80087a0 ) + 800878a: 681a ldr r2, [r3, #0] + 800878c: 687b ldr r3, [r7, #4] + 800878e: 605a str r2, [r3, #4] } - 8004648: bf00 nop - 800464a: 370c adds r7, #12 - 800464c: 46bd mov sp, r7 - 800464e: f85d 7b04 ldr.w r7, [sp], #4 - 8004652: 4770 bx lr - 8004654: 20000e24 .word 0x20000e24 - 8004658: 20000e10 .word 0x20000e10 + 8008790: bf00 nop + 8008792: 370c adds r7, #12 + 8008794: 46bd mov sp, r7 + 8008796: f85d 7b04 ldr.w r7, [sp], #4 + 800879a: 4770 bx lr + 800879c: 20000fac .word 0x20000fac + 80087a0: 20000f98 .word 0x20000f98 -0800465c : +080087a4 : /*-----------------------------------------------------------*/ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) { - 800465c: b580 push {r7, lr} - 800465e: b088 sub sp, #32 - 8004660: af00 add r7, sp, #0 - 8004662: 6078 str r0, [r7, #4] - 8004664: 6039 str r1, [r7, #0] + 80087a4: b580 push {r7, lr} + 80087a6: b088 sub sp, #32 + 80087a8: af00 add r7, sp, #0 + 80087aa: 6078 str r0, [r7, #4] + 80087ac: 6039 str r1, [r7, #0] BaseType_t xReturn; configASSERT( pxTimeOut ); - 8004666: 687b ldr r3, [r7, #4] - 8004668: 2b00 cmp r3, #0 - 800466a: d10b bne.n 8004684 + 80087ae: 687b ldr r3, [r7, #4] + 80087b0: 2b00 cmp r3, #0 + 80087b2: d10b bne.n 80087cc __asm volatile - 800466c: f04f 0350 mov.w r3, #80 @ 0x50 - 8004670: f383 8811 msr BASEPRI, r3 - 8004674: f3bf 8f6f isb sy - 8004678: f3bf 8f4f dsb sy - 800467c: 613b str r3, [r7, #16] + 80087b4: f04f 0350 mov.w r3, #80 @ 0x50 + 80087b8: f383 8811 msr BASEPRI, r3 + 80087bc: f3bf 8f6f isb sy + 80087c0: f3bf 8f4f dsb sy + 80087c4: 613b str r3, [r7, #16] } - 800467e: bf00 nop - 8004680: bf00 nop - 8004682: e7fd b.n 8004680 + 80087c6: bf00 nop + 80087c8: bf00 nop + 80087ca: e7fd b.n 80087c8 configASSERT( pxTicksToWait ); - 8004684: 683b ldr r3, [r7, #0] - 8004686: 2b00 cmp r3, #0 - 8004688: d10b bne.n 80046a2 + 80087cc: 683b ldr r3, [r7, #0] + 80087ce: 2b00 cmp r3, #0 + 80087d0: d10b bne.n 80087ea __asm volatile - 800468a: f04f 0350 mov.w r3, #80 @ 0x50 - 800468e: f383 8811 msr BASEPRI, r3 - 8004692: f3bf 8f6f isb sy - 8004696: f3bf 8f4f dsb sy - 800469a: 60fb str r3, [r7, #12] + 80087d2: f04f 0350 mov.w r3, #80 @ 0x50 + 80087d6: f383 8811 msr BASEPRI, r3 + 80087da: f3bf 8f6f isb sy + 80087de: f3bf 8f4f dsb sy + 80087e2: 60fb str r3, [r7, #12] } - 800469c: bf00 nop - 800469e: bf00 nop - 80046a0: e7fd b.n 800469e + 80087e4: bf00 nop + 80087e6: bf00 nop + 80087e8: e7fd b.n 80087e6 taskENTER_CRITICAL(); - 80046a2: f000 fe91 bl 80053c8 + 80087ea: f001 f855 bl 8009898 { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount; - 80046a6: 4b1d ldr r3, [pc, #116] @ (800471c ) - 80046a8: 681b ldr r3, [r3, #0] - 80046aa: 61bb str r3, [r7, #24] + 80087ee: 4b1d ldr r3, [pc, #116] @ (8008864 ) + 80087f0: 681b ldr r3, [r3, #0] + 80087f2: 61bb str r3, [r7, #24] const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering; - 80046ac: 687b ldr r3, [r7, #4] - 80046ae: 685b ldr r3, [r3, #4] - 80046b0: 69ba ldr r2, [r7, #24] - 80046b2: 1ad3 subs r3, r2, r3 - 80046b4: 617b str r3, [r7, #20] + 80087f4: 687b ldr r3, [r7, #4] + 80087f6: 685b ldr r3, [r3, #4] + 80087f8: 69ba ldr r2, [r7, #24] + 80087fa: 1ad3 subs r3, r2, r3 + 80087fc: 617b str r3, [r7, #20] } else #endif #if ( INCLUDE_vTaskSuspend == 1 ) if( *pxTicksToWait == portMAX_DELAY ) - 80046b6: 683b ldr r3, [r7, #0] - 80046b8: 681b ldr r3, [r3, #0] - 80046ba: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff - 80046be: d102 bne.n 80046c6 + 80087fe: 683b ldr r3, [r7, #0] + 8008800: 681b ldr r3, [r3, #0] + 8008802: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8008806: d102 bne.n 800880e { /* If INCLUDE_vTaskSuspend is set to 1 and the block time specified is the maximum block time then the task should block indefinitely, and therefore never time out. */ xReturn = pdFALSE; - 80046c0: 2300 movs r3, #0 - 80046c2: 61fb str r3, [r7, #28] - 80046c4: e023 b.n 800470e + 8008808: 2300 movs r3, #0 + 800880a: 61fb str r3, [r7, #28] + 800880c: e023 b.n 8008856 } else #endif if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */ - 80046c6: 687b ldr r3, [r7, #4] - 80046c8: 681a ldr r2, [r3, #0] - 80046ca: 4b15 ldr r3, [pc, #84] @ (8004720 ) - 80046cc: 681b ldr r3, [r3, #0] - 80046ce: 429a cmp r2, r3 - 80046d0: d007 beq.n 80046e2 - 80046d2: 687b ldr r3, [r7, #4] - 80046d4: 685b ldr r3, [r3, #4] - 80046d6: 69ba ldr r2, [r7, #24] - 80046d8: 429a cmp r2, r3 - 80046da: d302 bcc.n 80046e2 + 800880e: 687b ldr r3, [r7, #4] + 8008810: 681a ldr r2, [r3, #0] + 8008812: 4b15 ldr r3, [pc, #84] @ (8008868 ) + 8008814: 681b ldr r3, [r3, #0] + 8008816: 429a cmp r2, r3 + 8008818: d007 beq.n 800882a + 800881a: 687b ldr r3, [r7, #4] + 800881c: 685b ldr r3, [r3, #4] + 800881e: 69ba ldr r2, [r7, #24] + 8008820: 429a cmp r2, r3 + 8008822: d302 bcc.n 800882a /* The tick count is greater than the time at which vTaskSetTimeout() was called, but has also overflowed since vTaskSetTimeOut() was called. It must have wrapped all the way around and gone past again. This passed since vTaskSetTimeout() was called. */ xReturn = pdTRUE; - 80046dc: 2301 movs r3, #1 - 80046de: 61fb str r3, [r7, #28] - 80046e0: e015 b.n 800470e + 8008824: 2301 movs r3, #1 + 8008826: 61fb str r3, [r7, #28] + 8008828: e015 b.n 8008856 } else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */ - 80046e2: 683b ldr r3, [r7, #0] - 80046e4: 681b ldr r3, [r3, #0] - 80046e6: 697a ldr r2, [r7, #20] - 80046e8: 429a cmp r2, r3 - 80046ea: d20b bcs.n 8004704 + 800882a: 683b ldr r3, [r7, #0] + 800882c: 681b ldr r3, [r3, #0] + 800882e: 697a ldr r2, [r7, #20] + 8008830: 429a cmp r2, r3 + 8008832: d20b bcs.n 800884c { /* Not a genuine timeout. Adjust parameters for time remaining. */ *pxTicksToWait -= xElapsedTime; - 80046ec: 683b ldr r3, [r7, #0] - 80046ee: 681a ldr r2, [r3, #0] - 80046f0: 697b ldr r3, [r7, #20] - 80046f2: 1ad2 subs r2, r2, r3 - 80046f4: 683b ldr r3, [r7, #0] - 80046f6: 601a str r2, [r3, #0] + 8008834: 683b ldr r3, [r7, #0] + 8008836: 681a ldr r2, [r3, #0] + 8008838: 697b ldr r3, [r7, #20] + 800883a: 1ad2 subs r2, r2, r3 + 800883c: 683b ldr r3, [r7, #0] + 800883e: 601a str r2, [r3, #0] vTaskInternalSetTimeOutState( pxTimeOut ); - 80046f8: 6878 ldr r0, [r7, #4] - 80046fa: f7ff ff99 bl 8004630 + 8008840: 6878 ldr r0, [r7, #4] + 8008842: f7ff ff99 bl 8008778 xReturn = pdFALSE; - 80046fe: 2300 movs r3, #0 - 8004700: 61fb str r3, [r7, #28] - 8004702: e004 b.n 800470e + 8008846: 2300 movs r3, #0 + 8008848: 61fb str r3, [r7, #28] + 800884a: e004 b.n 8008856 } else { *pxTicksToWait = 0; - 8004704: 683b ldr r3, [r7, #0] - 8004706: 2200 movs r2, #0 - 8004708: 601a str r2, [r3, #0] + 800884c: 683b ldr r3, [r7, #0] + 800884e: 2200 movs r2, #0 + 8008850: 601a str r2, [r3, #0] xReturn = pdTRUE; - 800470a: 2301 movs r3, #1 - 800470c: 61fb str r3, [r7, #28] + 8008852: 2301 movs r3, #1 + 8008854: 61fb str r3, [r7, #28] } } taskEXIT_CRITICAL(); - 800470e: f000 fe8d bl 800542c + 8008856: f001 f851 bl 80098fc return xReturn; - 8004712: 69fb ldr r3, [r7, #28] + 800885a: 69fb ldr r3, [r7, #28] } - 8004714: 4618 mov r0, r3 - 8004716: 3720 adds r7, #32 - 8004718: 46bd mov sp, r7 - 800471a: bd80 pop {r7, pc} - 800471c: 20000e10 .word 0x20000e10 - 8004720: 20000e24 .word 0x20000e24 + 800885c: 4618 mov r0, r3 + 800885e: 3720 adds r7, #32 + 8008860: 46bd mov sp, r7 + 8008862: bd80 pop {r7, pc} + 8008864: 20000f98 .word 0x20000f98 + 8008868: 20000fac .word 0x20000fac -08004724 : +0800886c : /*-----------------------------------------------------------*/ void vTaskMissedYield( void ) { - 8004724: b480 push {r7} - 8004726: af00 add r7, sp, #0 + 800886c: b480 push {r7} + 800886e: af00 add r7, sp, #0 xYieldPending = pdTRUE; - 8004728: 4b03 ldr r3, [pc, #12] @ (8004738 ) - 800472a: 2201 movs r2, #1 - 800472c: 601a str r2, [r3, #0] + 8008870: 4b03 ldr r3, [pc, #12] @ (8008880 ) + 8008872: 2201 movs r2, #1 + 8008874: 601a str r2, [r3, #0] } - 800472e: bf00 nop - 8004730: 46bd mov sp, r7 - 8004732: f85d 7b04 ldr.w r7, [sp], #4 - 8004736: 4770 bx lr - 8004738: 20000e20 .word 0x20000e20 + 8008876: bf00 nop + 8008878: 46bd mov sp, r7 + 800887a: f85d 7b04 ldr.w r7, [sp], #4 + 800887e: 4770 bx lr + 8008880: 20000fa8 .word 0x20000fa8 -0800473c : +08008884 : * * void prvIdleTask( void *pvParameters ); * */ static portTASK_FUNCTION( prvIdleTask, pvParameters ) { - 800473c: b580 push {r7, lr} - 800473e: b082 sub sp, #8 - 8004740: af00 add r7, sp, #0 - 8004742: 6078 str r0, [r7, #4] + 8008884: b580 push {r7, lr} + 8008886: b082 sub sp, #8 + 8008888: af00 add r7, sp, #0 + 800888a: 6078 str r0, [r7, #4] for( ;; ) { /* See if any tasks have deleted themselves - if so then the idle task is responsible for freeing the deleted task's TCB and stack. */ prvCheckTasksWaitingTermination(); - 8004744: f000 f852 bl 80047ec + 800888c: f000 f852 bl 8008934 A critical region is not required here as we are just reading from the list, and an occasional incorrect value will not matter. If the ready list at the idle priority contains more than one task then a task other than the idle task is ready to execute. */ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 ) - 8004748: 4b06 ldr r3, [pc, #24] @ (8004764 ) - 800474a: 681b ldr r3, [r3, #0] - 800474c: 2b01 cmp r3, #1 - 800474e: d9f9 bls.n 8004744 + 8008890: 4b06 ldr r3, [pc, #24] @ (80088ac ) + 8008892: 681b ldr r3, [r3, #0] + 8008894: 2b01 cmp r3, #1 + 8008896: d9f9 bls.n 800888c { taskYIELD(); - 8004750: 4b05 ldr r3, [pc, #20] @ (8004768 ) - 8004752: f04f 5280 mov.w r2, #268435456 @ 0x10000000 - 8004756: 601a str r2, [r3, #0] - 8004758: f3bf 8f4f dsb sy - 800475c: f3bf 8f6f isb sy + 8008898: 4b05 ldr r3, [pc, #20] @ (80088b0 ) + 800889a: f04f 5280 mov.w r2, #268435456 @ 0x10000000 + 800889e: 601a str r2, [r3, #0] + 80088a0: f3bf 8f4f dsb sy + 80088a4: f3bf 8f6f isb sy prvCheckTasksWaitingTermination(); - 8004760: e7f0 b.n 8004744 - 8004762: bf00 nop - 8004764: 2000093c .word 0x2000093c - 8004768: e000ed04 .word 0xe000ed04 + 80088a8: e7f0 b.n 800888c + 80088aa: bf00 nop + 80088ac: 20000ac4 .word 0x20000ac4 + 80088b0: e000ed04 .word 0xe000ed04 -0800476c : +080088b4 : #endif /* portUSING_MPU_WRAPPERS */ /*-----------------------------------------------------------*/ static void prvInitialiseTaskLists( void ) { - 800476c: b580 push {r7, lr} - 800476e: b082 sub sp, #8 - 8004770: af00 add r7, sp, #0 + 80088b4: b580 push {r7, lr} + 80088b6: b082 sub sp, #8 + 80088b8: af00 add r7, sp, #0 UBaseType_t uxPriority; for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) - 8004772: 2300 movs r3, #0 - 8004774: 607b str r3, [r7, #4] - 8004776: e00c b.n 8004792 + 80088ba: 2300 movs r3, #0 + 80088bc: 607b str r3, [r7, #4] + 80088be: e00c b.n 80088da { vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) ); - 8004778: 687a ldr r2, [r7, #4] - 800477a: 4613 mov r3, r2 - 800477c: 009b lsls r3, r3, #2 - 800477e: 4413 add r3, r2 - 8004780: 009b lsls r3, r3, #2 - 8004782: 4a12 ldr r2, [pc, #72] @ (80047cc ) - 8004784: 4413 add r3, r2 - 8004786: 4618 mov r0, r3 - 8004788: f7fe fcae bl 80030e8 + 80088c0: 687a ldr r2, [r7, #4] + 80088c2: 4613 mov r3, r2 + 80088c4: 009b lsls r3, r3, #2 + 80088c6: 4413 add r3, r2 + 80088c8: 009b lsls r3, r3, #2 + 80088ca: 4a12 ldr r2, [pc, #72] @ (8008914 ) + 80088cc: 4413 add r3, r2 + 80088ce: 4618 mov r0, r3 + 80088d0: f7fe f9b2 bl 8006c38 for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) - 800478c: 687b ldr r3, [r7, #4] - 800478e: 3301 adds r3, #1 - 8004790: 607b str r3, [r7, #4] - 8004792: 687b ldr r3, [r7, #4] - 8004794: 2b37 cmp r3, #55 @ 0x37 - 8004796: d9ef bls.n 8004778 + 80088d4: 687b ldr r3, [r7, #4] + 80088d6: 3301 adds r3, #1 + 80088d8: 607b str r3, [r7, #4] + 80088da: 687b ldr r3, [r7, #4] + 80088dc: 2b37 cmp r3, #55 @ 0x37 + 80088de: d9ef bls.n 80088c0 } vListInitialise( &xDelayedTaskList1 ); - 8004798: 480d ldr r0, [pc, #52] @ (80047d0 ) - 800479a: f7fe fca5 bl 80030e8 + 80088e0: 480d ldr r0, [pc, #52] @ (8008918 ) + 80088e2: f7fe f9a9 bl 8006c38 vListInitialise( &xDelayedTaskList2 ); - 800479e: 480d ldr r0, [pc, #52] @ (80047d4 ) - 80047a0: f7fe fca2 bl 80030e8 + 80088e6: 480d ldr r0, [pc, #52] @ (800891c ) + 80088e8: f7fe f9a6 bl 8006c38 vListInitialise( &xPendingReadyList ); - 80047a4: 480c ldr r0, [pc, #48] @ (80047d8 ) - 80047a6: f7fe fc9f bl 80030e8 + 80088ec: 480c ldr r0, [pc, #48] @ (8008920 ) + 80088ee: f7fe f9a3 bl 8006c38 #if ( INCLUDE_vTaskDelete == 1 ) { vListInitialise( &xTasksWaitingTermination ); - 80047aa: 480c ldr r0, [pc, #48] @ (80047dc ) - 80047ac: f7fe fc9c bl 80030e8 + 80088f2: 480c ldr r0, [pc, #48] @ (8008924 ) + 80088f4: f7fe f9a0 bl 8006c38 } #endif /* INCLUDE_vTaskDelete */ #if ( INCLUDE_vTaskSuspend == 1 ) { vListInitialise( &xSuspendedTaskList ); - 80047b0: 480b ldr r0, [pc, #44] @ (80047e0 ) - 80047b2: f7fe fc99 bl 80030e8 + 80088f8: 480b ldr r0, [pc, #44] @ (8008928 ) + 80088fa: f7fe f99d bl 8006c38 } #endif /* INCLUDE_vTaskSuspend */ /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList using list2. */ pxDelayedTaskList = &xDelayedTaskList1; - 80047b6: 4b0b ldr r3, [pc, #44] @ (80047e4 ) - 80047b8: 4a05 ldr r2, [pc, #20] @ (80047d0 ) - 80047ba: 601a str r2, [r3, #0] + 80088fe: 4b0b ldr r3, [pc, #44] @ (800892c ) + 8008900: 4a05 ldr r2, [pc, #20] @ (8008918 ) + 8008902: 601a str r2, [r3, #0] pxOverflowDelayedTaskList = &xDelayedTaskList2; - 80047bc: 4b0a ldr r3, [pc, #40] @ (80047e8 ) - 80047be: 4a05 ldr r2, [pc, #20] @ (80047d4 ) - 80047c0: 601a str r2, [r3, #0] + 8008904: 4b0a ldr r3, [pc, #40] @ (8008930 ) + 8008906: 4a05 ldr r2, [pc, #20] @ (800891c ) + 8008908: 601a str r2, [r3, #0] } - 80047c2: bf00 nop - 80047c4: 3708 adds r7, #8 - 80047c6: 46bd mov sp, r7 - 80047c8: bd80 pop {r7, pc} - 80047ca: bf00 nop - 80047cc: 2000093c .word 0x2000093c - 80047d0: 20000d9c .word 0x20000d9c - 80047d4: 20000db0 .word 0x20000db0 - 80047d8: 20000dcc .word 0x20000dcc - 80047dc: 20000de0 .word 0x20000de0 - 80047e0: 20000df8 .word 0x20000df8 - 80047e4: 20000dc4 .word 0x20000dc4 - 80047e8: 20000dc8 .word 0x20000dc8 + 800890a: bf00 nop + 800890c: 3708 adds r7, #8 + 800890e: 46bd mov sp, r7 + 8008910: bd80 pop {r7, pc} + 8008912: bf00 nop + 8008914: 20000ac4 .word 0x20000ac4 + 8008918: 20000f24 .word 0x20000f24 + 800891c: 20000f38 .word 0x20000f38 + 8008920: 20000f54 .word 0x20000f54 + 8008924: 20000f68 .word 0x20000f68 + 8008928: 20000f80 .word 0x20000f80 + 800892c: 20000f4c .word 0x20000f4c + 8008930: 20000f50 .word 0x20000f50 -080047ec : +08008934 : /*-----------------------------------------------------------*/ static void prvCheckTasksWaitingTermination( void ) { - 80047ec: b580 push {r7, lr} - 80047ee: b082 sub sp, #8 - 80047f0: af00 add r7, sp, #0 + 8008934: b580 push {r7, lr} + 8008936: b082 sub sp, #8 + 8008938: af00 add r7, sp, #0 { TCB_t *pxTCB; /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL() being called too often in the idle task. */ while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) - 80047f2: e019 b.n 8004828 + 800893a: e019 b.n 8008970 { taskENTER_CRITICAL(); - 80047f4: f000 fde8 bl 80053c8 + 800893c: f000 ffac bl 8009898 { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ - 80047f8: 4b10 ldr r3, [pc, #64] @ (800483c ) - 80047fa: 68db ldr r3, [r3, #12] - 80047fc: 68db ldr r3, [r3, #12] - 80047fe: 607b str r3, [r7, #4] + 8008940: 4b10 ldr r3, [pc, #64] @ (8008984 ) + 8008942: 68db ldr r3, [r3, #12] + 8008944: 68db ldr r3, [r3, #12] + 8008946: 607b str r3, [r7, #4] ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); - 8004800: 687b ldr r3, [r7, #4] - 8004802: 3304 adds r3, #4 - 8004804: 4618 mov r0, r3 - 8004806: f7fe fcf9 bl 80031fc + 8008948: 687b ldr r3, [r7, #4] + 800894a: 3304 adds r3, #4 + 800894c: 4618 mov r0, r3 + 800894e: f7fe f9fd bl 8006d4c --uxCurrentNumberOfTasks; - 800480a: 4b0d ldr r3, [pc, #52] @ (8004840 ) - 800480c: 681b ldr r3, [r3, #0] - 800480e: 3b01 subs r3, #1 - 8004810: 4a0b ldr r2, [pc, #44] @ (8004840 ) - 8004812: 6013 str r3, [r2, #0] + 8008952: 4b0d ldr r3, [pc, #52] @ (8008988 ) + 8008954: 681b ldr r3, [r3, #0] + 8008956: 3b01 subs r3, #1 + 8008958: 4a0b ldr r2, [pc, #44] @ (8008988 ) + 800895a: 6013 str r3, [r2, #0] --uxDeletedTasksWaitingCleanUp; - 8004814: 4b0b ldr r3, [pc, #44] @ (8004844 ) - 8004816: 681b ldr r3, [r3, #0] - 8004818: 3b01 subs r3, #1 - 800481a: 4a0a ldr r2, [pc, #40] @ (8004844 ) - 800481c: 6013 str r3, [r2, #0] + 800895c: 4b0b ldr r3, [pc, #44] @ (800898c ) + 800895e: 681b ldr r3, [r3, #0] + 8008960: 3b01 subs r3, #1 + 8008962: 4a0a ldr r2, [pc, #40] @ (800898c ) + 8008964: 6013 str r3, [r2, #0] } taskEXIT_CRITICAL(); - 800481e: f000 fe05 bl 800542c + 8008966: f000 ffc9 bl 80098fc prvDeleteTCB( pxTCB ); - 8004822: 6878 ldr r0, [r7, #4] - 8004824: f000 f810 bl 8004848 + 800896a: 6878 ldr r0, [r7, #4] + 800896c: f000 f810 bl 8008990 while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) - 8004828: 4b06 ldr r3, [pc, #24] @ (8004844 ) - 800482a: 681b ldr r3, [r3, #0] - 800482c: 2b00 cmp r3, #0 - 800482e: d1e1 bne.n 80047f4 + 8008970: 4b06 ldr r3, [pc, #24] @ (800898c ) + 8008972: 681b ldr r3, [r3, #0] + 8008974: 2b00 cmp r3, #0 + 8008976: d1e1 bne.n 800893c } } #endif /* INCLUDE_vTaskDelete */ } - 8004830: bf00 nop - 8004832: bf00 nop - 8004834: 3708 adds r7, #8 - 8004836: 46bd mov sp, r7 - 8004838: bd80 pop {r7, pc} - 800483a: bf00 nop - 800483c: 20000de0 .word 0x20000de0 - 8004840: 20000e0c .word 0x20000e0c - 8004844: 20000df4 .word 0x20000df4 + 8008978: bf00 nop + 800897a: bf00 nop + 800897c: 3708 adds r7, #8 + 800897e: 46bd mov sp, r7 + 8008980: bd80 pop {r7, pc} + 8008982: bf00 nop + 8008984: 20000f68 .word 0x20000f68 + 8008988: 20000f94 .word 0x20000f94 + 800898c: 20000f7c .word 0x20000f7c -08004848 : +08008990 : /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelete == 1 ) static void prvDeleteTCB( TCB_t *pxTCB ) { - 8004848: b580 push {r7, lr} - 800484a: b084 sub sp, #16 - 800484c: af00 add r7, sp, #0 - 800484e: 6078 str r0, [r7, #4] + 8008990: b580 push {r7, lr} + 8008992: b084 sub sp, #16 + 8008994: af00 add r7, sp, #0 + 8008996: 6078 str r0, [r7, #4] to the task to free any memory allocated at the application level. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ #if ( configUSE_NEWLIB_REENTRANT == 1 ) { _reclaim_reent( &( pxTCB->xNewLib_reent ) ); - 8004850: 687b ldr r3, [r7, #4] - 8004852: 3354 adds r3, #84 @ 0x54 - 8004854: 4618 mov r0, r3 - 8004856: f001 f8ff bl 8005a58 <_reclaim_reent> + 8008998: 687b ldr r3, [r7, #4] + 800899a: 3354 adds r3, #84 @ 0x54 + 800899c: 4618 mov r0, r3 + 800899e: f001 fac3 bl 8009f28 <_reclaim_reent> #elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* The task could have been allocated statically or dynamically, so check what was statically allocated before trying to free the memory. */ if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ) - 800485a: 687b ldr r3, [r7, #4] - 800485c: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 - 8004860: 2b00 cmp r3, #0 - 8004862: d108 bne.n 8004876 + 80089a2: 687b ldr r3, [r7, #4] + 80089a4: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 + 80089a8: 2b00 cmp r3, #0 + 80089aa: d108 bne.n 80089be { /* Both the stack and TCB were allocated dynamically, so both must be freed. */ vPortFree( pxTCB->pxStack ); - 8004864: 687b ldr r3, [r7, #4] - 8004866: 6b1b ldr r3, [r3, #48] @ 0x30 - 8004868: 4618 mov r0, r3 - 800486a: f000 ff9d bl 80057a8 + 80089ac: 687b ldr r3, [r7, #4] + 80089ae: 6b1b ldr r3, [r3, #48] @ 0x30 + 80089b0: 4618 mov r0, r3 + 80089b2: f001 f961 bl 8009c78 vPortFree( pxTCB ); - 800486e: 6878 ldr r0, [r7, #4] - 8004870: f000 ff9a bl 80057a8 + 80089b6: 6878 ldr r0, [r7, #4] + 80089b8: f001 f95e bl 8009c78 configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); mtCOVERAGE_TEST_MARKER(); } } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ } - 8004874: e019 b.n 80048aa + 80089bc: e019 b.n 80089f2 else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY ) - 8004876: 687b ldr r3, [r7, #4] - 8004878: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 - 800487c: 2b01 cmp r3, #1 - 800487e: d103 bne.n 8004888 + 80089be: 687b ldr r3, [r7, #4] + 80089c0: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 + 80089c4: 2b01 cmp r3, #1 + 80089c6: d103 bne.n 80089d0 vPortFree( pxTCB ); - 8004880: 6878 ldr r0, [r7, #4] - 8004882: f000 ff91 bl 80057a8 + 80089c8: 6878 ldr r0, [r7, #4] + 80089ca: f001 f955 bl 8009c78 } - 8004886: e010 b.n 80048aa + 80089ce: e010 b.n 80089f2 configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); - 8004888: 687b ldr r3, [r7, #4] - 800488a: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 - 800488e: 2b02 cmp r3, #2 - 8004890: d00b beq.n 80048aa + 80089d0: 687b ldr r3, [r7, #4] + 80089d2: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 + 80089d6: 2b02 cmp r3, #2 + 80089d8: d00b beq.n 80089f2 __asm volatile - 8004892: f04f 0350 mov.w r3, #80 @ 0x50 - 8004896: f383 8811 msr BASEPRI, r3 - 800489a: f3bf 8f6f isb sy - 800489e: f3bf 8f4f dsb sy - 80048a2: 60fb str r3, [r7, #12] + 80089da: f04f 0350 mov.w r3, #80 @ 0x50 + 80089de: f383 8811 msr BASEPRI, r3 + 80089e2: f3bf 8f6f isb sy + 80089e6: f3bf 8f4f dsb sy + 80089ea: 60fb str r3, [r7, #12] } - 80048a4: bf00 nop - 80048a6: bf00 nop - 80048a8: e7fd b.n 80048a6 + 80089ec: bf00 nop + 80089ee: bf00 nop + 80089f0: e7fd b.n 80089ee } - 80048aa: bf00 nop - 80048ac: 3710 adds r7, #16 - 80048ae: 46bd mov sp, r7 - 80048b0: bd80 pop {r7, pc} + 80089f2: bf00 nop + 80089f4: 3710 adds r7, #16 + 80089f6: 46bd mov sp, r7 + 80089f8: bd80 pop {r7, pc} ... -080048b4 : +080089fc : #endif /* INCLUDE_vTaskDelete */ /*-----------------------------------------------------------*/ static void prvResetNextTaskUnblockTime( void ) { - 80048b4: b480 push {r7} - 80048b6: b083 sub sp, #12 - 80048b8: af00 add r7, sp, #0 + 80089fc: b480 push {r7} + 80089fe: b083 sub sp, #12 + 8008a00: af00 add r7, sp, #0 TCB_t *pxTCB; if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) - 80048ba: 4b0c ldr r3, [pc, #48] @ (80048ec ) - 80048bc: 681b ldr r3, [r3, #0] - 80048be: 681b ldr r3, [r3, #0] - 80048c0: 2b00 cmp r3, #0 - 80048c2: d104 bne.n 80048ce + 8008a02: 4b0c ldr r3, [pc, #48] @ (8008a34 ) + 8008a04: 681b ldr r3, [r3, #0] + 8008a06: 681b ldr r3, [r3, #0] + 8008a08: 2b00 cmp r3, #0 + 8008a0a: d104 bne.n 8008a16 { /* The new current delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass until there is an item in the delayed list. */ xNextTaskUnblockTime = portMAX_DELAY; - 80048c4: 4b0a ldr r3, [pc, #40] @ (80048f0 ) - 80048c6: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff - 80048ca: 601a str r2, [r3, #0] + 8008a0c: 4b0a ldr r3, [pc, #40] @ (8008a38 ) + 8008a0e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8008a12: 601a str r2, [r3, #0] which the task at the head of the delayed list should be removed from the Blocked state. */ ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); } } - 80048cc: e008 b.n 80048e0 + 8008a14: e008 b.n 8008a28 ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ - 80048ce: 4b07 ldr r3, [pc, #28] @ (80048ec ) - 80048d0: 681b ldr r3, [r3, #0] - 80048d2: 68db ldr r3, [r3, #12] - 80048d4: 68db ldr r3, [r3, #12] - 80048d6: 607b str r3, [r7, #4] + 8008a16: 4b07 ldr r3, [pc, #28] @ (8008a34 ) + 8008a18: 681b ldr r3, [r3, #0] + 8008a1a: 68db ldr r3, [r3, #12] + 8008a1c: 68db ldr r3, [r3, #12] + 8008a1e: 607b str r3, [r7, #4] xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); - 80048d8: 687b ldr r3, [r7, #4] - 80048da: 685b ldr r3, [r3, #4] - 80048dc: 4a04 ldr r2, [pc, #16] @ (80048f0 ) - 80048de: 6013 str r3, [r2, #0] + 8008a20: 687b ldr r3, [r7, #4] + 8008a22: 685b ldr r3, [r3, #4] + 8008a24: 4a04 ldr r2, [pc, #16] @ (8008a38 ) + 8008a26: 6013 str r3, [r2, #0] } - 80048e0: bf00 nop - 80048e2: 370c adds r7, #12 - 80048e4: 46bd mov sp, r7 - 80048e6: f85d 7b04 ldr.w r7, [sp], #4 - 80048ea: 4770 bx lr - 80048ec: 20000dc4 .word 0x20000dc4 - 80048f0: 20000e2c .word 0x20000e2c + 8008a28: bf00 nop + 8008a2a: 370c adds r7, #12 + 8008a2c: 46bd mov sp, r7 + 8008a2e: f85d 7b04 ldr.w r7, [sp], #4 + 8008a32: 4770 bx lr + 8008a34: 20000f4c .word 0x20000f4c + 8008a38: 20000fb4 .word 0x20000fb4 -080048f4 : +08008a3c : /*-----------------------------------------------------------*/ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) BaseType_t xTaskGetSchedulerState( void ) { - 80048f4: b480 push {r7} - 80048f6: b083 sub sp, #12 - 80048f8: af00 add r7, sp, #0 + 8008a3c: b480 push {r7} + 8008a3e: b083 sub sp, #12 + 8008a40: af00 add r7, sp, #0 BaseType_t xReturn; if( xSchedulerRunning == pdFALSE ) - 80048fa: 4b0b ldr r3, [pc, #44] @ (8004928 ) - 80048fc: 681b ldr r3, [r3, #0] - 80048fe: 2b00 cmp r3, #0 - 8004900: d102 bne.n 8004908 + 8008a42: 4b0b ldr r3, [pc, #44] @ (8008a70 ) + 8008a44: 681b ldr r3, [r3, #0] + 8008a46: 2b00 cmp r3, #0 + 8008a48: d102 bne.n 8008a50 { xReturn = taskSCHEDULER_NOT_STARTED; - 8004902: 2301 movs r3, #1 - 8004904: 607b str r3, [r7, #4] - 8004906: e008 b.n 800491a + 8008a4a: 2301 movs r3, #1 + 8008a4c: 607b str r3, [r7, #4] + 8008a4e: e008 b.n 8008a62 } else { if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) - 8004908: 4b08 ldr r3, [pc, #32] @ (800492c ) - 800490a: 681b ldr r3, [r3, #0] - 800490c: 2b00 cmp r3, #0 - 800490e: d102 bne.n 8004916 + 8008a50: 4b08 ldr r3, [pc, #32] @ (8008a74 ) + 8008a52: 681b ldr r3, [r3, #0] + 8008a54: 2b00 cmp r3, #0 + 8008a56: d102 bne.n 8008a5e { xReturn = taskSCHEDULER_RUNNING; - 8004910: 2302 movs r3, #2 - 8004912: 607b str r3, [r7, #4] - 8004914: e001 b.n 800491a + 8008a58: 2302 movs r3, #2 + 8008a5a: 607b str r3, [r7, #4] + 8008a5c: e001 b.n 8008a62 } else { xReturn = taskSCHEDULER_SUSPENDED; - 8004916: 2300 movs r3, #0 - 8004918: 607b str r3, [r7, #4] + 8008a5e: 2300 movs r3, #0 + 8008a60: 607b str r3, [r7, #4] } } return xReturn; - 800491a: 687b ldr r3, [r7, #4] + 8008a62: 687b ldr r3, [r7, #4] } - 800491c: 4618 mov r0, r3 - 800491e: 370c adds r7, #12 - 8004920: 46bd mov sp, r7 - 8004922: f85d 7b04 ldr.w r7, [sp], #4 - 8004926: 4770 bx lr - 8004928: 20000e18 .word 0x20000e18 - 800492c: 20000e34 .word 0x20000e34 + 8008a64: 4618 mov r0, r3 + 8008a66: 370c adds r7, #12 + 8008a68: 46bd mov sp, r7 + 8008a6a: f85d 7b04 ldr.w r7, [sp], #4 + 8008a6e: 4770 bx lr + 8008a70: 20000fa0 .word 0x20000fa0 + 8008a74: 20000fbc .word 0x20000fbc -08004930 : +08008a78 : +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) + { + 8008a78: b580 push {r7, lr} + 8008a7a: b084 sub sp, #16 + 8008a7c: af00 add r7, sp, #0 + 8008a7e: 6078 str r0, [r7, #4] + TCB_t * const pxMutexHolderTCB = pxMutexHolder; + 8008a80: 687b ldr r3, [r7, #4] + 8008a82: 60bb str r3, [r7, #8] + BaseType_t xReturn = pdFALSE; + 8008a84: 2300 movs r3, #0 + 8008a86: 60fb str r3, [r7, #12] + + /* If the mutex was given back by an interrupt while the queue was + locked then the mutex holder might now be NULL. _RB_ Is this still + needed as interrupts can no longer use mutexes? */ + if( pxMutexHolder != NULL ) + 8008a88: 687b ldr r3, [r7, #4] + 8008a8a: 2b00 cmp r3, #0 + 8008a8c: d051 beq.n 8008b32 + { + /* If the holder of the mutex has a priority below the priority of + the task attempting to obtain the mutex then it will temporarily + inherit the priority of the task attempting to obtain the mutex. */ + if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority ) + 8008a8e: 68bb ldr r3, [r7, #8] + 8008a90: 6ada ldr r2, [r3, #44] @ 0x2c + 8008a92: 4b2a ldr r3, [pc, #168] @ (8008b3c ) + 8008a94: 681b ldr r3, [r3, #0] + 8008a96: 6adb ldr r3, [r3, #44] @ 0x2c + 8008a98: 429a cmp r2, r3 + 8008a9a: d241 bcs.n 8008b20 + { + /* Adjust the mutex holder state to account for its new + priority. Only reset the event list item value if the value is + not being used for anything else. */ + if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) + 8008a9c: 68bb ldr r3, [r7, #8] + 8008a9e: 699b ldr r3, [r3, #24] + 8008aa0: 2b00 cmp r3, #0 + 8008aa2: db06 blt.n 8008ab2 + { + listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 8008aa4: 4b25 ldr r3, [pc, #148] @ (8008b3c ) + 8008aa6: 681b ldr r3, [r3, #0] + 8008aa8: 6adb ldr r3, [r3, #44] @ 0x2c + 8008aaa: f1c3 0238 rsb r2, r3, #56 @ 0x38 + 8008aae: 68bb ldr r3, [r7, #8] + 8008ab0: 619a str r2, [r3, #24] + mtCOVERAGE_TEST_MARKER(); + } + + /* If the task being modified is in the ready state it will need + to be moved into a new list. */ + if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE ) + 8008ab2: 68bb ldr r3, [r7, #8] + 8008ab4: 6959 ldr r1, [r3, #20] + 8008ab6: 68bb ldr r3, [r7, #8] + 8008ab8: 6ada ldr r2, [r3, #44] @ 0x2c + 8008aba: 4613 mov r3, r2 + 8008abc: 009b lsls r3, r3, #2 + 8008abe: 4413 add r3, r2 + 8008ac0: 009b lsls r3, r3, #2 + 8008ac2: 4a1f ldr r2, [pc, #124] @ (8008b40 ) + 8008ac4: 4413 add r3, r2 + 8008ac6: 4299 cmp r1, r3 + 8008ac8: d122 bne.n 8008b10 + { + if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + 8008aca: 68bb ldr r3, [r7, #8] + 8008acc: 3304 adds r3, #4 + 8008ace: 4618 mov r0, r3 + 8008ad0: f7fe f93c bl 8006d4c + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Inherit the priority before being moved into the new list. */ + pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; + 8008ad4: 4b19 ldr r3, [pc, #100] @ (8008b3c ) + 8008ad6: 681b ldr r3, [r3, #0] + 8008ad8: 6ada ldr r2, [r3, #44] @ 0x2c + 8008ada: 68bb ldr r3, [r7, #8] + 8008adc: 62da str r2, [r3, #44] @ 0x2c + prvAddTaskToReadyList( pxMutexHolderTCB ); + 8008ade: 68bb ldr r3, [r7, #8] + 8008ae0: 6ada ldr r2, [r3, #44] @ 0x2c + 8008ae2: 4b18 ldr r3, [pc, #96] @ (8008b44 ) + 8008ae4: 681b ldr r3, [r3, #0] + 8008ae6: 429a cmp r2, r3 + 8008ae8: d903 bls.n 8008af2 + 8008aea: 68bb ldr r3, [r7, #8] + 8008aec: 6adb ldr r3, [r3, #44] @ 0x2c + 8008aee: 4a15 ldr r2, [pc, #84] @ (8008b44 ) + 8008af0: 6013 str r3, [r2, #0] + 8008af2: 68bb ldr r3, [r7, #8] + 8008af4: 6ada ldr r2, [r3, #44] @ 0x2c + 8008af6: 4613 mov r3, r2 + 8008af8: 009b lsls r3, r3, #2 + 8008afa: 4413 add r3, r2 + 8008afc: 009b lsls r3, r3, #2 + 8008afe: 4a10 ldr r2, [pc, #64] @ (8008b40 ) + 8008b00: 441a add r2, r3 + 8008b02: 68bb ldr r3, [r7, #8] + 8008b04: 3304 adds r3, #4 + 8008b06: 4619 mov r1, r3 + 8008b08: 4610 mov r0, r2 + 8008b0a: f7fe f8c2 bl 8006c92 + 8008b0e: e004 b.n 8008b1a + } + else + { + /* Just inherit the priority. */ + pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; + 8008b10: 4b0a ldr r3, [pc, #40] @ (8008b3c ) + 8008b12: 681b ldr r3, [r3, #0] + 8008b14: 6ada ldr r2, [r3, #44] @ 0x2c + 8008b16: 68bb ldr r3, [r7, #8] + 8008b18: 62da str r2, [r3, #44] @ 0x2c + } + + traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority ); + + /* Inheritance occurred. */ + xReturn = pdTRUE; + 8008b1a: 2301 movs r3, #1 + 8008b1c: 60fb str r3, [r7, #12] + 8008b1e: e008 b.n 8008b32 + } + else + { + if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority ) + 8008b20: 68bb ldr r3, [r7, #8] + 8008b22: 6cda ldr r2, [r3, #76] @ 0x4c + 8008b24: 4b05 ldr r3, [pc, #20] @ (8008b3c ) + 8008b26: 681b ldr r3, [r3, #0] + 8008b28: 6adb ldr r3, [r3, #44] @ 0x2c + 8008b2a: 429a cmp r2, r3 + 8008b2c: d201 bcs.n 8008b32 + current priority of the mutex holder is not lower than the + priority of the task attempting to take the mutex. + Therefore the mutex holder must have already inherited a + priority, but inheritance would have occurred if that had + not been the case. */ + xReturn = pdTRUE; + 8008b2e: 2301 movs r3, #1 + 8008b30: 60fb str r3, [r7, #12] + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; + 8008b32: 68fb ldr r3, [r7, #12] + } + 8008b34: 4618 mov r0, r3 + 8008b36: 3710 adds r7, #16 + 8008b38: 46bd mov sp, r7 + 8008b3a: bd80 pop {r7, pc} + 8008b3c: 20000ac0 .word 0x20000ac0 + 8008b40: 20000ac4 .word 0x20000ac4 + 8008b44: 20000f9c .word 0x20000f9c + +08008b48 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) { - 8004930: b580 push {r7, lr} - 8004932: b086 sub sp, #24 - 8004934: af00 add r7, sp, #0 - 8004936: 6078 str r0, [r7, #4] + 8008b48: b580 push {r7, lr} + 8008b4a: b086 sub sp, #24 + 8008b4c: af00 add r7, sp, #0 + 8008b4e: 6078 str r0, [r7, #4] TCB_t * const pxTCB = pxMutexHolder; - 8004938: 687b ldr r3, [r7, #4] - 800493a: 613b str r3, [r7, #16] + 8008b50: 687b ldr r3, [r7, #4] + 8008b52: 613b str r3, [r7, #16] BaseType_t xReturn = pdFALSE; - 800493c: 2300 movs r3, #0 - 800493e: 617b str r3, [r7, #20] + 8008b54: 2300 movs r3, #0 + 8008b56: 617b str r3, [r7, #20] if( pxMutexHolder != NULL ) - 8004940: 687b ldr r3, [r7, #4] - 8004942: 2b00 cmp r3, #0 - 8004944: d058 beq.n 80049f8 + 8008b58: 687b ldr r3, [r7, #4] + 8008b5a: 2b00 cmp r3, #0 + 8008b5c: d058 beq.n 8008c10 { /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. */ configASSERT( pxTCB == pxCurrentTCB ); - 8004946: 4b2f ldr r3, [pc, #188] @ (8004a04 ) - 8004948: 681b ldr r3, [r3, #0] - 800494a: 693a ldr r2, [r7, #16] - 800494c: 429a cmp r2, r3 - 800494e: d00b beq.n 8004968 + 8008b5e: 4b2f ldr r3, [pc, #188] @ (8008c1c ) + 8008b60: 681b ldr r3, [r3, #0] + 8008b62: 693a ldr r2, [r7, #16] + 8008b64: 429a cmp r2, r3 + 8008b66: d00b beq.n 8008b80 __asm volatile - 8004950: f04f 0350 mov.w r3, #80 @ 0x50 - 8004954: f383 8811 msr BASEPRI, r3 - 8004958: f3bf 8f6f isb sy - 800495c: f3bf 8f4f dsb sy - 8004960: 60fb str r3, [r7, #12] + 8008b68: f04f 0350 mov.w r3, #80 @ 0x50 + 8008b6c: f383 8811 msr BASEPRI, r3 + 8008b70: f3bf 8f6f isb sy + 8008b74: f3bf 8f4f dsb sy + 8008b78: 60fb str r3, [r7, #12] } - 8004962: bf00 nop - 8004964: bf00 nop - 8004966: e7fd b.n 8004964 + 8008b7a: bf00 nop + 8008b7c: bf00 nop + 8008b7e: e7fd b.n 8008b7c configASSERT( pxTCB->uxMutexesHeld ); - 8004968: 693b ldr r3, [r7, #16] - 800496a: 6d1b ldr r3, [r3, #80] @ 0x50 - 800496c: 2b00 cmp r3, #0 - 800496e: d10b bne.n 8004988 + 8008b80: 693b ldr r3, [r7, #16] + 8008b82: 6d1b ldr r3, [r3, #80] @ 0x50 + 8008b84: 2b00 cmp r3, #0 + 8008b86: d10b bne.n 8008ba0 __asm volatile - 8004970: f04f 0350 mov.w r3, #80 @ 0x50 - 8004974: f383 8811 msr BASEPRI, r3 - 8004978: f3bf 8f6f isb sy - 800497c: f3bf 8f4f dsb sy - 8004980: 60bb str r3, [r7, #8] + 8008b88: f04f 0350 mov.w r3, #80 @ 0x50 + 8008b8c: f383 8811 msr BASEPRI, r3 + 8008b90: f3bf 8f6f isb sy + 8008b94: f3bf 8f4f dsb sy + 8008b98: 60bb str r3, [r7, #8] } - 8004982: bf00 nop - 8004984: bf00 nop - 8004986: e7fd b.n 8004984 + 8008b9a: bf00 nop + 8008b9c: bf00 nop + 8008b9e: e7fd b.n 8008b9c ( pxTCB->uxMutexesHeld )--; - 8004988: 693b ldr r3, [r7, #16] - 800498a: 6d1b ldr r3, [r3, #80] @ 0x50 - 800498c: 1e5a subs r2, r3, #1 - 800498e: 693b ldr r3, [r7, #16] - 8004990: 651a str r2, [r3, #80] @ 0x50 + 8008ba0: 693b ldr r3, [r7, #16] + 8008ba2: 6d1b ldr r3, [r3, #80] @ 0x50 + 8008ba4: 1e5a subs r2, r3, #1 + 8008ba6: 693b ldr r3, [r7, #16] + 8008ba8: 651a str r2, [r3, #80] @ 0x50 /* Has the holder of the mutex inherited the priority of another task? */ if( pxTCB->uxPriority != pxTCB->uxBasePriority ) - 8004992: 693b ldr r3, [r7, #16] - 8004994: 6ada ldr r2, [r3, #44] @ 0x2c - 8004996: 693b ldr r3, [r7, #16] - 8004998: 6cdb ldr r3, [r3, #76] @ 0x4c - 800499a: 429a cmp r2, r3 - 800499c: d02c beq.n 80049f8 + 8008baa: 693b ldr r3, [r7, #16] + 8008bac: 6ada ldr r2, [r3, #44] @ 0x2c + 8008bae: 693b ldr r3, [r7, #16] + 8008bb0: 6cdb ldr r3, [r3, #76] @ 0x4c + 8008bb2: 429a cmp r2, r3 + 8008bb4: d02c beq.n 8008c10 { /* Only disinherit if no other mutexes are held. */ if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 ) - 800499e: 693b ldr r3, [r7, #16] - 80049a0: 6d1b ldr r3, [r3, #80] @ 0x50 - 80049a2: 2b00 cmp r3, #0 - 80049a4: d128 bne.n 80049f8 + 8008bb6: 693b ldr r3, [r7, #16] + 8008bb8: 6d1b ldr r3, [r3, #80] @ 0x50 + 8008bba: 2b00 cmp r3, #0 + 8008bbc: d128 bne.n 8008c10 /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. Remove the holding task from the ready/delayed list. */ if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) - 80049a6: 693b ldr r3, [r7, #16] - 80049a8: 3304 adds r3, #4 - 80049aa: 4618 mov r0, r3 - 80049ac: f7fe fc26 bl 80031fc + 8008bbe: 693b ldr r3, [r7, #16] + 8008bc0: 3304 adds r3, #4 + 8008bc2: 4618 mov r0, r3 + 8008bc4: f7fe f8c2 bl 8006d4c } /* Disinherit the priority before adding the task into the new ready list. */ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); pxTCB->uxPriority = pxTCB->uxBasePriority; - 80049b0: 693b ldr r3, [r7, #16] - 80049b2: 6cda ldr r2, [r3, #76] @ 0x4c - 80049b4: 693b ldr r3, [r7, #16] - 80049b6: 62da str r2, [r3, #44] @ 0x2c + 8008bc8: 693b ldr r3, [r7, #16] + 8008bca: 6cda ldr r2, [r3, #76] @ 0x4c + 8008bcc: 693b ldr r3, [r7, #16] + 8008bce: 62da str r2, [r3, #44] @ 0x2c /* Reset the event list item value. It cannot be in use for any other purpose if this task is running, and it must be running to give back the mutex. */ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ - 80049b8: 693b ldr r3, [r7, #16] - 80049ba: 6adb ldr r3, [r3, #44] @ 0x2c - 80049bc: f1c3 0238 rsb r2, r3, #56 @ 0x38 - 80049c0: 693b ldr r3, [r7, #16] - 80049c2: 619a str r2, [r3, #24] + 8008bd0: 693b ldr r3, [r7, #16] + 8008bd2: 6adb ldr r3, [r3, #44] @ 0x2c + 8008bd4: f1c3 0238 rsb r2, r3, #56 @ 0x38 + 8008bd8: 693b ldr r3, [r7, #16] + 8008bda: 619a str r2, [r3, #24] prvAddTaskToReadyList( pxTCB ); - 80049c4: 693b ldr r3, [r7, #16] - 80049c6: 6ada ldr r2, [r3, #44] @ 0x2c - 80049c8: 4b0f ldr r3, [pc, #60] @ (8004a08 ) - 80049ca: 681b ldr r3, [r3, #0] - 80049cc: 429a cmp r2, r3 - 80049ce: d903 bls.n 80049d8 - 80049d0: 693b ldr r3, [r7, #16] - 80049d2: 6adb ldr r3, [r3, #44] @ 0x2c - 80049d4: 4a0c ldr r2, [pc, #48] @ (8004a08 ) - 80049d6: 6013 str r3, [r2, #0] - 80049d8: 693b ldr r3, [r7, #16] - 80049da: 6ada ldr r2, [r3, #44] @ 0x2c - 80049dc: 4613 mov r3, r2 - 80049de: 009b lsls r3, r3, #2 - 80049e0: 4413 add r3, r2 - 80049e2: 009b lsls r3, r3, #2 - 80049e4: 4a09 ldr r2, [pc, #36] @ (8004a0c ) - 80049e6: 441a add r2, r3 - 80049e8: 693b ldr r3, [r7, #16] - 80049ea: 3304 adds r3, #4 - 80049ec: 4619 mov r1, r3 - 80049ee: 4610 mov r0, r2 - 80049f0: f7fe fba7 bl 8003142 + 8008bdc: 693b ldr r3, [r7, #16] + 8008bde: 6ada ldr r2, [r3, #44] @ 0x2c + 8008be0: 4b0f ldr r3, [pc, #60] @ (8008c20 ) + 8008be2: 681b ldr r3, [r3, #0] + 8008be4: 429a cmp r2, r3 + 8008be6: d903 bls.n 8008bf0 + 8008be8: 693b ldr r3, [r7, #16] + 8008bea: 6adb ldr r3, [r3, #44] @ 0x2c + 8008bec: 4a0c ldr r2, [pc, #48] @ (8008c20 ) + 8008bee: 6013 str r3, [r2, #0] + 8008bf0: 693b ldr r3, [r7, #16] + 8008bf2: 6ada ldr r2, [r3, #44] @ 0x2c + 8008bf4: 4613 mov r3, r2 + 8008bf6: 009b lsls r3, r3, #2 + 8008bf8: 4413 add r3, r2 + 8008bfa: 009b lsls r3, r3, #2 + 8008bfc: 4a09 ldr r2, [pc, #36] @ (8008c24 ) + 8008bfe: 441a add r2, r3 + 8008c00: 693b ldr r3, [r7, #16] + 8008c02: 3304 adds r3, #4 + 8008c04: 4619 mov r1, r3 + 8008c06: 4610 mov r0, r2 + 8008c08: f7fe f843 bl 8006c92 in an order different to that in which they were taken. If a context switch did not occur when the first mutex was returned, even if a task was waiting on it, then a context switch should occur when the last mutex is returned whether a task is waiting on it or not. */ xReturn = pdTRUE; - 80049f4: 2301 movs r3, #1 - 80049f6: 617b str r3, [r7, #20] + 8008c0c: 2301 movs r3, #1 + 8008c0e: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } return xReturn; - 80049f8: 697b ldr r3, [r7, #20] + 8008c10: 697b ldr r3, [r7, #20] } - 80049fa: 4618 mov r0, r3 - 80049fc: 3718 adds r7, #24 - 80049fe: 46bd mov sp, r7 - 8004a00: bd80 pop {r7, pc} - 8004a02: bf00 nop - 8004a04: 20000938 .word 0x20000938 - 8004a08: 20000e14 .word 0x20000e14 - 8004a0c: 2000093c .word 0x2000093c + 8008c12: 4618 mov r0, r3 + 8008c14: 3718 adds r7, #24 + 8008c16: 46bd mov sp, r7 + 8008c18: bd80 pop {r7, pc} + 8008c1a: bf00 nop + 8008c1c: 20000ac0 .word 0x20000ac0 + 8008c20: 20000f9c .word 0x20000f9c + 8008c24: 20000ac4 .word 0x20000ac4 -08004a10 : +08008c28 : +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) + { + 8008c28: b580 push {r7, lr} + 8008c2a: b088 sub sp, #32 + 8008c2c: af00 add r7, sp, #0 + 8008c2e: 6078 str r0, [r7, #4] + 8008c30: 6039 str r1, [r7, #0] + TCB_t * const pxTCB = pxMutexHolder; + 8008c32: 687b ldr r3, [r7, #4] + 8008c34: 61bb str r3, [r7, #24] + UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse; + const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1; + 8008c36: 2301 movs r3, #1 + 8008c38: 617b str r3, [r7, #20] + + if( pxMutexHolder != NULL ) + 8008c3a: 687b ldr r3, [r7, #4] + 8008c3c: 2b00 cmp r3, #0 + 8008c3e: d06c beq.n 8008d1a + { + /* If pxMutexHolder is not NULL then the holder must hold at least + one mutex. */ + configASSERT( pxTCB->uxMutexesHeld ); + 8008c40: 69bb ldr r3, [r7, #24] + 8008c42: 6d1b ldr r3, [r3, #80] @ 0x50 + 8008c44: 2b00 cmp r3, #0 + 8008c46: d10b bne.n 8008c60 + __asm volatile + 8008c48: f04f 0350 mov.w r3, #80 @ 0x50 + 8008c4c: f383 8811 msr BASEPRI, r3 + 8008c50: f3bf 8f6f isb sy + 8008c54: f3bf 8f4f dsb sy + 8008c58: 60fb str r3, [r7, #12] +} + 8008c5a: bf00 nop + 8008c5c: bf00 nop + 8008c5e: e7fd b.n 8008c5c + + /* Determine the priority to which the priority of the task that + holds the mutex should be set. This will be the greater of the + holding task's base priority and the priority of the highest + priority task that is waiting to obtain the mutex. */ + if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask ) + 8008c60: 69bb ldr r3, [r7, #24] + 8008c62: 6cdb ldr r3, [r3, #76] @ 0x4c + 8008c64: 683a ldr r2, [r7, #0] + 8008c66: 429a cmp r2, r3 + 8008c68: d902 bls.n 8008c70 + { + uxPriorityToUse = uxHighestPriorityWaitingTask; + 8008c6a: 683b ldr r3, [r7, #0] + 8008c6c: 61fb str r3, [r7, #28] + 8008c6e: e002 b.n 8008c76 + } + else + { + uxPriorityToUse = pxTCB->uxBasePriority; + 8008c70: 69bb ldr r3, [r7, #24] + 8008c72: 6cdb ldr r3, [r3, #76] @ 0x4c + 8008c74: 61fb str r3, [r7, #28] + } + + /* Does the priority need to change? */ + if( pxTCB->uxPriority != uxPriorityToUse ) + 8008c76: 69bb ldr r3, [r7, #24] + 8008c78: 6adb ldr r3, [r3, #44] @ 0x2c + 8008c7a: 69fa ldr r2, [r7, #28] + 8008c7c: 429a cmp r2, r3 + 8008c7e: d04c beq.n 8008d1a + { + /* Only disinherit if no other mutexes are held. This is a + simplification in the priority inheritance implementation. If + the task that holds the mutex is also holding other mutexes then + the other mutexes may have caused the priority inheritance. */ + if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld ) + 8008c80: 69bb ldr r3, [r7, #24] + 8008c82: 6d1b ldr r3, [r3, #80] @ 0x50 + 8008c84: 697a ldr r2, [r7, #20] + 8008c86: 429a cmp r2, r3 + 8008c88: d147 bne.n 8008d1a + { + /* If a task has timed out because it already holds the + mutex it was trying to obtain then it cannot of inherited + its own priority. */ + configASSERT( pxTCB != pxCurrentTCB ); + 8008c8a: 4b26 ldr r3, [pc, #152] @ (8008d24 ) + 8008c8c: 681b ldr r3, [r3, #0] + 8008c8e: 69ba ldr r2, [r7, #24] + 8008c90: 429a cmp r2, r3 + 8008c92: d10b bne.n 8008cac + __asm volatile + 8008c94: f04f 0350 mov.w r3, #80 @ 0x50 + 8008c98: f383 8811 msr BASEPRI, r3 + 8008c9c: f3bf 8f6f isb sy + 8008ca0: f3bf 8f4f dsb sy + 8008ca4: 60bb str r3, [r7, #8] +} + 8008ca6: bf00 nop + 8008ca8: bf00 nop + 8008caa: e7fd b.n 8008ca8 + + /* Disinherit the priority, remembering the previous + priority to facilitate determining the subject task's + state. */ + traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); + uxPriorityUsedOnEntry = pxTCB->uxPriority; + 8008cac: 69bb ldr r3, [r7, #24] + 8008cae: 6adb ldr r3, [r3, #44] @ 0x2c + 8008cb0: 613b str r3, [r7, #16] + pxTCB->uxPriority = uxPriorityToUse; + 8008cb2: 69bb ldr r3, [r7, #24] + 8008cb4: 69fa ldr r2, [r7, #28] + 8008cb6: 62da str r2, [r3, #44] @ 0x2c + + /* Only reset the event list item value if the value is not + being used for anything else. */ + if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) + 8008cb8: 69bb ldr r3, [r7, #24] + 8008cba: 699b ldr r3, [r3, #24] + 8008cbc: 2b00 cmp r3, #0 + 8008cbe: db04 blt.n 8008cca + { + listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 8008cc0: 69fb ldr r3, [r7, #28] + 8008cc2: f1c3 0238 rsb r2, r3, #56 @ 0x38 + 8008cc6: 69bb ldr r3, [r7, #24] + 8008cc8: 619a str r2, [r3, #24] + then the task that holds the mutex could be in either the + Ready, Blocked or Suspended states. Only remove the task + from its current state list if it is in the Ready state as + the task's priority is going to change and there is one + Ready list per priority. */ + if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE ) + 8008cca: 69bb ldr r3, [r7, #24] + 8008ccc: 6959 ldr r1, [r3, #20] + 8008cce: 693a ldr r2, [r7, #16] + 8008cd0: 4613 mov r3, r2 + 8008cd2: 009b lsls r3, r3, #2 + 8008cd4: 4413 add r3, r2 + 8008cd6: 009b lsls r3, r3, #2 + 8008cd8: 4a13 ldr r2, [pc, #76] @ (8008d28 ) + 8008cda: 4413 add r3, r2 + 8008cdc: 4299 cmp r1, r3 + 8008cde: d11c bne.n 8008d1a + { + if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + 8008ce0: 69bb ldr r3, [r7, #24] + 8008ce2: 3304 adds r3, #4 + 8008ce4: 4618 mov r0, r3 + 8008ce6: f7fe f831 bl 8006d4c + else + { + mtCOVERAGE_TEST_MARKER(); + } + + prvAddTaskToReadyList( pxTCB ); + 8008cea: 69bb ldr r3, [r7, #24] + 8008cec: 6ada ldr r2, [r3, #44] @ 0x2c + 8008cee: 4b0f ldr r3, [pc, #60] @ (8008d2c ) + 8008cf0: 681b ldr r3, [r3, #0] + 8008cf2: 429a cmp r2, r3 + 8008cf4: d903 bls.n 8008cfe + 8008cf6: 69bb ldr r3, [r7, #24] + 8008cf8: 6adb ldr r3, [r3, #44] @ 0x2c + 8008cfa: 4a0c ldr r2, [pc, #48] @ (8008d2c ) + 8008cfc: 6013 str r3, [r2, #0] + 8008cfe: 69bb ldr r3, [r7, #24] + 8008d00: 6ada ldr r2, [r3, #44] @ 0x2c + 8008d02: 4613 mov r3, r2 + 8008d04: 009b lsls r3, r3, #2 + 8008d06: 4413 add r3, r2 + 8008d08: 009b lsls r3, r3, #2 + 8008d0a: 4a07 ldr r2, [pc, #28] @ (8008d28 ) + 8008d0c: 441a add r2, r3 + 8008d0e: 69bb ldr r3, [r7, #24] + 8008d10: 3304 adds r3, #4 + 8008d12: 4619 mov r1, r3 + 8008d14: 4610 mov r0, r2 + 8008d16: f7fd ffbc bl 8006c92 + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + 8008d1a: bf00 nop + 8008d1c: 3720 adds r7, #32 + 8008d1e: 46bd mov sp, r7 + 8008d20: bd80 pop {r7, pc} + 8008d22: bf00 nop + 8008d24: 20000ac0 .word 0x20000ac0 + 8008d28: 20000ac4 .word 0x20000ac4 + 8008d2c: 20000f9c .word 0x20000f9c + +08008d30 : +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + TaskHandle_t pvTaskIncrementMutexHeldCount( void ) + { + 8008d30: b480 push {r7} + 8008d32: af00 add r7, sp, #0 + /* If xSemaphoreCreateMutex() is called before any tasks have been created + then pxCurrentTCB will be NULL. */ + if( pxCurrentTCB != NULL ) + 8008d34: 4b07 ldr r3, [pc, #28] @ (8008d54 ) + 8008d36: 681b ldr r3, [r3, #0] + 8008d38: 2b00 cmp r3, #0 + 8008d3a: d004 beq.n 8008d46 + { + ( pxCurrentTCB->uxMutexesHeld )++; + 8008d3c: 4b05 ldr r3, [pc, #20] @ (8008d54 ) + 8008d3e: 681b ldr r3, [r3, #0] + 8008d40: 6d1a ldr r2, [r3, #80] @ 0x50 + 8008d42: 3201 adds r2, #1 + 8008d44: 651a str r2, [r3, #80] @ 0x50 + } + + return pxCurrentTCB; + 8008d46: 4b03 ldr r3, [pc, #12] @ (8008d54 ) + 8008d48: 681b ldr r3, [r3, #0] + } + 8008d4a: 4618 mov r0, r3 + 8008d4c: 46bd mov sp, r7 + 8008d4e: f85d 7b04 ldr.w r7, [sp], #4 + 8008d52: 4770 bx lr + 8008d54: 20000ac0 .word 0x20000ac0 + +08008d58 : #endif /*-----------------------------------------------------------*/ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) { - 8004a10: b580 push {r7, lr} - 8004a12: b084 sub sp, #16 - 8004a14: af00 add r7, sp, #0 - 8004a16: 6078 str r0, [r7, #4] - 8004a18: 6039 str r1, [r7, #0] + 8008d58: b580 push {r7, lr} + 8008d5a: b084 sub sp, #16 + 8008d5c: af00 add r7, sp, #0 + 8008d5e: 6078 str r0, [r7, #4] + 8008d60: 6039 str r1, [r7, #0] TickType_t xTimeToWake; const TickType_t xConstTickCount = xTickCount; - 8004a1a: 4b21 ldr r3, [pc, #132] @ (8004aa0 ) - 8004a1c: 681b ldr r3, [r3, #0] - 8004a1e: 60fb str r3, [r7, #12] + 8008d62: 4b21 ldr r3, [pc, #132] @ (8008de8 ) + 8008d64: 681b ldr r3, [r3, #0] + 8008d66: 60fb str r3, [r7, #12] } #endif /* Remove the task from the ready list before adding it to the blocked list as the same list item is used for both lists. */ if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) - 8004a20: 4b20 ldr r3, [pc, #128] @ (8004aa4 ) - 8004a22: 681b ldr r3, [r3, #0] - 8004a24: 3304 adds r3, #4 - 8004a26: 4618 mov r0, r3 - 8004a28: f7fe fbe8 bl 80031fc + 8008d68: 4b20 ldr r3, [pc, #128] @ (8008dec ) + 8008d6a: 681b ldr r3, [r3, #0] + 8008d6c: 3304 adds r3, #4 + 8008d6e: 4618 mov r0, r3 + 8008d70: f7fd ffec bl 8006d4c mtCOVERAGE_TEST_MARKER(); } #if ( INCLUDE_vTaskSuspend == 1 ) { if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) - 8004a2c: 687b ldr r3, [r7, #4] - 8004a2e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff - 8004a32: d10a bne.n 8004a4a - 8004a34: 683b ldr r3, [r7, #0] - 8004a36: 2b00 cmp r3, #0 - 8004a38: d007 beq.n 8004a4a + 8008d74: 687b ldr r3, [r7, #4] + 8008d76: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8008d7a: d10a bne.n 8008d92 + 8008d7c: 683b ldr r3, [r7, #0] + 8008d7e: 2b00 cmp r3, #0 + 8008d80: d007 beq.n 8008d92 { /* Add the task to the suspended task list instead of a delayed task list to ensure it is not woken by a timing event. It will block indefinitely. */ vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); - 8004a3a: 4b1a ldr r3, [pc, #104] @ (8004aa4 ) - 8004a3c: 681b ldr r3, [r3, #0] - 8004a3e: 3304 adds r3, #4 - 8004a40: 4619 mov r1, r3 - 8004a42: 4819 ldr r0, [pc, #100] @ (8004aa8 ) - 8004a44: f7fe fb7d bl 8003142 + 8008d82: 4b1a ldr r3, [pc, #104] @ (8008dec ) + 8008d84: 681b ldr r3, [r3, #0] + 8008d86: 3304 adds r3, #4 + 8008d88: 4619 mov r1, r3 + 8008d8a: 4819 ldr r0, [pc, #100] @ (8008df0 ) + 8008d8c: f7fd ff81 bl 8006c92 /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ ( void ) xCanBlockIndefinitely; } #endif /* INCLUDE_vTaskSuspend */ } - 8004a48: e026 b.n 8004a98 + 8008d90: e026 b.n 8008de0 xTimeToWake = xConstTickCount + xTicksToWait; - 8004a4a: 68fa ldr r2, [r7, #12] - 8004a4c: 687b ldr r3, [r7, #4] - 8004a4e: 4413 add r3, r2 - 8004a50: 60bb str r3, [r7, #8] + 8008d92: 68fa ldr r2, [r7, #12] + 8008d94: 687b ldr r3, [r7, #4] + 8008d96: 4413 add r3, r2 + 8008d98: 60bb str r3, [r7, #8] listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); - 8004a52: 4b14 ldr r3, [pc, #80] @ (8004aa4 ) - 8004a54: 681b ldr r3, [r3, #0] - 8004a56: 68ba ldr r2, [r7, #8] - 8004a58: 605a str r2, [r3, #4] + 8008d9a: 4b14 ldr r3, [pc, #80] @ (8008dec ) + 8008d9c: 681b ldr r3, [r3, #0] + 8008d9e: 68ba ldr r2, [r7, #8] + 8008da0: 605a str r2, [r3, #4] if( xTimeToWake < xConstTickCount ) - 8004a5a: 68ba ldr r2, [r7, #8] - 8004a5c: 68fb ldr r3, [r7, #12] - 8004a5e: 429a cmp r2, r3 - 8004a60: d209 bcs.n 8004a76 + 8008da2: 68ba ldr r2, [r7, #8] + 8008da4: 68fb ldr r3, [r7, #12] + 8008da6: 429a cmp r2, r3 + 8008da8: d209 bcs.n 8008dbe vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); - 8004a62: 4b12 ldr r3, [pc, #72] @ (8004aac ) - 8004a64: 681a ldr r2, [r3, #0] - 8004a66: 4b0f ldr r3, [pc, #60] @ (8004aa4 ) - 8004a68: 681b ldr r3, [r3, #0] - 8004a6a: 3304 adds r3, #4 - 8004a6c: 4619 mov r1, r3 - 8004a6e: 4610 mov r0, r2 - 8004a70: f7fe fb8b bl 800318a + 8008daa: 4b12 ldr r3, [pc, #72] @ (8008df4 ) + 8008dac: 681a ldr r2, [r3, #0] + 8008dae: 4b0f ldr r3, [pc, #60] @ (8008dec ) + 8008db0: 681b ldr r3, [r3, #0] + 8008db2: 3304 adds r3, #4 + 8008db4: 4619 mov r1, r3 + 8008db6: 4610 mov r0, r2 + 8008db8: f7fd ff8f bl 8006cda } - 8004a74: e010 b.n 8004a98 + 8008dbc: e010 b.n 8008de0 vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); - 8004a76: 4b0e ldr r3, [pc, #56] @ (8004ab0 ) - 8004a78: 681a ldr r2, [r3, #0] - 8004a7a: 4b0a ldr r3, [pc, #40] @ (8004aa4 ) - 8004a7c: 681b ldr r3, [r3, #0] - 8004a7e: 3304 adds r3, #4 - 8004a80: 4619 mov r1, r3 - 8004a82: 4610 mov r0, r2 - 8004a84: f7fe fb81 bl 800318a + 8008dbe: 4b0e ldr r3, [pc, #56] @ (8008df8 ) + 8008dc0: 681a ldr r2, [r3, #0] + 8008dc2: 4b0a ldr r3, [pc, #40] @ (8008dec ) + 8008dc4: 681b ldr r3, [r3, #0] + 8008dc6: 3304 adds r3, #4 + 8008dc8: 4619 mov r1, r3 + 8008dca: 4610 mov r0, r2 + 8008dcc: f7fd ff85 bl 8006cda if( xTimeToWake < xNextTaskUnblockTime ) - 8004a88: 4b0a ldr r3, [pc, #40] @ (8004ab4 ) - 8004a8a: 681b ldr r3, [r3, #0] - 8004a8c: 68ba ldr r2, [r7, #8] - 8004a8e: 429a cmp r2, r3 - 8004a90: d202 bcs.n 8004a98 + 8008dd0: 4b0a ldr r3, [pc, #40] @ (8008dfc ) + 8008dd2: 681b ldr r3, [r3, #0] + 8008dd4: 68ba ldr r2, [r7, #8] + 8008dd6: 429a cmp r2, r3 + 8008dd8: d202 bcs.n 8008de0 xNextTaskUnblockTime = xTimeToWake; - 8004a92: 4a08 ldr r2, [pc, #32] @ (8004ab4 ) - 8004a94: 68bb ldr r3, [r7, #8] - 8004a96: 6013 str r3, [r2, #0] + 8008dda: 4a08 ldr r2, [pc, #32] @ (8008dfc ) + 8008ddc: 68bb ldr r3, [r7, #8] + 8008dde: 6013 str r3, [r2, #0] } - 8004a98: bf00 nop - 8004a9a: 3710 adds r7, #16 - 8004a9c: 46bd mov sp, r7 - 8004a9e: bd80 pop {r7, pc} - 8004aa0: 20000e10 .word 0x20000e10 - 8004aa4: 20000938 .word 0x20000938 - 8004aa8: 20000df8 .word 0x20000df8 - 8004aac: 20000dc8 .word 0x20000dc8 - 8004ab0: 20000dc4 .word 0x20000dc4 - 8004ab4: 20000e2c .word 0x20000e2c + 8008de0: bf00 nop + 8008de2: 3710 adds r7, #16 + 8008de4: 46bd mov sp, r7 + 8008de6: bd80 pop {r7, pc} + 8008de8: 20000f98 .word 0x20000f98 + 8008dec: 20000ac0 .word 0x20000ac0 + 8008df0: 20000f80 .word 0x20000f80 + 8008df4: 20000f50 .word 0x20000f50 + 8008df8: 20000f4c .word 0x20000f4c + 8008dfc: 20000fb4 .word 0x20000fb4 -08004ab8 : +08008e00 : TimerCallbackFunction_t pxCallbackFunction, Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ BaseType_t xTimerCreateTimerTask( void ) { - 8004ab8: b580 push {r7, lr} - 8004aba: b08a sub sp, #40 @ 0x28 - 8004abc: af04 add r7, sp, #16 + 8008e00: b580 push {r7, lr} + 8008e02: b08a sub sp, #40 @ 0x28 + 8008e04: af04 add r7, sp, #16 BaseType_t xReturn = pdFAIL; - 8004abe: 2300 movs r3, #0 - 8004ac0: 617b str r3, [r7, #20] + 8008e06: 2300 movs r3, #0 + 8008e08: 617b str r3, [r7, #20] /* This function is called when the scheduler is started if configUSE_TIMERS is set to 1. Check that the infrastructure used by the timer service task has been created/initialised. If timers have already been created then the initialisation will already have been performed. */ prvCheckForValidListAndQueue(); - 8004ac2: f000 fb13 bl 80050ec + 8008e0a: f000 fbb1 bl 8009570 if( xTimerQueue != NULL ) - 8004ac6: 4b1d ldr r3, [pc, #116] @ (8004b3c ) - 8004ac8: 681b ldr r3, [r3, #0] - 8004aca: 2b00 cmp r3, #0 - 8004acc: d021 beq.n 8004b12 + 8008e0e: 4b1d ldr r3, [pc, #116] @ (8008e84 ) + 8008e10: 681b ldr r3, [r3, #0] + 8008e12: 2b00 cmp r3, #0 + 8008e14: d021 beq.n 8008e5a { #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t *pxTimerTaskTCBBuffer = NULL; - 8004ace: 2300 movs r3, #0 - 8004ad0: 60fb str r3, [r7, #12] + 8008e16: 2300 movs r3, #0 + 8008e18: 60fb str r3, [r7, #12] StackType_t *pxTimerTaskStackBuffer = NULL; - 8004ad2: 2300 movs r3, #0 - 8004ad4: 60bb str r3, [r7, #8] + 8008e1a: 2300 movs r3, #0 + 8008e1c: 60bb str r3, [r7, #8] uint32_t ulTimerTaskStackSize; vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize ); - 8004ad6: 1d3a adds r2, r7, #4 - 8004ad8: f107 0108 add.w r1, r7, #8 - 8004adc: f107 030c add.w r3, r7, #12 - 8004ae0: 4618 mov r0, r3 - 8004ae2: f7fe fae7 bl 80030b4 + 8008e1e: 1d3a adds r2, r7, #4 + 8008e20: f107 0108 add.w r1, r7, #8 + 8008e24: f107 030c add.w r3, r7, #12 + 8008e28: 4618 mov r0, r3 + 8008e2a: f7fd feeb bl 8006c04 xTimerTaskHandle = xTaskCreateStatic( prvTimerTask, - 8004ae6: 6879 ldr r1, [r7, #4] - 8004ae8: 68bb ldr r3, [r7, #8] - 8004aea: 68fa ldr r2, [r7, #12] - 8004aec: 9202 str r2, [sp, #8] - 8004aee: 9301 str r3, [sp, #4] - 8004af0: 2302 movs r3, #2 - 8004af2: 9300 str r3, [sp, #0] - 8004af4: 2300 movs r3, #0 - 8004af6: 460a mov r2, r1 - 8004af8: 4911 ldr r1, [pc, #68] @ (8004b40 ) - 8004afa: 4812 ldr r0, [pc, #72] @ (8004b44 ) - 8004afc: f7ff f8a2 bl 8003c44 - 8004b00: 4603 mov r3, r0 - 8004b02: 4a11 ldr r2, [pc, #68] @ (8004b48 ) - 8004b04: 6013 str r3, [r2, #0] + 8008e2e: 6879 ldr r1, [r7, #4] + 8008e30: 68bb ldr r3, [r7, #8] + 8008e32: 68fa ldr r2, [r7, #12] + 8008e34: 9202 str r2, [sp, #8] + 8008e36: 9301 str r3, [sp, #4] + 8008e38: 2302 movs r3, #2 + 8008e3a: 9300 str r3, [sp, #0] + 8008e3c: 2300 movs r3, #0 + 8008e3e: 460a mov r2, r1 + 8008e40: 4911 ldr r1, [pc, #68] @ (8008e88 ) + 8008e42: 4812 ldr r0, [pc, #72] @ (8008e8c ) + 8008e44: f7fe ffd8 bl 8007df8 + 8008e48: 4603 mov r3, r0 + 8008e4a: 4a11 ldr r2, [pc, #68] @ (8008e90 ) + 8008e4c: 6013 str r3, [r2, #0] NULL, ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, pxTimerTaskStackBuffer, pxTimerTaskTCBBuffer ); if( xTimerTaskHandle != NULL ) - 8004b06: 4b10 ldr r3, [pc, #64] @ (8004b48 ) - 8004b08: 681b ldr r3, [r3, #0] - 8004b0a: 2b00 cmp r3, #0 - 8004b0c: d001 beq.n 8004b12 + 8008e4e: 4b10 ldr r3, [pc, #64] @ (8008e90 ) + 8008e50: 681b ldr r3, [r3, #0] + 8008e52: 2b00 cmp r3, #0 + 8008e54: d001 beq.n 8008e5a { xReturn = pdPASS; - 8004b0e: 2301 movs r3, #1 - 8004b10: 617b str r3, [r7, #20] + 8008e56: 2301 movs r3, #1 + 8008e58: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } configASSERT( xReturn ); - 8004b12: 697b ldr r3, [r7, #20] - 8004b14: 2b00 cmp r3, #0 - 8004b16: d10b bne.n 8004b30 + 8008e5a: 697b ldr r3, [r7, #20] + 8008e5c: 2b00 cmp r3, #0 + 8008e5e: d10b bne.n 8008e78 __asm volatile - 8004b18: f04f 0350 mov.w r3, #80 @ 0x50 - 8004b1c: f383 8811 msr BASEPRI, r3 - 8004b20: f3bf 8f6f isb sy - 8004b24: f3bf 8f4f dsb sy - 8004b28: 613b str r3, [r7, #16] + 8008e60: f04f 0350 mov.w r3, #80 @ 0x50 + 8008e64: f383 8811 msr BASEPRI, r3 + 8008e68: f3bf 8f6f isb sy + 8008e6c: f3bf 8f4f dsb sy + 8008e70: 613b str r3, [r7, #16] } - 8004b2a: bf00 nop - 8004b2c: bf00 nop - 8004b2e: e7fd b.n 8004b2c + 8008e72: bf00 nop + 8008e74: bf00 nop + 8008e76: e7fd b.n 8008e74 return xReturn; - 8004b30: 697b ldr r3, [r7, #20] + 8008e78: 697b ldr r3, [r7, #20] } - 8004b32: 4618 mov r0, r3 - 8004b34: 3718 adds r7, #24 - 8004b36: 46bd mov sp, r7 - 8004b38: bd80 pop {r7, pc} - 8004b3a: bf00 nop - 8004b3c: 20000e68 .word 0x20000e68 - 8004b40: 08005d10 .word 0x08005d10 - 8004b44: 08004c85 .word 0x08004c85 - 8004b48: 20000e6c .word 0x20000e6c + 8008e7a: 4618 mov r0, r3 + 8008e7c: 3718 adds r7, #24 + 8008e7e: 46bd mov sp, r7 + 8008e80: bd80 pop {r7, pc} + 8008e82: bf00 nop + 8008e84: 20000ff0 .word 0x20000ff0 + 8008e88: 0800a290 .word 0x0800a290 + 8008e8c: 08009109 .word 0x08009109 + 8008e90: 20000ff4 .word 0x20000ff4 -08004b4c : +08008e94 : + TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const TickType_t xTimerPeriodInTicks, + const UBaseType_t uxAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction ) + { + 8008e94: b580 push {r7, lr} + 8008e96: b088 sub sp, #32 + 8008e98: af02 add r7, sp, #8 + 8008e9a: 60f8 str r0, [r7, #12] + 8008e9c: 60b9 str r1, [r7, #8] + 8008e9e: 607a str r2, [r7, #4] + 8008ea0: 603b str r3, [r7, #0] + Timer_t *pxNewTimer; + + pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */ + 8008ea2: 202c movs r0, #44 @ 0x2c + 8008ea4: f000 fe1a bl 8009adc + 8008ea8: 6178 str r0, [r7, #20] + + if( pxNewTimer != NULL ) + 8008eaa: 697b ldr r3, [r7, #20] + 8008eac: 2b00 cmp r3, #0 + 8008eae: d00d beq.n 8008ecc + { + /* Status is thus far zero as the timer is not created statically + and has not been started. The auto-reload bit may get set in + prvInitialiseNewTimer. */ + pxNewTimer->ucStatus = 0x00; + 8008eb0: 697b ldr r3, [r7, #20] + 8008eb2: 2200 movs r2, #0 + 8008eb4: f883 2028 strb.w r2, [r3, #40] @ 0x28 + prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); + 8008eb8: 697b ldr r3, [r7, #20] + 8008eba: 9301 str r3, [sp, #4] + 8008ebc: 6a3b ldr r3, [r7, #32] + 8008ebe: 9300 str r3, [sp, #0] + 8008ec0: 683b ldr r3, [r7, #0] + 8008ec2: 687a ldr r2, [r7, #4] + 8008ec4: 68b9 ldr r1, [r7, #8] + 8008ec6: 68f8 ldr r0, [r7, #12] + 8008ec8: f000 f845 bl 8008f56 + } + + return pxNewTimer; + 8008ecc: 697b ldr r3, [r7, #20] + } + 8008ece: 4618 mov r0, r3 + 8008ed0: 3718 adds r7, #24 + 8008ed2: 46bd mov sp, r7 + 8008ed4: bd80 pop {r7, pc} + +08008ed6 : + const TickType_t xTimerPeriodInTicks, + const UBaseType_t uxAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction, + StaticTimer_t *pxTimerBuffer ) + { + 8008ed6: b580 push {r7, lr} + 8008ed8: b08a sub sp, #40 @ 0x28 + 8008eda: af02 add r7, sp, #8 + 8008edc: 60f8 str r0, [r7, #12] + 8008ede: 60b9 str r1, [r7, #8] + 8008ee0: 607a str r2, [r7, #4] + 8008ee2: 603b str r3, [r7, #0] + #if( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + variable of type StaticTimer_t equals the size of the real timer + structure. */ + volatile size_t xSize = sizeof( StaticTimer_t ); + 8008ee4: 232c movs r3, #44 @ 0x2c + 8008ee6: 613b str r3, [r7, #16] + configASSERT( xSize == sizeof( Timer_t ) ); + 8008ee8: 693b ldr r3, [r7, #16] + 8008eea: 2b2c cmp r3, #44 @ 0x2c + 8008eec: d00b beq.n 8008f06 + __asm volatile + 8008eee: f04f 0350 mov.w r3, #80 @ 0x50 + 8008ef2: f383 8811 msr BASEPRI, r3 + 8008ef6: f3bf 8f6f isb sy + 8008efa: f3bf 8f4f dsb sy + 8008efe: 61bb str r3, [r7, #24] +} + 8008f00: bf00 nop + 8008f02: bf00 nop + 8008f04: e7fd b.n 8008f02 + ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ + 8008f06: 693b ldr r3, [r7, #16] + } + #endif /* configASSERT_DEFINED */ + + /* A pointer to a StaticTimer_t structure MUST be provided, use it. */ + configASSERT( pxTimerBuffer ); + 8008f08: 6afb ldr r3, [r7, #44] @ 0x2c + 8008f0a: 2b00 cmp r3, #0 + 8008f0c: d10b bne.n 8008f26 + __asm volatile + 8008f0e: f04f 0350 mov.w r3, #80 @ 0x50 + 8008f12: f383 8811 msr BASEPRI, r3 + 8008f16: f3bf 8f6f isb sy + 8008f1a: f3bf 8f4f dsb sy + 8008f1e: 617b str r3, [r7, #20] +} + 8008f20: bf00 nop + 8008f22: bf00 nop + 8008f24: e7fd b.n 8008f22 + pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */ + 8008f26: 6afb ldr r3, [r7, #44] @ 0x2c + 8008f28: 61fb str r3, [r7, #28] + + if( pxNewTimer != NULL ) + 8008f2a: 69fb ldr r3, [r7, #28] + 8008f2c: 2b00 cmp r3, #0 + 8008f2e: d00d beq.n 8008f4c + { + /* Timers can be created statically or dynamically so note this + timer was created statically in case it is later deleted. The + auto-reload bit may get set in prvInitialiseNewTimer(). */ + pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED; + 8008f30: 69fb ldr r3, [r7, #28] + 8008f32: 2202 movs r2, #2 + 8008f34: f883 2028 strb.w r2, [r3, #40] @ 0x28 + + prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); + 8008f38: 69fb ldr r3, [r7, #28] + 8008f3a: 9301 str r3, [sp, #4] + 8008f3c: 6abb ldr r3, [r7, #40] @ 0x28 + 8008f3e: 9300 str r3, [sp, #0] + 8008f40: 683b ldr r3, [r7, #0] + 8008f42: 687a ldr r2, [r7, #4] + 8008f44: 68b9 ldr r1, [r7, #8] + 8008f46: 68f8 ldr r0, [r7, #12] + 8008f48: f000 f805 bl 8008f56 + } + + return pxNewTimer; + 8008f4c: 69fb ldr r3, [r7, #28] + } + 8008f4e: 4618 mov r0, r3 + 8008f50: 3720 adds r7, #32 + 8008f52: 46bd mov sp, r7 + 8008f54: bd80 pop {r7, pc} + +08008f56 : + const TickType_t xTimerPeriodInTicks, + const UBaseType_t uxAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction, + Timer_t *pxNewTimer ) +{ + 8008f56: b580 push {r7, lr} + 8008f58: b086 sub sp, #24 + 8008f5a: af00 add r7, sp, #0 + 8008f5c: 60f8 str r0, [r7, #12] + 8008f5e: 60b9 str r1, [r7, #8] + 8008f60: 607a str r2, [r7, #4] + 8008f62: 603b str r3, [r7, #0] + /* 0 is not a valid value for xTimerPeriodInTicks. */ + configASSERT( ( xTimerPeriodInTicks > 0 ) ); + 8008f64: 68bb ldr r3, [r7, #8] + 8008f66: 2b00 cmp r3, #0 + 8008f68: d10b bne.n 8008f82 + __asm volatile + 8008f6a: f04f 0350 mov.w r3, #80 @ 0x50 + 8008f6e: f383 8811 msr BASEPRI, r3 + 8008f72: f3bf 8f6f isb sy + 8008f76: f3bf 8f4f dsb sy + 8008f7a: 617b str r3, [r7, #20] +} + 8008f7c: bf00 nop + 8008f7e: bf00 nop + 8008f80: e7fd b.n 8008f7e + + if( pxNewTimer != NULL ) + 8008f82: 6a7b ldr r3, [r7, #36] @ 0x24 + 8008f84: 2b00 cmp r3, #0 + 8008f86: d01e beq.n 8008fc6 + { + /* Ensure the infrastructure used by the timer service task has been + created/initialised. */ + prvCheckForValidListAndQueue(); + 8008f88: f000 faf2 bl 8009570 + + /* Initialise the timer structure members using the function + parameters. */ + pxNewTimer->pcTimerName = pcTimerName; + 8008f8c: 6a7b ldr r3, [r7, #36] @ 0x24 + 8008f8e: 68fa ldr r2, [r7, #12] + 8008f90: 601a str r2, [r3, #0] + pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks; + 8008f92: 6a7b ldr r3, [r7, #36] @ 0x24 + 8008f94: 68ba ldr r2, [r7, #8] + 8008f96: 619a str r2, [r3, #24] + pxNewTimer->pvTimerID = pvTimerID; + 8008f98: 6a7b ldr r3, [r7, #36] @ 0x24 + 8008f9a: 683a ldr r2, [r7, #0] + 8008f9c: 61da str r2, [r3, #28] + pxNewTimer->pxCallbackFunction = pxCallbackFunction; + 8008f9e: 6a7b ldr r3, [r7, #36] @ 0x24 + 8008fa0: 6a3a ldr r2, [r7, #32] + 8008fa2: 621a str r2, [r3, #32] + vListInitialiseItem( &( pxNewTimer->xTimerListItem ) ); + 8008fa4: 6a7b ldr r3, [r7, #36] @ 0x24 + 8008fa6: 3304 adds r3, #4 + 8008fa8: 4618 mov r0, r3 + 8008faa: f7fd fe65 bl 8006c78 + if( uxAutoReload != pdFALSE ) + 8008fae: 687b ldr r3, [r7, #4] + 8008fb0: 2b00 cmp r3, #0 + 8008fb2: d008 beq.n 8008fc6 + { + pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD; + 8008fb4: 6a7b ldr r3, [r7, #36] @ 0x24 + 8008fb6: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 + 8008fba: f043 0304 orr.w r3, r3, #4 + 8008fbe: b2da uxtb r2, r3 + 8008fc0: 6a7b ldr r3, [r7, #36] @ 0x24 + 8008fc2: f883 2028 strb.w r2, [r3, #40] @ 0x28 + } + traceTIMER_CREATE( pxNewTimer ); } } + 8008fc6: bf00 nop + 8008fc8: 3718 adds r7, #24 + 8008fca: 46bd mov sp, r7 + 8008fcc: bd80 pop {r7, pc} + ... + +08008fd0 : /*-----------------------------------------------------------*/ BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) { - 8004b4c: b580 push {r7, lr} - 8004b4e: b08a sub sp, #40 @ 0x28 - 8004b50: af00 add r7, sp, #0 - 8004b52: 60f8 str r0, [r7, #12] - 8004b54: 60b9 str r1, [r7, #8] - 8004b56: 607a str r2, [r7, #4] - 8004b58: 603b str r3, [r7, #0] + 8008fd0: b580 push {r7, lr} + 8008fd2: b08a sub sp, #40 @ 0x28 + 8008fd4: af00 add r7, sp, #0 + 8008fd6: 60f8 str r0, [r7, #12] + 8008fd8: 60b9 str r1, [r7, #8] + 8008fda: 607a str r2, [r7, #4] + 8008fdc: 603b str r3, [r7, #0] BaseType_t xReturn = pdFAIL; - 8004b5a: 2300 movs r3, #0 - 8004b5c: 627b str r3, [r7, #36] @ 0x24 + 8008fde: 2300 movs r3, #0 + 8008fe0: 627b str r3, [r7, #36] @ 0x24 DaemonTaskMessage_t xMessage; configASSERT( xTimer ); - 8004b5e: 68fb ldr r3, [r7, #12] - 8004b60: 2b00 cmp r3, #0 - 8004b62: d10b bne.n 8004b7c + 8008fe2: 68fb ldr r3, [r7, #12] + 8008fe4: 2b00 cmp r3, #0 + 8008fe6: d10b bne.n 8009000 __asm volatile - 8004b64: f04f 0350 mov.w r3, #80 @ 0x50 - 8004b68: f383 8811 msr BASEPRI, r3 - 8004b6c: f3bf 8f6f isb sy - 8004b70: f3bf 8f4f dsb sy - 8004b74: 623b str r3, [r7, #32] + 8008fe8: f04f 0350 mov.w r3, #80 @ 0x50 + 8008fec: f383 8811 msr BASEPRI, r3 + 8008ff0: f3bf 8f6f isb sy + 8008ff4: f3bf 8f4f dsb sy + 8008ff8: 623b str r3, [r7, #32] } - 8004b76: bf00 nop - 8004b78: bf00 nop - 8004b7a: e7fd b.n 8004b78 + 8008ffa: bf00 nop + 8008ffc: bf00 nop + 8008ffe: e7fd b.n 8008ffc /* Send a message to the timer service task to perform a particular action on a particular timer definition. */ if( xTimerQueue != NULL ) - 8004b7c: 4b19 ldr r3, [pc, #100] @ (8004be4 ) - 8004b7e: 681b ldr r3, [r3, #0] - 8004b80: 2b00 cmp r3, #0 - 8004b82: d02a beq.n 8004bda + 8009000: 4b19 ldr r3, [pc, #100] @ (8009068 ) + 8009002: 681b ldr r3, [r3, #0] + 8009004: 2b00 cmp r3, #0 + 8009006: d02a beq.n 800905e { /* Send a command to the timer service task to start the xTimer timer. */ xMessage.xMessageID = xCommandID; - 8004b84: 68bb ldr r3, [r7, #8] - 8004b86: 613b str r3, [r7, #16] + 8009008: 68bb ldr r3, [r7, #8] + 800900a: 613b str r3, [r7, #16] xMessage.u.xTimerParameters.xMessageValue = xOptionalValue; - 8004b88: 687b ldr r3, [r7, #4] - 8004b8a: 617b str r3, [r7, #20] + 800900c: 687b ldr r3, [r7, #4] + 800900e: 617b str r3, [r7, #20] xMessage.u.xTimerParameters.pxTimer = xTimer; - 8004b8c: 68fb ldr r3, [r7, #12] - 8004b8e: 61bb str r3, [r7, #24] + 8009010: 68fb ldr r3, [r7, #12] + 8009012: 61bb str r3, [r7, #24] if( xCommandID < tmrFIRST_FROM_ISR_COMMAND ) - 8004b90: 68bb ldr r3, [r7, #8] - 8004b92: 2b05 cmp r3, #5 - 8004b94: dc18 bgt.n 8004bc8 + 8009014: 68bb ldr r3, [r7, #8] + 8009016: 2b05 cmp r3, #5 + 8009018: dc18 bgt.n 800904c { if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING ) - 8004b96: f7ff fead bl 80048f4 - 8004b9a: 4603 mov r3, r0 - 8004b9c: 2b02 cmp r3, #2 - 8004b9e: d109 bne.n 8004bb4 + 800901a: f7ff fd0f bl 8008a3c + 800901e: 4603 mov r3, r0 + 8009020: 2b02 cmp r3, #2 + 8009022: d109 bne.n 8009038 { xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); - 8004ba0: 4b10 ldr r3, [pc, #64] @ (8004be4 ) - 8004ba2: 6818 ldr r0, [r3, #0] - 8004ba4: f107 0110 add.w r1, r7, #16 - 8004ba8: 2300 movs r3, #0 - 8004baa: 6b3a ldr r2, [r7, #48] @ 0x30 - 8004bac: f7fe fc5a bl 8003464 - 8004bb0: 6278 str r0, [r7, #36] @ 0x24 - 8004bb2: e012 b.n 8004bda + 8009024: 4b10 ldr r3, [pc, #64] @ (8009068 ) + 8009026: 6818 ldr r0, [r3, #0] + 8009028: f107 0110 add.w r1, r7, #16 + 800902c: 2300 movs r3, #0 + 800902e: 6b3a ldr r2, [r7, #48] @ 0x30 + 8009030: f7fe f86a bl 8007108 + 8009034: 6278 str r0, [r7, #36] @ 0x24 + 8009036: e012 b.n 800905e } else { xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY ); - 8004bb4: 4b0b ldr r3, [pc, #44] @ (8004be4 ) - 8004bb6: 6818 ldr r0, [r3, #0] - 8004bb8: f107 0110 add.w r1, r7, #16 - 8004bbc: 2300 movs r3, #0 - 8004bbe: 2200 movs r2, #0 - 8004bc0: f7fe fc50 bl 8003464 - 8004bc4: 6278 str r0, [r7, #36] @ 0x24 - 8004bc6: e008 b.n 8004bda + 8009038: 4b0b ldr r3, [pc, #44] @ (8009068 ) + 800903a: 6818 ldr r0, [r3, #0] + 800903c: f107 0110 add.w r1, r7, #16 + 8009040: 2300 movs r3, #0 + 8009042: 2200 movs r2, #0 + 8009044: f7fe f860 bl 8007108 + 8009048: 6278 str r0, [r7, #36] @ 0x24 + 800904a: e008 b.n 800905e } } else { xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken ); - 8004bc8: 4b06 ldr r3, [pc, #24] @ (8004be4 ) - 8004bca: 6818 ldr r0, [r3, #0] - 8004bcc: f107 0110 add.w r1, r7, #16 - 8004bd0: 2300 movs r3, #0 - 8004bd2: 683a ldr r2, [r7, #0] - 8004bd4: f7fe fd48 bl 8003668 - 8004bd8: 6278 str r0, [r7, #36] @ 0x24 + 800904c: 4b06 ldr r3, [pc, #24] @ (8009068 ) + 800904e: 6818 ldr r0, [r3, #0] + 8009050: f107 0110 add.w r1, r7, #16 + 8009054: 2300 movs r3, #0 + 8009056: 683a ldr r2, [r7, #0] + 8009058: f7fe f958 bl 800730c + 800905c: 6278 str r0, [r7, #36] @ 0x24 else { mtCOVERAGE_TEST_MARKER(); } return xReturn; - 8004bda: 6a7b ldr r3, [r7, #36] @ 0x24 + 800905e: 6a7b ldr r3, [r7, #36] @ 0x24 } - 8004bdc: 4618 mov r0, r3 - 8004bde: 3728 adds r7, #40 @ 0x28 - 8004be0: 46bd mov sp, r7 - 8004be2: bd80 pop {r7, pc} - 8004be4: 20000e68 .word 0x20000e68 + 8009060: 4618 mov r0, r3 + 8009062: 3728 adds r7, #40 @ 0x28 + 8009064: 46bd mov sp, r7 + 8009066: bd80 pop {r7, pc} + 8009068: 20000ff0 .word 0x20000ff0 -08004be8 : +0800906c : return pxTimer->pcTimerName; } /*-----------------------------------------------------------*/ static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) { - 8004be8: b580 push {r7, lr} - 8004bea: b088 sub sp, #32 - 8004bec: af02 add r7, sp, #8 - 8004bee: 6078 str r0, [r7, #4] - 8004bf0: 6039 str r1, [r7, #0] + 800906c: b580 push {r7, lr} + 800906e: b088 sub sp, #32 + 8009070: af02 add r7, sp, #8 + 8009072: 6078 str r0, [r7, #4] + 8009074: 6039 str r1, [r7, #0] BaseType_t xResult; Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ - 8004bf2: 4b23 ldr r3, [pc, #140] @ (8004c80 ) - 8004bf4: 681b ldr r3, [r3, #0] - 8004bf6: 68db ldr r3, [r3, #12] - 8004bf8: 68db ldr r3, [r3, #12] - 8004bfa: 617b str r3, [r7, #20] + 8009076: 4b23 ldr r3, [pc, #140] @ (8009104 ) + 8009078: 681b ldr r3, [r3, #0] + 800907a: 68db ldr r3, [r3, #12] + 800907c: 68db ldr r3, [r3, #12] + 800907e: 617b str r3, [r7, #20] /* Remove the timer from the list of active timers. A check has already been performed to ensure the list is not empty. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); - 8004bfc: 697b ldr r3, [r7, #20] - 8004bfe: 3304 adds r3, #4 - 8004c00: 4618 mov r0, r3 - 8004c02: f7fe fafb bl 80031fc + 8009080: 697b ldr r3, [r7, #20] + 8009082: 3304 adds r3, #4 + 8009084: 4618 mov r0, r3 + 8009086: f7fd fe61 bl 8006d4c traceTIMER_EXPIRED( pxTimer ); /* If the timer is an auto-reload timer then calculate the next expiry time and re-insert the timer in the list of active timers. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) - 8004c06: 697b ldr r3, [r7, #20] - 8004c08: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 - 8004c0c: f003 0304 and.w r3, r3, #4 - 8004c10: 2b00 cmp r3, #0 - 8004c12: d023 beq.n 8004c5c + 800908a: 697b ldr r3, [r7, #20] + 800908c: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 + 8009090: f003 0304 and.w r3, r3, #4 + 8009094: 2b00 cmp r3, #0 + 8009096: d023 beq.n 80090e0 { /* The timer is inserted into a list using a time relative to anything other than the current time. It will therefore be inserted into the correct list relative to the time this task thinks it is now. */ if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE ) - 8004c14: 697b ldr r3, [r7, #20] - 8004c16: 699a ldr r2, [r3, #24] - 8004c18: 687b ldr r3, [r7, #4] - 8004c1a: 18d1 adds r1, r2, r3 - 8004c1c: 687b ldr r3, [r7, #4] - 8004c1e: 683a ldr r2, [r7, #0] - 8004c20: 6978 ldr r0, [r7, #20] - 8004c22: f000 f8d5 bl 8004dd0 - 8004c26: 4603 mov r3, r0 - 8004c28: 2b00 cmp r3, #0 - 8004c2a: d020 beq.n 8004c6e + 8009098: 697b ldr r3, [r7, #20] + 800909a: 699a ldr r2, [r3, #24] + 800909c: 687b ldr r3, [r7, #4] + 800909e: 18d1 adds r1, r2, r3 + 80090a0: 687b ldr r3, [r7, #4] + 80090a2: 683a ldr r2, [r7, #0] + 80090a4: 6978 ldr r0, [r7, #20] + 80090a6: f000 f8d5 bl 8009254 + 80090aa: 4603 mov r3, r0 + 80090ac: 2b00 cmp r3, #0 + 80090ae: d020 beq.n 80090f2 { /* The timer expired before it was added to the active timer list. Reload it now. */ xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); - 8004c2c: 2300 movs r3, #0 - 8004c2e: 9300 str r3, [sp, #0] - 8004c30: 2300 movs r3, #0 - 8004c32: 687a ldr r2, [r7, #4] - 8004c34: 2100 movs r1, #0 - 8004c36: 6978 ldr r0, [r7, #20] - 8004c38: f7ff ff88 bl 8004b4c - 8004c3c: 6138 str r0, [r7, #16] + 80090b0: 2300 movs r3, #0 + 80090b2: 9300 str r3, [sp, #0] + 80090b4: 2300 movs r3, #0 + 80090b6: 687a ldr r2, [r7, #4] + 80090b8: 2100 movs r1, #0 + 80090ba: 6978 ldr r0, [r7, #20] + 80090bc: f7ff ff88 bl 8008fd0 + 80090c0: 6138 str r0, [r7, #16] configASSERT( xResult ); - 8004c3e: 693b ldr r3, [r7, #16] - 8004c40: 2b00 cmp r3, #0 - 8004c42: d114 bne.n 8004c6e + 80090c2: 693b ldr r3, [r7, #16] + 80090c4: 2b00 cmp r3, #0 + 80090c6: d114 bne.n 80090f2 __asm volatile - 8004c44: f04f 0350 mov.w r3, #80 @ 0x50 - 8004c48: f383 8811 msr BASEPRI, r3 - 8004c4c: f3bf 8f6f isb sy - 8004c50: f3bf 8f4f dsb sy - 8004c54: 60fb str r3, [r7, #12] + 80090c8: f04f 0350 mov.w r3, #80 @ 0x50 + 80090cc: f383 8811 msr BASEPRI, r3 + 80090d0: f3bf 8f6f isb sy + 80090d4: f3bf 8f4f dsb sy + 80090d8: 60fb str r3, [r7, #12] } - 8004c56: bf00 nop - 8004c58: bf00 nop - 8004c5a: e7fd b.n 8004c58 + 80090da: bf00 nop + 80090dc: bf00 nop + 80090de: e7fd b.n 80090dc mtCOVERAGE_TEST_MARKER(); } } else { pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; - 8004c5c: 697b ldr r3, [r7, #20] - 8004c5e: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 - 8004c62: f023 0301 bic.w r3, r3, #1 - 8004c66: b2da uxtb r2, r3 - 8004c68: 697b ldr r3, [r7, #20] - 8004c6a: f883 2028 strb.w r2, [r3, #40] @ 0x28 + 80090e0: 697b ldr r3, [r7, #20] + 80090e2: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 + 80090e6: f023 0301 bic.w r3, r3, #1 + 80090ea: b2da uxtb r2, r3 + 80090ec: 697b ldr r3, [r7, #20] + 80090ee: f883 2028 strb.w r2, [r3, #40] @ 0x28 mtCOVERAGE_TEST_MARKER(); } /* Call the timer callback. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); - 8004c6e: 697b ldr r3, [r7, #20] - 8004c70: 6a1b ldr r3, [r3, #32] - 8004c72: 6978 ldr r0, [r7, #20] - 8004c74: 4798 blx r3 + 80090f2: 697b ldr r3, [r7, #20] + 80090f4: 6a1b ldr r3, [r3, #32] + 80090f6: 6978 ldr r0, [r7, #20] + 80090f8: 4798 blx r3 } - 8004c76: bf00 nop - 8004c78: 3718 adds r7, #24 - 8004c7a: 46bd mov sp, r7 - 8004c7c: bd80 pop {r7, pc} - 8004c7e: bf00 nop - 8004c80: 20000e60 .word 0x20000e60 + 80090fa: bf00 nop + 80090fc: 3718 adds r7, #24 + 80090fe: 46bd mov sp, r7 + 8009100: bd80 pop {r7, pc} + 8009102: bf00 nop + 8009104: 20000fe8 .word 0x20000fe8 -08004c84 : +08009108 : /*-----------------------------------------------------------*/ static portTASK_FUNCTION( prvTimerTask, pvParameters ) { - 8004c84: b580 push {r7, lr} - 8004c86: b084 sub sp, #16 - 8004c88: af00 add r7, sp, #0 - 8004c8a: 6078 str r0, [r7, #4] + 8009108: b580 push {r7, lr} + 800910a: b084 sub sp, #16 + 800910c: af00 add r7, sp, #0 + 800910e: 6078 str r0, [r7, #4] for( ;; ) { /* Query the timers list to see if it contains any timers, and if so, obtain the time at which the next timer will expire. */ xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); - 8004c8c: f107 0308 add.w r3, r7, #8 - 8004c90: 4618 mov r0, r3 - 8004c92: f000 f859 bl 8004d48 - 8004c96: 60f8 str r0, [r7, #12] + 8009110: f107 0308 add.w r3, r7, #8 + 8009114: 4618 mov r0, r3 + 8009116: f000 f859 bl 80091cc + 800911a: 60f8 str r0, [r7, #12] /* If a timer has expired, process it. Otherwise, block this task until either a timer does expire, or a command is received. */ prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty ); - 8004c98: 68bb ldr r3, [r7, #8] - 8004c9a: 4619 mov r1, r3 - 8004c9c: 68f8 ldr r0, [r7, #12] - 8004c9e: f000 f805 bl 8004cac + 800911c: 68bb ldr r3, [r7, #8] + 800911e: 4619 mov r1, r3 + 8009120: 68f8 ldr r0, [r7, #12] + 8009122: f000 f805 bl 8009130 /* Empty the command queue. */ prvProcessReceivedCommands(); - 8004ca2: f000 f8d7 bl 8004e54 + 8009126: f000 f8d7 bl 80092d8 xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); - 8004ca6: bf00 nop - 8004ca8: e7f0 b.n 8004c8c + 800912a: bf00 nop + 800912c: e7f0 b.n 8009110 ... -08004cac : +08009130 : } } /*-----------------------------------------------------------*/ static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) { - 8004cac: b580 push {r7, lr} - 8004cae: b084 sub sp, #16 - 8004cb0: af00 add r7, sp, #0 - 8004cb2: 6078 str r0, [r7, #4] - 8004cb4: 6039 str r1, [r7, #0] + 8009130: b580 push {r7, lr} + 8009132: b084 sub sp, #16 + 8009134: af00 add r7, sp, #0 + 8009136: 6078 str r0, [r7, #4] + 8009138: 6039 str r1, [r7, #0] TickType_t xTimeNow; BaseType_t xTimerListsWereSwitched; vTaskSuspendAll(); - 8004cb6: f7ff fa29 bl 800410c + 800913a: f7ff f88b bl 8008254 /* Obtain the time now to make an assessment as to whether the timer has expired or not. If obtaining the time causes the lists to switch then don't process this timer as any timers that remained in the list when the lists were switched will have been processed within the prvSampleTimeNow() function. */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); - 8004cba: f107 0308 add.w r3, r7, #8 - 8004cbe: 4618 mov r0, r3 - 8004cc0: f000 f866 bl 8004d90 - 8004cc4: 60f8 str r0, [r7, #12] + 800913e: f107 0308 add.w r3, r7, #8 + 8009142: 4618 mov r0, r3 + 8009144: f000 f866 bl 8009214 + 8009148: 60f8 str r0, [r7, #12] if( xTimerListsWereSwitched == pdFALSE ) - 8004cc6: 68bb ldr r3, [r7, #8] - 8004cc8: 2b00 cmp r3, #0 - 8004cca: d130 bne.n 8004d2e + 800914a: 68bb ldr r3, [r7, #8] + 800914c: 2b00 cmp r3, #0 + 800914e: d130 bne.n 80091b2 { /* The tick count has not overflowed, has the timer expired? */ if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) ) - 8004ccc: 683b ldr r3, [r7, #0] - 8004cce: 2b00 cmp r3, #0 - 8004cd0: d10a bne.n 8004ce8 - 8004cd2: 687a ldr r2, [r7, #4] - 8004cd4: 68fb ldr r3, [r7, #12] - 8004cd6: 429a cmp r2, r3 - 8004cd8: d806 bhi.n 8004ce8 + 8009150: 683b ldr r3, [r7, #0] + 8009152: 2b00 cmp r3, #0 + 8009154: d10a bne.n 800916c + 8009156: 687a ldr r2, [r7, #4] + 8009158: 68fb ldr r3, [r7, #12] + 800915a: 429a cmp r2, r3 + 800915c: d806 bhi.n 800916c { ( void ) xTaskResumeAll(); - 8004cda: f7ff fa25 bl 8004128 + 800915e: f7ff f887 bl 8008270 prvProcessExpiredTimer( xNextExpireTime, xTimeNow ); - 8004cde: 68f9 ldr r1, [r7, #12] - 8004ce0: 6878 ldr r0, [r7, #4] - 8004ce2: f7ff ff81 bl 8004be8 + 8009162: 68f9 ldr r1, [r7, #12] + 8009164: 6878 ldr r0, [r7, #4] + 8009166: f7ff ff81 bl 800906c else { ( void ) xTaskResumeAll(); } } } - 8004ce6: e024 b.n 8004d32 + 800916a: e024 b.n 80091b6 if( xListWasEmpty != pdFALSE ) - 8004ce8: 683b ldr r3, [r7, #0] - 8004cea: 2b00 cmp r3, #0 - 8004cec: d008 beq.n 8004d00 + 800916c: 683b ldr r3, [r7, #0] + 800916e: 2b00 cmp r3, #0 + 8009170: d008 beq.n 8009184 xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList ); - 8004cee: 4b13 ldr r3, [pc, #76] @ (8004d3c ) - 8004cf0: 681b ldr r3, [r3, #0] - 8004cf2: 681b ldr r3, [r3, #0] - 8004cf4: 2b00 cmp r3, #0 - 8004cf6: d101 bne.n 8004cfc - 8004cf8: 2301 movs r3, #1 - 8004cfa: e000 b.n 8004cfe - 8004cfc: 2300 movs r3, #0 - 8004cfe: 603b str r3, [r7, #0] + 8009172: 4b13 ldr r3, [pc, #76] @ (80091c0 ) + 8009174: 681b ldr r3, [r3, #0] + 8009176: 681b ldr r3, [r3, #0] + 8009178: 2b00 cmp r3, #0 + 800917a: d101 bne.n 8009180 + 800917c: 2301 movs r3, #1 + 800917e: e000 b.n 8009182 + 8009180: 2300 movs r3, #0 + 8009182: 603b str r3, [r7, #0] vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty ); - 8004d00: 4b0f ldr r3, [pc, #60] @ (8004d40 ) - 8004d02: 6818 ldr r0, [r3, #0] - 8004d04: 687a ldr r2, [r7, #4] - 8004d06: 68fb ldr r3, [r7, #12] - 8004d08: 1ad3 subs r3, r2, r3 - 8004d0a: 683a ldr r2, [r7, #0] - 8004d0c: 4619 mov r1, r3 - 8004d0e: f7fe ff65 bl 8003bdc + 8009184: 4b0f ldr r3, [pc, #60] @ (80091c4 ) + 8009186: 6818 ldr r0, [r3, #0] + 8009188: 687a ldr r2, [r7, #4] + 800918a: 68fb ldr r3, [r7, #12] + 800918c: 1ad3 subs r3, r2, r3 + 800918e: 683a ldr r2, [r7, #0] + 8009190: 4619 mov r1, r3 + 8009192: f7fe fdfd bl 8007d90 if( xTaskResumeAll() == pdFALSE ) - 8004d12: f7ff fa09 bl 8004128 - 8004d16: 4603 mov r3, r0 - 8004d18: 2b00 cmp r3, #0 - 8004d1a: d10a bne.n 8004d32 + 8009196: f7ff f86b bl 8008270 + 800919a: 4603 mov r3, r0 + 800919c: 2b00 cmp r3, #0 + 800919e: d10a bne.n 80091b6 portYIELD_WITHIN_API(); - 8004d1c: 4b09 ldr r3, [pc, #36] @ (8004d44 ) - 8004d1e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 - 8004d22: 601a str r2, [r3, #0] - 8004d24: f3bf 8f4f dsb sy - 8004d28: f3bf 8f6f isb sy + 80091a0: 4b09 ldr r3, [pc, #36] @ (80091c8 ) + 80091a2: f04f 5280 mov.w r2, #268435456 @ 0x10000000 + 80091a6: 601a str r2, [r3, #0] + 80091a8: f3bf 8f4f dsb sy + 80091ac: f3bf 8f6f isb sy } - 8004d2c: e001 b.n 8004d32 + 80091b0: e001 b.n 80091b6 ( void ) xTaskResumeAll(); - 8004d2e: f7ff f9fb bl 8004128 + 80091b2: f7ff f85d bl 8008270 } - 8004d32: bf00 nop - 8004d34: 3710 adds r7, #16 - 8004d36: 46bd mov sp, r7 - 8004d38: bd80 pop {r7, pc} - 8004d3a: bf00 nop - 8004d3c: 20000e64 .word 0x20000e64 - 8004d40: 20000e68 .word 0x20000e68 - 8004d44: e000ed04 .word 0xe000ed04 + 80091b6: bf00 nop + 80091b8: 3710 adds r7, #16 + 80091ba: 46bd mov sp, r7 + 80091bc: bd80 pop {r7, pc} + 80091be: bf00 nop + 80091c0: 20000fec .word 0x20000fec + 80091c4: 20000ff0 .word 0x20000ff0 + 80091c8: e000ed04 .word 0xe000ed04 -08004d48 : +080091cc : /*-----------------------------------------------------------*/ static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) { - 8004d48: b480 push {r7} - 8004d4a: b085 sub sp, #20 - 8004d4c: af00 add r7, sp, #0 - 8004d4e: 6078 str r0, [r7, #4] + 80091cc: b480 push {r7} + 80091ce: b085 sub sp, #20 + 80091d0: af00 add r7, sp, #0 + 80091d2: 6078 str r0, [r7, #4] the timer with the nearest expiry time will expire. If there are no active timers then just set the next expire time to 0. That will cause this task to unblock when the tick count overflows, at which point the timer lists will be switched and the next expiry time can be re-assessed. */ *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList ); - 8004d50: 4b0e ldr r3, [pc, #56] @ (8004d8c ) - 8004d52: 681b ldr r3, [r3, #0] - 8004d54: 681b ldr r3, [r3, #0] - 8004d56: 2b00 cmp r3, #0 - 8004d58: d101 bne.n 8004d5e - 8004d5a: 2201 movs r2, #1 - 8004d5c: e000 b.n 8004d60 - 8004d5e: 2200 movs r2, #0 - 8004d60: 687b ldr r3, [r7, #4] - 8004d62: 601a str r2, [r3, #0] + 80091d4: 4b0e ldr r3, [pc, #56] @ (8009210 ) + 80091d6: 681b ldr r3, [r3, #0] + 80091d8: 681b ldr r3, [r3, #0] + 80091da: 2b00 cmp r3, #0 + 80091dc: d101 bne.n 80091e2 + 80091de: 2201 movs r2, #1 + 80091e0: e000 b.n 80091e4 + 80091e2: 2200 movs r2, #0 + 80091e4: 687b ldr r3, [r7, #4] + 80091e6: 601a str r2, [r3, #0] if( *pxListWasEmpty == pdFALSE ) - 8004d64: 687b ldr r3, [r7, #4] - 8004d66: 681b ldr r3, [r3, #0] - 8004d68: 2b00 cmp r3, #0 - 8004d6a: d105 bne.n 8004d78 + 80091e8: 687b ldr r3, [r7, #4] + 80091ea: 681b ldr r3, [r3, #0] + 80091ec: 2b00 cmp r3, #0 + 80091ee: d105 bne.n 80091fc { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); - 8004d6c: 4b07 ldr r3, [pc, #28] @ (8004d8c ) - 8004d6e: 681b ldr r3, [r3, #0] - 8004d70: 68db ldr r3, [r3, #12] - 8004d72: 681b ldr r3, [r3, #0] - 8004d74: 60fb str r3, [r7, #12] - 8004d76: e001 b.n 8004d7c + 80091f0: 4b07 ldr r3, [pc, #28] @ (8009210 ) + 80091f2: 681b ldr r3, [r3, #0] + 80091f4: 68db ldr r3, [r3, #12] + 80091f6: 681b ldr r3, [r3, #0] + 80091f8: 60fb str r3, [r7, #12] + 80091fa: e001 b.n 8009200 } else { /* Ensure the task unblocks when the tick count rolls over. */ xNextExpireTime = ( TickType_t ) 0U; - 8004d78: 2300 movs r3, #0 - 8004d7a: 60fb str r3, [r7, #12] + 80091fc: 2300 movs r3, #0 + 80091fe: 60fb str r3, [r7, #12] } return xNextExpireTime; - 8004d7c: 68fb ldr r3, [r7, #12] + 8009200: 68fb ldr r3, [r7, #12] } - 8004d7e: 4618 mov r0, r3 - 8004d80: 3714 adds r7, #20 - 8004d82: 46bd mov sp, r7 - 8004d84: f85d 7b04 ldr.w r7, [sp], #4 - 8004d88: 4770 bx lr - 8004d8a: bf00 nop - 8004d8c: 20000e60 .word 0x20000e60 + 8009202: 4618 mov r0, r3 + 8009204: 3714 adds r7, #20 + 8009206: 46bd mov sp, r7 + 8009208: f85d 7b04 ldr.w r7, [sp], #4 + 800920c: 4770 bx lr + 800920e: bf00 nop + 8009210: 20000fe8 .word 0x20000fe8 -08004d90 : +08009214 : /*-----------------------------------------------------------*/ static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) { - 8004d90: b580 push {r7, lr} - 8004d92: b084 sub sp, #16 - 8004d94: af00 add r7, sp, #0 - 8004d96: 6078 str r0, [r7, #4] + 8009214: b580 push {r7, lr} + 8009216: b084 sub sp, #16 + 8009218: af00 add r7, sp, #0 + 800921a: 6078 str r0, [r7, #4] TickType_t xTimeNow; PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */ xTimeNow = xTaskGetTickCount(); - 8004d98: f7ff fa64 bl 8004264 - 8004d9c: 60f8 str r0, [r7, #12] + 800921c: f7ff f8c6 bl 80083ac + 8009220: 60f8 str r0, [r7, #12] if( xTimeNow < xLastTime ) - 8004d9e: 4b0b ldr r3, [pc, #44] @ (8004dcc ) - 8004da0: 681b ldr r3, [r3, #0] - 8004da2: 68fa ldr r2, [r7, #12] - 8004da4: 429a cmp r2, r3 - 8004da6: d205 bcs.n 8004db4 + 8009222: 4b0b ldr r3, [pc, #44] @ (8009250 ) + 8009224: 681b ldr r3, [r3, #0] + 8009226: 68fa ldr r2, [r7, #12] + 8009228: 429a cmp r2, r3 + 800922a: d205 bcs.n 8009238 { prvSwitchTimerLists(); - 8004da8: f000 f93a bl 8005020 + 800922c: f000 f93a bl 80094a4 *pxTimerListsWereSwitched = pdTRUE; - 8004dac: 687b ldr r3, [r7, #4] - 8004dae: 2201 movs r2, #1 - 8004db0: 601a str r2, [r3, #0] - 8004db2: e002 b.n 8004dba + 8009230: 687b ldr r3, [r7, #4] + 8009232: 2201 movs r2, #1 + 8009234: 601a str r2, [r3, #0] + 8009236: e002 b.n 800923e } else { *pxTimerListsWereSwitched = pdFALSE; - 8004db4: 687b ldr r3, [r7, #4] - 8004db6: 2200 movs r2, #0 - 8004db8: 601a str r2, [r3, #0] + 8009238: 687b ldr r3, [r7, #4] + 800923a: 2200 movs r2, #0 + 800923c: 601a str r2, [r3, #0] } xLastTime = xTimeNow; - 8004dba: 4a04 ldr r2, [pc, #16] @ (8004dcc ) - 8004dbc: 68fb ldr r3, [r7, #12] - 8004dbe: 6013 str r3, [r2, #0] + 800923e: 4a04 ldr r2, [pc, #16] @ (8009250 ) + 8009240: 68fb ldr r3, [r7, #12] + 8009242: 6013 str r3, [r2, #0] return xTimeNow; - 8004dc0: 68fb ldr r3, [r7, #12] + 8009244: 68fb ldr r3, [r7, #12] } - 8004dc2: 4618 mov r0, r3 - 8004dc4: 3710 adds r7, #16 - 8004dc6: 46bd mov sp, r7 - 8004dc8: bd80 pop {r7, pc} - 8004dca: bf00 nop - 8004dcc: 20000e70 .word 0x20000e70 + 8009246: 4618 mov r0, r3 + 8009248: 3710 adds r7, #16 + 800924a: 46bd mov sp, r7 + 800924c: bd80 pop {r7, pc} + 800924e: bf00 nop + 8009250: 20000ff8 .word 0x20000ff8 -08004dd0 : +08009254 : /*-----------------------------------------------------------*/ static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) { - 8004dd0: b580 push {r7, lr} - 8004dd2: b086 sub sp, #24 - 8004dd4: af00 add r7, sp, #0 - 8004dd6: 60f8 str r0, [r7, #12] - 8004dd8: 60b9 str r1, [r7, #8] - 8004dda: 607a str r2, [r7, #4] - 8004ddc: 603b str r3, [r7, #0] + 8009254: b580 push {r7, lr} + 8009256: b086 sub sp, #24 + 8009258: af00 add r7, sp, #0 + 800925a: 60f8 str r0, [r7, #12] + 800925c: 60b9 str r1, [r7, #8] + 800925e: 607a str r2, [r7, #4] + 8009260: 603b str r3, [r7, #0] BaseType_t xProcessTimerNow = pdFALSE; - 8004dde: 2300 movs r3, #0 - 8004de0: 617b str r3, [r7, #20] + 8009262: 2300 movs r3, #0 + 8009264: 617b str r3, [r7, #20] listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime ); - 8004de2: 68fb ldr r3, [r7, #12] - 8004de4: 68ba ldr r2, [r7, #8] - 8004de6: 605a str r2, [r3, #4] + 8009266: 68fb ldr r3, [r7, #12] + 8009268: 68ba ldr r2, [r7, #8] + 800926a: 605a str r2, [r3, #4] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); - 8004de8: 68fb ldr r3, [r7, #12] - 8004dea: 68fa ldr r2, [r7, #12] - 8004dec: 611a str r2, [r3, #16] + 800926c: 68fb ldr r3, [r7, #12] + 800926e: 68fa ldr r2, [r7, #12] + 8009270: 611a str r2, [r3, #16] if( xNextExpiryTime <= xTimeNow ) - 8004dee: 68ba ldr r2, [r7, #8] - 8004df0: 687b ldr r3, [r7, #4] - 8004df2: 429a cmp r2, r3 - 8004df4: d812 bhi.n 8004e1c + 8009272: 68ba ldr r2, [r7, #8] + 8009274: 687b ldr r3, [r7, #4] + 8009276: 429a cmp r2, r3 + 8009278: d812 bhi.n 80092a0 { /* Has the expiry time elapsed between the command to start/reset a timer was issued, and the time the command was processed? */ if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ - 8004df6: 687a ldr r2, [r7, #4] - 8004df8: 683b ldr r3, [r7, #0] - 8004dfa: 1ad2 subs r2, r2, r3 - 8004dfc: 68fb ldr r3, [r7, #12] - 8004dfe: 699b ldr r3, [r3, #24] - 8004e00: 429a cmp r2, r3 - 8004e02: d302 bcc.n 8004e0a + 800927a: 687a ldr r2, [r7, #4] + 800927c: 683b ldr r3, [r7, #0] + 800927e: 1ad2 subs r2, r2, r3 + 8009280: 68fb ldr r3, [r7, #12] + 8009282: 699b ldr r3, [r3, #24] + 8009284: 429a cmp r2, r3 + 8009286: d302 bcc.n 800928e { /* The time between a command being issued and the command being processed actually exceeds the timers period. */ xProcessTimerNow = pdTRUE; - 8004e04: 2301 movs r3, #1 - 8004e06: 617b str r3, [r7, #20] - 8004e08: e01b b.n 8004e42 + 8009288: 2301 movs r3, #1 + 800928a: 617b str r3, [r7, #20] + 800928c: e01b b.n 80092c6 } else { vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) ); - 8004e0a: 4b10 ldr r3, [pc, #64] @ (8004e4c ) - 8004e0c: 681a ldr r2, [r3, #0] - 8004e0e: 68fb ldr r3, [r7, #12] - 8004e10: 3304 adds r3, #4 - 8004e12: 4619 mov r1, r3 - 8004e14: 4610 mov r0, r2 - 8004e16: f7fe f9b8 bl 800318a - 8004e1a: e012 b.n 8004e42 + 800928e: 4b10 ldr r3, [pc, #64] @ (80092d0 ) + 8009290: 681a ldr r2, [r3, #0] + 8009292: 68fb ldr r3, [r7, #12] + 8009294: 3304 adds r3, #4 + 8009296: 4619 mov r1, r3 + 8009298: 4610 mov r0, r2 + 800929a: f7fd fd1e bl 8006cda + 800929e: e012 b.n 80092c6 } } else { if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) ) - 8004e1c: 687a ldr r2, [r7, #4] - 8004e1e: 683b ldr r3, [r7, #0] - 8004e20: 429a cmp r2, r3 - 8004e22: d206 bcs.n 8004e32 - 8004e24: 68ba ldr r2, [r7, #8] - 8004e26: 683b ldr r3, [r7, #0] - 8004e28: 429a cmp r2, r3 - 8004e2a: d302 bcc.n 8004e32 + 80092a0: 687a ldr r2, [r7, #4] + 80092a2: 683b ldr r3, [r7, #0] + 80092a4: 429a cmp r2, r3 + 80092a6: d206 bcs.n 80092b6 + 80092a8: 68ba ldr r2, [r7, #8] + 80092aa: 683b ldr r3, [r7, #0] + 80092ac: 429a cmp r2, r3 + 80092ae: d302 bcc.n 80092b6 { /* If, since the command was issued, the tick count has overflowed but the expiry time has not, then the timer must have already passed its expiry time and should be processed immediately. */ xProcessTimerNow = pdTRUE; - 8004e2c: 2301 movs r3, #1 - 8004e2e: 617b str r3, [r7, #20] - 8004e30: e007 b.n 8004e42 + 80092b0: 2301 movs r3, #1 + 80092b2: 617b str r3, [r7, #20] + 80092b4: e007 b.n 80092c6 } else { vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); - 8004e32: 4b07 ldr r3, [pc, #28] @ (8004e50 ) - 8004e34: 681a ldr r2, [r3, #0] - 8004e36: 68fb ldr r3, [r7, #12] - 8004e38: 3304 adds r3, #4 - 8004e3a: 4619 mov r1, r3 - 8004e3c: 4610 mov r0, r2 - 8004e3e: f7fe f9a4 bl 800318a + 80092b6: 4b07 ldr r3, [pc, #28] @ (80092d4 ) + 80092b8: 681a ldr r2, [r3, #0] + 80092ba: 68fb ldr r3, [r7, #12] + 80092bc: 3304 adds r3, #4 + 80092be: 4619 mov r1, r3 + 80092c0: 4610 mov r0, r2 + 80092c2: f7fd fd0a bl 8006cda } } return xProcessTimerNow; - 8004e42: 697b ldr r3, [r7, #20] + 80092c6: 697b ldr r3, [r7, #20] } - 8004e44: 4618 mov r0, r3 - 8004e46: 3718 adds r7, #24 - 8004e48: 46bd mov sp, r7 - 8004e4a: bd80 pop {r7, pc} - 8004e4c: 20000e64 .word 0x20000e64 - 8004e50: 20000e60 .word 0x20000e60 + 80092c8: 4618 mov r0, r3 + 80092ca: 3718 adds r7, #24 + 80092cc: 46bd mov sp, r7 + 80092ce: bd80 pop {r7, pc} + 80092d0: 20000fec .word 0x20000fec + 80092d4: 20000fe8 .word 0x20000fe8 -08004e54 : +080092d8 : /*-----------------------------------------------------------*/ static void prvProcessReceivedCommands( void ) { - 8004e54: b580 push {r7, lr} - 8004e56: b08e sub sp, #56 @ 0x38 - 8004e58: af02 add r7, sp, #8 + 80092d8: b580 push {r7, lr} + 80092da: b08e sub sp, #56 @ 0x38 + 80092dc: af02 add r7, sp, #8 DaemonTaskMessage_t xMessage; Timer_t *pxTimer; BaseType_t xTimerListsWereSwitched, xResult; TickType_t xTimeNow; while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ - 8004e5a: e0ce b.n 8004ffa + 80092de: e0ce b.n 800947e { #if ( INCLUDE_xTimerPendFunctionCall == 1 ) { /* Negative commands are pended function calls rather than timer commands. */ if( xMessage.xMessageID < ( BaseType_t ) 0 ) - 8004e5c: 687b ldr r3, [r7, #4] - 8004e5e: 2b00 cmp r3, #0 - 8004e60: da19 bge.n 8004e96 + 80092e0: 687b ldr r3, [r7, #4] + 80092e2: 2b00 cmp r3, #0 + 80092e4: da19 bge.n 800931a { const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters ); - 8004e62: 1d3b adds r3, r7, #4 - 8004e64: 3304 adds r3, #4 - 8004e66: 62fb str r3, [r7, #44] @ 0x2c + 80092e6: 1d3b adds r3, r7, #4 + 80092e8: 3304 adds r3, #4 + 80092ea: 62fb str r3, [r7, #44] @ 0x2c /* The timer uses the xCallbackParameters member to request a callback be executed. Check the callback is not NULL. */ configASSERT( pxCallback ); - 8004e68: 6afb ldr r3, [r7, #44] @ 0x2c - 8004e6a: 2b00 cmp r3, #0 - 8004e6c: d10b bne.n 8004e86 + 80092ec: 6afb ldr r3, [r7, #44] @ 0x2c + 80092ee: 2b00 cmp r3, #0 + 80092f0: d10b bne.n 800930a __asm volatile - 8004e6e: f04f 0350 mov.w r3, #80 @ 0x50 - 8004e72: f383 8811 msr BASEPRI, r3 - 8004e76: f3bf 8f6f isb sy - 8004e7a: f3bf 8f4f dsb sy - 8004e7e: 61fb str r3, [r7, #28] + 80092f2: f04f 0350 mov.w r3, #80 @ 0x50 + 80092f6: f383 8811 msr BASEPRI, r3 + 80092fa: f3bf 8f6f isb sy + 80092fe: f3bf 8f4f dsb sy + 8009302: 61fb str r3, [r7, #28] } - 8004e80: bf00 nop - 8004e82: bf00 nop - 8004e84: e7fd b.n 8004e82 + 8009304: bf00 nop + 8009306: bf00 nop + 8009308: e7fd b.n 8009306 /* Call the function. */ pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 ); - 8004e86: 6afb ldr r3, [r7, #44] @ 0x2c - 8004e88: 681b ldr r3, [r3, #0] - 8004e8a: 6afa ldr r2, [r7, #44] @ 0x2c - 8004e8c: 6850 ldr r0, [r2, #4] - 8004e8e: 6afa ldr r2, [r7, #44] @ 0x2c - 8004e90: 6892 ldr r2, [r2, #8] - 8004e92: 4611 mov r1, r2 - 8004e94: 4798 blx r3 + 800930a: 6afb ldr r3, [r7, #44] @ 0x2c + 800930c: 681b ldr r3, [r3, #0] + 800930e: 6afa ldr r2, [r7, #44] @ 0x2c + 8009310: 6850 ldr r0, [r2, #4] + 8009312: 6afa ldr r2, [r7, #44] @ 0x2c + 8009314: 6892 ldr r2, [r2, #8] + 8009316: 4611 mov r1, r2 + 8009318: 4798 blx r3 } #endif /* INCLUDE_xTimerPendFunctionCall */ /* Commands that are positive are timer commands rather than pended function calls. */ if( xMessage.xMessageID >= ( BaseType_t ) 0 ) - 8004e96: 687b ldr r3, [r7, #4] - 8004e98: 2b00 cmp r3, #0 - 8004e9a: f2c0 80ae blt.w 8004ffa + 800931a: 687b ldr r3, [r7, #4] + 800931c: 2b00 cmp r3, #0 + 800931e: f2c0 80ae blt.w 800947e { /* The messages uses the xTimerParameters member to work on a software timer. */ pxTimer = xMessage.u.xTimerParameters.pxTimer; - 8004e9e: 68fb ldr r3, [r7, #12] - 8004ea0: 62bb str r3, [r7, #40] @ 0x28 + 8009322: 68fb ldr r3, [r7, #12] + 8009324: 62bb str r3, [r7, #40] @ 0x28 if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */ - 8004ea2: 6abb ldr r3, [r7, #40] @ 0x28 - 8004ea4: 695b ldr r3, [r3, #20] - 8004ea6: 2b00 cmp r3, #0 - 8004ea8: d004 beq.n 8004eb4 + 8009326: 6abb ldr r3, [r7, #40] @ 0x28 + 8009328: 695b ldr r3, [r3, #20] + 800932a: 2b00 cmp r3, #0 + 800932c: d004 beq.n 8009338 { /* The timer is in a list, remove it. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); - 8004eaa: 6abb ldr r3, [r7, #40] @ 0x28 - 8004eac: 3304 adds r3, #4 - 8004eae: 4618 mov r0, r3 - 8004eb0: f7fe f9a4 bl 80031fc + 800932e: 6abb ldr r3, [r7, #40] @ 0x28 + 8009330: 3304 adds r3, #4 + 8009332: 4618 mov r0, r3 + 8009334: f7fd fd0a bl 8006d4c it must be present in the function call. prvSampleTimeNow() must be called after the message is received from xTimerQueue so there is no possibility of a higher priority task adding a message to the message queue with a time that is ahead of the timer daemon task (because it pre-empted the timer daemon task after the xTimeNow value was set). */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); - 8004eb4: 463b mov r3, r7 - 8004eb6: 4618 mov r0, r3 - 8004eb8: f7ff ff6a bl 8004d90 - 8004ebc: 6278 str r0, [r7, #36] @ 0x24 + 8009338: 463b mov r3, r7 + 800933a: 4618 mov r0, r3 + 800933c: f7ff ff6a bl 8009214 + 8009340: 6278 str r0, [r7, #36] @ 0x24 switch( xMessage.xMessageID ) - 8004ebe: 687b ldr r3, [r7, #4] - 8004ec0: 2b09 cmp r3, #9 - 8004ec2: f200 8097 bhi.w 8004ff4 - 8004ec6: a201 add r2, pc, #4 @ (adr r2, 8004ecc ) - 8004ec8: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 8004ecc: 08004ef5 .word 0x08004ef5 - 8004ed0: 08004ef5 .word 0x08004ef5 - 8004ed4: 08004ef5 .word 0x08004ef5 - 8004ed8: 08004f6b .word 0x08004f6b - 8004edc: 08004f7f .word 0x08004f7f - 8004ee0: 08004fcb .word 0x08004fcb - 8004ee4: 08004ef5 .word 0x08004ef5 - 8004ee8: 08004ef5 .word 0x08004ef5 - 8004eec: 08004f6b .word 0x08004f6b - 8004ef0: 08004f7f .word 0x08004f7f + 8009342: 687b ldr r3, [r7, #4] + 8009344: 2b09 cmp r3, #9 + 8009346: f200 8097 bhi.w 8009478 + 800934a: a201 add r2, pc, #4 @ (adr r2, 8009350 ) + 800934c: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8009350: 08009379 .word 0x08009379 + 8009354: 08009379 .word 0x08009379 + 8009358: 08009379 .word 0x08009379 + 800935c: 080093ef .word 0x080093ef + 8009360: 08009403 .word 0x08009403 + 8009364: 0800944f .word 0x0800944f + 8009368: 08009379 .word 0x08009379 + 800936c: 08009379 .word 0x08009379 + 8009370: 080093ef .word 0x080093ef + 8009374: 08009403 .word 0x08009403 case tmrCOMMAND_START_FROM_ISR : case tmrCOMMAND_RESET : case tmrCOMMAND_RESET_FROM_ISR : case tmrCOMMAND_START_DONT_TRACE : /* Start or restart a timer. */ pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; - 8004ef4: 6abb ldr r3, [r7, #40] @ 0x28 - 8004ef6: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 - 8004efa: f043 0301 orr.w r3, r3, #1 - 8004efe: b2da uxtb r2, r3 - 8004f00: 6abb ldr r3, [r7, #40] @ 0x28 - 8004f02: f883 2028 strb.w r2, [r3, #40] @ 0x28 + 8009378: 6abb ldr r3, [r7, #40] @ 0x28 + 800937a: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 + 800937e: f043 0301 orr.w r3, r3, #1 + 8009382: b2da uxtb r2, r3 + 8009384: 6abb ldr r3, [r7, #40] @ 0x28 + 8009386: f883 2028 strb.w r2, [r3, #40] @ 0x28 if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE ) - 8004f06: 68ba ldr r2, [r7, #8] - 8004f08: 6abb ldr r3, [r7, #40] @ 0x28 - 8004f0a: 699b ldr r3, [r3, #24] - 8004f0c: 18d1 adds r1, r2, r3 - 8004f0e: 68bb ldr r3, [r7, #8] - 8004f10: 6a7a ldr r2, [r7, #36] @ 0x24 - 8004f12: 6ab8 ldr r0, [r7, #40] @ 0x28 - 8004f14: f7ff ff5c bl 8004dd0 - 8004f18: 4603 mov r3, r0 - 8004f1a: 2b00 cmp r3, #0 - 8004f1c: d06c beq.n 8004ff8 + 800938a: 68ba ldr r2, [r7, #8] + 800938c: 6abb ldr r3, [r7, #40] @ 0x28 + 800938e: 699b ldr r3, [r3, #24] + 8009390: 18d1 adds r1, r2, r3 + 8009392: 68bb ldr r3, [r7, #8] + 8009394: 6a7a ldr r2, [r7, #36] @ 0x24 + 8009396: 6ab8 ldr r0, [r7, #40] @ 0x28 + 8009398: f7ff ff5c bl 8009254 + 800939c: 4603 mov r3, r0 + 800939e: 2b00 cmp r3, #0 + 80093a0: d06c beq.n 800947c { /* The timer expired before it was added to the active timer list. Process it now. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); - 8004f1e: 6abb ldr r3, [r7, #40] @ 0x28 - 8004f20: 6a1b ldr r3, [r3, #32] - 8004f22: 6ab8 ldr r0, [r7, #40] @ 0x28 - 8004f24: 4798 blx r3 + 80093a2: 6abb ldr r3, [r7, #40] @ 0x28 + 80093a4: 6a1b ldr r3, [r3, #32] + 80093a6: 6ab8 ldr r0, [r7, #40] @ 0x28 + 80093a8: 4798 blx r3 traceTIMER_EXPIRED( pxTimer ); if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) - 8004f26: 6abb ldr r3, [r7, #40] @ 0x28 - 8004f28: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 - 8004f2c: f003 0304 and.w r3, r3, #4 - 8004f30: 2b00 cmp r3, #0 - 8004f32: d061 beq.n 8004ff8 + 80093aa: 6abb ldr r3, [r7, #40] @ 0x28 + 80093ac: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 + 80093b0: f003 0304 and.w r3, r3, #4 + 80093b4: 2b00 cmp r3, #0 + 80093b6: d061 beq.n 800947c { xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY ); - 8004f34: 68ba ldr r2, [r7, #8] - 8004f36: 6abb ldr r3, [r7, #40] @ 0x28 - 8004f38: 699b ldr r3, [r3, #24] - 8004f3a: 441a add r2, r3 - 8004f3c: 2300 movs r3, #0 - 8004f3e: 9300 str r3, [sp, #0] - 8004f40: 2300 movs r3, #0 - 8004f42: 2100 movs r1, #0 - 8004f44: 6ab8 ldr r0, [r7, #40] @ 0x28 - 8004f46: f7ff fe01 bl 8004b4c - 8004f4a: 6238 str r0, [r7, #32] + 80093b8: 68ba ldr r2, [r7, #8] + 80093ba: 6abb ldr r3, [r7, #40] @ 0x28 + 80093bc: 699b ldr r3, [r3, #24] + 80093be: 441a add r2, r3 + 80093c0: 2300 movs r3, #0 + 80093c2: 9300 str r3, [sp, #0] + 80093c4: 2300 movs r3, #0 + 80093c6: 2100 movs r1, #0 + 80093c8: 6ab8 ldr r0, [r7, #40] @ 0x28 + 80093ca: f7ff fe01 bl 8008fd0 + 80093ce: 6238 str r0, [r7, #32] configASSERT( xResult ); - 8004f4c: 6a3b ldr r3, [r7, #32] - 8004f4e: 2b00 cmp r3, #0 - 8004f50: d152 bne.n 8004ff8 + 80093d0: 6a3b ldr r3, [r7, #32] + 80093d2: 2b00 cmp r3, #0 + 80093d4: d152 bne.n 800947c __asm volatile - 8004f52: f04f 0350 mov.w r3, #80 @ 0x50 - 8004f56: f383 8811 msr BASEPRI, r3 - 8004f5a: f3bf 8f6f isb sy - 8004f5e: f3bf 8f4f dsb sy - 8004f62: 61bb str r3, [r7, #24] + 80093d6: f04f 0350 mov.w r3, #80 @ 0x50 + 80093da: f383 8811 msr BASEPRI, r3 + 80093de: f3bf 8f6f isb sy + 80093e2: f3bf 8f4f dsb sy + 80093e6: 61bb str r3, [r7, #24] } - 8004f64: bf00 nop - 8004f66: bf00 nop - 8004f68: e7fd b.n 8004f66 + 80093e8: bf00 nop + 80093ea: bf00 nop + 80093ec: e7fd b.n 80093ea break; case tmrCOMMAND_STOP : case tmrCOMMAND_STOP_FROM_ISR : /* The timer has already been removed from the active list. */ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; - 8004f6a: 6abb ldr r3, [r7, #40] @ 0x28 - 8004f6c: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 - 8004f70: f023 0301 bic.w r3, r3, #1 - 8004f74: b2da uxtb r2, r3 - 8004f76: 6abb ldr r3, [r7, #40] @ 0x28 - 8004f78: f883 2028 strb.w r2, [r3, #40] @ 0x28 + 80093ee: 6abb ldr r3, [r7, #40] @ 0x28 + 80093f0: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 + 80093f4: f023 0301 bic.w r3, r3, #1 + 80093f8: b2da uxtb r2, r3 + 80093fa: 6abb ldr r3, [r7, #40] @ 0x28 + 80093fc: f883 2028 strb.w r2, [r3, #40] @ 0x28 break; - 8004f7c: e03d b.n 8004ffa + 8009400: e03d b.n 800947e case tmrCOMMAND_CHANGE_PERIOD : case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR : pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; - 8004f7e: 6abb ldr r3, [r7, #40] @ 0x28 - 8004f80: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 - 8004f84: f043 0301 orr.w r3, r3, #1 - 8004f88: b2da uxtb r2, r3 - 8004f8a: 6abb ldr r3, [r7, #40] @ 0x28 - 8004f8c: f883 2028 strb.w r2, [r3, #40] @ 0x28 + 8009402: 6abb ldr r3, [r7, #40] @ 0x28 + 8009404: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 + 8009408: f043 0301 orr.w r3, r3, #1 + 800940c: b2da uxtb r2, r3 + 800940e: 6abb ldr r3, [r7, #40] @ 0x28 + 8009410: f883 2028 strb.w r2, [r3, #40] @ 0x28 pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue; - 8004f90: 68ba ldr r2, [r7, #8] - 8004f92: 6abb ldr r3, [r7, #40] @ 0x28 - 8004f94: 619a str r2, [r3, #24] + 8009414: 68ba ldr r2, [r7, #8] + 8009416: 6abb ldr r3, [r7, #40] @ 0x28 + 8009418: 619a str r2, [r3, #24] configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) ); - 8004f96: 6abb ldr r3, [r7, #40] @ 0x28 - 8004f98: 699b ldr r3, [r3, #24] - 8004f9a: 2b00 cmp r3, #0 - 8004f9c: d10b bne.n 8004fb6 + 800941a: 6abb ldr r3, [r7, #40] @ 0x28 + 800941c: 699b ldr r3, [r3, #24] + 800941e: 2b00 cmp r3, #0 + 8009420: d10b bne.n 800943a __asm volatile - 8004f9e: f04f 0350 mov.w r3, #80 @ 0x50 - 8004fa2: f383 8811 msr BASEPRI, r3 - 8004fa6: f3bf 8f6f isb sy - 8004faa: f3bf 8f4f dsb sy - 8004fae: 617b str r3, [r7, #20] + 8009422: f04f 0350 mov.w r3, #80 @ 0x50 + 8009426: f383 8811 msr BASEPRI, r3 + 800942a: f3bf 8f6f isb sy + 800942e: f3bf 8f4f dsb sy + 8009432: 617b str r3, [r7, #20] } - 8004fb0: bf00 nop - 8004fb2: bf00 nop - 8004fb4: e7fd b.n 8004fb2 + 8009434: bf00 nop + 8009436: bf00 nop + 8009438: e7fd b.n 8009436 be longer or shorter than the old one. The command time is therefore set to the current time, and as the period cannot be zero the next expiry time can only be in the future, meaning (unlike for the xTimerStart() case above) there is no fail case that needs to be handled here. */ ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow ); - 8004fb6: 6abb ldr r3, [r7, #40] @ 0x28 - 8004fb8: 699a ldr r2, [r3, #24] - 8004fba: 6a7b ldr r3, [r7, #36] @ 0x24 - 8004fbc: 18d1 adds r1, r2, r3 - 8004fbe: 6a7b ldr r3, [r7, #36] @ 0x24 - 8004fc0: 6a7a ldr r2, [r7, #36] @ 0x24 - 8004fc2: 6ab8 ldr r0, [r7, #40] @ 0x28 - 8004fc4: f7ff ff04 bl 8004dd0 + 800943a: 6abb ldr r3, [r7, #40] @ 0x28 + 800943c: 699a ldr r2, [r3, #24] + 800943e: 6a7b ldr r3, [r7, #36] @ 0x24 + 8009440: 18d1 adds r1, r2, r3 + 8009442: 6a7b ldr r3, [r7, #36] @ 0x24 + 8009444: 6a7a ldr r2, [r7, #36] @ 0x24 + 8009446: 6ab8 ldr r0, [r7, #40] @ 0x28 + 8009448: f7ff ff04 bl 8009254 break; - 8004fc8: e017 b.n 8004ffa + 800944c: e017 b.n 800947e #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* The timer has already been removed from the active list, just free up the memory if the memory was dynamically allocated. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 ) - 8004fca: 6abb ldr r3, [r7, #40] @ 0x28 - 8004fcc: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 - 8004fd0: f003 0302 and.w r3, r3, #2 - 8004fd4: 2b00 cmp r3, #0 - 8004fd6: d103 bne.n 8004fe0 + 800944e: 6abb ldr r3, [r7, #40] @ 0x28 + 8009450: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 + 8009454: f003 0302 and.w r3, r3, #2 + 8009458: 2b00 cmp r3, #0 + 800945a: d103 bne.n 8009464 { vPortFree( pxTimer ); - 8004fd8: 6ab8 ldr r0, [r7, #40] @ 0x28 - 8004fda: f000 fbe5 bl 80057a8 + 800945c: 6ab8 ldr r0, [r7, #40] @ 0x28 + 800945e: f000 fc0b bl 8009c78 no need to free the memory - just mark the timer as "not active". */ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ break; - 8004fde: e00c b.n 8004ffa + 8009462: e00c b.n 800947e pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; - 8004fe0: 6abb ldr r3, [r7, #40] @ 0x28 - 8004fe2: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 - 8004fe6: f023 0301 bic.w r3, r3, #1 - 8004fea: b2da uxtb r2, r3 - 8004fec: 6abb ldr r3, [r7, #40] @ 0x28 - 8004fee: f883 2028 strb.w r2, [r3, #40] @ 0x28 + 8009464: 6abb ldr r3, [r7, #40] @ 0x28 + 8009466: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 + 800946a: f023 0301 bic.w r3, r3, #1 + 800946e: b2da uxtb r2, r3 + 8009470: 6abb ldr r3, [r7, #40] @ 0x28 + 8009472: f883 2028 strb.w r2, [r3, #40] @ 0x28 break; - 8004ff2: e002 b.n 8004ffa + 8009476: e002 b.n 800947e default : /* Don't expect to get here. */ break; - 8004ff4: bf00 nop - 8004ff6: e000 b.n 8004ffa + 8009478: bf00 nop + 800947a: e000 b.n 800947e break; - 8004ff8: bf00 nop + 800947c: bf00 nop while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ - 8004ffa: 4b08 ldr r3, [pc, #32] @ (800501c ) - 8004ffc: 681b ldr r3, [r3, #0] - 8004ffe: 1d39 adds r1, r7, #4 - 8005000: 2200 movs r2, #0 - 8005002: 4618 mov r0, r3 - 8005004: f7fe fbce bl 80037a4 - 8005008: 4603 mov r3, r0 - 800500a: 2b00 cmp r3, #0 - 800500c: f47f af26 bne.w 8004e5c + 800947e: 4b08 ldr r3, [pc, #32] @ (80094a0 ) + 8009480: 681b ldr r3, [r3, #0] + 8009482: 1d39 adds r1, r7, #4 + 8009484: 2200 movs r2, #0 + 8009486: 4618 mov r0, r3 + 8009488: f7fe f86e bl 8007568 + 800948c: 4603 mov r3, r0 + 800948e: 2b00 cmp r3, #0 + 8009490: f47f af26 bne.w 80092e0 } } } } - 8005010: bf00 nop - 8005012: bf00 nop - 8005014: 3730 adds r7, #48 @ 0x30 - 8005016: 46bd mov sp, r7 - 8005018: bd80 pop {r7, pc} - 800501a: bf00 nop - 800501c: 20000e68 .word 0x20000e68 + 8009494: bf00 nop + 8009496: bf00 nop + 8009498: 3730 adds r7, #48 @ 0x30 + 800949a: 46bd mov sp, r7 + 800949c: bd80 pop {r7, pc} + 800949e: bf00 nop + 80094a0: 20000ff0 .word 0x20000ff0 -08005020 : +080094a4 : /*-----------------------------------------------------------*/ static void prvSwitchTimerLists( void ) { - 8005020: b580 push {r7, lr} - 8005022: b088 sub sp, #32 - 8005024: af02 add r7, sp, #8 + 80094a4: b580 push {r7, lr} + 80094a6: b088 sub sp, #32 + 80094a8: af02 add r7, sp, #8 /* The tick count has overflowed. The timer lists must be switched. If there are any timers still referenced from the current timer list then they must have expired and should be processed before the lists are switched. */ while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) - 8005026: e049 b.n 80050bc + 80094aa: e049 b.n 8009540 { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); - 8005028: 4b2e ldr r3, [pc, #184] @ (80050e4 ) - 800502a: 681b ldr r3, [r3, #0] - 800502c: 68db ldr r3, [r3, #12] - 800502e: 681b ldr r3, [r3, #0] - 8005030: 613b str r3, [r7, #16] + 80094ac: 4b2e ldr r3, [pc, #184] @ (8009568 ) + 80094ae: 681b ldr r3, [r3, #0] + 80094b0: 68db ldr r3, [r3, #12] + 80094b2: 681b ldr r3, [r3, #0] + 80094b4: 613b str r3, [r7, #16] /* Remove the timer from the list. */ pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ - 8005032: 4b2c ldr r3, [pc, #176] @ (80050e4 ) - 8005034: 681b ldr r3, [r3, #0] - 8005036: 68db ldr r3, [r3, #12] - 8005038: 68db ldr r3, [r3, #12] - 800503a: 60fb str r3, [r7, #12] + 80094b6: 4b2c ldr r3, [pc, #176] @ (8009568 ) + 80094b8: 681b ldr r3, [r3, #0] + 80094ba: 68db ldr r3, [r3, #12] + 80094bc: 68db ldr r3, [r3, #12] + 80094be: 60fb str r3, [r7, #12] ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); - 800503c: 68fb ldr r3, [r7, #12] - 800503e: 3304 adds r3, #4 - 8005040: 4618 mov r0, r3 - 8005042: f7fe f8db bl 80031fc + 80094c0: 68fb ldr r3, [r7, #12] + 80094c2: 3304 adds r3, #4 + 80094c4: 4618 mov r0, r3 + 80094c6: f7fd fc41 bl 8006d4c traceTIMER_EXPIRED( pxTimer ); /* Execute its callback, then send a command to restart the timer if it is an auto-reload timer. It cannot be restarted here as the lists have not yet been switched. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); - 8005046: 68fb ldr r3, [r7, #12] - 8005048: 6a1b ldr r3, [r3, #32] - 800504a: 68f8 ldr r0, [r7, #12] - 800504c: 4798 blx r3 + 80094ca: 68fb ldr r3, [r7, #12] + 80094cc: 6a1b ldr r3, [r3, #32] + 80094ce: 68f8 ldr r0, [r7, #12] + 80094d0: 4798 blx r3 if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) - 800504e: 68fb ldr r3, [r7, #12] - 8005050: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 - 8005054: f003 0304 and.w r3, r3, #4 - 8005058: 2b00 cmp r3, #0 - 800505a: d02f beq.n 80050bc + 80094d2: 68fb ldr r3, [r7, #12] + 80094d4: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 + 80094d8: f003 0304 and.w r3, r3, #4 + 80094dc: 2b00 cmp r3, #0 + 80094de: d02f beq.n 8009540 the timer going into the same timer list then it has already expired and the timer should be re-inserted into the current list so it is processed again within this loop. Otherwise a command should be sent to restart the timer to ensure it is only inserted into a list after the lists have been swapped. */ xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ); - 800505c: 68fb ldr r3, [r7, #12] - 800505e: 699b ldr r3, [r3, #24] - 8005060: 693a ldr r2, [r7, #16] - 8005062: 4413 add r3, r2 - 8005064: 60bb str r3, [r7, #8] + 80094e0: 68fb ldr r3, [r7, #12] + 80094e2: 699b ldr r3, [r3, #24] + 80094e4: 693a ldr r2, [r7, #16] + 80094e6: 4413 add r3, r2 + 80094e8: 60bb str r3, [r7, #8] if( xReloadTime > xNextExpireTime ) - 8005066: 68ba ldr r2, [r7, #8] - 8005068: 693b ldr r3, [r7, #16] - 800506a: 429a cmp r2, r3 - 800506c: d90e bls.n 800508c + 80094ea: 68ba ldr r2, [r7, #8] + 80094ec: 693b ldr r3, [r7, #16] + 80094ee: 429a cmp r2, r3 + 80094f0: d90e bls.n 8009510 { listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime ); - 800506e: 68fb ldr r3, [r7, #12] - 8005070: 68ba ldr r2, [r7, #8] - 8005072: 605a str r2, [r3, #4] + 80094f2: 68fb ldr r3, [r7, #12] + 80094f4: 68ba ldr r2, [r7, #8] + 80094f6: 605a str r2, [r3, #4] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); - 8005074: 68fb ldr r3, [r7, #12] - 8005076: 68fa ldr r2, [r7, #12] - 8005078: 611a str r2, [r3, #16] + 80094f8: 68fb ldr r3, [r7, #12] + 80094fa: 68fa ldr r2, [r7, #12] + 80094fc: 611a str r2, [r3, #16] vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); - 800507a: 4b1a ldr r3, [pc, #104] @ (80050e4 ) - 800507c: 681a ldr r2, [r3, #0] - 800507e: 68fb ldr r3, [r7, #12] - 8005080: 3304 adds r3, #4 - 8005082: 4619 mov r1, r3 - 8005084: 4610 mov r0, r2 - 8005086: f7fe f880 bl 800318a - 800508a: e017 b.n 80050bc + 80094fe: 4b1a ldr r3, [pc, #104] @ (8009568 ) + 8009500: 681a ldr r2, [r3, #0] + 8009502: 68fb ldr r3, [r7, #12] + 8009504: 3304 adds r3, #4 + 8009506: 4619 mov r1, r3 + 8009508: 4610 mov r0, r2 + 800950a: f7fd fbe6 bl 8006cda + 800950e: e017 b.n 8009540 } else { xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); - 800508c: 2300 movs r3, #0 - 800508e: 9300 str r3, [sp, #0] - 8005090: 2300 movs r3, #0 - 8005092: 693a ldr r2, [r7, #16] - 8005094: 2100 movs r1, #0 - 8005096: 68f8 ldr r0, [r7, #12] - 8005098: f7ff fd58 bl 8004b4c - 800509c: 6078 str r0, [r7, #4] + 8009510: 2300 movs r3, #0 + 8009512: 9300 str r3, [sp, #0] + 8009514: 2300 movs r3, #0 + 8009516: 693a ldr r2, [r7, #16] + 8009518: 2100 movs r1, #0 + 800951a: 68f8 ldr r0, [r7, #12] + 800951c: f7ff fd58 bl 8008fd0 + 8009520: 6078 str r0, [r7, #4] configASSERT( xResult ); - 800509e: 687b ldr r3, [r7, #4] - 80050a0: 2b00 cmp r3, #0 - 80050a2: d10b bne.n 80050bc + 8009522: 687b ldr r3, [r7, #4] + 8009524: 2b00 cmp r3, #0 + 8009526: d10b bne.n 8009540 __asm volatile - 80050a4: f04f 0350 mov.w r3, #80 @ 0x50 - 80050a8: f383 8811 msr BASEPRI, r3 - 80050ac: f3bf 8f6f isb sy - 80050b0: f3bf 8f4f dsb sy - 80050b4: 603b str r3, [r7, #0] + 8009528: f04f 0350 mov.w r3, #80 @ 0x50 + 800952c: f383 8811 msr BASEPRI, r3 + 8009530: f3bf 8f6f isb sy + 8009534: f3bf 8f4f dsb sy + 8009538: 603b str r3, [r7, #0] } - 80050b6: bf00 nop - 80050b8: bf00 nop - 80050ba: e7fd b.n 80050b8 + 800953a: bf00 nop + 800953c: bf00 nop + 800953e: e7fd b.n 800953c while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) - 80050bc: 4b09 ldr r3, [pc, #36] @ (80050e4 ) - 80050be: 681b ldr r3, [r3, #0] - 80050c0: 681b ldr r3, [r3, #0] - 80050c2: 2b00 cmp r3, #0 - 80050c4: d1b0 bne.n 8005028 + 8009540: 4b09 ldr r3, [pc, #36] @ (8009568 ) + 8009542: 681b ldr r3, [r3, #0] + 8009544: 681b ldr r3, [r3, #0] + 8009546: 2b00 cmp r3, #0 + 8009548: d1b0 bne.n 80094ac { mtCOVERAGE_TEST_MARKER(); } } pxTemp = pxCurrentTimerList; - 80050c6: 4b07 ldr r3, [pc, #28] @ (80050e4 ) - 80050c8: 681b ldr r3, [r3, #0] - 80050ca: 617b str r3, [r7, #20] + 800954a: 4b07 ldr r3, [pc, #28] @ (8009568 ) + 800954c: 681b ldr r3, [r3, #0] + 800954e: 617b str r3, [r7, #20] pxCurrentTimerList = pxOverflowTimerList; - 80050cc: 4b06 ldr r3, [pc, #24] @ (80050e8 ) - 80050ce: 681b ldr r3, [r3, #0] - 80050d0: 4a04 ldr r2, [pc, #16] @ (80050e4 ) - 80050d2: 6013 str r3, [r2, #0] + 8009550: 4b06 ldr r3, [pc, #24] @ (800956c ) + 8009552: 681b ldr r3, [r3, #0] + 8009554: 4a04 ldr r2, [pc, #16] @ (8009568 ) + 8009556: 6013 str r3, [r2, #0] pxOverflowTimerList = pxTemp; - 80050d4: 4a04 ldr r2, [pc, #16] @ (80050e8 ) - 80050d6: 697b ldr r3, [r7, #20] - 80050d8: 6013 str r3, [r2, #0] + 8009558: 4a04 ldr r2, [pc, #16] @ (800956c ) + 800955a: 697b ldr r3, [r7, #20] + 800955c: 6013 str r3, [r2, #0] } - 80050da: bf00 nop - 80050dc: 3718 adds r7, #24 - 80050de: 46bd mov sp, r7 - 80050e0: bd80 pop {r7, pc} - 80050e2: bf00 nop - 80050e4: 20000e60 .word 0x20000e60 - 80050e8: 20000e64 .word 0x20000e64 + 800955e: bf00 nop + 8009560: 3718 adds r7, #24 + 8009562: 46bd mov sp, r7 + 8009564: bd80 pop {r7, pc} + 8009566: bf00 nop + 8009568: 20000fe8 .word 0x20000fe8 + 800956c: 20000fec .word 0x20000fec -080050ec : +08009570 : /*-----------------------------------------------------------*/ static void prvCheckForValidListAndQueue( void ) { - 80050ec: b580 push {r7, lr} - 80050ee: b082 sub sp, #8 - 80050f0: af02 add r7, sp, #8 + 8009570: b580 push {r7, lr} + 8009572: b082 sub sp, #8 + 8009574: af02 add r7, sp, #8 /* Check that the list from which active timers are referenced, and the queue used to communicate with the timer service, have been initialised. */ taskENTER_CRITICAL(); - 80050f2: f000 f969 bl 80053c8 + 8009576: f000 f98f bl 8009898 { if( xTimerQueue == NULL ) - 80050f6: 4b15 ldr r3, [pc, #84] @ (800514c ) - 80050f8: 681b ldr r3, [r3, #0] - 80050fa: 2b00 cmp r3, #0 - 80050fc: d120 bne.n 8005140 + 800957a: 4b15 ldr r3, [pc, #84] @ (80095d0 ) + 800957c: 681b ldr r3, [r3, #0] + 800957e: 2b00 cmp r3, #0 + 8009580: d120 bne.n 80095c4 { vListInitialise( &xActiveTimerList1 ); - 80050fe: 4814 ldr r0, [pc, #80] @ (8005150 ) - 8005100: f7fd fff2 bl 80030e8 + 8009582: 4814 ldr r0, [pc, #80] @ (80095d4 ) + 8009584: f7fd fb58 bl 8006c38 vListInitialise( &xActiveTimerList2 ); - 8005104: 4813 ldr r0, [pc, #76] @ (8005154 ) - 8005106: f7fd ffef bl 80030e8 + 8009588: 4813 ldr r0, [pc, #76] @ (80095d8 ) + 800958a: f7fd fb55 bl 8006c38 pxCurrentTimerList = &xActiveTimerList1; - 800510a: 4b13 ldr r3, [pc, #76] @ (8005158 ) - 800510c: 4a10 ldr r2, [pc, #64] @ (8005150 ) - 800510e: 601a str r2, [r3, #0] + 800958e: 4b13 ldr r3, [pc, #76] @ (80095dc ) + 8009590: 4a10 ldr r2, [pc, #64] @ (80095d4 ) + 8009592: 601a str r2, [r3, #0] pxOverflowTimerList = &xActiveTimerList2; - 8005110: 4b12 ldr r3, [pc, #72] @ (800515c ) - 8005112: 4a10 ldr r2, [pc, #64] @ (8005154 ) - 8005114: 601a str r2, [r3, #0] + 8009594: 4b12 ldr r3, [pc, #72] @ (80095e0 ) + 8009596: 4a10 ldr r2, [pc, #64] @ (80095d8 ) + 8009598: 601a str r2, [r3, #0] /* The timer queue is allocated statically in case configSUPPORT_DYNAMIC_ALLOCATION is 0. */ static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); - 8005116: 2300 movs r3, #0 - 8005118: 9300 str r3, [sp, #0] - 800511a: 4b11 ldr r3, [pc, #68] @ (8005160 ) - 800511c: 4a11 ldr r2, [pc, #68] @ (8005164 ) - 800511e: 2110 movs r1, #16 - 8005120: 200a movs r0, #10 - 8005122: f7fe f8ff bl 8003324 - 8005126: 4603 mov r3, r0 - 8005128: 4a08 ldr r2, [pc, #32] @ (800514c ) - 800512a: 6013 str r3, [r2, #0] + 800959a: 2300 movs r3, #0 + 800959c: 9300 str r3, [sp, #0] + 800959e: 4b11 ldr r3, [pc, #68] @ (80095e4 ) + 80095a0: 4a11 ldr r2, [pc, #68] @ (80095e8 ) + 80095a2: 2110 movs r1, #16 + 80095a4: 200a movs r0, #10 + 80095a6: f7fd fc65 bl 8006e74 + 80095aa: 4603 mov r3, r0 + 80095ac: 4a08 ldr r2, [pc, #32] @ (80095d0 ) + 80095ae: 6013 str r3, [r2, #0] } #endif #if ( configQUEUE_REGISTRY_SIZE > 0 ) { if( xTimerQueue != NULL ) - 800512c: 4b07 ldr r3, [pc, #28] @ (800514c ) - 800512e: 681b ldr r3, [r3, #0] - 8005130: 2b00 cmp r3, #0 - 8005132: d005 beq.n 8005140 + 80095b0: 4b07 ldr r3, [pc, #28] @ (80095d0 ) + 80095b2: 681b ldr r3, [r3, #0] + 80095b4: 2b00 cmp r3, #0 + 80095b6: d005 beq.n 80095c4 { vQueueAddToRegistry( xTimerQueue, "TmrQ" ); - 8005134: 4b05 ldr r3, [pc, #20] @ (800514c ) - 8005136: 681b ldr r3, [r3, #0] - 8005138: 490b ldr r1, [pc, #44] @ (8005168 ) - 800513a: 4618 mov r0, r3 - 800513c: f7fe fd24 bl 8003b88 + 80095b8: 4b05 ldr r3, [pc, #20] @ (80095d0 ) + 80095ba: 681b ldr r3, [r3, #0] + 80095bc: 490b ldr r1, [pc, #44] @ (80095ec ) + 80095be: 4618 mov r0, r3 + 80095c0: f7fe fb92 bl 8007ce8 else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); - 8005140: f000 f974 bl 800542c + 80095c4: f000 f99a bl 80098fc } - 8005144: bf00 nop - 8005146: 46bd mov sp, r7 - 8005148: bd80 pop {r7, pc} - 800514a: bf00 nop - 800514c: 20000e68 .word 0x20000e68 - 8005150: 20000e38 .word 0x20000e38 - 8005154: 20000e4c .word 0x20000e4c - 8005158: 20000e60 .word 0x20000e60 - 800515c: 20000e64 .word 0x20000e64 - 8005160: 20000f14 .word 0x20000f14 - 8005164: 20000e74 .word 0x20000e74 - 8005168: 08005d18 .word 0x08005d18 + 80095c8: bf00 nop + 80095ca: 46bd mov sp, r7 + 80095cc: bd80 pop {r7, pc} + 80095ce: bf00 nop + 80095d0: 20000ff0 .word 0x20000ff0 + 80095d4: 20000fc0 .word 0x20000fc0 + 80095d8: 20000fd4 .word 0x20000fd4 + 80095dc: 20000fe8 .word 0x20000fe8 + 80095e0: 20000fec .word 0x20000fec + 80095e4: 2000109c .word 0x2000109c + 80095e8: 20000ffc .word 0x20000ffc + 80095ec: 0800a298 .word 0x0800a298 -0800516c : +080095f0 : + return xReturn; +} /*lint !e818 Can't be pointer to const due to the typedef. */ +/*-----------------------------------------------------------*/ + +void *pvTimerGetTimerID( const TimerHandle_t xTimer ) +{ + 80095f0: b580 push {r7, lr} + 80095f2: b086 sub sp, #24 + 80095f4: af00 add r7, sp, #0 + 80095f6: 6078 str r0, [r7, #4] +Timer_t * const pxTimer = xTimer; + 80095f8: 687b ldr r3, [r7, #4] + 80095fa: 617b str r3, [r7, #20] +void *pvReturn; + + configASSERT( xTimer ); + 80095fc: 687b ldr r3, [r7, #4] + 80095fe: 2b00 cmp r3, #0 + 8009600: d10b bne.n 800961a + __asm volatile + 8009602: f04f 0350 mov.w r3, #80 @ 0x50 + 8009606: f383 8811 msr BASEPRI, r3 + 800960a: f3bf 8f6f isb sy + 800960e: f3bf 8f4f dsb sy + 8009612: 60fb str r3, [r7, #12] +} + 8009614: bf00 nop + 8009616: bf00 nop + 8009618: e7fd b.n 8009616 + + taskENTER_CRITICAL(); + 800961a: f000 f93d bl 8009898 + { + pvReturn = pxTimer->pvTimerID; + 800961e: 697b ldr r3, [r7, #20] + 8009620: 69db ldr r3, [r3, #28] + 8009622: 613b str r3, [r7, #16] + } + taskEXIT_CRITICAL(); + 8009624: f000 f96a bl 80098fc + + return pvReturn; + 8009628: 693b ldr r3, [r7, #16] +} + 800962a: 4618 mov r0, r3 + 800962c: 3718 adds r7, #24 + 800962e: 46bd mov sp, r7 + 8009630: bd80 pop {r7, pc} + ... + +08009634 : /* * See header file for description. */ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) { - 800516c: b480 push {r7} - 800516e: b085 sub sp, #20 - 8005170: af00 add r7, sp, #0 - 8005172: 60f8 str r0, [r7, #12] - 8005174: 60b9 str r1, [r7, #8] - 8005176: 607a str r2, [r7, #4] + 8009634: b480 push {r7} + 8009636: b085 sub sp, #20 + 8009638: af00 add r7, sp, #0 + 800963a: 60f8 str r0, [r7, #12] + 800963c: 60b9 str r1, [r7, #8] + 800963e: 607a str r2, [r7, #4] /* Simulate the stack frame as it would be created by a context switch interrupt. */ /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts, and to ensure alignment. */ pxTopOfStack--; - 8005178: 68fb ldr r3, [r7, #12] - 800517a: 3b04 subs r3, #4 - 800517c: 60fb str r3, [r7, #12] + 8009640: 68fb ldr r3, [r7, #12] + 8009642: 3b04 subs r3, #4 + 8009644: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ - 800517e: 68fb ldr r3, [r7, #12] - 8005180: f04f 7280 mov.w r2, #16777216 @ 0x1000000 - 8005184: 601a str r2, [r3, #0] + 8009646: 68fb ldr r3, [r7, #12] + 8009648: f04f 7280 mov.w r2, #16777216 @ 0x1000000 + 800964c: 601a str r2, [r3, #0] pxTopOfStack--; - 8005186: 68fb ldr r3, [r7, #12] - 8005188: 3b04 subs r3, #4 - 800518a: 60fb str r3, [r7, #12] + 800964e: 68fb ldr r3, [r7, #12] + 8009650: 3b04 subs r3, #4 + 8009652: 60fb str r3, [r7, #12] *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ - 800518c: 68bb ldr r3, [r7, #8] - 800518e: f023 0201 bic.w r2, r3, #1 - 8005192: 68fb ldr r3, [r7, #12] - 8005194: 601a str r2, [r3, #0] + 8009654: 68bb ldr r3, [r7, #8] + 8009656: f023 0201 bic.w r2, r3, #1 + 800965a: 68fb ldr r3, [r7, #12] + 800965c: 601a str r2, [r3, #0] pxTopOfStack--; - 8005196: 68fb ldr r3, [r7, #12] - 8005198: 3b04 subs r3, #4 - 800519a: 60fb str r3, [r7, #12] + 800965e: 68fb ldr r3, [r7, #12] + 8009660: 3b04 subs r3, #4 + 8009662: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ - 800519c: 4a0c ldr r2, [pc, #48] @ (80051d0 ) - 800519e: 68fb ldr r3, [r7, #12] - 80051a0: 601a str r2, [r3, #0] + 8009664: 4a0c ldr r2, [pc, #48] @ (8009698 ) + 8009666: 68fb ldr r3, [r7, #12] + 8009668: 601a str r2, [r3, #0] /* Save code space by skipping register initialisation. */ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ - 80051a2: 68fb ldr r3, [r7, #12] - 80051a4: 3b14 subs r3, #20 - 80051a6: 60fb str r3, [r7, #12] + 800966a: 68fb ldr r3, [r7, #12] + 800966c: 3b14 subs r3, #20 + 800966e: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ - 80051a8: 687a ldr r2, [r7, #4] - 80051aa: 68fb ldr r3, [r7, #12] - 80051ac: 601a str r2, [r3, #0] + 8009670: 687a ldr r2, [r7, #4] + 8009672: 68fb ldr r3, [r7, #12] + 8009674: 601a str r2, [r3, #0] /* A save method is being used that requires each task to maintain its own exec return value. */ pxTopOfStack--; - 80051ae: 68fb ldr r3, [r7, #12] - 80051b0: 3b04 subs r3, #4 - 80051b2: 60fb str r3, [r7, #12] + 8009676: 68fb ldr r3, [r7, #12] + 8009678: 3b04 subs r3, #4 + 800967a: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_EXC_RETURN; - 80051b4: 68fb ldr r3, [r7, #12] - 80051b6: f06f 0202 mvn.w r2, #2 - 80051ba: 601a str r2, [r3, #0] + 800967c: 68fb ldr r3, [r7, #12] + 800967e: f06f 0202 mvn.w r2, #2 + 8009682: 601a str r2, [r3, #0] pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ - 80051bc: 68fb ldr r3, [r7, #12] - 80051be: 3b20 subs r3, #32 - 80051c0: 60fb str r3, [r7, #12] + 8009684: 68fb ldr r3, [r7, #12] + 8009686: 3b20 subs r3, #32 + 8009688: 60fb str r3, [r7, #12] return pxTopOfStack; - 80051c2: 68fb ldr r3, [r7, #12] + 800968a: 68fb ldr r3, [r7, #12] } - 80051c4: 4618 mov r0, r3 - 80051c6: 3714 adds r7, #20 - 80051c8: 46bd mov sp, r7 - 80051ca: f85d 7b04 ldr.w r7, [sp], #4 - 80051ce: 4770 bx lr - 80051d0: 080051d5 .word 0x080051d5 + 800968c: 4618 mov r0, r3 + 800968e: 3714 adds r7, #20 + 8009690: 46bd mov sp, r7 + 8009692: f85d 7b04 ldr.w r7, [sp], #4 + 8009696: 4770 bx lr + 8009698: 0800969d .word 0x0800969d -080051d4 : +0800969c : /*-----------------------------------------------------------*/ static void prvTaskExitError( void ) { - 80051d4: b480 push {r7} - 80051d6: b085 sub sp, #20 - 80051d8: af00 add r7, sp, #0 + 800969c: b480 push {r7} + 800969e: b085 sub sp, #20 + 80096a0: af00 add r7, sp, #0 volatile uint32_t ulDummy = 0; - 80051da: 2300 movs r3, #0 - 80051dc: 607b str r3, [r7, #4] + 80096a2: 2300 movs r3, #0 + 80096a4: 607b str r3, [r7, #4] its caller as there is nothing to return to. If a task wants to exit it should instead call vTaskDelete( NULL ). Artificially force an assert() to be triggered if configASSERT() is defined, then stop here so application writers can catch the error. */ configASSERT( uxCriticalNesting == ~0UL ); - 80051de: 4b13 ldr r3, [pc, #76] @ (800522c ) - 80051e0: 681b ldr r3, [r3, #0] - 80051e2: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff - 80051e6: d00b beq.n 8005200 + 80096a6: 4b13 ldr r3, [pc, #76] @ (80096f4 ) + 80096a8: 681b ldr r3, [r3, #0] + 80096aa: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 80096ae: d00b beq.n 80096c8 __asm volatile - 80051e8: f04f 0350 mov.w r3, #80 @ 0x50 - 80051ec: f383 8811 msr BASEPRI, r3 - 80051f0: f3bf 8f6f isb sy - 80051f4: f3bf 8f4f dsb sy - 80051f8: 60fb str r3, [r7, #12] + 80096b0: f04f 0350 mov.w r3, #80 @ 0x50 + 80096b4: f383 8811 msr BASEPRI, r3 + 80096b8: f3bf 8f6f isb sy + 80096bc: f3bf 8f4f dsb sy + 80096c0: 60fb str r3, [r7, #12] } - 80051fa: bf00 nop - 80051fc: bf00 nop - 80051fe: e7fd b.n 80051fc + 80096c2: bf00 nop + 80096c4: bf00 nop + 80096c6: e7fd b.n 80096c4 __asm volatile - 8005200: f04f 0350 mov.w r3, #80 @ 0x50 - 8005204: f383 8811 msr BASEPRI, r3 - 8005208: f3bf 8f6f isb sy - 800520c: f3bf 8f4f dsb sy - 8005210: 60bb str r3, [r7, #8] + 80096c8: f04f 0350 mov.w r3, #80 @ 0x50 + 80096cc: f383 8811 msr BASEPRI, r3 + 80096d0: f3bf 8f6f isb sy + 80096d4: f3bf 8f4f dsb sy + 80096d8: 60bb str r3, [r7, #8] } - 8005212: bf00 nop + 80096da: bf00 nop portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) - 8005214: bf00 nop - 8005216: 687b ldr r3, [r7, #4] - 8005218: 2b00 cmp r3, #0 - 800521a: d0fc beq.n 8005216 + 80096dc: bf00 nop + 80096de: 687b ldr r3, [r7, #4] + 80096e0: 2b00 cmp r3, #0 + 80096e2: d0fc beq.n 80096de about code appearing after this function is called - making ulDummy volatile makes the compiler think the function could return and therefore not output an 'unreachable code' warning for code that appears after it. */ } } - 800521c: bf00 nop - 800521e: bf00 nop - 8005220: 3714 adds r7, #20 - 8005222: 46bd mov sp, r7 - 8005224: f85d 7b04 ldr.w r7, [sp], #4 - 8005228: 4770 bx lr - 800522a: bf00 nop - 800522c: 2000000c .word 0x2000000c + 80096e4: bf00 nop + 80096e6: bf00 nop + 80096e8: 3714 adds r7, #20 + 80096ea: 46bd mov sp, r7 + 80096ec: f85d 7b04 ldr.w r7, [sp], #4 + 80096f0: 4770 bx lr + 80096f2: bf00 nop + 80096f4: 20000024 .word 0x20000024 + ... -08005230 : +08009700 : /*-----------------------------------------------------------*/ void vPortSVCHandler( void ) { __asm volatile ( - 8005230: 4b07 ldr r3, [pc, #28] @ (8005250 ) - 8005232: 6819 ldr r1, [r3, #0] - 8005234: 6808 ldr r0, [r1, #0] - 8005236: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 800523a: f380 8809 msr PSP, r0 - 800523e: f3bf 8f6f isb sy - 8005242: f04f 0000 mov.w r0, #0 - 8005246: f380 8811 msr BASEPRI, r0 - 800524a: 4770 bx lr - 800524c: f3af 8000 nop.w + 8009700: 4b07 ldr r3, [pc, #28] @ (8009720 ) + 8009702: 6819 ldr r1, [r3, #0] + 8009704: 6808 ldr r0, [r1, #0] + 8009706: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800970a: f380 8809 msr PSP, r0 + 800970e: f3bf 8f6f isb sy + 8009712: f04f 0000 mov.w r0, #0 + 8009716: f380 8811 msr BASEPRI, r0 + 800971a: 4770 bx lr + 800971c: f3af 8000 nop.w -08005250 : - 8005250: 20000938 .word 0x20000938 +08009720 : + 8009720: 20000ac0 .word 0x20000ac0 " bx r14 \n" " \n" " .align 4 \n" "pxCurrentTCBConst2: .word pxCurrentTCB \n" ); } - 8005254: bf00 nop - 8005256: bf00 nop + 8009724: bf00 nop + 8009726: bf00 nop -08005258 : +08009728 : { /* Start the first task. This also clears the bit that indicates the FPU is in use in case the FPU was used before the scheduler was started - which would otherwise result in the unnecessary leaving of space in the SVC stack for lazy saving of FPU registers. */ __asm volatile( - 8005258: 4808 ldr r0, [pc, #32] @ (800527c ) - 800525a: 6800 ldr r0, [r0, #0] - 800525c: 6800 ldr r0, [r0, #0] - 800525e: f380 8808 msr MSP, r0 - 8005262: f04f 0000 mov.w r0, #0 - 8005266: f380 8814 msr CONTROL, r0 - 800526a: b662 cpsie i - 800526c: b661 cpsie f - 800526e: f3bf 8f4f dsb sy - 8005272: f3bf 8f6f isb sy - 8005276: df00 svc 0 - 8005278: bf00 nop + 8009728: 4808 ldr r0, [pc, #32] @ (800974c ) + 800972a: 6800 ldr r0, [r0, #0] + 800972c: 6800 ldr r0, [r0, #0] + 800972e: f380 8808 msr MSP, r0 + 8009732: f04f 0000 mov.w r0, #0 + 8009736: f380 8814 msr CONTROL, r0 + 800973a: b662 cpsie i + 800973c: b661 cpsie f + 800973e: f3bf 8f4f dsb sy + 8009742: f3bf 8f6f isb sy + 8009746: df00 svc 0 + 8009748: bf00 nop " dsb \n" " isb \n" " svc 0 \n" /* System call to start first task. */ " nop \n" ); } - 800527a: bf00 nop - 800527c: e000ed08 .word 0xe000ed08 + 800974a: bf00 nop + 800974c: e000ed08 .word 0xe000ed08 -08005280 : +08009750 : /* * See header file for description. */ BaseType_t xPortStartScheduler( void ) { - 8005280: b580 push {r7, lr} - 8005282: b086 sub sp, #24 - 8005284: af00 add r7, sp, #0 + 8009750: b580 push {r7, lr} + 8009752: b086 sub sp, #24 + 8009754: af00 add r7, sp, #0 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); /* This port can be used on all revisions of the Cortex-M7 core other than the r0p1 parts. r0p1 parts should use the port from the /source/portable/GCC/ARM_CM7/r0p1 directory. */ configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); - 8005286: 4b47 ldr r3, [pc, #284] @ (80053a4 ) - 8005288: 681b ldr r3, [r3, #0] - 800528a: 4a47 ldr r2, [pc, #284] @ (80053a8 ) - 800528c: 4293 cmp r3, r2 - 800528e: d10b bne.n 80052a8 + 8009756: 4b47 ldr r3, [pc, #284] @ (8009874 ) + 8009758: 681b ldr r3, [r3, #0] + 800975a: 4a47 ldr r2, [pc, #284] @ (8009878 ) + 800975c: 4293 cmp r3, r2 + 800975e: d10b bne.n 8009778 __asm volatile - 8005290: f04f 0350 mov.w r3, #80 @ 0x50 - 8005294: f383 8811 msr BASEPRI, r3 - 8005298: f3bf 8f6f isb sy - 800529c: f3bf 8f4f dsb sy - 80052a0: 60fb str r3, [r7, #12] + 8009760: f04f 0350 mov.w r3, #80 @ 0x50 + 8009764: f383 8811 msr BASEPRI, r3 + 8009768: f3bf 8f6f isb sy + 800976c: f3bf 8f4f dsb sy + 8009770: 60fb str r3, [r7, #12] } - 80052a2: bf00 nop - 80052a4: bf00 nop - 80052a6: e7fd b.n 80052a4 + 8009772: bf00 nop + 8009774: bf00 nop + 8009776: e7fd b.n 8009774 configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); - 80052a8: 4b3e ldr r3, [pc, #248] @ (80053a4 ) - 80052aa: 681b ldr r3, [r3, #0] - 80052ac: 4a3f ldr r2, [pc, #252] @ (80053ac ) - 80052ae: 4293 cmp r3, r2 - 80052b0: d10b bne.n 80052ca + 8009778: 4b3e ldr r3, [pc, #248] @ (8009874 ) + 800977a: 681b ldr r3, [r3, #0] + 800977c: 4a3f ldr r2, [pc, #252] @ (800987c ) + 800977e: 4293 cmp r3, r2 + 8009780: d10b bne.n 800979a __asm volatile - 80052b2: f04f 0350 mov.w r3, #80 @ 0x50 - 80052b6: f383 8811 msr BASEPRI, r3 - 80052ba: f3bf 8f6f isb sy - 80052be: f3bf 8f4f dsb sy - 80052c2: 613b str r3, [r7, #16] + 8009782: f04f 0350 mov.w r3, #80 @ 0x50 + 8009786: f383 8811 msr BASEPRI, r3 + 800978a: f3bf 8f6f isb sy + 800978e: f3bf 8f4f dsb sy + 8009792: 613b str r3, [r7, #16] } - 80052c4: bf00 nop - 80052c6: bf00 nop - 80052c8: e7fd b.n 80052c6 + 8009794: bf00 nop + 8009796: bf00 nop + 8009798: e7fd b.n 8009796 #if( configASSERT_DEFINED == 1 ) { volatile uint32_t ulOriginalPriority; volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); - 80052ca: 4b39 ldr r3, [pc, #228] @ (80053b0 ) - 80052cc: 617b str r3, [r7, #20] + 800979a: 4b39 ldr r3, [pc, #228] @ (8009880 ) + 800979c: 617b str r3, [r7, #20] functions can be called. ISR safe functions are those that end in "FromISR". FreeRTOS maintains separate thread and ISR API functions to ensure interrupt entry is as fast and simple as possible. Save the interrupt priority value that is about to be clobbered. */ ulOriginalPriority = *pucFirstUserPriorityRegister; - 80052ce: 697b ldr r3, [r7, #20] - 80052d0: 781b ldrb r3, [r3, #0] - 80052d2: b2db uxtb r3, r3 - 80052d4: 607b str r3, [r7, #4] + 800979e: 697b ldr r3, [r7, #20] + 80097a0: 781b ldrb r3, [r3, #0] + 80097a2: b2db uxtb r3, r3 + 80097a4: 607b str r3, [r7, #4] /* Determine the number of priority bits available. First write to all possible bits. */ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; - 80052d6: 697b ldr r3, [r7, #20] - 80052d8: 22ff movs r2, #255 @ 0xff - 80052da: 701a strb r2, [r3, #0] + 80097a6: 697b ldr r3, [r7, #20] + 80097a8: 22ff movs r2, #255 @ 0xff + 80097aa: 701a strb r2, [r3, #0] /* Read the value back to see how many bits stuck. */ ucMaxPriorityValue = *pucFirstUserPriorityRegister; - 80052dc: 697b ldr r3, [r7, #20] - 80052de: 781b ldrb r3, [r3, #0] - 80052e0: b2db uxtb r3, r3 - 80052e2: 70fb strb r3, [r7, #3] + 80097ac: 697b ldr r3, [r7, #20] + 80097ae: 781b ldrb r3, [r3, #0] + 80097b0: b2db uxtb r3, r3 + 80097b2: 70fb strb r3, [r7, #3] /* Use the same mask on the maximum system call priority. */ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - 80052e4: 78fb ldrb r3, [r7, #3] - 80052e6: b2db uxtb r3, r3 - 80052e8: f003 0350 and.w r3, r3, #80 @ 0x50 - 80052ec: b2da uxtb r2, r3 - 80052ee: 4b31 ldr r3, [pc, #196] @ (80053b4 ) - 80052f0: 701a strb r2, [r3, #0] + 80097b4: 78fb ldrb r3, [r7, #3] + 80097b6: b2db uxtb r3, r3 + 80097b8: f003 0350 and.w r3, r3, #80 @ 0x50 + 80097bc: b2da uxtb r2, r3 + 80097be: 4b31 ldr r3, [pc, #196] @ (8009884 ) + 80097c0: 701a strb r2, [r3, #0] /* Calculate the maximum acceptable priority group value for the number of bits read back. */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; - 80052f2: 4b31 ldr r3, [pc, #196] @ (80053b8 ) - 80052f4: 2207 movs r2, #7 - 80052f6: 601a str r2, [r3, #0] + 80097c2: 4b31 ldr r3, [pc, #196] @ (8009888 ) + 80097c4: 2207 movs r2, #7 + 80097c6: 601a str r2, [r3, #0] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - 80052f8: e009 b.n 800530e + 80097c8: e009 b.n 80097de { ulMaxPRIGROUPValue--; - 80052fa: 4b2f ldr r3, [pc, #188] @ (80053b8 ) - 80052fc: 681b ldr r3, [r3, #0] - 80052fe: 3b01 subs r3, #1 - 8005300: 4a2d ldr r2, [pc, #180] @ (80053b8 ) - 8005302: 6013 str r3, [r2, #0] + 80097ca: 4b2f ldr r3, [pc, #188] @ (8009888 ) + 80097cc: 681b ldr r3, [r3, #0] + 80097ce: 3b01 subs r3, #1 + 80097d0: 4a2d ldr r2, [pc, #180] @ (8009888 ) + 80097d2: 6013 str r3, [r2, #0] ucMaxPriorityValue <<= ( uint8_t ) 0x01; - 8005304: 78fb ldrb r3, [r7, #3] - 8005306: b2db uxtb r3, r3 - 8005308: 005b lsls r3, r3, #1 - 800530a: b2db uxtb r3, r3 - 800530c: 70fb strb r3, [r7, #3] + 80097d4: 78fb ldrb r3, [r7, #3] + 80097d6: b2db uxtb r3, r3 + 80097d8: 005b lsls r3, r3, #1 + 80097da: b2db uxtb r3, r3 + 80097dc: 70fb strb r3, [r7, #3] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - 800530e: 78fb ldrb r3, [r7, #3] - 8005310: b2db uxtb r3, r3 - 8005312: f003 0380 and.w r3, r3, #128 @ 0x80 - 8005316: 2b80 cmp r3, #128 @ 0x80 - 8005318: d0ef beq.n 80052fa + 80097de: 78fb ldrb r3, [r7, #3] + 80097e0: b2db uxtb r3, r3 + 80097e2: f003 0380 and.w r3, r3, #128 @ 0x80 + 80097e6: 2b80 cmp r3, #128 @ 0x80 + 80097e8: d0ef beq.n 80097ca #ifdef configPRIO_BITS { /* Check the FreeRTOS configuration that defines the number of priority bits matches the number of priority bits actually queried from the hardware. */ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); - 800531a: 4b27 ldr r3, [pc, #156] @ (80053b8 ) - 800531c: 681b ldr r3, [r3, #0] - 800531e: f1c3 0307 rsb r3, r3, #7 - 8005322: 2b04 cmp r3, #4 - 8005324: d00b beq.n 800533e + 80097ea: 4b27 ldr r3, [pc, #156] @ (8009888 ) + 80097ec: 681b ldr r3, [r3, #0] + 80097ee: f1c3 0307 rsb r3, r3, #7 + 80097f2: 2b04 cmp r3, #4 + 80097f4: d00b beq.n 800980e __asm volatile - 8005326: f04f 0350 mov.w r3, #80 @ 0x50 - 800532a: f383 8811 msr BASEPRI, r3 - 800532e: f3bf 8f6f isb sy - 8005332: f3bf 8f4f dsb sy - 8005336: 60bb str r3, [r7, #8] + 80097f6: f04f 0350 mov.w r3, #80 @ 0x50 + 80097fa: f383 8811 msr BASEPRI, r3 + 80097fe: f3bf 8f6f isb sy + 8009802: f3bf 8f4f dsb sy + 8009806: 60bb str r3, [r7, #8] } - 8005338: bf00 nop - 800533a: bf00 nop - 800533c: e7fd b.n 800533a + 8009808: bf00 nop + 800980a: bf00 nop + 800980c: e7fd b.n 800980a } #endif /* Shift the priority group value back to its position within the AIRCR register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - 800533e: 4b1e ldr r3, [pc, #120] @ (80053b8 ) - 8005340: 681b ldr r3, [r3, #0] - 8005342: 021b lsls r3, r3, #8 - 8005344: 4a1c ldr r2, [pc, #112] @ (80053b8 ) - 8005346: 6013 str r3, [r2, #0] + 800980e: 4b1e ldr r3, [pc, #120] @ (8009888 ) + 8009810: 681b ldr r3, [r3, #0] + 8009812: 021b lsls r3, r3, #8 + 8009814: 4a1c ldr r2, [pc, #112] @ (8009888 ) + 8009816: 6013 str r3, [r2, #0] ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - 8005348: 4b1b ldr r3, [pc, #108] @ (80053b8 ) - 800534a: 681b ldr r3, [r3, #0] - 800534c: f403 63e0 and.w r3, r3, #1792 @ 0x700 - 8005350: 4a19 ldr r2, [pc, #100] @ (80053b8 ) - 8005352: 6013 str r3, [r2, #0] + 8009818: 4b1b ldr r3, [pc, #108] @ (8009888 ) + 800981a: 681b ldr r3, [r3, #0] + 800981c: f403 63e0 and.w r3, r3, #1792 @ 0x700 + 8009820: 4a19 ldr r2, [pc, #100] @ (8009888 ) + 8009822: 6013 str r3, [r2, #0] /* Restore the clobbered interrupt priority register to its original value. */ *pucFirstUserPriorityRegister = ulOriginalPriority; - 8005354: 687b ldr r3, [r7, #4] - 8005356: b2da uxtb r2, r3 - 8005358: 697b ldr r3, [r7, #20] - 800535a: 701a strb r2, [r3, #0] + 8009824: 687b ldr r3, [r7, #4] + 8009826: b2da uxtb r2, r3 + 8009828: 697b ldr r3, [r7, #20] + 800982a: 701a strb r2, [r3, #0] } #endif /* conifgASSERT_DEFINED */ /* Make PendSV and SysTick the lowest priority interrupts. */ portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI; - 800535c: 4b17 ldr r3, [pc, #92] @ (80053bc ) - 800535e: 681b ldr r3, [r3, #0] - 8005360: 4a16 ldr r2, [pc, #88] @ (80053bc ) - 8005362: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 - 8005366: 6013 str r3, [r2, #0] + 800982c: 4b17 ldr r3, [pc, #92] @ (800988c ) + 800982e: 681b ldr r3, [r3, #0] + 8009830: 4a16 ldr r2, [pc, #88] @ (800988c ) + 8009832: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 + 8009836: 6013 str r3, [r2, #0] portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI; - 8005368: 4b14 ldr r3, [pc, #80] @ (80053bc ) - 800536a: 681b ldr r3, [r3, #0] - 800536c: 4a13 ldr r2, [pc, #76] @ (80053bc ) - 800536e: f043 4370 orr.w r3, r3, #4026531840 @ 0xf0000000 - 8005372: 6013 str r3, [r2, #0] + 8009838: 4b14 ldr r3, [pc, #80] @ (800988c ) + 800983a: 681b ldr r3, [r3, #0] + 800983c: 4a13 ldr r2, [pc, #76] @ (800988c ) + 800983e: f043 4370 orr.w r3, r3, #4026531840 @ 0xf0000000 + 8009842: 6013 str r3, [r2, #0] /* Start the timer that generates the tick ISR. Interrupts are disabled here already. */ vPortSetupTimerInterrupt(); - 8005374: f000 f8da bl 800552c + 8009844: f000 f8da bl 80099fc /* Initialise the critical nesting count ready for the first task. */ uxCriticalNesting = 0; - 8005378: 4b11 ldr r3, [pc, #68] @ (80053c0 ) - 800537a: 2200 movs r2, #0 - 800537c: 601a str r2, [r3, #0] + 8009848: 4b11 ldr r3, [pc, #68] @ (8009890 ) + 800984a: 2200 movs r2, #0 + 800984c: 601a str r2, [r3, #0] /* Ensure the VFP is enabled - it should be anyway. */ vPortEnableVFP(); - 800537e: f000 f8f9 bl 8005574 + 800984e: f000 f8f9 bl 8009a44 /* Lazy save always. */ *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; - 8005382: 4b10 ldr r3, [pc, #64] @ (80053c4 ) - 8005384: 681b ldr r3, [r3, #0] - 8005386: 4a0f ldr r2, [pc, #60] @ (80053c4 ) - 8005388: f043 4340 orr.w r3, r3, #3221225472 @ 0xc0000000 - 800538c: 6013 str r3, [r2, #0] + 8009852: 4b10 ldr r3, [pc, #64] @ (8009894 ) + 8009854: 681b ldr r3, [r3, #0] + 8009856: 4a0f ldr r2, [pc, #60] @ (8009894 ) + 8009858: f043 4340 orr.w r3, r3, #3221225472 @ 0xc0000000 + 800985c: 6013 str r3, [r2, #0] /* Start the first task. */ prvPortStartFirstTask(); - 800538e: f7ff ff63 bl 8005258 + 800985e: f7ff ff63 bl 8009728 exit error function to prevent compiler warnings about a static function not being called in the case that the application writer overrides this functionality by defining configTASK_RETURN_ADDRESS. Call vTaskSwitchContext() so link time optimisation does not remove the symbol. */ vTaskSwitchContext(); - 8005392: f7ff f831 bl 80043f8 + 8009862: f7fe fe6d bl 8008540 prvTaskExitError(); - 8005396: f7ff ff1d bl 80051d4 + 8009866: f7ff ff19 bl 800969c /* Should not get here! */ return 0; - 800539a: 2300 movs r3, #0 + 800986a: 2300 movs r3, #0 } - 800539c: 4618 mov r0, r3 - 800539e: 3718 adds r7, #24 - 80053a0: 46bd mov sp, r7 - 80053a2: bd80 pop {r7, pc} - 80053a4: e000ed00 .word 0xe000ed00 - 80053a8: 410fc271 .word 0x410fc271 - 80053ac: 410fc270 .word 0x410fc270 - 80053b0: e000e400 .word 0xe000e400 - 80053b4: 20000f64 .word 0x20000f64 - 80053b8: 20000f68 .word 0x20000f68 - 80053bc: e000ed20 .word 0xe000ed20 - 80053c0: 2000000c .word 0x2000000c - 80053c4: e000ef34 .word 0xe000ef34 + 800986c: 4618 mov r0, r3 + 800986e: 3718 adds r7, #24 + 8009870: 46bd mov sp, r7 + 8009872: bd80 pop {r7, pc} + 8009874: e000ed00 .word 0xe000ed00 + 8009878: 410fc271 .word 0x410fc271 + 800987c: 410fc270 .word 0x410fc270 + 8009880: e000e400 .word 0xe000e400 + 8009884: 200010ec .word 0x200010ec + 8009888: 200010f0 .word 0x200010f0 + 800988c: e000ed20 .word 0xe000ed20 + 8009890: 20000024 .word 0x20000024 + 8009894: e000ef34 .word 0xe000ef34 -080053c8 : +08009898 : configASSERT( uxCriticalNesting == 1000UL ); } /*-----------------------------------------------------------*/ void vPortEnterCritical( void ) { - 80053c8: b480 push {r7} - 80053ca: b083 sub sp, #12 - 80053cc: af00 add r7, sp, #0 + 8009898: b480 push {r7} + 800989a: b083 sub sp, #12 + 800989c: af00 add r7, sp, #0 __asm volatile - 80053ce: f04f 0350 mov.w r3, #80 @ 0x50 - 80053d2: f383 8811 msr BASEPRI, r3 - 80053d6: f3bf 8f6f isb sy - 80053da: f3bf 8f4f dsb sy - 80053de: 607b str r3, [r7, #4] + 800989e: f04f 0350 mov.w r3, #80 @ 0x50 + 80098a2: f383 8811 msr BASEPRI, r3 + 80098a6: f3bf 8f6f isb sy + 80098aa: f3bf 8f4f dsb sy + 80098ae: 607b str r3, [r7, #4] } - 80053e0: bf00 nop + 80098b0: bf00 nop portDISABLE_INTERRUPTS(); uxCriticalNesting++; - 80053e2: 4b10 ldr r3, [pc, #64] @ (8005424 ) - 80053e4: 681b ldr r3, [r3, #0] - 80053e6: 3301 adds r3, #1 - 80053e8: 4a0e ldr r2, [pc, #56] @ (8005424 ) - 80053ea: 6013 str r3, [r2, #0] + 80098b2: 4b10 ldr r3, [pc, #64] @ (80098f4 ) + 80098b4: 681b ldr r3, [r3, #0] + 80098b6: 3301 adds r3, #1 + 80098b8: 4a0e ldr r2, [pc, #56] @ (80098f4 ) + 80098ba: 6013 str r3, [r2, #0] /* This is not the interrupt safe version of the enter critical function so assert() if it is being called from an interrupt context. Only API functions that end in "FromISR" can be used in an interrupt. Only assert if the critical nesting count is 1 to protect against recursive calls if the assert function also uses a critical section. */ if( uxCriticalNesting == 1 ) - 80053ec: 4b0d ldr r3, [pc, #52] @ (8005424 ) - 80053ee: 681b ldr r3, [r3, #0] - 80053f0: 2b01 cmp r3, #1 - 80053f2: d110 bne.n 8005416 + 80098bc: 4b0d ldr r3, [pc, #52] @ (80098f4 ) + 80098be: 681b ldr r3, [r3, #0] + 80098c0: 2b01 cmp r3, #1 + 80098c2: d110 bne.n 80098e6 { configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); - 80053f4: 4b0c ldr r3, [pc, #48] @ (8005428 ) - 80053f6: 681b ldr r3, [r3, #0] - 80053f8: b2db uxtb r3, r3 - 80053fa: 2b00 cmp r3, #0 - 80053fc: d00b beq.n 8005416 + 80098c4: 4b0c ldr r3, [pc, #48] @ (80098f8 ) + 80098c6: 681b ldr r3, [r3, #0] + 80098c8: b2db uxtb r3, r3 + 80098ca: 2b00 cmp r3, #0 + 80098cc: d00b beq.n 80098e6 __asm volatile - 80053fe: f04f 0350 mov.w r3, #80 @ 0x50 - 8005402: f383 8811 msr BASEPRI, r3 - 8005406: f3bf 8f6f isb sy - 800540a: f3bf 8f4f dsb sy - 800540e: 603b str r3, [r7, #0] + 80098ce: f04f 0350 mov.w r3, #80 @ 0x50 + 80098d2: f383 8811 msr BASEPRI, r3 + 80098d6: f3bf 8f6f isb sy + 80098da: f3bf 8f4f dsb sy + 80098de: 603b str r3, [r7, #0] } - 8005410: bf00 nop - 8005412: bf00 nop - 8005414: e7fd b.n 8005412 + 80098e0: bf00 nop + 80098e2: bf00 nop + 80098e4: e7fd b.n 80098e2 } } - 8005416: bf00 nop - 8005418: 370c adds r7, #12 - 800541a: 46bd mov sp, r7 - 800541c: f85d 7b04 ldr.w r7, [sp], #4 - 8005420: 4770 bx lr - 8005422: bf00 nop - 8005424: 2000000c .word 0x2000000c - 8005428: e000ed04 .word 0xe000ed04 + 80098e6: bf00 nop + 80098e8: 370c adds r7, #12 + 80098ea: 46bd mov sp, r7 + 80098ec: f85d 7b04 ldr.w r7, [sp], #4 + 80098f0: 4770 bx lr + 80098f2: bf00 nop + 80098f4: 20000024 .word 0x20000024 + 80098f8: e000ed04 .word 0xe000ed04 -0800542c : +080098fc : /*-----------------------------------------------------------*/ void vPortExitCritical( void ) { - 800542c: b480 push {r7} - 800542e: b083 sub sp, #12 - 8005430: af00 add r7, sp, #0 + 80098fc: b480 push {r7} + 80098fe: b083 sub sp, #12 + 8009900: af00 add r7, sp, #0 configASSERT( uxCriticalNesting ); - 8005432: 4b12 ldr r3, [pc, #72] @ (800547c ) - 8005434: 681b ldr r3, [r3, #0] - 8005436: 2b00 cmp r3, #0 - 8005438: d10b bne.n 8005452 + 8009902: 4b12 ldr r3, [pc, #72] @ (800994c ) + 8009904: 681b ldr r3, [r3, #0] + 8009906: 2b00 cmp r3, #0 + 8009908: d10b bne.n 8009922 __asm volatile - 800543a: f04f 0350 mov.w r3, #80 @ 0x50 - 800543e: f383 8811 msr BASEPRI, r3 - 8005442: f3bf 8f6f isb sy - 8005446: f3bf 8f4f dsb sy - 800544a: 607b str r3, [r7, #4] + 800990a: f04f 0350 mov.w r3, #80 @ 0x50 + 800990e: f383 8811 msr BASEPRI, r3 + 8009912: f3bf 8f6f isb sy + 8009916: f3bf 8f4f dsb sy + 800991a: 607b str r3, [r7, #4] } - 800544c: bf00 nop - 800544e: bf00 nop - 8005450: e7fd b.n 800544e + 800991c: bf00 nop + 800991e: bf00 nop + 8009920: e7fd b.n 800991e uxCriticalNesting--; - 8005452: 4b0a ldr r3, [pc, #40] @ (800547c ) - 8005454: 681b ldr r3, [r3, #0] - 8005456: 3b01 subs r3, #1 - 8005458: 4a08 ldr r2, [pc, #32] @ (800547c ) - 800545a: 6013 str r3, [r2, #0] + 8009922: 4b0a ldr r3, [pc, #40] @ (800994c ) + 8009924: 681b ldr r3, [r3, #0] + 8009926: 3b01 subs r3, #1 + 8009928: 4a08 ldr r2, [pc, #32] @ (800994c ) + 800992a: 6013 str r3, [r2, #0] if( uxCriticalNesting == 0 ) - 800545c: 4b07 ldr r3, [pc, #28] @ (800547c ) - 800545e: 681b ldr r3, [r3, #0] - 8005460: 2b00 cmp r3, #0 - 8005462: d105 bne.n 8005470 - 8005464: 2300 movs r3, #0 - 8005466: 603b str r3, [r7, #0] + 800992c: 4b07 ldr r3, [pc, #28] @ (800994c ) + 800992e: 681b ldr r3, [r3, #0] + 8009930: 2b00 cmp r3, #0 + 8009932: d105 bne.n 8009940 + 8009934: 2300 movs r3, #0 + 8009936: 603b str r3, [r7, #0] __asm volatile - 8005468: 683b ldr r3, [r7, #0] - 800546a: f383 8811 msr BASEPRI, r3 + 8009938: 683b ldr r3, [r7, #0] + 800993a: f383 8811 msr BASEPRI, r3 } - 800546e: bf00 nop + 800993e: bf00 nop { portENABLE_INTERRUPTS(); } } - 8005470: bf00 nop - 8005472: 370c adds r7, #12 - 8005474: 46bd mov sp, r7 - 8005476: f85d 7b04 ldr.w r7, [sp], #4 - 800547a: 4770 bx lr - 800547c: 2000000c .word 0x2000000c + 8009940: bf00 nop + 8009942: 370c adds r7, #12 + 8009944: 46bd mov sp, r7 + 8009946: f85d 7b04 ldr.w r7, [sp], #4 + 800994a: 4770 bx lr + 800994c: 20000024 .word 0x20000024 -08005480 : +08009950 : void xPortPendSVHandler( void ) { /* This is a naked function. */ __asm volatile - 8005480: f3ef 8009 mrs r0, PSP - 8005484: f3bf 8f6f isb sy - 8005488: 4b15 ldr r3, [pc, #84] @ (80054e0 ) - 800548a: 681a ldr r2, [r3, #0] - 800548c: f01e 0f10 tst.w lr, #16 - 8005490: bf08 it eq - 8005492: ed20 8a10 vstmdbeq r0!, {s16-s31} - 8005496: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 800549a: 6010 str r0, [r2, #0] - 800549c: b409 push {r0, r3} - 800549e: f04f 0050 mov.w r0, #80 @ 0x50 - 80054a2: f380 8811 msr BASEPRI, r0 - 80054a6: f3bf 8f4f dsb sy - 80054aa: f3bf 8f6f isb sy - 80054ae: f7fe ffa3 bl 80043f8 - 80054b2: f04f 0000 mov.w r0, #0 - 80054b6: f380 8811 msr BASEPRI, r0 - 80054ba: bc09 pop {r0, r3} - 80054bc: 6819 ldr r1, [r3, #0] - 80054be: 6808 ldr r0, [r1, #0] - 80054c0: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 80054c4: f01e 0f10 tst.w lr, #16 - 80054c8: bf08 it eq - 80054ca: ecb0 8a10 vldmiaeq r0!, {s16-s31} - 80054ce: f380 8809 msr PSP, r0 - 80054d2: f3bf 8f6f isb sy - 80054d6: 4770 bx lr - 80054d8: f3af 8000 nop.w - 80054dc: f3af 8000 nop.w + 8009950: f3ef 8009 mrs r0, PSP + 8009954: f3bf 8f6f isb sy + 8009958: 4b15 ldr r3, [pc, #84] @ (80099b0 ) + 800995a: 681a ldr r2, [r3, #0] + 800995c: f01e 0f10 tst.w lr, #16 + 8009960: bf08 it eq + 8009962: ed20 8a10 vstmdbeq r0!, {s16-s31} + 8009966: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800996a: 6010 str r0, [r2, #0] + 800996c: b409 push {r0, r3} + 800996e: f04f 0050 mov.w r0, #80 @ 0x50 + 8009972: f380 8811 msr BASEPRI, r0 + 8009976: f3bf 8f4f dsb sy + 800997a: f3bf 8f6f isb sy + 800997e: f7fe fddf bl 8008540 + 8009982: f04f 0000 mov.w r0, #0 + 8009986: f380 8811 msr BASEPRI, r0 + 800998a: bc09 pop {r0, r3} + 800998c: 6819 ldr r1, [r3, #0] + 800998e: 6808 ldr r0, [r1, #0] + 8009990: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8009994: f01e 0f10 tst.w lr, #16 + 8009998: bf08 it eq + 800999a: ecb0 8a10 vldmiaeq r0!, {s16-s31} + 800999e: f380 8809 msr PSP, r0 + 80099a2: f3bf 8f6f isb sy + 80099a6: 4770 bx lr + 80099a8: f3af 8000 nop.w + 80099ac: f3af 8000 nop.w -080054e0 : - 80054e0: 20000938 .word 0x20000938 +080099b0 : + 80099b0: 20000ac0 .word 0x20000ac0 " \n" " .align 4 \n" "pxCurrentTCBConst: .word pxCurrentTCB \n" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ); } - 80054e4: bf00 nop - 80054e6: bf00 nop + 80099b4: bf00 nop + 80099b6: bf00 nop -080054e8 : +080099b8 : /*-----------------------------------------------------------*/ void xPortSysTickHandler( void ) { - 80054e8: b580 push {r7, lr} - 80054ea: b082 sub sp, #8 - 80054ec: af00 add r7, sp, #0 + 80099b8: b580 push {r7, lr} + 80099ba: b082 sub sp, #8 + 80099bc: af00 add r7, sp, #0 __asm volatile - 80054ee: f04f 0350 mov.w r3, #80 @ 0x50 - 80054f2: f383 8811 msr BASEPRI, r3 - 80054f6: f3bf 8f6f isb sy - 80054fa: f3bf 8f4f dsb sy - 80054fe: 607b str r3, [r7, #4] + 80099be: f04f 0350 mov.w r3, #80 @ 0x50 + 80099c2: f383 8811 msr BASEPRI, r3 + 80099c6: f3bf 8f6f isb sy + 80099ca: f3bf 8f4f dsb sy + 80099ce: 607b str r3, [r7, #4] } - 8005500: bf00 nop + 80099d0: bf00 nop save and then restore the interrupt mask value as its value is already known. */ portDISABLE_INTERRUPTS(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) - 8005502: f7fe febf bl 8004284 - 8005506: 4603 mov r3, r0 - 8005508: 2b00 cmp r3, #0 - 800550a: d003 beq.n 8005514 + 80099d2: f7fe fcfb bl 80083cc + 80099d6: 4603 mov r3, r0 + 80099d8: 2b00 cmp r3, #0 + 80099da: d003 beq.n 80099e4 { /* A context switch is required. Context switching is performed in the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; - 800550c: 4b06 ldr r3, [pc, #24] @ (8005528 ) - 800550e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 - 8005512: 601a str r2, [r3, #0] - 8005514: 2300 movs r3, #0 - 8005516: 603b str r3, [r7, #0] + 80099dc: 4b06 ldr r3, [pc, #24] @ (80099f8 ) + 80099de: f04f 5280 mov.w r2, #268435456 @ 0x10000000 + 80099e2: 601a str r2, [r3, #0] + 80099e4: 2300 movs r3, #0 + 80099e6: 603b str r3, [r7, #0] __asm volatile - 8005518: 683b ldr r3, [r7, #0] - 800551a: f383 8811 msr BASEPRI, r3 + 80099e8: 683b ldr r3, [r7, #0] + 80099ea: f383 8811 msr BASEPRI, r3 } - 800551e: bf00 nop + 80099ee: bf00 nop } } portENABLE_INTERRUPTS(); } - 8005520: bf00 nop - 8005522: 3708 adds r7, #8 - 8005524: 46bd mov sp, r7 - 8005526: bd80 pop {r7, pc} - 8005528: e000ed04 .word 0xe000ed04 + 80099f0: bf00 nop + 80099f2: 3708 adds r7, #8 + 80099f4: 46bd mov sp, r7 + 80099f6: bd80 pop {r7, pc} + 80099f8: e000ed04 .word 0xe000ed04 -0800552c : +080099fc : /* * Setup the systick timer to generate the tick interrupts at the required * frequency. */ __attribute__(( weak )) void vPortSetupTimerInterrupt( void ) { - 800552c: b480 push {r7} - 800552e: af00 add r7, sp, #0 + 80099fc: b480 push {r7} + 80099fe: af00 add r7, sp, #0 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); } #endif /* configUSE_TICKLESS_IDLE */ /* Stop and clear the SysTick. */ portNVIC_SYSTICK_CTRL_REG = 0UL; - 8005530: 4b0b ldr r3, [pc, #44] @ (8005560 ) - 8005532: 2200 movs r2, #0 - 8005534: 601a str r2, [r3, #0] + 8009a00: 4b0b ldr r3, [pc, #44] @ (8009a30 ) + 8009a02: 2200 movs r2, #0 + 8009a04: 601a str r2, [r3, #0] portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; - 8005536: 4b0b ldr r3, [pc, #44] @ (8005564 ) - 8005538: 2200 movs r2, #0 - 800553a: 601a str r2, [r3, #0] + 8009a06: 4b0b ldr r3, [pc, #44] @ (8009a34 ) + 8009a08: 2200 movs r2, #0 + 8009a0a: 601a str r2, [r3, #0] /* Configure SysTick to interrupt at the requested rate. */ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; - 800553c: 4b0a ldr r3, [pc, #40] @ (8005568 ) - 800553e: 681b ldr r3, [r3, #0] - 8005540: 4a0a ldr r2, [pc, #40] @ (800556c ) - 8005542: fba2 2303 umull r2, r3, r2, r3 - 8005546: 099b lsrs r3, r3, #6 - 8005548: 4a09 ldr r2, [pc, #36] @ (8005570 ) - 800554a: 3b01 subs r3, #1 - 800554c: 6013 str r3, [r2, #0] + 8009a0c: 4b0a ldr r3, [pc, #40] @ (8009a38 ) + 8009a0e: 681b ldr r3, [r3, #0] + 8009a10: 4a0a ldr r2, [pc, #40] @ (8009a3c ) + 8009a12: fba2 2303 umull r2, r3, r2, r3 + 8009a16: 099b lsrs r3, r3, #6 + 8009a18: 4a09 ldr r2, [pc, #36] @ (8009a40 ) + 8009a1a: 3b01 subs r3, #1 + 8009a1c: 6013 str r3, [r2, #0] portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); - 800554e: 4b04 ldr r3, [pc, #16] @ (8005560 ) - 8005550: 2207 movs r2, #7 - 8005552: 601a str r2, [r3, #0] + 8009a1e: 4b04 ldr r3, [pc, #16] @ (8009a30 ) + 8009a20: 2207 movs r2, #7 + 8009a22: 601a str r2, [r3, #0] } - 8005554: bf00 nop - 8005556: 46bd mov sp, r7 - 8005558: f85d 7b04 ldr.w r7, [sp], #4 - 800555c: 4770 bx lr - 800555e: bf00 nop - 8005560: e000e010 .word 0xe000e010 - 8005564: e000e018 .word 0xe000e018 - 8005568: 20000000 .word 0x20000000 - 800556c: 10624dd3 .word 0x10624dd3 - 8005570: e000e014 .word 0xe000e014 + 8009a24: bf00 nop + 8009a26: 46bd mov sp, r7 + 8009a28: f85d 7b04 ldr.w r7, [sp], #4 + 8009a2c: 4770 bx lr + 8009a2e: bf00 nop + 8009a30: e000e010 .word 0xe000e010 + 8009a34: e000e018 .word 0xe000e018 + 8009a38: 20000018 .word 0x20000018 + 8009a3c: 10624dd3 .word 0x10624dd3 + 8009a40: e000e014 .word 0xe000e014 -08005574 : +08009a44 : /*-----------------------------------------------------------*/ /* This is a naked function. */ static void vPortEnableVFP( void ) { __asm volatile - 8005574: f8df 000c ldr.w r0, [pc, #12] @ 8005584 - 8005578: 6801 ldr r1, [r0, #0] - 800557a: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 - 800557e: 6001 str r1, [r0, #0] - 8005580: 4770 bx lr + 8009a44: f8df 000c ldr.w r0, [pc, #12] @ 8009a54 + 8009a48: 6801 ldr r1, [r0, #0] + 8009a4a: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 + 8009a4e: 6001 str r1, [r0, #0] + 8009a50: 4770 bx lr " \n" " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */ " str r1, [r0] \n" " bx r14 " ); } - 8005582: bf00 nop - 8005584: e000ed88 .word 0xe000ed88 + 8009a52: bf00 nop + 8009a54: e000ed88 .word 0xe000ed88 -08005588 : +08009a58 : /*-----------------------------------------------------------*/ #if( configASSERT_DEFINED == 1 ) void vPortValidateInterruptPriority( void ) { - 8005588: b480 push {r7} - 800558a: b085 sub sp, #20 - 800558c: af00 add r7, sp, #0 + 8009a58: b480 push {r7} + 8009a5a: b085 sub sp, #20 + 8009a5c: af00 add r7, sp, #0 uint32_t ulCurrentInterrupt; uint8_t ucCurrentPriority; /* Obtain the number of the currently executing interrupt. */ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); - 800558e: f3ef 8305 mrs r3, IPSR - 8005592: 60fb str r3, [r7, #12] + 8009a5e: f3ef 8305 mrs r3, IPSR + 8009a62: 60fb str r3, [r7, #12] /* Is the interrupt number a user defined interrupt? */ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) - 8005594: 68fb ldr r3, [r7, #12] - 8005596: 2b0f cmp r3, #15 - 8005598: d915 bls.n 80055c6 + 8009a64: 68fb ldr r3, [r7, #12] + 8009a66: 2b0f cmp r3, #15 + 8009a68: d915 bls.n 8009a96 { /* Look up the interrupt's priority. */ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; - 800559a: 4a18 ldr r2, [pc, #96] @ (80055fc ) - 800559c: 68fb ldr r3, [r7, #12] - 800559e: 4413 add r3, r2 - 80055a0: 781b ldrb r3, [r3, #0] - 80055a2: 72fb strb r3, [r7, #11] + 8009a6a: 4a18 ldr r2, [pc, #96] @ (8009acc ) + 8009a6c: 68fb ldr r3, [r7, #12] + 8009a6e: 4413 add r3, r2 + 8009a70: 781b ldrb r3, [r3, #0] + 8009a72: 72fb strb r3, [r7, #11] interrupt entry is as fast and simple as possible. The following links provide detailed information: http://www.freertos.org/RTOS-Cortex-M3-M4.html http://www.freertos.org/FAQHelp.html */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); - 80055a4: 4b16 ldr r3, [pc, #88] @ (8005600 ) - 80055a6: 781b ldrb r3, [r3, #0] - 80055a8: 7afa ldrb r2, [r7, #11] - 80055aa: 429a cmp r2, r3 - 80055ac: d20b bcs.n 80055c6 + 8009a74: 4b16 ldr r3, [pc, #88] @ (8009ad0 ) + 8009a76: 781b ldrb r3, [r3, #0] + 8009a78: 7afa ldrb r2, [r7, #11] + 8009a7a: 429a cmp r2, r3 + 8009a7c: d20b bcs.n 8009a96 __asm volatile - 80055ae: f04f 0350 mov.w r3, #80 @ 0x50 - 80055b2: f383 8811 msr BASEPRI, r3 - 80055b6: f3bf 8f6f isb sy - 80055ba: f3bf 8f4f dsb sy - 80055be: 607b str r3, [r7, #4] + 8009a7e: f04f 0350 mov.w r3, #80 @ 0x50 + 8009a82: f383 8811 msr BASEPRI, r3 + 8009a86: f3bf 8f6f isb sy + 8009a8a: f3bf 8f4f dsb sy + 8009a8e: 607b str r3, [r7, #4] } - 80055c0: bf00 nop - 80055c2: bf00 nop - 80055c4: e7fd b.n 80055c2 + 8009a90: bf00 nop + 8009a92: bf00 nop + 8009a94: e7fd b.n 8009a92 configuration then the correct setting can be achieved on all Cortex-M devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the scheduler. Note however that some vendor specific peripheral libraries assume a non-zero priority group setting, in which cases using a value of zero will result in unpredictable behaviour. */ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); - 80055c6: 4b0f ldr r3, [pc, #60] @ (8005604 ) - 80055c8: 681b ldr r3, [r3, #0] - 80055ca: f403 62e0 and.w r2, r3, #1792 @ 0x700 - 80055ce: 4b0e ldr r3, [pc, #56] @ (8005608 ) - 80055d0: 681b ldr r3, [r3, #0] - 80055d2: 429a cmp r2, r3 - 80055d4: d90b bls.n 80055ee + 8009a96: 4b0f ldr r3, [pc, #60] @ (8009ad4 ) + 8009a98: 681b ldr r3, [r3, #0] + 8009a9a: f403 62e0 and.w r2, r3, #1792 @ 0x700 + 8009a9e: 4b0e ldr r3, [pc, #56] @ (8009ad8 ) + 8009aa0: 681b ldr r3, [r3, #0] + 8009aa2: 429a cmp r2, r3 + 8009aa4: d90b bls.n 8009abe __asm volatile - 80055d6: f04f 0350 mov.w r3, #80 @ 0x50 - 80055da: f383 8811 msr BASEPRI, r3 - 80055de: f3bf 8f6f isb sy - 80055e2: f3bf 8f4f dsb sy - 80055e6: 603b str r3, [r7, #0] + 8009aa6: f04f 0350 mov.w r3, #80 @ 0x50 + 8009aaa: f383 8811 msr BASEPRI, r3 + 8009aae: f3bf 8f6f isb sy + 8009ab2: f3bf 8f4f dsb sy + 8009ab6: 603b str r3, [r7, #0] } - 80055e8: bf00 nop - 80055ea: bf00 nop - 80055ec: e7fd b.n 80055ea + 8009ab8: bf00 nop + 8009aba: bf00 nop + 8009abc: e7fd b.n 8009aba } - 80055ee: bf00 nop - 80055f0: 3714 adds r7, #20 - 80055f2: 46bd mov sp, r7 - 80055f4: f85d 7b04 ldr.w r7, [sp], #4 - 80055f8: 4770 bx lr - 80055fa: bf00 nop - 80055fc: e000e3f0 .word 0xe000e3f0 - 8005600: 20000f64 .word 0x20000f64 - 8005604: e000ed0c .word 0xe000ed0c - 8005608: 20000f68 .word 0x20000f68 + 8009abe: bf00 nop + 8009ac0: 3714 adds r7, #20 + 8009ac2: 46bd mov sp, r7 + 8009ac4: f85d 7b04 ldr.w r7, [sp], #4 + 8009ac8: 4770 bx lr + 8009aca: bf00 nop + 8009acc: e000e3f0 .word 0xe000e3f0 + 8009ad0: 200010ec .word 0x200010ec + 8009ad4: e000ed0c .word 0xe000ed0c + 8009ad8: 200010f0 .word 0x200010f0 -0800560c : +08009adc : static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ void *pvPortMalloc( size_t xWantedSize ) { - 800560c: b580 push {r7, lr} - 800560e: b08a sub sp, #40 @ 0x28 - 8005610: af00 add r7, sp, #0 - 8005612: 6078 str r0, [r7, #4] + 8009adc: b580 push {r7, lr} + 8009ade: b08a sub sp, #40 @ 0x28 + 8009ae0: af00 add r7, sp, #0 + 8009ae2: 6078 str r0, [r7, #4] BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink; void *pvReturn = NULL; - 8005614: 2300 movs r3, #0 - 8005616: 61fb str r3, [r7, #28] + 8009ae4: 2300 movs r3, #0 + 8009ae6: 61fb str r3, [r7, #28] vTaskSuspendAll(); - 8005618: f7fe fd78 bl 800410c + 8009ae8: f7fe fbb4 bl 8008254 { /* If this is the first call to malloc then the heap will require initialisation to setup the list of free blocks. */ if( pxEnd == NULL ) - 800561c: 4b5c ldr r3, [pc, #368] @ (8005790 ) - 800561e: 681b ldr r3, [r3, #0] - 8005620: 2b00 cmp r3, #0 - 8005622: d101 bne.n 8005628 + 8009aec: 4b5c ldr r3, [pc, #368] @ (8009c60 ) + 8009aee: 681b ldr r3, [r3, #0] + 8009af0: 2b00 cmp r3, #0 + 8009af2: d101 bne.n 8009af8 { prvHeapInit(); - 8005624: f000 f924 bl 8005870 + 8009af4: f000 f924 bl 8009d40 /* Check the requested block size is not so large that the top bit is set. The top bit of the block size member of the BlockLink_t structure is used to determine who owns the block - the application or the kernel, so it must be free. */ if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) - 8005628: 4b5a ldr r3, [pc, #360] @ (8005794 ) - 800562a: 681a ldr r2, [r3, #0] - 800562c: 687b ldr r3, [r7, #4] - 800562e: 4013 ands r3, r2 - 8005630: 2b00 cmp r3, #0 - 8005632: f040 8095 bne.w 8005760 + 8009af8: 4b5a ldr r3, [pc, #360] @ (8009c64 ) + 8009afa: 681a ldr r2, [r3, #0] + 8009afc: 687b ldr r3, [r7, #4] + 8009afe: 4013 ands r3, r2 + 8009b00: 2b00 cmp r3, #0 + 8009b02: f040 8095 bne.w 8009c30 { /* The wanted size is increased so it can contain a BlockLink_t structure in addition to the requested amount of bytes. */ if( xWantedSize > 0 ) - 8005636: 687b ldr r3, [r7, #4] - 8005638: 2b00 cmp r3, #0 - 800563a: d01e beq.n 800567a + 8009b06: 687b ldr r3, [r7, #4] + 8009b08: 2b00 cmp r3, #0 + 8009b0a: d01e beq.n 8009b4a { xWantedSize += xHeapStructSize; - 800563c: 2208 movs r2, #8 - 800563e: 687b ldr r3, [r7, #4] - 8005640: 4413 add r3, r2 - 8005642: 607b str r3, [r7, #4] + 8009b0c: 2208 movs r2, #8 + 8009b0e: 687b ldr r3, [r7, #4] + 8009b10: 4413 add r3, r2 + 8009b12: 607b str r3, [r7, #4] /* Ensure that blocks are always aligned to the required number of bytes. */ if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) - 8005644: 687b ldr r3, [r7, #4] - 8005646: f003 0307 and.w r3, r3, #7 - 800564a: 2b00 cmp r3, #0 - 800564c: d015 beq.n 800567a + 8009b14: 687b ldr r3, [r7, #4] + 8009b16: f003 0307 and.w r3, r3, #7 + 8009b1a: 2b00 cmp r3, #0 + 8009b1c: d015 beq.n 8009b4a { /* Byte alignment required. */ xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); - 800564e: 687b ldr r3, [r7, #4] - 8005650: f023 0307 bic.w r3, r3, #7 - 8005654: 3308 adds r3, #8 - 8005656: 607b str r3, [r7, #4] + 8009b1e: 687b ldr r3, [r7, #4] + 8009b20: f023 0307 bic.w r3, r3, #7 + 8009b24: 3308 adds r3, #8 + 8009b26: 607b str r3, [r7, #4] configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 ); - 8005658: 687b ldr r3, [r7, #4] - 800565a: f003 0307 and.w r3, r3, #7 - 800565e: 2b00 cmp r3, #0 - 8005660: d00b beq.n 800567a + 8009b28: 687b ldr r3, [r7, #4] + 8009b2a: f003 0307 and.w r3, r3, #7 + 8009b2e: 2b00 cmp r3, #0 + 8009b30: d00b beq.n 8009b4a __asm volatile - 8005662: f04f 0350 mov.w r3, #80 @ 0x50 - 8005666: f383 8811 msr BASEPRI, r3 - 800566a: f3bf 8f6f isb sy - 800566e: f3bf 8f4f dsb sy - 8005672: 617b str r3, [r7, #20] + 8009b32: f04f 0350 mov.w r3, #80 @ 0x50 + 8009b36: f383 8811 msr BASEPRI, r3 + 8009b3a: f3bf 8f6f isb sy + 8009b3e: f3bf 8f4f dsb sy + 8009b42: 617b str r3, [r7, #20] } - 8005674: bf00 nop - 8005676: bf00 nop - 8005678: e7fd b.n 8005676 + 8009b44: bf00 nop + 8009b46: bf00 nop + 8009b48: e7fd b.n 8009b46 else { mtCOVERAGE_TEST_MARKER(); } if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) - 800567a: 687b ldr r3, [r7, #4] - 800567c: 2b00 cmp r3, #0 - 800567e: d06f beq.n 8005760 - 8005680: 4b45 ldr r3, [pc, #276] @ (8005798 ) - 8005682: 681b ldr r3, [r3, #0] - 8005684: 687a ldr r2, [r7, #4] - 8005686: 429a cmp r2, r3 - 8005688: d86a bhi.n 8005760 + 8009b4a: 687b ldr r3, [r7, #4] + 8009b4c: 2b00 cmp r3, #0 + 8009b4e: d06f beq.n 8009c30 + 8009b50: 4b45 ldr r3, [pc, #276] @ (8009c68 ) + 8009b52: 681b ldr r3, [r3, #0] + 8009b54: 687a ldr r2, [r7, #4] + 8009b56: 429a cmp r2, r3 + 8009b58: d86a bhi.n 8009c30 { /* Traverse the list from the start (lowest address) block until one of adequate size is found. */ pxPreviousBlock = &xStart; - 800568a: 4b44 ldr r3, [pc, #272] @ (800579c ) - 800568c: 623b str r3, [r7, #32] + 8009b5a: 4b44 ldr r3, [pc, #272] @ (8009c6c ) + 8009b5c: 623b str r3, [r7, #32] pxBlock = xStart.pxNextFreeBlock; - 800568e: 4b43 ldr r3, [pc, #268] @ (800579c ) - 8005690: 681b ldr r3, [r3, #0] - 8005692: 627b str r3, [r7, #36] @ 0x24 + 8009b5e: 4b43 ldr r3, [pc, #268] @ (8009c6c ) + 8009b60: 681b ldr r3, [r3, #0] + 8009b62: 627b str r3, [r7, #36] @ 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) - 8005694: e004 b.n 80056a0 + 8009b64: e004 b.n 8009b70 { pxPreviousBlock = pxBlock; - 8005696: 6a7b ldr r3, [r7, #36] @ 0x24 - 8005698: 623b str r3, [r7, #32] + 8009b66: 6a7b ldr r3, [r7, #36] @ 0x24 + 8009b68: 623b str r3, [r7, #32] pxBlock = pxBlock->pxNextFreeBlock; - 800569a: 6a7b ldr r3, [r7, #36] @ 0x24 - 800569c: 681b ldr r3, [r3, #0] - 800569e: 627b str r3, [r7, #36] @ 0x24 + 8009b6a: 6a7b ldr r3, [r7, #36] @ 0x24 + 8009b6c: 681b ldr r3, [r3, #0] + 8009b6e: 627b str r3, [r7, #36] @ 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) - 80056a0: 6a7b ldr r3, [r7, #36] @ 0x24 - 80056a2: 685b ldr r3, [r3, #4] - 80056a4: 687a ldr r2, [r7, #4] - 80056a6: 429a cmp r2, r3 - 80056a8: d903 bls.n 80056b2 - 80056aa: 6a7b ldr r3, [r7, #36] @ 0x24 - 80056ac: 681b ldr r3, [r3, #0] - 80056ae: 2b00 cmp r3, #0 - 80056b0: d1f1 bne.n 8005696 + 8009b70: 6a7b ldr r3, [r7, #36] @ 0x24 + 8009b72: 685b ldr r3, [r3, #4] + 8009b74: 687a ldr r2, [r7, #4] + 8009b76: 429a cmp r2, r3 + 8009b78: d903 bls.n 8009b82 + 8009b7a: 6a7b ldr r3, [r7, #36] @ 0x24 + 8009b7c: 681b ldr r3, [r3, #0] + 8009b7e: 2b00 cmp r3, #0 + 8009b80: d1f1 bne.n 8009b66 } /* If the end marker was reached then a block of adequate size was not found. */ if( pxBlock != pxEnd ) - 80056b2: 4b37 ldr r3, [pc, #220] @ (8005790 ) - 80056b4: 681b ldr r3, [r3, #0] - 80056b6: 6a7a ldr r2, [r7, #36] @ 0x24 - 80056b8: 429a cmp r2, r3 - 80056ba: d051 beq.n 8005760 + 8009b82: 4b37 ldr r3, [pc, #220] @ (8009c60 ) + 8009b84: 681b ldr r3, [r3, #0] + 8009b86: 6a7a ldr r2, [r7, #36] @ 0x24 + 8009b88: 429a cmp r2, r3 + 8009b8a: d051 beq.n 8009c30 { /* Return the memory space pointed to - jumping over the BlockLink_t structure at its start. */ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); - 80056bc: 6a3b ldr r3, [r7, #32] - 80056be: 681b ldr r3, [r3, #0] - 80056c0: 2208 movs r2, #8 - 80056c2: 4413 add r3, r2 - 80056c4: 61fb str r3, [r7, #28] + 8009b8c: 6a3b ldr r3, [r7, #32] + 8009b8e: 681b ldr r3, [r3, #0] + 8009b90: 2208 movs r2, #8 + 8009b92: 4413 add r3, r2 + 8009b94: 61fb str r3, [r7, #28] /* This block is being returned for use so must be taken out of the list of free blocks. */ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; - 80056c6: 6a7b ldr r3, [r7, #36] @ 0x24 - 80056c8: 681a ldr r2, [r3, #0] - 80056ca: 6a3b ldr r3, [r7, #32] - 80056cc: 601a str r2, [r3, #0] + 8009b96: 6a7b ldr r3, [r7, #36] @ 0x24 + 8009b98: 681a ldr r2, [r3, #0] + 8009b9a: 6a3b ldr r3, [r7, #32] + 8009b9c: 601a str r2, [r3, #0] /* If the block is larger than required it can be split into two. */ if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) - 80056ce: 6a7b ldr r3, [r7, #36] @ 0x24 - 80056d0: 685a ldr r2, [r3, #4] - 80056d2: 687b ldr r3, [r7, #4] - 80056d4: 1ad2 subs r2, r2, r3 - 80056d6: 2308 movs r3, #8 - 80056d8: 005b lsls r3, r3, #1 - 80056da: 429a cmp r2, r3 - 80056dc: d920 bls.n 8005720 + 8009b9e: 6a7b ldr r3, [r7, #36] @ 0x24 + 8009ba0: 685a ldr r2, [r3, #4] + 8009ba2: 687b ldr r3, [r7, #4] + 8009ba4: 1ad2 subs r2, r2, r3 + 8009ba6: 2308 movs r3, #8 + 8009ba8: 005b lsls r3, r3, #1 + 8009baa: 429a cmp r2, r3 + 8009bac: d920 bls.n 8009bf0 { /* This block is to be split into two. Create a new block following the number of bytes requested. The void cast is used to prevent byte alignment warnings from the compiler. */ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); - 80056de: 6a7a ldr r2, [r7, #36] @ 0x24 - 80056e0: 687b ldr r3, [r7, #4] - 80056e2: 4413 add r3, r2 - 80056e4: 61bb str r3, [r7, #24] + 8009bae: 6a7a ldr r2, [r7, #36] @ 0x24 + 8009bb0: 687b ldr r3, [r7, #4] + 8009bb2: 4413 add r3, r2 + 8009bb4: 61bb str r3, [r7, #24] configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 ); - 80056e6: 69bb ldr r3, [r7, #24] - 80056e8: f003 0307 and.w r3, r3, #7 - 80056ec: 2b00 cmp r3, #0 - 80056ee: d00b beq.n 8005708 + 8009bb6: 69bb ldr r3, [r7, #24] + 8009bb8: f003 0307 and.w r3, r3, #7 + 8009bbc: 2b00 cmp r3, #0 + 8009bbe: d00b beq.n 8009bd8 __asm volatile - 80056f0: f04f 0350 mov.w r3, #80 @ 0x50 - 80056f4: f383 8811 msr BASEPRI, r3 - 80056f8: f3bf 8f6f isb sy - 80056fc: f3bf 8f4f dsb sy - 8005700: 613b str r3, [r7, #16] + 8009bc0: f04f 0350 mov.w r3, #80 @ 0x50 + 8009bc4: f383 8811 msr BASEPRI, r3 + 8009bc8: f3bf 8f6f isb sy + 8009bcc: f3bf 8f4f dsb sy + 8009bd0: 613b str r3, [r7, #16] } - 8005702: bf00 nop - 8005704: bf00 nop - 8005706: e7fd b.n 8005704 + 8009bd2: bf00 nop + 8009bd4: bf00 nop + 8009bd6: e7fd b.n 8009bd4 /* Calculate the sizes of two blocks split from the single block. */ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; - 8005708: 6a7b ldr r3, [r7, #36] @ 0x24 - 800570a: 685a ldr r2, [r3, #4] - 800570c: 687b ldr r3, [r7, #4] - 800570e: 1ad2 subs r2, r2, r3 - 8005710: 69bb ldr r3, [r7, #24] - 8005712: 605a str r2, [r3, #4] + 8009bd8: 6a7b ldr r3, [r7, #36] @ 0x24 + 8009bda: 685a ldr r2, [r3, #4] + 8009bdc: 687b ldr r3, [r7, #4] + 8009bde: 1ad2 subs r2, r2, r3 + 8009be0: 69bb ldr r3, [r7, #24] + 8009be2: 605a str r2, [r3, #4] pxBlock->xBlockSize = xWantedSize; - 8005714: 6a7b ldr r3, [r7, #36] @ 0x24 - 8005716: 687a ldr r2, [r7, #4] - 8005718: 605a str r2, [r3, #4] + 8009be4: 6a7b ldr r3, [r7, #36] @ 0x24 + 8009be6: 687a ldr r2, [r7, #4] + 8009be8: 605a str r2, [r3, #4] /* Insert the new block into the list of free blocks. */ prvInsertBlockIntoFreeList( pxNewBlockLink ); - 800571a: 69b8 ldr r0, [r7, #24] - 800571c: f000 f90a bl 8005934 + 8009bea: 69b8 ldr r0, [r7, #24] + 8009bec: f000 f90a bl 8009e04 else { mtCOVERAGE_TEST_MARKER(); } xFreeBytesRemaining -= pxBlock->xBlockSize; - 8005720: 4b1d ldr r3, [pc, #116] @ (8005798 ) - 8005722: 681a ldr r2, [r3, #0] - 8005724: 6a7b ldr r3, [r7, #36] @ 0x24 - 8005726: 685b ldr r3, [r3, #4] - 8005728: 1ad3 subs r3, r2, r3 - 800572a: 4a1b ldr r2, [pc, #108] @ (8005798 ) - 800572c: 6013 str r3, [r2, #0] + 8009bf0: 4b1d ldr r3, [pc, #116] @ (8009c68 ) + 8009bf2: 681a ldr r2, [r3, #0] + 8009bf4: 6a7b ldr r3, [r7, #36] @ 0x24 + 8009bf6: 685b ldr r3, [r3, #4] + 8009bf8: 1ad3 subs r3, r2, r3 + 8009bfa: 4a1b ldr r2, [pc, #108] @ (8009c68 ) + 8009bfc: 6013 str r3, [r2, #0] if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) - 800572e: 4b1a ldr r3, [pc, #104] @ (8005798 ) - 8005730: 681a ldr r2, [r3, #0] - 8005732: 4b1b ldr r3, [pc, #108] @ (80057a0 ) - 8005734: 681b ldr r3, [r3, #0] - 8005736: 429a cmp r2, r3 - 8005738: d203 bcs.n 8005742 + 8009bfe: 4b1a ldr r3, [pc, #104] @ (8009c68 ) + 8009c00: 681a ldr r2, [r3, #0] + 8009c02: 4b1b ldr r3, [pc, #108] @ (8009c70 ) + 8009c04: 681b ldr r3, [r3, #0] + 8009c06: 429a cmp r2, r3 + 8009c08: d203 bcs.n 8009c12 { xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; - 800573a: 4b17 ldr r3, [pc, #92] @ (8005798 ) - 800573c: 681b ldr r3, [r3, #0] - 800573e: 4a18 ldr r2, [pc, #96] @ (80057a0 ) - 8005740: 6013 str r3, [r2, #0] + 8009c0a: 4b17 ldr r3, [pc, #92] @ (8009c68 ) + 8009c0c: 681b ldr r3, [r3, #0] + 8009c0e: 4a18 ldr r2, [pc, #96] @ (8009c70 ) + 8009c10: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } /* The block is being returned - it is allocated and owned by the application and has no "next" block. */ pxBlock->xBlockSize |= xBlockAllocatedBit; - 8005742: 6a7b ldr r3, [r7, #36] @ 0x24 - 8005744: 685a ldr r2, [r3, #4] - 8005746: 4b13 ldr r3, [pc, #76] @ (8005794 ) - 8005748: 681b ldr r3, [r3, #0] - 800574a: 431a orrs r2, r3 - 800574c: 6a7b ldr r3, [r7, #36] @ 0x24 - 800574e: 605a str r2, [r3, #4] + 8009c12: 6a7b ldr r3, [r7, #36] @ 0x24 + 8009c14: 685a ldr r2, [r3, #4] + 8009c16: 4b13 ldr r3, [pc, #76] @ (8009c64 ) + 8009c18: 681b ldr r3, [r3, #0] + 8009c1a: 431a orrs r2, r3 + 8009c1c: 6a7b ldr r3, [r7, #36] @ 0x24 + 8009c1e: 605a str r2, [r3, #4] pxBlock->pxNextFreeBlock = NULL; - 8005750: 6a7b ldr r3, [r7, #36] @ 0x24 - 8005752: 2200 movs r2, #0 - 8005754: 601a str r2, [r3, #0] + 8009c20: 6a7b ldr r3, [r7, #36] @ 0x24 + 8009c22: 2200 movs r2, #0 + 8009c24: 601a str r2, [r3, #0] xNumberOfSuccessfulAllocations++; - 8005756: 4b13 ldr r3, [pc, #76] @ (80057a4 ) - 8005758: 681b ldr r3, [r3, #0] - 800575a: 3301 adds r3, #1 - 800575c: 4a11 ldr r2, [pc, #68] @ (80057a4 ) - 800575e: 6013 str r3, [r2, #0] + 8009c26: 4b13 ldr r3, [pc, #76] @ (8009c74 ) + 8009c28: 681b ldr r3, [r3, #0] + 8009c2a: 3301 adds r3, #1 + 8009c2c: 4a11 ldr r2, [pc, #68] @ (8009c74 ) + 8009c2e: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } traceMALLOC( pvReturn, xWantedSize ); } ( void ) xTaskResumeAll(); - 8005760: f7fe fce2 bl 8004128 + 8009c30: f7fe fb1e bl 8008270 mtCOVERAGE_TEST_MARKER(); } } #endif configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); - 8005764: 69fb ldr r3, [r7, #28] - 8005766: f003 0307 and.w r3, r3, #7 - 800576a: 2b00 cmp r3, #0 - 800576c: d00b beq.n 8005786 + 8009c34: 69fb ldr r3, [r7, #28] + 8009c36: f003 0307 and.w r3, r3, #7 + 8009c3a: 2b00 cmp r3, #0 + 8009c3c: d00b beq.n 8009c56 __asm volatile - 800576e: f04f 0350 mov.w r3, #80 @ 0x50 - 8005772: f383 8811 msr BASEPRI, r3 - 8005776: f3bf 8f6f isb sy - 800577a: f3bf 8f4f dsb sy - 800577e: 60fb str r3, [r7, #12] + 8009c3e: f04f 0350 mov.w r3, #80 @ 0x50 + 8009c42: f383 8811 msr BASEPRI, r3 + 8009c46: f3bf 8f6f isb sy + 8009c4a: f3bf 8f4f dsb sy + 8009c4e: 60fb str r3, [r7, #12] } - 8005780: bf00 nop - 8005782: bf00 nop - 8005784: e7fd b.n 8005782 + 8009c50: bf00 nop + 8009c52: bf00 nop + 8009c54: e7fd b.n 8009c52 return pvReturn; - 8005786: 69fb ldr r3, [r7, #28] + 8009c56: 69fb ldr r3, [r7, #28] } - 8005788: 4618 mov r0, r3 - 800578a: 3728 adds r7, #40 @ 0x28 - 800578c: 46bd mov sp, r7 - 800578e: bd80 pop {r7, pc} - 8005790: 20004b74 .word 0x20004b74 - 8005794: 20004b88 .word 0x20004b88 - 8005798: 20004b78 .word 0x20004b78 - 800579c: 20004b6c .word 0x20004b6c - 80057a0: 20004b7c .word 0x20004b7c - 80057a4: 20004b80 .word 0x20004b80 + 8009c58: 4618 mov r0, r3 + 8009c5a: 3728 adds r7, #40 @ 0x28 + 8009c5c: 46bd mov sp, r7 + 8009c5e: bd80 pop {r7, pc} + 8009c60: 20004cfc .word 0x20004cfc + 8009c64: 20004d10 .word 0x20004d10 + 8009c68: 20004d00 .word 0x20004d00 + 8009c6c: 20004cf4 .word 0x20004cf4 + 8009c70: 20004d04 .word 0x20004d04 + 8009c74: 20004d08 .word 0x20004d08 -080057a8 : +08009c78 : /*-----------------------------------------------------------*/ void vPortFree( void *pv ) { - 80057a8: b580 push {r7, lr} - 80057aa: b086 sub sp, #24 - 80057ac: af00 add r7, sp, #0 - 80057ae: 6078 str r0, [r7, #4] + 8009c78: b580 push {r7, lr} + 8009c7a: b086 sub sp, #24 + 8009c7c: af00 add r7, sp, #0 + 8009c7e: 6078 str r0, [r7, #4] uint8_t *puc = ( uint8_t * ) pv; - 80057b0: 687b ldr r3, [r7, #4] - 80057b2: 617b str r3, [r7, #20] + 8009c80: 687b ldr r3, [r7, #4] + 8009c82: 617b str r3, [r7, #20] BlockLink_t *pxLink; if( pv != NULL ) - 80057b4: 687b ldr r3, [r7, #4] - 80057b6: 2b00 cmp r3, #0 - 80057b8: d04f beq.n 800585a + 8009c84: 687b ldr r3, [r7, #4] + 8009c86: 2b00 cmp r3, #0 + 8009c88: d04f beq.n 8009d2a { /* The memory being freed will have an BlockLink_t structure immediately before it. */ puc -= xHeapStructSize; - 80057ba: 2308 movs r3, #8 - 80057bc: 425b negs r3, r3 - 80057be: 697a ldr r2, [r7, #20] - 80057c0: 4413 add r3, r2 - 80057c2: 617b str r3, [r7, #20] + 8009c8a: 2308 movs r3, #8 + 8009c8c: 425b negs r3, r3 + 8009c8e: 697a ldr r2, [r7, #20] + 8009c90: 4413 add r3, r2 + 8009c92: 617b str r3, [r7, #20] /* This casting is to keep the compiler from issuing warnings. */ pxLink = ( void * ) puc; - 80057c4: 697b ldr r3, [r7, #20] - 80057c6: 613b str r3, [r7, #16] + 8009c94: 697b ldr r3, [r7, #20] + 8009c96: 613b str r3, [r7, #16] /* Check the block is actually allocated. */ configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); - 80057c8: 693b ldr r3, [r7, #16] - 80057ca: 685a ldr r2, [r3, #4] - 80057cc: 4b25 ldr r3, [pc, #148] @ (8005864 ) - 80057ce: 681b ldr r3, [r3, #0] - 80057d0: 4013 ands r3, r2 - 80057d2: 2b00 cmp r3, #0 - 80057d4: d10b bne.n 80057ee + 8009c98: 693b ldr r3, [r7, #16] + 8009c9a: 685a ldr r2, [r3, #4] + 8009c9c: 4b25 ldr r3, [pc, #148] @ (8009d34 ) + 8009c9e: 681b ldr r3, [r3, #0] + 8009ca0: 4013 ands r3, r2 + 8009ca2: 2b00 cmp r3, #0 + 8009ca4: d10b bne.n 8009cbe __asm volatile - 80057d6: f04f 0350 mov.w r3, #80 @ 0x50 - 80057da: f383 8811 msr BASEPRI, r3 - 80057de: f3bf 8f6f isb sy - 80057e2: f3bf 8f4f dsb sy - 80057e6: 60fb str r3, [r7, #12] + 8009ca6: f04f 0350 mov.w r3, #80 @ 0x50 + 8009caa: f383 8811 msr BASEPRI, r3 + 8009cae: f3bf 8f6f isb sy + 8009cb2: f3bf 8f4f dsb sy + 8009cb6: 60fb str r3, [r7, #12] } - 80057e8: bf00 nop - 80057ea: bf00 nop - 80057ec: e7fd b.n 80057ea + 8009cb8: bf00 nop + 8009cba: bf00 nop + 8009cbc: e7fd b.n 8009cba configASSERT( pxLink->pxNextFreeBlock == NULL ); - 80057ee: 693b ldr r3, [r7, #16] - 80057f0: 681b ldr r3, [r3, #0] - 80057f2: 2b00 cmp r3, #0 - 80057f4: d00b beq.n 800580e + 8009cbe: 693b ldr r3, [r7, #16] + 8009cc0: 681b ldr r3, [r3, #0] + 8009cc2: 2b00 cmp r3, #0 + 8009cc4: d00b beq.n 8009cde __asm volatile - 80057f6: f04f 0350 mov.w r3, #80 @ 0x50 - 80057fa: f383 8811 msr BASEPRI, r3 - 80057fe: f3bf 8f6f isb sy - 8005802: f3bf 8f4f dsb sy - 8005806: 60bb str r3, [r7, #8] + 8009cc6: f04f 0350 mov.w r3, #80 @ 0x50 + 8009cca: f383 8811 msr BASEPRI, r3 + 8009cce: f3bf 8f6f isb sy + 8009cd2: f3bf 8f4f dsb sy + 8009cd6: 60bb str r3, [r7, #8] } - 8005808: bf00 nop - 800580a: bf00 nop - 800580c: e7fd b.n 800580a + 8009cd8: bf00 nop + 8009cda: bf00 nop + 8009cdc: e7fd b.n 8009cda if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) - 800580e: 693b ldr r3, [r7, #16] - 8005810: 685a ldr r2, [r3, #4] - 8005812: 4b14 ldr r3, [pc, #80] @ (8005864 ) - 8005814: 681b ldr r3, [r3, #0] - 8005816: 4013 ands r3, r2 - 8005818: 2b00 cmp r3, #0 - 800581a: d01e beq.n 800585a + 8009cde: 693b ldr r3, [r7, #16] + 8009ce0: 685a ldr r2, [r3, #4] + 8009ce2: 4b14 ldr r3, [pc, #80] @ (8009d34 ) + 8009ce4: 681b ldr r3, [r3, #0] + 8009ce6: 4013 ands r3, r2 + 8009ce8: 2b00 cmp r3, #0 + 8009cea: d01e beq.n 8009d2a { if( pxLink->pxNextFreeBlock == NULL ) - 800581c: 693b ldr r3, [r7, #16] - 800581e: 681b ldr r3, [r3, #0] - 8005820: 2b00 cmp r3, #0 - 8005822: d11a bne.n 800585a + 8009cec: 693b ldr r3, [r7, #16] + 8009cee: 681b ldr r3, [r3, #0] + 8009cf0: 2b00 cmp r3, #0 + 8009cf2: d11a bne.n 8009d2a { /* The block is being returned to the heap - it is no longer allocated. */ pxLink->xBlockSize &= ~xBlockAllocatedBit; - 8005824: 693b ldr r3, [r7, #16] - 8005826: 685a ldr r2, [r3, #4] - 8005828: 4b0e ldr r3, [pc, #56] @ (8005864 ) - 800582a: 681b ldr r3, [r3, #0] - 800582c: 43db mvns r3, r3 - 800582e: 401a ands r2, r3 - 8005830: 693b ldr r3, [r7, #16] - 8005832: 605a str r2, [r3, #4] + 8009cf4: 693b ldr r3, [r7, #16] + 8009cf6: 685a ldr r2, [r3, #4] + 8009cf8: 4b0e ldr r3, [pc, #56] @ (8009d34 ) + 8009cfa: 681b ldr r3, [r3, #0] + 8009cfc: 43db mvns r3, r3 + 8009cfe: 401a ands r2, r3 + 8009d00: 693b ldr r3, [r7, #16] + 8009d02: 605a str r2, [r3, #4] vTaskSuspendAll(); - 8005834: f7fe fc6a bl 800410c + 8009d04: f7fe faa6 bl 8008254 { /* Add this block to the list of free blocks. */ xFreeBytesRemaining += pxLink->xBlockSize; - 8005838: 693b ldr r3, [r7, #16] - 800583a: 685a ldr r2, [r3, #4] - 800583c: 4b0a ldr r3, [pc, #40] @ (8005868 ) - 800583e: 681b ldr r3, [r3, #0] - 8005840: 4413 add r3, r2 - 8005842: 4a09 ldr r2, [pc, #36] @ (8005868 ) - 8005844: 6013 str r3, [r2, #0] + 8009d08: 693b ldr r3, [r7, #16] + 8009d0a: 685a ldr r2, [r3, #4] + 8009d0c: 4b0a ldr r3, [pc, #40] @ (8009d38 ) + 8009d0e: 681b ldr r3, [r3, #0] + 8009d10: 4413 add r3, r2 + 8009d12: 4a09 ldr r2, [pc, #36] @ (8009d38 ) + 8009d14: 6013 str r3, [r2, #0] traceFREE( pv, pxLink->xBlockSize ); prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); - 8005846: 6938 ldr r0, [r7, #16] - 8005848: f000 f874 bl 8005934 + 8009d16: 6938 ldr r0, [r7, #16] + 8009d18: f000 f874 bl 8009e04 xNumberOfSuccessfulFrees++; - 800584c: 4b07 ldr r3, [pc, #28] @ (800586c ) - 800584e: 681b ldr r3, [r3, #0] - 8005850: 3301 adds r3, #1 - 8005852: 4a06 ldr r2, [pc, #24] @ (800586c ) - 8005854: 6013 str r3, [r2, #0] + 8009d1c: 4b07 ldr r3, [pc, #28] @ (8009d3c ) + 8009d1e: 681b ldr r3, [r3, #0] + 8009d20: 3301 adds r3, #1 + 8009d22: 4a06 ldr r2, [pc, #24] @ (8009d3c ) + 8009d24: 6013 str r3, [r2, #0] } ( void ) xTaskResumeAll(); - 8005856: f7fe fc67 bl 8004128 + 8009d26: f7fe faa3 bl 8008270 else { mtCOVERAGE_TEST_MARKER(); } } } - 800585a: bf00 nop - 800585c: 3718 adds r7, #24 - 800585e: 46bd mov sp, r7 - 8005860: bd80 pop {r7, pc} - 8005862: bf00 nop - 8005864: 20004b88 .word 0x20004b88 - 8005868: 20004b78 .word 0x20004b78 - 800586c: 20004b84 .word 0x20004b84 + 8009d2a: bf00 nop + 8009d2c: 3718 adds r7, #24 + 8009d2e: 46bd mov sp, r7 + 8009d30: bd80 pop {r7, pc} + 8009d32: bf00 nop + 8009d34: 20004d10 .word 0x20004d10 + 8009d38: 20004d00 .word 0x20004d00 + 8009d3c: 20004d0c .word 0x20004d0c -08005870 : +08009d40 : /* This just exists to keep the linker quiet. */ } /*-----------------------------------------------------------*/ static void prvHeapInit( void ) { - 8005870: b480 push {r7} - 8005872: b085 sub sp, #20 - 8005874: af00 add r7, sp, #0 + 8009d40: b480 push {r7} + 8009d42: b085 sub sp, #20 + 8009d44: af00 add r7, sp, #0 BlockLink_t *pxFirstFreeBlock; uint8_t *pucAlignedHeap; size_t uxAddress; size_t xTotalHeapSize = configTOTAL_HEAP_SIZE; - 8005876: f44f 5370 mov.w r3, #15360 @ 0x3c00 - 800587a: 60bb str r3, [r7, #8] + 8009d46: f44f 5370 mov.w r3, #15360 @ 0x3c00 + 8009d4a: 60bb str r3, [r7, #8] /* Ensure the heap starts on a correctly aligned boundary. */ uxAddress = ( size_t ) ucHeap; - 800587c: 4b27 ldr r3, [pc, #156] @ (800591c ) - 800587e: 60fb str r3, [r7, #12] + 8009d4c: 4b27 ldr r3, [pc, #156] @ (8009dec ) + 8009d4e: 60fb str r3, [r7, #12] if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) - 8005880: 68fb ldr r3, [r7, #12] - 8005882: f003 0307 and.w r3, r3, #7 - 8005886: 2b00 cmp r3, #0 - 8005888: d00c beq.n 80058a4 + 8009d50: 68fb ldr r3, [r7, #12] + 8009d52: f003 0307 and.w r3, r3, #7 + 8009d56: 2b00 cmp r3, #0 + 8009d58: d00c beq.n 8009d74 { uxAddress += ( portBYTE_ALIGNMENT - 1 ); - 800588a: 68fb ldr r3, [r7, #12] - 800588c: 3307 adds r3, #7 - 800588e: 60fb str r3, [r7, #12] + 8009d5a: 68fb ldr r3, [r7, #12] + 8009d5c: 3307 adds r3, #7 + 8009d5e: 60fb str r3, [r7, #12] uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); - 8005890: 68fb ldr r3, [r7, #12] - 8005892: f023 0307 bic.w r3, r3, #7 - 8005896: 60fb str r3, [r7, #12] + 8009d60: 68fb ldr r3, [r7, #12] + 8009d62: f023 0307 bic.w r3, r3, #7 + 8009d66: 60fb str r3, [r7, #12] xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; - 8005898: 68ba ldr r2, [r7, #8] - 800589a: 68fb ldr r3, [r7, #12] - 800589c: 1ad3 subs r3, r2, r3 - 800589e: 4a1f ldr r2, [pc, #124] @ (800591c ) - 80058a0: 4413 add r3, r2 - 80058a2: 60bb str r3, [r7, #8] + 8009d68: 68ba ldr r2, [r7, #8] + 8009d6a: 68fb ldr r3, [r7, #12] + 8009d6c: 1ad3 subs r3, r2, r3 + 8009d6e: 4a1f ldr r2, [pc, #124] @ (8009dec ) + 8009d70: 4413 add r3, r2 + 8009d72: 60bb str r3, [r7, #8] } pucAlignedHeap = ( uint8_t * ) uxAddress; - 80058a4: 68fb ldr r3, [r7, #12] - 80058a6: 607b str r3, [r7, #4] + 8009d74: 68fb ldr r3, [r7, #12] + 8009d76: 607b str r3, [r7, #4] /* xStart is used to hold a pointer to the first item in the list of free blocks. The void cast is used to prevent compiler warnings. */ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; - 80058a8: 4a1d ldr r2, [pc, #116] @ (8005920 ) - 80058aa: 687b ldr r3, [r7, #4] - 80058ac: 6013 str r3, [r2, #0] + 8009d78: 4a1d ldr r2, [pc, #116] @ (8009df0 ) + 8009d7a: 687b ldr r3, [r7, #4] + 8009d7c: 6013 str r3, [r2, #0] xStart.xBlockSize = ( size_t ) 0; - 80058ae: 4b1c ldr r3, [pc, #112] @ (8005920 ) - 80058b0: 2200 movs r2, #0 - 80058b2: 605a str r2, [r3, #4] + 8009d7e: 4b1c ldr r3, [pc, #112] @ (8009df0 ) + 8009d80: 2200 movs r2, #0 + 8009d82: 605a str r2, [r3, #4] /* pxEnd is used to mark the end of the list of free blocks and is inserted at the end of the heap space. */ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; - 80058b4: 687b ldr r3, [r7, #4] - 80058b6: 68ba ldr r2, [r7, #8] - 80058b8: 4413 add r3, r2 - 80058ba: 60fb str r3, [r7, #12] + 8009d84: 687b ldr r3, [r7, #4] + 8009d86: 68ba ldr r2, [r7, #8] + 8009d88: 4413 add r3, r2 + 8009d8a: 60fb str r3, [r7, #12] uxAddress -= xHeapStructSize; - 80058bc: 2208 movs r2, #8 - 80058be: 68fb ldr r3, [r7, #12] - 80058c0: 1a9b subs r3, r3, r2 - 80058c2: 60fb str r3, [r7, #12] + 8009d8c: 2208 movs r2, #8 + 8009d8e: 68fb ldr r3, [r7, #12] + 8009d90: 1a9b subs r3, r3, r2 + 8009d92: 60fb str r3, [r7, #12] uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); - 80058c4: 68fb ldr r3, [r7, #12] - 80058c6: f023 0307 bic.w r3, r3, #7 - 80058ca: 60fb str r3, [r7, #12] + 8009d94: 68fb ldr r3, [r7, #12] + 8009d96: f023 0307 bic.w r3, r3, #7 + 8009d9a: 60fb str r3, [r7, #12] pxEnd = ( void * ) uxAddress; - 80058cc: 68fb ldr r3, [r7, #12] - 80058ce: 4a15 ldr r2, [pc, #84] @ (8005924 ) - 80058d0: 6013 str r3, [r2, #0] + 8009d9c: 68fb ldr r3, [r7, #12] + 8009d9e: 4a15 ldr r2, [pc, #84] @ (8009df4 ) + 8009da0: 6013 str r3, [r2, #0] pxEnd->xBlockSize = 0; - 80058d2: 4b14 ldr r3, [pc, #80] @ (8005924 ) - 80058d4: 681b ldr r3, [r3, #0] - 80058d6: 2200 movs r2, #0 - 80058d8: 605a str r2, [r3, #4] + 8009da2: 4b14 ldr r3, [pc, #80] @ (8009df4 ) + 8009da4: 681b ldr r3, [r3, #0] + 8009da6: 2200 movs r2, #0 + 8009da8: 605a str r2, [r3, #4] pxEnd->pxNextFreeBlock = NULL; - 80058da: 4b12 ldr r3, [pc, #72] @ (8005924 ) - 80058dc: 681b ldr r3, [r3, #0] - 80058de: 2200 movs r2, #0 - 80058e0: 601a str r2, [r3, #0] + 8009daa: 4b12 ldr r3, [pc, #72] @ (8009df4 ) + 8009dac: 681b ldr r3, [r3, #0] + 8009dae: 2200 movs r2, #0 + 8009db0: 601a str r2, [r3, #0] /* To start with there is a single free block that is sized to take up the entire heap space, minus the space taken by pxEnd. */ pxFirstFreeBlock = ( void * ) pucAlignedHeap; - 80058e2: 687b ldr r3, [r7, #4] - 80058e4: 603b str r3, [r7, #0] + 8009db2: 687b ldr r3, [r7, #4] + 8009db4: 603b str r3, [r7, #0] pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; - 80058e6: 683b ldr r3, [r7, #0] - 80058e8: 68fa ldr r2, [r7, #12] - 80058ea: 1ad2 subs r2, r2, r3 - 80058ec: 683b ldr r3, [r7, #0] - 80058ee: 605a str r2, [r3, #4] + 8009db6: 683b ldr r3, [r7, #0] + 8009db8: 68fa ldr r2, [r7, #12] + 8009dba: 1ad2 subs r2, r2, r3 + 8009dbc: 683b ldr r3, [r7, #0] + 8009dbe: 605a str r2, [r3, #4] pxFirstFreeBlock->pxNextFreeBlock = pxEnd; - 80058f0: 4b0c ldr r3, [pc, #48] @ (8005924 ) - 80058f2: 681a ldr r2, [r3, #0] - 80058f4: 683b ldr r3, [r7, #0] - 80058f6: 601a str r2, [r3, #0] + 8009dc0: 4b0c ldr r3, [pc, #48] @ (8009df4 ) + 8009dc2: 681a ldr r2, [r3, #0] + 8009dc4: 683b ldr r3, [r7, #0] + 8009dc6: 601a str r2, [r3, #0] /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; - 80058f8: 683b ldr r3, [r7, #0] - 80058fa: 685b ldr r3, [r3, #4] - 80058fc: 4a0a ldr r2, [pc, #40] @ (8005928 ) - 80058fe: 6013 str r3, [r2, #0] + 8009dc8: 683b ldr r3, [r7, #0] + 8009dca: 685b ldr r3, [r3, #4] + 8009dcc: 4a0a ldr r2, [pc, #40] @ (8009df8 ) + 8009dce: 6013 str r3, [r2, #0] xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; - 8005900: 683b ldr r3, [r7, #0] - 8005902: 685b ldr r3, [r3, #4] - 8005904: 4a09 ldr r2, [pc, #36] @ (800592c ) - 8005906: 6013 str r3, [r2, #0] + 8009dd0: 683b ldr r3, [r7, #0] + 8009dd2: 685b ldr r3, [r3, #4] + 8009dd4: 4a09 ldr r2, [pc, #36] @ (8009dfc ) + 8009dd6: 6013 str r3, [r2, #0] /* Work out the position of the top bit in a size_t variable. */ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ); - 8005908: 4b09 ldr r3, [pc, #36] @ (8005930 ) - 800590a: f04f 4200 mov.w r2, #2147483648 @ 0x80000000 - 800590e: 601a str r2, [r3, #0] + 8009dd8: 4b09 ldr r3, [pc, #36] @ (8009e00 ) + 8009dda: f04f 4200 mov.w r2, #2147483648 @ 0x80000000 + 8009dde: 601a str r2, [r3, #0] } - 8005910: bf00 nop - 8005912: 3714 adds r7, #20 - 8005914: 46bd mov sp, r7 - 8005916: f85d 7b04 ldr.w r7, [sp], #4 - 800591a: 4770 bx lr - 800591c: 20000f6c .word 0x20000f6c - 8005920: 20004b6c .word 0x20004b6c - 8005924: 20004b74 .word 0x20004b74 - 8005928: 20004b7c .word 0x20004b7c - 800592c: 20004b78 .word 0x20004b78 - 8005930: 20004b88 .word 0x20004b88 + 8009de0: bf00 nop + 8009de2: 3714 adds r7, #20 + 8009de4: 46bd mov sp, r7 + 8009de6: f85d 7b04 ldr.w r7, [sp], #4 + 8009dea: 4770 bx lr + 8009dec: 200010f4 .word 0x200010f4 + 8009df0: 20004cf4 .word 0x20004cf4 + 8009df4: 20004cfc .word 0x20004cfc + 8009df8: 20004d04 .word 0x20004d04 + 8009dfc: 20004d00 .word 0x20004d00 + 8009e00: 20004d10 .word 0x20004d10 -08005934 : +08009e04 : /*-----------------------------------------------------------*/ static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert ) { - 8005934: b480 push {r7} - 8005936: b085 sub sp, #20 - 8005938: af00 add r7, sp, #0 - 800593a: 6078 str r0, [r7, #4] + 8009e04: b480 push {r7} + 8009e06: b085 sub sp, #20 + 8009e08: af00 add r7, sp, #0 + 8009e0a: 6078 str r0, [r7, #4] BlockLink_t *pxIterator; uint8_t *puc; /* Iterate through the list until a block is found that has a higher address than the block being inserted. */ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) - 800593c: 4b28 ldr r3, [pc, #160] @ (80059e0 ) - 800593e: 60fb str r3, [r7, #12] - 8005940: e002 b.n 8005948 - 8005942: 68fb ldr r3, [r7, #12] - 8005944: 681b ldr r3, [r3, #0] - 8005946: 60fb str r3, [r7, #12] - 8005948: 68fb ldr r3, [r7, #12] - 800594a: 681b ldr r3, [r3, #0] - 800594c: 687a ldr r2, [r7, #4] - 800594e: 429a cmp r2, r3 - 8005950: d8f7 bhi.n 8005942 + 8009e0c: 4b28 ldr r3, [pc, #160] @ (8009eb0 ) + 8009e0e: 60fb str r3, [r7, #12] + 8009e10: e002 b.n 8009e18 + 8009e12: 68fb ldr r3, [r7, #12] + 8009e14: 681b ldr r3, [r3, #0] + 8009e16: 60fb str r3, [r7, #12] + 8009e18: 68fb ldr r3, [r7, #12] + 8009e1a: 681b ldr r3, [r3, #0] + 8009e1c: 687a ldr r2, [r7, #4] + 8009e1e: 429a cmp r2, r3 + 8009e20: d8f7 bhi.n 8009e12 /* Nothing to do here, just iterate to the right position. */ } /* Do the block being inserted, and the block it is being inserted after make a contiguous block of memory? */ puc = ( uint8_t * ) pxIterator; - 8005952: 68fb ldr r3, [r7, #12] - 8005954: 60bb str r3, [r7, #8] + 8009e22: 68fb ldr r3, [r7, #12] + 8009e24: 60bb str r3, [r7, #8] if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) - 8005956: 68fb ldr r3, [r7, #12] - 8005958: 685b ldr r3, [r3, #4] - 800595a: 68ba ldr r2, [r7, #8] - 800595c: 4413 add r3, r2 - 800595e: 687a ldr r2, [r7, #4] - 8005960: 429a cmp r2, r3 - 8005962: d108 bne.n 8005976 + 8009e26: 68fb ldr r3, [r7, #12] + 8009e28: 685b ldr r3, [r3, #4] + 8009e2a: 68ba ldr r2, [r7, #8] + 8009e2c: 4413 add r3, r2 + 8009e2e: 687a ldr r2, [r7, #4] + 8009e30: 429a cmp r2, r3 + 8009e32: d108 bne.n 8009e46 { pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; - 8005964: 68fb ldr r3, [r7, #12] - 8005966: 685a ldr r2, [r3, #4] - 8005968: 687b ldr r3, [r7, #4] - 800596a: 685b ldr r3, [r3, #4] - 800596c: 441a add r2, r3 - 800596e: 68fb ldr r3, [r7, #12] - 8005970: 605a str r2, [r3, #4] + 8009e34: 68fb ldr r3, [r7, #12] + 8009e36: 685a ldr r2, [r3, #4] + 8009e38: 687b ldr r3, [r7, #4] + 8009e3a: 685b ldr r3, [r3, #4] + 8009e3c: 441a add r2, r3 + 8009e3e: 68fb ldr r3, [r7, #12] + 8009e40: 605a str r2, [r3, #4] pxBlockToInsert = pxIterator; - 8005972: 68fb ldr r3, [r7, #12] - 8005974: 607b str r3, [r7, #4] + 8009e42: 68fb ldr r3, [r7, #12] + 8009e44: 607b str r3, [r7, #4] mtCOVERAGE_TEST_MARKER(); } /* Do the block being inserted, and the block it is being inserted before make a contiguous block of memory? */ puc = ( uint8_t * ) pxBlockToInsert; - 8005976: 687b ldr r3, [r7, #4] - 8005978: 60bb str r3, [r7, #8] + 8009e46: 687b ldr r3, [r7, #4] + 8009e48: 60bb str r3, [r7, #8] if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) - 800597a: 687b ldr r3, [r7, #4] - 800597c: 685b ldr r3, [r3, #4] - 800597e: 68ba ldr r2, [r7, #8] - 8005980: 441a add r2, r3 - 8005982: 68fb ldr r3, [r7, #12] - 8005984: 681b ldr r3, [r3, #0] - 8005986: 429a cmp r2, r3 - 8005988: d118 bne.n 80059bc + 8009e4a: 687b ldr r3, [r7, #4] + 8009e4c: 685b ldr r3, [r3, #4] + 8009e4e: 68ba ldr r2, [r7, #8] + 8009e50: 441a add r2, r3 + 8009e52: 68fb ldr r3, [r7, #12] + 8009e54: 681b ldr r3, [r3, #0] + 8009e56: 429a cmp r2, r3 + 8009e58: d118 bne.n 8009e8c { if( pxIterator->pxNextFreeBlock != pxEnd ) - 800598a: 68fb ldr r3, [r7, #12] - 800598c: 681a ldr r2, [r3, #0] - 800598e: 4b15 ldr r3, [pc, #84] @ (80059e4 ) - 8005990: 681b ldr r3, [r3, #0] - 8005992: 429a cmp r2, r3 - 8005994: d00d beq.n 80059b2 + 8009e5a: 68fb ldr r3, [r7, #12] + 8009e5c: 681a ldr r2, [r3, #0] + 8009e5e: 4b15 ldr r3, [pc, #84] @ (8009eb4 ) + 8009e60: 681b ldr r3, [r3, #0] + 8009e62: 429a cmp r2, r3 + 8009e64: d00d beq.n 8009e82 { /* Form one big block from the two blocks. */ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; - 8005996: 687b ldr r3, [r7, #4] - 8005998: 685a ldr r2, [r3, #4] - 800599a: 68fb ldr r3, [r7, #12] - 800599c: 681b ldr r3, [r3, #0] - 800599e: 685b ldr r3, [r3, #4] - 80059a0: 441a add r2, r3 - 80059a2: 687b ldr r3, [r7, #4] - 80059a4: 605a str r2, [r3, #4] + 8009e66: 687b ldr r3, [r7, #4] + 8009e68: 685a ldr r2, [r3, #4] + 8009e6a: 68fb ldr r3, [r7, #12] + 8009e6c: 681b ldr r3, [r3, #0] + 8009e6e: 685b ldr r3, [r3, #4] + 8009e70: 441a add r2, r3 + 8009e72: 687b ldr r3, [r7, #4] + 8009e74: 605a str r2, [r3, #4] pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; - 80059a6: 68fb ldr r3, [r7, #12] - 80059a8: 681b ldr r3, [r3, #0] - 80059aa: 681a ldr r2, [r3, #0] - 80059ac: 687b ldr r3, [r7, #4] - 80059ae: 601a str r2, [r3, #0] - 80059b0: e008 b.n 80059c4 + 8009e76: 68fb ldr r3, [r7, #12] + 8009e78: 681b ldr r3, [r3, #0] + 8009e7a: 681a ldr r2, [r3, #0] + 8009e7c: 687b ldr r3, [r7, #4] + 8009e7e: 601a str r2, [r3, #0] + 8009e80: e008 b.n 8009e94 } else { pxBlockToInsert->pxNextFreeBlock = pxEnd; - 80059b2: 4b0c ldr r3, [pc, #48] @ (80059e4 ) - 80059b4: 681a ldr r2, [r3, #0] - 80059b6: 687b ldr r3, [r7, #4] - 80059b8: 601a str r2, [r3, #0] - 80059ba: e003 b.n 80059c4 + 8009e82: 4b0c ldr r3, [pc, #48] @ (8009eb4 ) + 8009e84: 681a ldr r2, [r3, #0] + 8009e86: 687b ldr r3, [r7, #4] + 8009e88: 601a str r2, [r3, #0] + 8009e8a: e003 b.n 8009e94 } } else { pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; - 80059bc: 68fb ldr r3, [r7, #12] - 80059be: 681a ldr r2, [r3, #0] - 80059c0: 687b ldr r3, [r7, #4] - 80059c2: 601a str r2, [r3, #0] + 8009e8c: 68fb ldr r3, [r7, #12] + 8009e8e: 681a ldr r2, [r3, #0] + 8009e90: 687b ldr r3, [r7, #4] + 8009e92: 601a str r2, [r3, #0] /* If the block being inserted plugged a gab, so was merged with the block before and the block after, then it's pxNextFreeBlock pointer will have already been set, and should not be set here as that would make it point to itself. */ if( pxIterator != pxBlockToInsert ) - 80059c4: 68fa ldr r2, [r7, #12] - 80059c6: 687b ldr r3, [r7, #4] - 80059c8: 429a cmp r2, r3 - 80059ca: d002 beq.n 80059d2 + 8009e94: 68fa ldr r2, [r7, #12] + 8009e96: 687b ldr r3, [r7, #4] + 8009e98: 429a cmp r2, r3 + 8009e9a: d002 beq.n 8009ea2 { pxIterator->pxNextFreeBlock = pxBlockToInsert; - 80059cc: 68fb ldr r3, [r7, #12] - 80059ce: 687a ldr r2, [r7, #4] - 80059d0: 601a str r2, [r3, #0] + 8009e9c: 68fb ldr r3, [r7, #12] + 8009e9e: 687a ldr r2, [r7, #4] + 8009ea0: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } - 80059d2: bf00 nop - 80059d4: 3714 adds r7, #20 - 80059d6: 46bd mov sp, r7 - 80059d8: f85d 7b04 ldr.w r7, [sp], #4 - 80059dc: 4770 bx lr - 80059de: bf00 nop - 80059e0: 20004b6c .word 0x20004b6c - 80059e4: 20004b74 .word 0x20004b74 + 8009ea2: bf00 nop + 8009ea4: 3714 adds r7, #20 + 8009ea6: 46bd mov sp, r7 + 8009ea8: f85d 7b04 ldr.w r7, [sp], #4 + 8009eac: 4770 bx lr + 8009eae: bf00 nop + 8009eb0: 20004cf4 .word 0x20004cf4 + 8009eb4: 20004cfc .word 0x20004cfc -080059e8 <__malloc_lock>: - 80059e8: 4801 ldr r0, [pc, #4] @ (80059f0 <__malloc_lock+0x8>) - 80059ea: f7fb b940 b.w 8000c6e <__retarget_lock_acquire_recursive> - 80059ee: bf00 nop - 80059f0: 20000194 .word 0x20000194 +08009eb8 <__malloc_lock>: + 8009eb8: 4801 ldr r0, [pc, #4] @ (8009ec0 <__malloc_lock+0x8>) + 8009eba: f7f7 ba5c b.w 8001376 <__retarget_lock_acquire_recursive> + 8009ebe: bf00 nop + 8009ec0: 2000031c .word 0x2000031c -080059f4 <__malloc_unlock>: - 80059f4: 4801 ldr r0, [pc, #4] @ (80059fc <__malloc_unlock+0x8>) - 80059f6: f7fb b94f b.w 8000c98 <__retarget_lock_release_recursive> - 80059fa: bf00 nop - 80059fc: 20000194 .word 0x20000194 +08009ec4 <__malloc_unlock>: + 8009ec4: 4801 ldr r0, [pc, #4] @ (8009ecc <__malloc_unlock+0x8>) + 8009ec6: f7f7 ba6b b.w 80013a0 <__retarget_lock_release_recursive> + 8009eca: bf00 nop + 8009ecc: 2000031c .word 0x2000031c -08005a00 : - 8005a00: 4402 add r2, r0 - 8005a02: 4603 mov r3, r0 - 8005a04: 4293 cmp r3, r2 - 8005a06: d100 bne.n 8005a0a - 8005a08: 4770 bx lr - 8005a0a: f803 1b01 strb.w r1, [r3], #1 - 8005a0e: e7f9 b.n 8005a04 +08009ed0 : + 8009ed0: 4402 add r2, r0 + 8009ed2: 4603 mov r3, r0 + 8009ed4: 4293 cmp r3, r2 + 8009ed6: d100 bne.n 8009eda + 8009ed8: 4770 bx lr + 8009eda: f803 1b01 strb.w r1, [r3], #1 + 8009ede: e7f9 b.n 8009ed4 -08005a10 <__libc_init_array>: - 8005a10: b570 push {r4, r5, r6, lr} - 8005a12: 4b0d ldr r3, [pc, #52] @ (8005a48 <__libc_init_array+0x38>) - 8005a14: 4d0d ldr r5, [pc, #52] @ (8005a4c <__libc_init_array+0x3c>) - 8005a16: 1b5b subs r3, r3, r5 - 8005a18: 109c asrs r4, r3, #2 - 8005a1a: 2600 movs r6, #0 - 8005a1c: 42a6 cmp r6, r4 - 8005a1e: d109 bne.n 8005a34 <__libc_init_array+0x24> - 8005a20: f000 f8d0 bl 8005bc4 <_init> - 8005a24: 4d0a ldr r5, [pc, #40] @ (8005a50 <__libc_init_array+0x40>) - 8005a26: 4b0b ldr r3, [pc, #44] @ (8005a54 <__libc_init_array+0x44>) - 8005a28: 1b5b subs r3, r3, r5 - 8005a2a: 109c asrs r4, r3, #2 - 8005a2c: 2600 movs r6, #0 - 8005a2e: 42a6 cmp r6, r4 - 8005a30: d105 bne.n 8005a3e <__libc_init_array+0x2e> - 8005a32: bd70 pop {r4, r5, r6, pc} - 8005a34: f855 3b04 ldr.w r3, [r5], #4 - 8005a38: 4798 blx r3 - 8005a3a: 3601 adds r6, #1 - 8005a3c: e7ee b.n 8005a1c <__libc_init_array+0xc> - 8005a3e: f855 3b04 ldr.w r3, [r5], #4 - 8005a42: 4798 blx r3 - 8005a44: 3601 adds r6, #1 - 8005a46: e7f2 b.n 8005a2e <__libc_init_array+0x1e> - 8005a48: 08005d64 .word 0x08005d64 - 8005a4c: 08005d64 .word 0x08005d64 - 8005a50: 08005d64 .word 0x08005d64 - 8005a54: 08005d68 .word 0x08005d68 +08009ee0 <__libc_init_array>: + 8009ee0: b570 push {r4, r5, r6, lr} + 8009ee2: 4b0d ldr r3, [pc, #52] @ (8009f18 <__libc_init_array+0x38>) + 8009ee4: 4d0d ldr r5, [pc, #52] @ (8009f1c <__libc_init_array+0x3c>) + 8009ee6: 1b5b subs r3, r3, r5 + 8009ee8: 109c asrs r4, r3, #2 + 8009eea: 2600 movs r6, #0 + 8009eec: 42a6 cmp r6, r4 + 8009eee: d109 bne.n 8009f04 <__libc_init_array+0x24> + 8009ef0: f000 f8d0 bl 800a094 <_init> + 8009ef4: 4d0a ldr r5, [pc, #40] @ (8009f20 <__libc_init_array+0x40>) + 8009ef6: 4b0b ldr r3, [pc, #44] @ (8009f24 <__libc_init_array+0x44>) + 8009ef8: 1b5b subs r3, r3, r5 + 8009efa: 109c asrs r4, r3, #2 + 8009efc: 2600 movs r6, #0 + 8009efe: 42a6 cmp r6, r4 + 8009f00: d105 bne.n 8009f0e <__libc_init_array+0x2e> + 8009f02: bd70 pop {r4, r5, r6, pc} + 8009f04: f855 3b04 ldr.w r3, [r5], #4 + 8009f08: 4798 blx r3 + 8009f0a: 3601 adds r6, #1 + 8009f0c: e7ee b.n 8009eec <__libc_init_array+0xc> + 8009f0e: f855 3b04 ldr.w r3, [r5], #4 + 8009f12: 4798 blx r3 + 8009f14: 3601 adds r6, #1 + 8009f16: e7f2 b.n 8009efe <__libc_init_array+0x1e> + 8009f18: 0800a2c8 .word 0x0800a2c8 + 8009f1c: 0800a2c8 .word 0x0800a2c8 + 8009f20: 0800a2c8 .word 0x0800a2c8 + 8009f24: 0800a2cc .word 0x0800a2cc -08005a58 <_reclaim_reent>: - 8005a58: 4b2d ldr r3, [pc, #180] @ (8005b10 <_reclaim_reent+0xb8>) - 8005a5a: 681b ldr r3, [r3, #0] - 8005a5c: 4283 cmp r3, r0 - 8005a5e: b570 push {r4, r5, r6, lr} - 8005a60: 4604 mov r4, r0 - 8005a62: d053 beq.n 8005b0c <_reclaim_reent+0xb4> - 8005a64: 69c3 ldr r3, [r0, #28] - 8005a66: b31b cbz r3, 8005ab0 <_reclaim_reent+0x58> - 8005a68: 68db ldr r3, [r3, #12] - 8005a6a: b163 cbz r3, 8005a86 <_reclaim_reent+0x2e> - 8005a6c: 2500 movs r5, #0 - 8005a6e: 69e3 ldr r3, [r4, #28] - 8005a70: 68db ldr r3, [r3, #12] - 8005a72: 5959 ldr r1, [r3, r5] - 8005a74: b9b1 cbnz r1, 8005aa4 <_reclaim_reent+0x4c> - 8005a76: 3504 adds r5, #4 - 8005a78: 2d80 cmp r5, #128 @ 0x80 - 8005a7a: d1f8 bne.n 8005a6e <_reclaim_reent+0x16> - 8005a7c: 69e3 ldr r3, [r4, #28] - 8005a7e: 4620 mov r0, r4 - 8005a80: 68d9 ldr r1, [r3, #12] - 8005a82: f000 f855 bl 8005b30 <_free_r> - 8005a86: 69e3 ldr r3, [r4, #28] - 8005a88: 6819 ldr r1, [r3, #0] - 8005a8a: b111 cbz r1, 8005a92 <_reclaim_reent+0x3a> - 8005a8c: 4620 mov r0, r4 - 8005a8e: f000 f84f bl 8005b30 <_free_r> - 8005a92: 69e3 ldr r3, [r4, #28] - 8005a94: 689d ldr r5, [r3, #8] - 8005a96: b15d cbz r5, 8005ab0 <_reclaim_reent+0x58> - 8005a98: 4629 mov r1, r5 - 8005a9a: 4620 mov r0, r4 - 8005a9c: 682d ldr r5, [r5, #0] - 8005a9e: f000 f847 bl 8005b30 <_free_r> - 8005aa2: e7f8 b.n 8005a96 <_reclaim_reent+0x3e> - 8005aa4: 680e ldr r6, [r1, #0] - 8005aa6: 4620 mov r0, r4 - 8005aa8: f000 f842 bl 8005b30 <_free_r> - 8005aac: 4631 mov r1, r6 - 8005aae: e7e1 b.n 8005a74 <_reclaim_reent+0x1c> - 8005ab0: 6961 ldr r1, [r4, #20] - 8005ab2: b111 cbz r1, 8005aba <_reclaim_reent+0x62> - 8005ab4: 4620 mov r0, r4 - 8005ab6: f000 f83b bl 8005b30 <_free_r> - 8005aba: 69e1 ldr r1, [r4, #28] - 8005abc: b111 cbz r1, 8005ac4 <_reclaim_reent+0x6c> - 8005abe: 4620 mov r0, r4 - 8005ac0: f000 f836 bl 8005b30 <_free_r> - 8005ac4: 6b21 ldr r1, [r4, #48] @ 0x30 - 8005ac6: b111 cbz r1, 8005ace <_reclaim_reent+0x76> - 8005ac8: 4620 mov r0, r4 - 8005aca: f000 f831 bl 8005b30 <_free_r> - 8005ace: 6b61 ldr r1, [r4, #52] @ 0x34 - 8005ad0: b111 cbz r1, 8005ad8 <_reclaim_reent+0x80> - 8005ad2: 4620 mov r0, r4 - 8005ad4: f000 f82c bl 8005b30 <_free_r> - 8005ad8: 6ba1 ldr r1, [r4, #56] @ 0x38 - 8005ada: b111 cbz r1, 8005ae2 <_reclaim_reent+0x8a> - 8005adc: 4620 mov r0, r4 - 8005ade: f000 f827 bl 8005b30 <_free_r> - 8005ae2: 6ca1 ldr r1, [r4, #72] @ 0x48 - 8005ae4: b111 cbz r1, 8005aec <_reclaim_reent+0x94> - 8005ae6: 4620 mov r0, r4 - 8005ae8: f000 f822 bl 8005b30 <_free_r> - 8005aec: 6c61 ldr r1, [r4, #68] @ 0x44 - 8005aee: b111 cbz r1, 8005af6 <_reclaim_reent+0x9e> - 8005af0: 4620 mov r0, r4 - 8005af2: f000 f81d bl 8005b30 <_free_r> - 8005af6: 6ae1 ldr r1, [r4, #44] @ 0x2c - 8005af8: b111 cbz r1, 8005b00 <_reclaim_reent+0xa8> - 8005afa: 4620 mov r0, r4 - 8005afc: f000 f818 bl 8005b30 <_free_r> - 8005b00: 6a23 ldr r3, [r4, #32] - 8005b02: b11b cbz r3, 8005b0c <_reclaim_reent+0xb4> - 8005b04: 4620 mov r0, r4 - 8005b06: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} - 8005b0a: 4718 bx r3 - 8005b0c: bd70 pop {r4, r5, r6, pc} - 8005b0e: bf00 nop - 8005b10: 20000010 .word 0x20000010 +08009f28 <_reclaim_reent>: + 8009f28: 4b2d ldr r3, [pc, #180] @ (8009fe0 <_reclaim_reent+0xb8>) + 8009f2a: 681b ldr r3, [r3, #0] + 8009f2c: 4283 cmp r3, r0 + 8009f2e: b570 push {r4, r5, r6, lr} + 8009f30: 4604 mov r4, r0 + 8009f32: d053 beq.n 8009fdc <_reclaim_reent+0xb4> + 8009f34: 69c3 ldr r3, [r0, #28] + 8009f36: b31b cbz r3, 8009f80 <_reclaim_reent+0x58> + 8009f38: 68db ldr r3, [r3, #12] + 8009f3a: b163 cbz r3, 8009f56 <_reclaim_reent+0x2e> + 8009f3c: 2500 movs r5, #0 + 8009f3e: 69e3 ldr r3, [r4, #28] + 8009f40: 68db ldr r3, [r3, #12] + 8009f42: 5959 ldr r1, [r3, r5] + 8009f44: b9b1 cbnz r1, 8009f74 <_reclaim_reent+0x4c> + 8009f46: 3504 adds r5, #4 + 8009f48: 2d80 cmp r5, #128 @ 0x80 + 8009f4a: d1f8 bne.n 8009f3e <_reclaim_reent+0x16> + 8009f4c: 69e3 ldr r3, [r4, #28] + 8009f4e: 4620 mov r0, r4 + 8009f50: 68d9 ldr r1, [r3, #12] + 8009f52: f000 f855 bl 800a000 <_free_r> + 8009f56: 69e3 ldr r3, [r4, #28] + 8009f58: 6819 ldr r1, [r3, #0] + 8009f5a: b111 cbz r1, 8009f62 <_reclaim_reent+0x3a> + 8009f5c: 4620 mov r0, r4 + 8009f5e: f000 f84f bl 800a000 <_free_r> + 8009f62: 69e3 ldr r3, [r4, #28] + 8009f64: 689d ldr r5, [r3, #8] + 8009f66: b15d cbz r5, 8009f80 <_reclaim_reent+0x58> + 8009f68: 4629 mov r1, r5 + 8009f6a: 4620 mov r0, r4 + 8009f6c: 682d ldr r5, [r5, #0] + 8009f6e: f000 f847 bl 800a000 <_free_r> + 8009f72: e7f8 b.n 8009f66 <_reclaim_reent+0x3e> + 8009f74: 680e ldr r6, [r1, #0] + 8009f76: 4620 mov r0, r4 + 8009f78: f000 f842 bl 800a000 <_free_r> + 8009f7c: 4631 mov r1, r6 + 8009f7e: e7e1 b.n 8009f44 <_reclaim_reent+0x1c> + 8009f80: 6961 ldr r1, [r4, #20] + 8009f82: b111 cbz r1, 8009f8a <_reclaim_reent+0x62> + 8009f84: 4620 mov r0, r4 + 8009f86: f000 f83b bl 800a000 <_free_r> + 8009f8a: 69e1 ldr r1, [r4, #28] + 8009f8c: b111 cbz r1, 8009f94 <_reclaim_reent+0x6c> + 8009f8e: 4620 mov r0, r4 + 8009f90: f000 f836 bl 800a000 <_free_r> + 8009f94: 6b21 ldr r1, [r4, #48] @ 0x30 + 8009f96: b111 cbz r1, 8009f9e <_reclaim_reent+0x76> + 8009f98: 4620 mov r0, r4 + 8009f9a: f000 f831 bl 800a000 <_free_r> + 8009f9e: 6b61 ldr r1, [r4, #52] @ 0x34 + 8009fa0: b111 cbz r1, 8009fa8 <_reclaim_reent+0x80> + 8009fa2: 4620 mov r0, r4 + 8009fa4: f000 f82c bl 800a000 <_free_r> + 8009fa8: 6ba1 ldr r1, [r4, #56] @ 0x38 + 8009faa: b111 cbz r1, 8009fb2 <_reclaim_reent+0x8a> + 8009fac: 4620 mov r0, r4 + 8009fae: f000 f827 bl 800a000 <_free_r> + 8009fb2: 6ca1 ldr r1, [r4, #72] @ 0x48 + 8009fb4: b111 cbz r1, 8009fbc <_reclaim_reent+0x94> + 8009fb6: 4620 mov r0, r4 + 8009fb8: f000 f822 bl 800a000 <_free_r> + 8009fbc: 6c61 ldr r1, [r4, #68] @ 0x44 + 8009fbe: b111 cbz r1, 8009fc6 <_reclaim_reent+0x9e> + 8009fc0: 4620 mov r0, r4 + 8009fc2: f000 f81d bl 800a000 <_free_r> + 8009fc6: 6ae1 ldr r1, [r4, #44] @ 0x2c + 8009fc8: b111 cbz r1, 8009fd0 <_reclaim_reent+0xa8> + 8009fca: 4620 mov r0, r4 + 8009fcc: f000 f818 bl 800a000 <_free_r> + 8009fd0: 6a23 ldr r3, [r4, #32] + 8009fd2: b11b cbz r3, 8009fdc <_reclaim_reent+0xb4> + 8009fd4: 4620 mov r0, r4 + 8009fd6: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + 8009fda: 4718 bx r3 + 8009fdc: bd70 pop {r4, r5, r6, pc} + 8009fde: bf00 nop + 8009fe0: 20000028 .word 0x20000028 -08005b14 : - 8005b14: 440a add r2, r1 - 8005b16: 4291 cmp r1, r2 - 8005b18: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff - 8005b1c: d100 bne.n 8005b20 - 8005b1e: 4770 bx lr - 8005b20: b510 push {r4, lr} - 8005b22: f811 4b01 ldrb.w r4, [r1], #1 - 8005b26: f803 4f01 strb.w r4, [r3, #1]! - 8005b2a: 4291 cmp r1, r2 - 8005b2c: d1f9 bne.n 8005b22 - 8005b2e: bd10 pop {r4, pc} +08009fe4 : + 8009fe4: 440a add r2, r1 + 8009fe6: 4291 cmp r1, r2 + 8009fe8: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff + 8009fec: d100 bne.n 8009ff0 + 8009fee: 4770 bx lr + 8009ff0: b510 push {r4, lr} + 8009ff2: f811 4b01 ldrb.w r4, [r1], #1 + 8009ff6: f803 4f01 strb.w r4, [r3, #1]! + 8009ffa: 4291 cmp r1, r2 + 8009ffc: d1f9 bne.n 8009ff2 + 8009ffe: bd10 pop {r4, pc} -08005b30 <_free_r>: - 8005b30: b538 push {r3, r4, r5, lr} - 8005b32: 4605 mov r5, r0 - 8005b34: 2900 cmp r1, #0 - 8005b36: d041 beq.n 8005bbc <_free_r+0x8c> - 8005b38: f851 3c04 ldr.w r3, [r1, #-4] - 8005b3c: 1f0c subs r4, r1, #4 - 8005b3e: 2b00 cmp r3, #0 - 8005b40: bfb8 it lt - 8005b42: 18e4 addlt r4, r4, r3 - 8005b44: f7ff ff50 bl 80059e8 <__malloc_lock> - 8005b48: 4a1d ldr r2, [pc, #116] @ (8005bc0 <_free_r+0x90>) - 8005b4a: 6813 ldr r3, [r2, #0] - 8005b4c: b933 cbnz r3, 8005b5c <_free_r+0x2c> - 8005b4e: 6063 str r3, [r4, #4] - 8005b50: 6014 str r4, [r2, #0] - 8005b52: 4628 mov r0, r5 - 8005b54: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} - 8005b58: f7ff bf4c b.w 80059f4 <__malloc_unlock> - 8005b5c: 42a3 cmp r3, r4 - 8005b5e: d908 bls.n 8005b72 <_free_r+0x42> - 8005b60: 6820 ldr r0, [r4, #0] - 8005b62: 1821 adds r1, r4, r0 - 8005b64: 428b cmp r3, r1 - 8005b66: bf01 itttt eq - 8005b68: 6819 ldreq r1, [r3, #0] - 8005b6a: 685b ldreq r3, [r3, #4] - 8005b6c: 1809 addeq r1, r1, r0 - 8005b6e: 6021 streq r1, [r4, #0] - 8005b70: e7ed b.n 8005b4e <_free_r+0x1e> - 8005b72: 461a mov r2, r3 - 8005b74: 685b ldr r3, [r3, #4] - 8005b76: b10b cbz r3, 8005b7c <_free_r+0x4c> - 8005b78: 42a3 cmp r3, r4 - 8005b7a: d9fa bls.n 8005b72 <_free_r+0x42> - 8005b7c: 6811 ldr r1, [r2, #0] - 8005b7e: 1850 adds r0, r2, r1 - 8005b80: 42a0 cmp r0, r4 - 8005b82: d10b bne.n 8005b9c <_free_r+0x6c> - 8005b84: 6820 ldr r0, [r4, #0] - 8005b86: 4401 add r1, r0 - 8005b88: 1850 adds r0, r2, r1 - 8005b8a: 4283 cmp r3, r0 - 8005b8c: 6011 str r1, [r2, #0] - 8005b8e: d1e0 bne.n 8005b52 <_free_r+0x22> - 8005b90: 6818 ldr r0, [r3, #0] - 8005b92: 685b ldr r3, [r3, #4] - 8005b94: 6053 str r3, [r2, #4] - 8005b96: 4408 add r0, r1 - 8005b98: 6010 str r0, [r2, #0] - 8005b9a: e7da b.n 8005b52 <_free_r+0x22> - 8005b9c: d902 bls.n 8005ba4 <_free_r+0x74> - 8005b9e: 230c movs r3, #12 - 8005ba0: 602b str r3, [r5, #0] - 8005ba2: e7d6 b.n 8005b52 <_free_r+0x22> - 8005ba4: 6820 ldr r0, [r4, #0] - 8005ba6: 1821 adds r1, r4, r0 - 8005ba8: 428b cmp r3, r1 - 8005baa: bf04 itt eq - 8005bac: 6819 ldreq r1, [r3, #0] - 8005bae: 685b ldreq r3, [r3, #4] - 8005bb0: 6063 str r3, [r4, #4] - 8005bb2: bf04 itt eq - 8005bb4: 1809 addeq r1, r1, r0 - 8005bb6: 6021 streq r1, [r4, #0] - 8005bb8: 6054 str r4, [r2, #4] - 8005bba: e7ca b.n 8005b52 <_free_r+0x22> - 8005bbc: bd38 pop {r3, r4, r5, pc} - 8005bbe: bf00 nop - 8005bc0: 20004b8c .word 0x20004b8c +0800a000 <_free_r>: + 800a000: b538 push {r3, r4, r5, lr} + 800a002: 4605 mov r5, r0 + 800a004: 2900 cmp r1, #0 + 800a006: d041 beq.n 800a08c <_free_r+0x8c> + 800a008: f851 3c04 ldr.w r3, [r1, #-4] + 800a00c: 1f0c subs r4, r1, #4 + 800a00e: 2b00 cmp r3, #0 + 800a010: bfb8 it lt + 800a012: 18e4 addlt r4, r4, r3 + 800a014: f7ff ff50 bl 8009eb8 <__malloc_lock> + 800a018: 4a1d ldr r2, [pc, #116] @ (800a090 <_free_r+0x90>) + 800a01a: 6813 ldr r3, [r2, #0] + 800a01c: b933 cbnz r3, 800a02c <_free_r+0x2c> + 800a01e: 6063 str r3, [r4, #4] + 800a020: 6014 str r4, [r2, #0] + 800a022: 4628 mov r0, r5 + 800a024: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 800a028: f7ff bf4c b.w 8009ec4 <__malloc_unlock> + 800a02c: 42a3 cmp r3, r4 + 800a02e: d908 bls.n 800a042 <_free_r+0x42> + 800a030: 6820 ldr r0, [r4, #0] + 800a032: 1821 adds r1, r4, r0 + 800a034: 428b cmp r3, r1 + 800a036: bf01 itttt eq + 800a038: 6819 ldreq r1, [r3, #0] + 800a03a: 685b ldreq r3, [r3, #4] + 800a03c: 1809 addeq r1, r1, r0 + 800a03e: 6021 streq r1, [r4, #0] + 800a040: e7ed b.n 800a01e <_free_r+0x1e> + 800a042: 461a mov r2, r3 + 800a044: 685b ldr r3, [r3, #4] + 800a046: b10b cbz r3, 800a04c <_free_r+0x4c> + 800a048: 42a3 cmp r3, r4 + 800a04a: d9fa bls.n 800a042 <_free_r+0x42> + 800a04c: 6811 ldr r1, [r2, #0] + 800a04e: 1850 adds r0, r2, r1 + 800a050: 42a0 cmp r0, r4 + 800a052: d10b bne.n 800a06c <_free_r+0x6c> + 800a054: 6820 ldr r0, [r4, #0] + 800a056: 4401 add r1, r0 + 800a058: 1850 adds r0, r2, r1 + 800a05a: 4283 cmp r3, r0 + 800a05c: 6011 str r1, [r2, #0] + 800a05e: d1e0 bne.n 800a022 <_free_r+0x22> + 800a060: 6818 ldr r0, [r3, #0] + 800a062: 685b ldr r3, [r3, #4] + 800a064: 6053 str r3, [r2, #4] + 800a066: 4408 add r0, r1 + 800a068: 6010 str r0, [r2, #0] + 800a06a: e7da b.n 800a022 <_free_r+0x22> + 800a06c: d902 bls.n 800a074 <_free_r+0x74> + 800a06e: 230c movs r3, #12 + 800a070: 602b str r3, [r5, #0] + 800a072: e7d6 b.n 800a022 <_free_r+0x22> + 800a074: 6820 ldr r0, [r4, #0] + 800a076: 1821 adds r1, r4, r0 + 800a078: 428b cmp r3, r1 + 800a07a: bf04 itt eq + 800a07c: 6819 ldreq r1, [r3, #0] + 800a07e: 685b ldreq r3, [r3, #4] + 800a080: 6063 str r3, [r4, #4] + 800a082: bf04 itt eq + 800a084: 1809 addeq r1, r1, r0 + 800a086: 6021 streq r1, [r4, #0] + 800a088: 6054 str r4, [r2, #4] + 800a08a: e7ca b.n 800a022 <_free_r+0x22> + 800a08c: bd38 pop {r3, r4, r5, pc} + 800a08e: bf00 nop + 800a090: 20004d14 .word 0x20004d14 -08005bc4 <_init>: - 8005bc4: b5f8 push {r3, r4, r5, r6, r7, lr} - 8005bc6: bf00 nop - 8005bc8: bcf8 pop {r3, r4, r5, r6, r7} - 8005bca: bc08 pop {r3} - 8005bcc: 469e mov lr, r3 - 8005bce: 4770 bx lr +0800a094 <_init>: + 800a094: b5f8 push {r3, r4, r5, r6, r7, lr} + 800a096: bf00 nop + 800a098: bcf8 pop {r3, r4, r5, r6, r7} + 800a09a: bc08 pop {r3} + 800a09c: 469e mov lr, r3 + 800a09e: 4770 bx lr -08005bd0 <_fini>: - 8005bd0: b5f8 push {r3, r4, r5, r6, r7, lr} - 8005bd2: bf00 nop - 8005bd4: bcf8 pop {r3, r4, r5, r6, r7} - 8005bd6: bc08 pop {r3} - 8005bd8: 469e mov lr, r3 - 8005bda: 4770 bx lr +0800a0a0 <_fini>: + 800a0a0: b5f8 push {r3, r4, r5, r6, r7, lr} + 800a0a2: bf00 nop + 800a0a4: bcf8 pop {r3, r4, r5, r6, r7} + 800a0a6: bc08 pop {r3} + 800a0a8: 469e mov lr, r3 + 800a0aa: 4770 bx lr diff --git a/Debug/can_logger.map b/Debug/can_logger.map index 32c12c6..4452319 100644 --- a/Debug/can_logger.map +++ b/Debug/can_logger.map @@ -25,7 +25,7 @@ Archive member included to satisfy reference by file (symbol) /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-impure.o) ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o (_impure_ptr) /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-memcpy-stub.o) - ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o (memcpy) + ./Core/Src/canlog.o (memcpy) /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-freer.o) /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-malloc.o) (_free_r) /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-fflush.o) @@ -61,6 +61,83 @@ Discarded input sections .ARM.exidx 0x00000000 0x10 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o .ARM.attributes 0x00000000 0x20 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/canlog.o + .text 0x00000000 0x0 ./Core/Src/canlog.o + .data 0x00000000 0x0 ./Core/Src/canlog.o + .bss 0x00000000 0x0 ./Core/Src/canlog.o + .group 0x00000000 0xc ./Core/Src/freertos.o + .group 0x00000000 0xc ./Core/Src/freertos.o + .group 0x00000000 0xc ./Core/Src/freertos.o + .group 0x00000000 0xc ./Core/Src/freertos.o + .group 0x00000000 0xc ./Core/Src/freertos.o .group 0x00000000 0xc ./Core/Src/freertos.o .group 0x00000000 0xc ./Core/Src/freertos.o .group 0x00000000 0xc ./Core/Src/freertos.o @@ -130,7 +207,7 @@ Discarded input sections .debug_abbrev 0x00000000 0x28 ./Core/Src/freertos.o .debug_aranges 0x00000000 0x18 ./Core/Src/freertos.o - .debug_macro 0x00000000 0x2f0 ./Core/Src/freertos.o + .debug_macro 0x00000000 0x339 ./Core/Src/freertos.o .debug_macro 0x00000000 0xade ./Core/Src/freertos.o .debug_macro 0x00000000 0x190 ./Core/Src/freertos.o .debug_macro 0x00000000 0x22 ./Core/Src/freertos.o @@ -162,7 +239,7 @@ Discarded input sections .debug_macro 0x00000000 0x4bf ./Core/Src/freertos.o .debug_macro 0x00000000 0xb5 ./Core/Src/freertos.o .debug_macro 0x00000000 0xaa ./Core/Src/freertos.o - .debug_macro 0x00000000 0x2a2 ./Core/Src/freertos.o + .debug_macro 0x00000000 0x2a8 ./Core/Src/freertos.o .debug_macro 0x00000000 0x2e ./Core/Src/freertos.o .debug_macro 0x00000000 0x2f ./Core/Src/freertos.o .debug_macro 0x00000000 0x1c ./Core/Src/freertos.o @@ -190,11 +267,16 @@ Discarded input sections .debug_macro 0x00000000 0x127 ./Core/Src/freertos.o .debug_macro 0x00000000 0x7e ./Core/Src/freertos.o .debug_macro 0x00000000 0x89 ./Core/Src/freertos.o + .debug_macro 0x00000000 0x868 ./Core/Src/freertos.o + .debug_macro 0x00000000 0x1d5 ./Core/Src/freertos.o .debug_macro 0x00000000 0x8ed ./Core/Src/freertos.o .debug_macro 0x00000000 0x4d ./Core/Src/freertos.o .debug_macro 0x00000000 0x12d ./Core/Src/freertos.o - .debug_line 0x00000000 0x972 ./Core/Src/freertos.o - .debug_str 0x00000000 0xc04f8 ./Core/Src/freertos.o + .debug_macro 0x00000000 0x6c ./Core/Src/freertos.o + .debug_macro 0x00000000 0x74 ./Core/Src/freertos.o + .debug_macro 0x00000000 0xdd ./Core/Src/freertos.o + .debug_line 0x00000000 0xa02 ./Core/Src/freertos.o + .debug_str 0x00000000 0xc5872 ./Core/Src/freertos.o .comment 0x00000000 0x44 ./Core/Src/freertos.o .ARM.attributes 0x00000000 0x34 ./Core/Src/freertos.o @@ -263,11 +345,13 @@ Discarded input sections .group 0x00000000 0xc ./Core/Src/main.o .group 0x00000000 0xc ./Core/Src/main.o .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o .text 0x00000000 0x0 ./Core/Src/main.o .data 0x00000000 0x0 ./Core/Src/main.o .bss 0x00000000 0x0 ./Core/Src/main.o .debug_macro 0x00000000 0xade ./Core/Src/main.o - .debug_macro 0x00000000 0x2a2 ./Core/Src/main.o + .debug_macro 0x00000000 0x2a8 ./Core/Src/main.o .debug_macro 0x00000000 0x2e ./Core/Src/main.o .debug_macro 0x00000000 0x2f ./Core/Src/main.o .debug_macro 0x00000000 0x22 ./Core/Src/main.o @@ -285,6 +369,7 @@ Discarded input sections .debug_macro 0x00000000 0x6d ./Core/Src/main.o .debug_macro 0x00000000 0x3693 ./Core/Src/main.o .debug_macro 0x00000000 0x190 ./Core/Src/main.o + .debug_macro 0x00000000 0x5c ./Core/Src/main.o .debug_macro 0x00000000 0x8bc ./Core/Src/main.o .debug_macro 0x00000000 0x9e9 ./Core/Src/main.o .debug_macro 0x00000000 0x115 ./Core/Src/main.o @@ -301,9 +386,12 @@ Discarded input sections .debug_macro 0x00000000 0x127 ./Core/Src/main.o .debug_macro 0x00000000 0x7e ./Core/Src/main.o .debug_macro 0x00000000 0x89 ./Core/Src/main.o + .debug_macro 0x00000000 0x868 ./Core/Src/main.o + .debug_macro 0x00000000 0x1d5 ./Core/Src/main.o .debug_macro 0x00000000 0x8ed ./Core/Src/main.o .debug_macro 0x00000000 0x4d ./Core/Src/main.o .debug_macro 0x00000000 0x12d ./Core/Src/main.o + .debug_macro 0x00000000 0x16f ./Core/Src/main.o .debug_macro 0x00000000 0x15a ./Core/Src/main.o .debug_macro 0x00000000 0xc9 ./Core/Src/main.o .debug_macro 0x00000000 0x1c ./Core/Src/main.o @@ -326,6 +414,37 @@ Discarded input sections .debug_macro 0x00000000 0x4bf ./Core/Src/main.o .debug_macro 0x00000000 0xb5 ./Core/Src/main.o .debug_macro 0x00000000 0xaa ./Core/Src/main.o + .debug_macro 0x00000000 0x66 ./Core/Src/main.o + .debug_macro 0x00000000 0x74 ./Core/Src/main.o + .debug_macro 0x00000000 0xdd ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_msp.o @@ -370,8 +489,10 @@ Discarded input sections .bss 0x00000000 0x0 ./Core/Src/stm32f4xx_hal_msp.o .text.HAL_CAN_MspDeInit 0x00000000 0x98 ./Core/Src/stm32f4xx_hal_msp.o + .text.HAL_SD_MspDeInit + 0x00000000 0x64 ./Core/Src/stm32f4xx_hal_msp.o .debug_macro 0x00000000 0xade ./Core/Src/stm32f4xx_hal_msp.o - .debug_macro 0x00000000 0x2a2 ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00000000 0x2a8 ./Core/Src/stm32f4xx_hal_msp.o .debug_macro 0x00000000 0x2e ./Core/Src/stm32f4xx_hal_msp.o .debug_macro 0x00000000 0x2f ./Core/Src/stm32f4xx_hal_msp.o .debug_macro 0x00000000 0x22 ./Core/Src/stm32f4xx_hal_msp.o @@ -406,9 +527,39 @@ Discarded input sections .debug_macro 0x00000000 0x127 ./Core/Src/stm32f4xx_hal_msp.o .debug_macro 0x00000000 0x7e ./Core/Src/stm32f4xx_hal_msp.o .debug_macro 0x00000000 0x89 ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00000000 0x868 ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00000000 0x1d5 ./Core/Src/stm32f4xx_hal_msp.o .debug_macro 0x00000000 0x8ed ./Core/Src/stm32f4xx_hal_msp.o .debug_macro 0x00000000 0x4d ./Core/Src/stm32f4xx_hal_msp.o .debug_macro 0x00000000 0x12d ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00000000 0x16f ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00000000 0x15a ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00000000 0xc9 ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00000000 0x1c ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00000000 0x26 ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00000000 0x61 ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00000000 0x2a ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00000000 0x43 ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00000000 0x34 ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00000000 0x364 ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00000000 0x16 ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00000000 0x4a ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00000000 0x34 ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00000000 0x10 ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00000000 0x58 ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00000000 0x8e ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00000000 0x1c ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00000000 0x17e ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00000000 0x10 ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00000000 0x3c ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00000000 0x4bf ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00000000 0xb5 ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00000000 0xaa ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00000000 0x66 ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00000000 0x74 ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00000000 0xdd ./Core/Src/stm32f4xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_timebase_tim.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_timebase_tim.o .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_timebase_tim.o .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_timebase_tim.o .group 0x00000000 0xc ./Core/Src/stm32f4xx_hal_timebase_tim.o @@ -456,7 +607,7 @@ Discarded input sections .text.HAL_ResumeTick 0x00000000 0x24 ./Core/Src/stm32f4xx_hal_timebase_tim.o .debug_macro 0x00000000 0xade ./Core/Src/stm32f4xx_hal_timebase_tim.o - .debug_macro 0x00000000 0x2a2 ./Core/Src/stm32f4xx_hal_timebase_tim.o + .debug_macro 0x00000000 0x2a8 ./Core/Src/stm32f4xx_hal_timebase_tim.o .debug_macro 0x00000000 0x2e ./Core/Src/stm32f4xx_hal_timebase_tim.o .debug_macro 0x00000000 0x2f ./Core/Src/stm32f4xx_hal_timebase_tim.o .debug_macro 0x00000000 0x22 ./Core/Src/stm32f4xx_hal_timebase_tim.o @@ -491,6 +642,8 @@ Discarded input sections .debug_macro 0x00000000 0x127 ./Core/Src/stm32f4xx_hal_timebase_tim.o .debug_macro 0x00000000 0x7e ./Core/Src/stm32f4xx_hal_timebase_tim.o .debug_macro 0x00000000 0x89 ./Core/Src/stm32f4xx_hal_timebase_tim.o + .debug_macro 0x00000000 0x868 ./Core/Src/stm32f4xx_hal_timebase_tim.o + .debug_macro 0x00000000 0x1d5 ./Core/Src/stm32f4xx_hal_timebase_tim.o .debug_macro 0x00000000 0x8ed ./Core/Src/stm32f4xx_hal_timebase_tim.o .debug_macro 0x00000000 0x4d ./Core/Src/stm32f4xx_hal_timebase_tim.o .debug_macro 0x00000000 0x12d ./Core/Src/stm32f4xx_hal_timebase_tim.o @@ -533,11 +686,39 @@ Discarded input sections .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f4xx_it.o .text 0x00000000 0x0 ./Core/Src/stm32f4xx_it.o .data 0x00000000 0x0 ./Core/Src/stm32f4xx_it.o .bss 0x00000000 0x0 ./Core/Src/stm32f4xx_it.o .debug_macro 0x00000000 0xade ./Core/Src/stm32f4xx_it.o - .debug_macro 0x00000000 0x2a2 ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00000000 0x2a8 ./Core/Src/stm32f4xx_it.o .debug_macro 0x00000000 0x2e ./Core/Src/stm32f4xx_it.o .debug_macro 0x00000000 0x2f ./Core/Src/stm32f4xx_it.o .debug_macro 0x00000000 0x22 ./Core/Src/stm32f4xx_it.o @@ -572,9 +753,37 @@ Discarded input sections .debug_macro 0x00000000 0x127 ./Core/Src/stm32f4xx_it.o .debug_macro 0x00000000 0x7e ./Core/Src/stm32f4xx_it.o .debug_macro 0x00000000 0x89 ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00000000 0x868 ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00000000 0x1d5 ./Core/Src/stm32f4xx_it.o .debug_macro 0x00000000 0x8ed ./Core/Src/stm32f4xx_it.o .debug_macro 0x00000000 0x4d ./Core/Src/stm32f4xx_it.o .debug_macro 0x00000000 0x12d ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00000000 0x16f ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00000000 0x15a ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00000000 0xc9 ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00000000 0x1c ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00000000 0x26 ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00000000 0x61 ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00000000 0x2a ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00000000 0x43 ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00000000 0x34 ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00000000 0x364 ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00000000 0x16 ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00000000 0x4a ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00000000 0x34 ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00000000 0x10 ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00000000 0x58 ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00000000 0x8e ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00000000 0x1c ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00000000 0x17e ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00000000 0x10 ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00000000 0x3c ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00000000 0x4bf ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00000000 0xb5 ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00000000 0xaa ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00000000 0x66 ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00000000 0x74 ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00000000 0xdd ./Core/Src/stm32f4xx_it.o .group 0x00000000 0xc ./Core/Src/syscalls.o .group 0x00000000 0xc ./Core/Src/syscalls.o .group 0x00000000 0xc ./Core/Src/syscalls.o @@ -705,7 +914,7 @@ Discarded input sections .debug_macro 0x00000000 0x16 ./Core/Src/syscalls.o .debug_macro 0x00000000 0xce ./Core/Src/syscalls.o .debug_line 0x00000000 0x8bd ./Core/Src/syscalls.o - .debug_str 0x00000000 0x99d1 ./Core/Src/syscalls.o + .debug_str 0x00000000 0x996c ./Core/Src/syscalls.o .comment 0x00000000 0x44 ./Core/Src/syscalls.o .debug_frame 0x00000000 0x288 ./Core/Src/syscalls.o .ARM.attributes @@ -770,7 +979,7 @@ Discarded input sections .debug_macro 0x00000000 0x6a ./Core/Src/sysmem.o .debug_macro 0x00000000 0x1df ./Core/Src/sysmem.o .debug_line 0x00000000 0x599 ./Core/Src/sysmem.o - .debug_str 0x00000000 0x777b ./Core/Src/sysmem.o + .debug_str 0x00000000 0x7716 ./Core/Src/sysmem.o .comment 0x00000000 0x44 ./Core/Src/sysmem.o .debug_frame 0x00000000 0x34 ./Core/Src/sysmem.o .ARM.attributes @@ -814,6 +1023,8 @@ Discarded input sections .group 0x00000000 0xc ./Core/Src/system_stm32f4xx.o .group 0x00000000 0xc ./Core/Src/system_stm32f4xx.o .group 0x00000000 0xc ./Core/Src/system_stm32f4xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f4xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f4xx.o .text 0x00000000 0x0 ./Core/Src/system_stm32f4xx.o .data 0x00000000 0x0 ./Core/Src/system_stm32f4xx.o .bss 0x00000000 0x0 ./Core/Src/system_stm32f4xx.o @@ -835,7 +1046,7 @@ Discarded input sections .debug_macro 0x00000000 0x11f ./Core/Src/system_stm32f4xx.o .debug_macro 0x00000000 0x1427b ./Core/Src/system_stm32f4xx.o .debug_macro 0x00000000 0x6d ./Core/Src/system_stm32f4xx.o - .debug_macro 0x00000000 0x2a2 ./Core/Src/system_stm32f4xx.o + .debug_macro 0x00000000 0x2a8 ./Core/Src/system_stm32f4xx.o .debug_macro 0x00000000 0x3693 ./Core/Src/system_stm32f4xx.o .debug_macro 0x00000000 0x190 ./Core/Src/system_stm32f4xx.o .debug_macro 0x00000000 0x5c ./Core/Src/system_stm32f4xx.o @@ -855,6 +1066,8 @@ Discarded input sections .debug_macro 0x00000000 0x127 ./Core/Src/system_stm32f4xx.o .debug_macro 0x00000000 0x7e ./Core/Src/system_stm32f4xx.o .debug_macro 0x00000000 0x89 ./Core/Src/system_stm32f4xx.o + .debug_macro 0x00000000 0x868 ./Core/Src/system_stm32f4xx.o + .debug_macro 0x00000000 0x1d5 ./Core/Src/system_stm32f4xx.o .debug_macro 0x00000000 0x8ed ./Core/Src/system_stm32f4xx.o .debug_macro 0x00000000 0x4d ./Core/Src/system_stm32f4xx.o .debug_macro 0x00000000 0x12d ./Core/Src/system_stm32f4xx.o @@ -1024,6 +1237,8 @@ Discarded input sections .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .text 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .data 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .bss 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o @@ -1042,8 +1257,6 @@ Discarded input sections 0x00000000 0x70 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .text.HAL_GetTickFreq 0x00000000 0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o - .text.HAL_Delay - 0x00000000 0x48 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .text.HAL_SuspendTick 0x00000000 0x20 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .text.HAL_ResumeTick @@ -1077,7 +1290,7 @@ Discarded input sections .text.HAL_GetUIDw2 0x00000000 0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .debug_macro 0x00000000 0xade ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o - .debug_macro 0x00000000 0x2a2 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x00000000 0x2a8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .debug_macro 0x00000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .debug_macro 0x00000000 0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .debug_macro 0x00000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o @@ -1112,6 +1325,8 @@ Discarded input sections .debug_macro 0x00000000 0x127 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .debug_macro 0x00000000 0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .debug_macro 0x00000000 0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x00000000 0x868 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x00000000 0x1d5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .debug_macro 0x00000000 0x8ed ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .debug_macro 0x00000000 0x4d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .debug_macro 0x00000000 0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o @@ -1154,6 +1369,8 @@ Discarded input sections .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o .text 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o .data 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o .bss 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o @@ -1167,10 +1384,6 @@ Discarded input sections 0x00000000 0x160 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o .text.HAL_CAN_UnRegisterCallback 0x00000000 0x184 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o - .text.HAL_CAN_ConfigFilter - 0x00000000 0x298 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o - .text.HAL_CAN_Start - 0x00000000 0x88 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o .text.HAL_CAN_Stop 0x00000000 0x92 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o .text.HAL_CAN_RequestSleep @@ -1189,24 +1402,18 @@ Discarded input sections 0x00000000 0x58 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o .text.HAL_CAN_GetTxTimestamp 0x00000000 0x88 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o - .text.HAL_CAN_GetRxMessage - 0x00000000 0x25c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o .text.HAL_CAN_GetRxFifoFillLevel 0x00000000 0x68 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o - .text.HAL_CAN_ActivateNotification - 0x00000000 0x64 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o .text.HAL_CAN_DeactivateNotification 0x00000000 0x64 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o .text.HAL_CAN_IRQHandler 0x00000000 0x38a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o - .text.HAL_CAN_GetState - 0x00000000 0x50 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o - .text.HAL_CAN_GetError - 0x00000000 0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o + .text.HAL_CAN_RxFifo0MsgPendingCallback + 0x00000000 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o .text.HAL_CAN_ResetError 0x00000000 0x46 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o .debug_macro 0x00000000 0xade ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o - .debug_macro 0x00000000 0x2a2 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o + .debug_macro 0x00000000 0x2a8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o .debug_macro 0x00000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o .debug_macro 0x00000000 0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o .debug_macro 0x00000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o @@ -1241,6 +1448,8 @@ Discarded input sections .debug_macro 0x00000000 0x127 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o .debug_macro 0x00000000 0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o .debug_macro 0x00000000 0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o + .debug_macro 0x00000000 0x868 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o + .debug_macro 0x00000000 0x1d5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o .debug_macro 0x00000000 0x8ed ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o .debug_macro 0x00000000 0x4d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o .debug_macro 0x00000000 0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o @@ -1283,6 +1492,8 @@ Discarded input sections .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .text 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .data 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .bss 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o @@ -1341,7 +1552,7 @@ Discarded input sections .text.HAL_SYSTICK_Callback 0x00000000 0xe ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .debug_macro 0x00000000 0xade ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o - .debug_macro 0x00000000 0x2a2 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x00000000 0x2a8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .debug_macro 0x00000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .debug_macro 0x00000000 0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .debug_macro 0x00000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o @@ -1376,6 +1587,8 @@ Discarded input sections .debug_macro 0x00000000 0x127 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .debug_macro 0x00000000 0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .debug_macro 0x00000000 0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x00000000 0x868 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x00000000 0x1d5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .debug_macro 0x00000000 0x8ed ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .debug_macro 0x00000000 0x4d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .debug_macro 0x00000000 0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o @@ -1418,12 +1631,11 @@ Discarded input sections .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .text 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .data 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .bss 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o - .rodata 0x00000000 0x38 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o - .text.HAL_DMA_Init - 0x00000000 0x434 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .text.HAL_DMA_DeInit 0x00000000 0x1ac ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .text.HAL_DMA_Start @@ -1432,12 +1644,8 @@ Discarded input sections 0x00000000 0xcc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .text.HAL_DMA_Abort 0x00000000 0xe0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o - .text.HAL_DMA_Abort_IT - 0x00000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .text.HAL_DMA_PollForTransfer 0x00000000 0x1be ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o - .text.HAL_DMA_IRQHandler - 0x00000000 0x314 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .text.HAL_DMA_RegisterCallback 0x00000000 0xa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .text.HAL_DMA_UnRegisterCallback @@ -1448,21 +1656,8 @@ Discarded input sections 0x00000000 0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .text.DMA_SetConfig 0x00000000 0x5c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o - .text.DMA_CalcBaseAndBitshift - 0x00000000 0x6c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o - .text.DMA_CheckFifoParam - 0x00000000 0xf8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o - .rodata.flagBitshiftOffset.0 - 0x00000000 0x8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o - .debug_info 0x00000000 0x904 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o - .debug_abbrev 0x00000000 0x279 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o - .debug_aranges - 0x00000000 0x90 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o - .debug_rnglists - 0x00000000 0x71 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o - .debug_macro 0x00000000 0x1d4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .debug_macro 0x00000000 0xade ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o - .debug_macro 0x00000000 0x2a2 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x00000000 0x2a8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .debug_macro 0x00000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .debug_macro 0x00000000 0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .debug_macro 0x00000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o @@ -1497,15 +1692,13 @@ Discarded input sections .debug_macro 0x00000000 0x127 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .debug_macro 0x00000000 0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .debug_macro 0x00000000 0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x00000000 0x868 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x00000000 0x1d5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .debug_macro 0x00000000 0x8ed ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .debug_macro 0x00000000 0x4d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .debug_macro 0x00000000 0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o - .debug_line 0x00000000 0x1156 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o - .debug_str 0x00000000 0xb9c33 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o - .comment 0x00000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o - .debug_frame 0x00000000 0x234 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o - .ARM.attributes - 0x00000000 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o @@ -1563,9 +1756,9 @@ Discarded input sections 0x00000000 0x38 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .debug_rnglists 0x00000000 0x27 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o - .debug_macro 0x00000000 0x1ce ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x00000000 0x1e7 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .debug_macro 0x00000000 0xade ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o - .debug_macro 0x00000000 0x2a2 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x00000000 0x2a8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .debug_macro 0x00000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .debug_macro 0x00000000 0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .debug_macro 0x00000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o @@ -1600,11 +1793,13 @@ Discarded input sections .debug_macro 0x00000000 0x127 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .debug_macro 0x00000000 0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .debug_macro 0x00000000 0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x00000000 0x868 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x00000000 0x1d5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .debug_macro 0x00000000 0x8ed ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .debug_macro 0x00000000 0x4d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .debug_macro 0x00000000 0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o - .debug_line 0x00000000 0x13c6 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o - .debug_str 0x00000000 0xb99ff ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_line 0x00000000 0x13f4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_str 0x00000000 0xbe1e1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .comment 0x00000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .debug_frame 0x00000000 0xa4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .ARM.attributes @@ -1648,6 +1843,8 @@ Discarded input sections .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .text 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .data 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .bss 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o @@ -1676,9 +1873,9 @@ Discarded input sections 0x00000000 0x60 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .debug_rnglists 0x00000000 0x49 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o - .debug_macro 0x00000000 0x1ce ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x00000000 0x1e7 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .debug_macro 0x00000000 0xade ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o - .debug_macro 0x00000000 0x2a2 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x00000000 0x2a8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .debug_macro 0x00000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .debug_macro 0x00000000 0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .debug_macro 0x00000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o @@ -1713,11 +1910,13 @@ Discarded input sections .debug_macro 0x00000000 0x127 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .debug_macro 0x00000000 0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .debug_macro 0x00000000 0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x00000000 0x868 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x00000000 0x1d5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .debug_macro 0x00000000 0x8ed ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .debug_macro 0x00000000 0x4d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .debug_macro 0x00000000 0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o - .debug_line 0x00000000 0xb6e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o - .debug_str 0x00000000 0xb9897 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_line 0x00000000 0xb9c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_str 0x00000000 0xbe079 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .comment 0x00000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .debug_frame 0x00000000 0x158 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .ARM.attributes @@ -1761,6 +1960,8 @@ Discarded input sections .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .text 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .data 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .bss 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o @@ -1806,9 +2007,9 @@ Discarded input sections 0x00000000 0xa0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .debug_rnglists 0x00000000 0x79 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o - .debug_macro 0x00000000 0x1d4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x00000000 0x1ed ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .debug_macro 0x00000000 0xade ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o - .debug_macro 0x00000000 0x2a2 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x00000000 0x2a8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .debug_macro 0x00000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .debug_macro 0x00000000 0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .debug_macro 0x00000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o @@ -1843,11 +2044,13 @@ Discarded input sections .debug_macro 0x00000000 0x127 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .debug_macro 0x00000000 0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .debug_macro 0x00000000 0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x00000000 0x868 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x00000000 0x1d5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .debug_macro 0x00000000 0x8ed ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .debug_macro 0x00000000 0x4d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .debug_macro 0x00000000 0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o - .debug_line 0x00000000 0xb5c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o - .debug_str 0x00000000 0xb9a09 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_line 0x00000000 0xb8a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_str 0x00000000 0xbe1eb ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .comment 0x00000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .debug_frame 0x00000000 0x244 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .ARM.attributes @@ -1891,6 +2094,8 @@ Discarded input sections .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .text 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .data 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .bss 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o @@ -1933,9 +2138,9 @@ Discarded input sections 0x00000000 0x98 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .debug_rnglists 0x00000000 0x73 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o - .debug_macro 0x00000000 0x1d4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x00000000 0x1ed ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .debug_macro 0x00000000 0xade ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o - .debug_macro 0x00000000 0x2a2 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x00000000 0x2a8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .debug_macro 0x00000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .debug_macro 0x00000000 0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .debug_macro 0x00000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o @@ -1970,11 +2175,13 @@ Discarded input sections .debug_macro 0x00000000 0x127 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .debug_macro 0x00000000 0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .debug_macro 0x00000000 0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x00000000 0x868 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x00000000 0x1d5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .debug_macro 0x00000000 0x8ed ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .debug_macro 0x00000000 0x4d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .debug_macro 0x00000000 0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o - .debug_line 0x00000000 0xc27 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o - .debug_str 0x00000000 0xb9a59 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_line 0x00000000 0xc55 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_str 0x00000000 0xbe23b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .comment 0x00000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .debug_frame 0x00000000 0x230 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .ARM.attributes @@ -2018,6 +2225,8 @@ Discarded input sections .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .text 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .data 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .bss 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o @@ -2025,9 +2234,9 @@ Discarded input sections .debug_abbrev 0x00000000 0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .debug_aranges 0x00000000 0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o - .debug_macro 0x00000000 0x1ce ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x00000000 0x1e7 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .debug_macro 0x00000000 0xade ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o - .debug_macro 0x00000000 0x2a2 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x00000000 0x2a8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .debug_macro 0x00000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .debug_macro 0x00000000 0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .debug_macro 0x00000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o @@ -2062,11 +2271,13 @@ Discarded input sections .debug_macro 0x00000000 0x127 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .debug_macro 0x00000000 0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .debug_macro 0x00000000 0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x00000000 0x868 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x00000000 0x1d5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .debug_macro 0x00000000 0x8ed ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .debug_macro 0x00000000 0x4d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .debug_macro 0x00000000 0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o - .debug_line 0x00000000 0x73a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o - .debug_str 0x00000000 0xb9650 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_line 0x00000000 0x768 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_str 0x00000000 0xbde32 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .comment 0x00000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .ARM.attributes 0x00000000 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o @@ -2109,6 +2320,8 @@ Discarded input sections .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .text 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .data 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .bss 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o @@ -2116,10 +2329,6 @@ Discarded input sections 0x00000000 0x24c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .text.HAL_GPIO_ReadPin 0x00000000 0x40 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o - .text.HAL_GPIO_WritePin - 0x00000000 0x58 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o - .text.HAL_GPIO_TogglePin - 0x00000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .text.HAL_GPIO_LockPin 0x00000000 0x60 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .text.HAL_GPIO_EXTI_IRQHandler @@ -2127,7 +2336,7 @@ Discarded input sections .text.HAL_GPIO_EXTI_Callback 0x00000000 0x16 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .debug_macro 0x00000000 0xade ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o - .debug_macro 0x00000000 0x2a2 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x00000000 0x2a8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .debug_macro 0x00000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .debug_macro 0x00000000 0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .debug_macro 0x00000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o @@ -2162,9 +2371,108 @@ Discarded input sections .debug_macro 0x00000000 0x127 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .debug_macro 0x00000000 0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .debug_macro 0x00000000 0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x00000000 0x868 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x00000000 0x1d5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .debug_macro 0x00000000 0x8ed ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .debug_macro 0x00000000 0x4d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .debug_macro 0x00000000 0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .text 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .data 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .bss 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_info 0x00000000 0x70 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_abbrev 0x00000000 0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_aranges + 0x00000000 0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x1e8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0xade ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x2a8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x8e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x51 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x103 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x6a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x1df ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0xfb ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x1011 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x11f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x1427b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x6d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x3693 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x190 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x5c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x8bc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x9e9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x115 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x130 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0xa5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x416 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x12c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x21e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x127 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x868 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x1d5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x8ed ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x4d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_macro 0x00000000 0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_line 0x00000000 0x75e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .debug_str 0x00000000 0xbde28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .comment 0x00000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .ARM.attributes + 0x00000000 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o @@ -2248,9 +2556,9 @@ Discarded input sections 0x00000000 0xa0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .debug_rnglists 0x00000000 0x75 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o - .debug_macro 0x00000000 0x1e6 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x00000000 0x1ff ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .debug_macro 0x00000000 0xade ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o - .debug_macro 0x00000000 0x2a2 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x00000000 0x2a8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .debug_macro 0x00000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .debug_macro 0x00000000 0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .debug_macro 0x00000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o @@ -2285,11 +2593,13 @@ Discarded input sections .debug_macro 0x00000000 0x127 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .debug_macro 0x00000000 0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .debug_macro 0x00000000 0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x00000000 0x868 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x00000000 0x1d5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .debug_macro 0x00000000 0x8ed ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .debug_macro 0x00000000 0x4d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .debug_macro 0x00000000 0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o - .debug_line 0x00000000 0x9d7 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o - .debug_str 0x00000000 0xb9a4f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_line 0x00000000 0xa05 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_str 0x00000000 0xbe231 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .comment 0x00000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .debug_frame 0x00000000 0x224 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .ARM.attributes @@ -2333,6 +2643,8 @@ Discarded input sections .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .text 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .data 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .bss 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o @@ -2355,9 +2667,9 @@ Discarded input sections 0x00000000 0x48 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .debug_rnglists 0x00000000 0x32 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o - .debug_macro 0x00000000 0x1e6 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x1ff ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .debug_macro 0x00000000 0xade ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o - .debug_macro 0x00000000 0x2a2 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x2a8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .debug_macro 0x00000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .debug_macro 0x00000000 0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .debug_macro 0x00000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o @@ -2392,11 +2704,13 @@ Discarded input sections .debug_macro 0x00000000 0x127 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .debug_macro 0x00000000 0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .debug_macro 0x00000000 0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x868 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x1d5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .debug_macro 0x00000000 0x8ed ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .debug_macro 0x00000000 0x4d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .debug_macro 0x00000000 0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o - .debug_line 0x00000000 0x852 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o - .debug_str 0x00000000 0xb992a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_line 0x00000000 0x880 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_str 0x00000000 0xbe10c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .comment 0x00000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .debug_frame 0x00000000 0xd0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .ARM.attributes @@ -2440,6 +2754,8 @@ Discarded input sections .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .text 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .data 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .bss 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o @@ -2460,7 +2776,7 @@ Discarded input sections .text.HAL_RCC_CSSCallback 0x00000000 0xe ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .debug_macro 0x00000000 0xade ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o - .debug_macro 0x00000000 0x2a2 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x00000000 0x2a8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .debug_macro 0x00000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .debug_macro 0x00000000 0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .debug_macro 0x00000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o @@ -2495,6 +2811,8 @@ Discarded input sections .debug_macro 0x00000000 0x127 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .debug_macro 0x00000000 0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .debug_macro 0x00000000 0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x00000000 0x868 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x00000000 0x1d5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .debug_macro 0x00000000 0x8ed ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .debug_macro 0x00000000 0x4d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .debug_macro 0x00000000 0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o @@ -2537,6 +2855,8 @@ Discarded input sections .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .text 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .data 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .bss 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o @@ -2559,9 +2879,9 @@ Discarded input sections 0x00000000 0x48 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .debug_rnglists 0x00000000 0x35 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o - .debug_macro 0x00000000 0x1ce ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x1e7 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .debug_macro 0x00000000 0xade ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o - .debug_macro 0x00000000 0x2a2 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x2a8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .debug_macro 0x00000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .debug_macro 0x00000000 0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .debug_macro 0x00000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o @@ -2596,15 +2916,148 @@ Discarded input sections .debug_macro 0x00000000 0x127 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .debug_macro 0x00000000 0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .debug_macro 0x00000000 0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x868 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x1d5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .debug_macro 0x00000000 0x8ed ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .debug_macro 0x00000000 0x4d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .debug_macro 0x00000000 0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o - .debug_line 0x00000000 0xb81 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o - .debug_str 0x00000000 0xb996b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_line 0x00000000 0xbaf ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_str 0x00000000 0xbe14d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .comment 0x00000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .debug_frame 0x00000000 0xec ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .ARM.attributes 0x00000000 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .data 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .bss 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.HAL_SD_DeInit + 0x00000000 0x5c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.HAL_SD_MspInit + 0x00000000 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.HAL_SD_MspDeInit + 0x00000000 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.HAL_SD_ReadBlocks + 0x00000000 0x3cc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.HAL_SD_WriteBlocks + 0x00000000 0x31c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.HAL_SD_ReadBlocks_IT + 0x00000000 0x134 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.HAL_SD_WriteBlocks_IT + 0x00000000 0x134 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.HAL_SD_ReadBlocks_DMA + 0x00000000 0x1c4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.HAL_SD_WriteBlocks_DMA + 0x00000000 0x1cc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.HAL_SD_Erase + 0x00000000 0x198 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.HAL_SD_GetState + 0x00000000 0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.HAL_SD_GetError + 0x00000000 0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.HAL_SD_GetCardCID + 0x00000000 0xae ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.HAL_SD_GetCardStatus + 0x00000000 0x144 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.HAL_SD_GetCardInfo + 0x00000000 0x58 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.HAL_SD_Abort + 0x00000000 0xfc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.HAL_SD_Abort_IT + 0x00000000 0x110 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.SD_DMATransmitCplt + 0x00000000 0x2a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.SD_DMAReceiveCplt + 0x00000000 0x70 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.SD_DMAError + 0x00000000 0xa4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.SD_PowerOFF + 0x00000000 0x1a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.SD_SendSDStatus + 0x00000000 0x1ae ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0xade ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x2a8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x8e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x51 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x103 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x6a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x1df ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0xfb ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x1011 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x11f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x1427b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x6d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x3693 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x190 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x5c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x8bc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x9e9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x115 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x130 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0xa5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x416 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x12c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x21e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x127 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x868 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x1d5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x8ed ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x4d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_macro 0x00000000 0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o @@ -2868,7 +3321,7 @@ Discarded input sections .text.TIM_CCxChannelCmd 0x00000000 0x108 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .debug_macro 0x00000000 0xade ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o - .debug_macro 0x00000000 0x2a2 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x00000000 0x2a8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .debug_macro 0x00000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .debug_macro 0x00000000 0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .debug_macro 0x00000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o @@ -2903,6 +3356,8 @@ Discarded input sections .debug_macro 0x00000000 0x127 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .debug_macro 0x00000000 0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .debug_macro 0x00000000 0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x00000000 0x868 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x00000000 0x1d5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .debug_macro 0x00000000 0x8ed ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .debug_macro 0x00000000 0x4d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .debug_macro 0x00000000 0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o @@ -2945,6 +3400,8 @@ Discarded input sections .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .text 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .data 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .bss 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o @@ -3030,7 +3487,7 @@ Discarded input sections .text.TIM_CCxNChannelCmd 0x00000000 0x4a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .debug_macro 0x00000000 0xade ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o - .debug_macro 0x00000000 0x2a2 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x00000000 0x2a8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .debug_macro 0x00000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .debug_macro 0x00000000 0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .debug_macro 0x00000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o @@ -3065,9 +3522,134 @@ Discarded input sections .debug_macro 0x00000000 0x127 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .debug_macro 0x00000000 0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .debug_macro 0x00000000 0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x00000000 0x868 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x00000000 0x1d5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .debug_macro 0x00000000 0x8ed ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .debug_macro 0x00000000 0x4d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .debug_macro 0x00000000 0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .text 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .data 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .bss 0x00000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .text.SDIO_PowerState_OFF + 0x00000000 0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .text.SDIO_GetDataCounter + 0x00000000 0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .text.SDIO_GetFIFOCount + 0x00000000 0x1a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .text.SDIO_SetSDMMCReadWaitMode + 0x00000000 0x40 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .text.SDMMC_CmdReadSingleBlock + 0x00000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .text.SDMMC_CmdReadMultiBlock + 0x00000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .text.SDMMC_CmdWriteSingleBlock + 0x00000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .text.SDMMC_CmdWriteMultiBlock + 0x00000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .text.SDMMC_CmdSDEraseStartAdd + 0x00000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .text.SDMMC_CmdSDEraseEndAdd + 0x00000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .text.SDMMC_CmdEraseStartAdd + 0x00000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .text.SDMMC_CmdEraseEndAdd + 0x00000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .text.SDMMC_CmdErase + 0x00000000 0x42 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .text.SDMMC_CmdSetRelAddMmc + 0x00000000 0x48 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .text.SDMMC_CmdStatusRegister + 0x00000000 0x42 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .text.SDMMC_CmdOpCondition + 0x00000000 0x3e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .text.SDMMC_CmdSwitch + 0x00000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .text.SDMMC_CmdSendEXTCSD + 0x00000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0xade ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x2a8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x8e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x51 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x103 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x6a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x1df ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0xfb ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x1011 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x11f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x1427b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x6d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x3693 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x190 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x5c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x8bc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x9e9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x115 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x130 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0xa5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x416 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x12c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x21e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x127 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x868 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x1d5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x8ed ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x4d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_macro 0x00000000 0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .group 0x00000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x00000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .group 0x00000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .group 0x00000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .group 0x00000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o @@ -3200,16 +3782,11 @@ Discarded input sections 0x00000000 0x42 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .text.osThreadFlagsWait 0x00000000 0x102 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .text.osDelay 0x00000000 0x36 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .text.osDelayUntil 0x00000000 0x5a ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o - .text.TimerCallback - 0x00000000 0x2a ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o - .text.osTimerNew - 0x00000000 0xf8 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .text.osTimerGetName 0x00000000 0x36 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o - .text.osTimerStart - 0x00000000 0x5c ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .text.osTimerStop 0x00000000 0x6e ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .text.osTimerIsRunning @@ -3238,22 +3815,10 @@ Discarded input sections 0x00000000 0x3a ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .text.osMutexDelete 0x00000000 0x4c ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o - .text.osSemaphoreNew - 0x00000000 0x112 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o - .text.osSemaphoreAcquire - 0x00000000 0xa4 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o - .text.osSemaphoreRelease - 0x00000000 0x88 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .text.osSemaphoreGetCount 0x00000000 0x40 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .text.osSemaphoreDelete 0x00000000 0x48 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o - .text.osMessageQueueNew - 0x00000000 0xe6 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o - .text.osMessageQueuePut - 0x00000000 0xc0 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o - .text.osMessageQueueGet - 0x00000000 0xbc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .text.osMessageQueueGetCapacity 0x00000000 0x2c ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .text.osMessageQueueGetMsgSize @@ -3309,6 +3874,7 @@ Discarded input sections .debug_macro 0x00000000 0x1c ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .debug_macro 0x00000000 0x17e ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .debug_macro 0x00000000 0x3c ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x00000000 0x20 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .debug_macro 0x00000000 0x103 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .debug_macro 0x00000000 0x6a ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .debug_macro 0x00000000 0x1df ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o @@ -3329,7 +3895,7 @@ Discarded input sections .debug_macro 0x00000000 0x11f ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .debug_macro 0x00000000 0x1427b ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .debug_macro 0x00000000 0x6d ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o - .debug_macro 0x00000000 0x2a2 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x00000000 0x2a8 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .debug_macro 0x00000000 0x3693 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .debug_macro 0x00000000 0x56 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .debug_macro 0x00000000 0x8bc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o @@ -3348,6 +3914,8 @@ Discarded input sections .debug_macro 0x00000000 0x127 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .debug_macro 0x00000000 0x7e ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .debug_macro 0x00000000 0x89 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x00000000 0x868 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x00000000 0x1d5 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .debug_macro 0x00000000 0x8ed ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .debug_macro 0x00000000 0x4d ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .debug_macro 0x00000000 0x12d ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o @@ -3424,7 +3992,7 @@ Discarded input sections .debug_macro 0x00000000 0xaa ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o .debug_macro 0x00000000 0x43 ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o .debug_line 0x00000000 0x689 ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o - .debug_str 0x00000000 0xb651 ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_str 0x00000000 0xb5ec ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o .comment 0x00000000 0x44 ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o .ARM.attributes 0x00000000 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o @@ -3541,7 +4109,7 @@ Discarded input sections .debug_macro 0x00000000 0xaa ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o .debug_macro 0x00000000 0x91 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o .debug_line 0x00000000 0xb90 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o - .debug_str 0x00000000 0xc0c5 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_str 0x00000000 0xc060 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o .comment 0x00000000 0x44 ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o .debug_frame 0x00000000 0x22c ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o .ARM.attributes @@ -3658,8 +4226,6 @@ Discarded input sections .text 0x00000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o .data 0x00000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o .bss 0x00000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o - .text.xQueueGenericCreate - 0x00000000 0x76 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o .text.prvInitialiseMutex 0x00000000 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o .text.xQueueCreateMutex @@ -3674,18 +4240,8 @@ Discarded input sections 0x00000000 0x6a ./Middlewares/Third_Party/FreeRTOS/Source/queue.o .text.xQueueTakeMutexRecursive 0x00000000 0x6e ./Middlewares/Third_Party/FreeRTOS/Source/queue.o - .text.xQueueCreateCountingSemaphoreStatic - 0x00000000 0x72 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o - .text.xQueueCreateCountingSemaphore - 0x00000000 0x6a ./Middlewares/Third_Party/FreeRTOS/Source/queue.o - .text.xQueueGiveFromISR - 0x00000000 0x120 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o - .text.xQueueSemaphoreTake - 0x00000000 0x220 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o .text.xQueuePeek 0x00000000 0x1c8 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o - .text.xQueueReceiveFromISR - 0x00000000 0x104 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o .text.xQueuePeekFromISR 0x00000000 0xd8 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o .text.uxQueueMessagesWaiting @@ -3694,24 +4250,18 @@ Discarded input sections 0x00000000 0x48 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o .text.uxQueueMessagesWaitingFromISR 0x00000000 0x3e ./Middlewares/Third_Party/FreeRTOS/Source/queue.o - .text.vQueueDelete - 0x00000000 0x48 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o .text.uxQueueGetQueueNumber 0x00000000 0x18 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o .text.vQueueSetQueueNumber 0x00000000 0x1c ./Middlewares/Third_Party/FreeRTOS/Source/queue.o .text.ucQueueGetQueueType 0x00000000 0x1a ./Middlewares/Third_Party/FreeRTOS/Source/queue.o - .text.prvGetDisinheritPriorityAfterTimeout - 0x00000000 0x30 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o .text.xQueueIsQueueEmptyFromISR 0x00000000 0x4a ./Middlewares/Third_Party/FreeRTOS/Source/queue.o .text.xQueueIsQueueFullFromISR 0x00000000 0x4e ./Middlewares/Third_Party/FreeRTOS/Source/queue.o .text.pcQueueGetName 0x00000000 0x4c ./Middlewares/Third_Party/FreeRTOS/Source/queue.o - .text.vQueueUnregisterQueue - 0x00000000 0x54 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o .debug_macro 0x00000000 0xade ./Middlewares/Third_Party/FreeRTOS/Source/queue.o .debug_macro 0x00000000 0x2a ./Middlewares/Third_Party/FreeRTOS/Source/queue.o .debug_macro 0x00000000 0x22 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o @@ -3734,6 +4284,7 @@ Discarded input sections .debug_macro 0x00000000 0x17e ./Middlewares/Third_Party/FreeRTOS/Source/queue.o .debug_macro 0x00000000 0x16 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o .debug_macro 0x00000000 0x29 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x00000000 0x16 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o .debug_macro 0x00000000 0x3c ./Middlewares/Third_Party/FreeRTOS/Source/queue.o .debug_macro 0x00000000 0x20 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o .debug_macro 0x00000000 0x103 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o @@ -3877,7 +4428,7 @@ Discarded input sections .debug_macro 0x00000000 0xaa ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o .debug_macro 0x00000000 0x18 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o .debug_line 0x00000000 0xfeb ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o - .debug_str 0x00000000 0xc175 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_str 0x00000000 0xc110 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o .comment 0x00000000 0x44 ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o .debug_frame 0x00000000 0x3ac ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o .ARM.attributes @@ -3928,6 +4479,8 @@ Discarded input sections 0x00000000 0xe8 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o .text.vTaskDelayUntil 0x00000000 0x100 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskDelay + 0x00000000 0x6c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o .text.eTaskGetState 0x00000000 0xd0 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o .text.uxTaskPriorityGet @@ -3976,14 +4529,8 @@ Discarded input sections 0x00000000 0x38 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o .text.xTaskGetCurrentTaskHandle 0x00000000 0x20 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o - .text.xTaskPriorityInherit - 0x00000000 0xd0 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o - .text.vTaskPriorityDisinheritAfterTimeout - 0x00000000 0x108 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o .text.uxTaskResetEventItemValue 0x00000000 0x30 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o - .text.pvTaskIncrementMutexHeldCount - 0x00000000 0x28 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o .text.ulTaskNotifyTake 0x00000000 0x98 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o .text.xTaskNotifyWait @@ -4076,12 +4623,6 @@ Discarded input sections .text 0x00000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o .data 0x00000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o .bss 0x00000000 0x0 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o - .text.xTimerCreate - 0x00000000 0x42 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o - .text.xTimerCreateStatic - 0x00000000 0x80 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o - .text.prvInitialiseNewTimer - 0x00000000 0x78 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o .text.xTimerGetTimerDaemonTaskHandle 0x00000000 0x3c ./Middlewares/Third_Party/FreeRTOS/Source/timers.o .text.xTimerGetPeriod @@ -4096,8 +4637,6 @@ Discarded input sections 0x00000000 0x3a ./Middlewares/Third_Party/FreeRTOS/Source/timers.o .text.xTimerIsTimerActive 0x00000000 0x54 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o - .text.pvTimerGetTimerID - 0x00000000 0x42 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o .text.vTimerSetTimerID 0x00000000 0x42 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o .text.xTimerPendFunctionCallFromISR @@ -4478,6 +5017,7 @@ Linker script and memory map LOAD /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/crti.o LOAD /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/crtbegin.o LOAD /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o +LOAD ./Core/Src/canlog.o LOAD ./Core/Src/freertos.o LOAD ./Core/Src/main.o LOAD ./Core/Src/stm32f4xx_hal_msp.o @@ -4498,12 +5038,15 @@ LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o LOAD ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o LOAD ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o LOAD ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o @@ -4545,7 +5088,7 @@ LOAD /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/ 0x08000000 g_pfnVectors 0x08000188 . = ALIGN (0x4) -.text 0x08000190 0x5a4c +.text 0x08000190 0x9f1c 0x08000190 . = ALIGN (0x4) *(.text) .text 0x08000190 0x40 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/crtbegin.o @@ -4557,640 +5100,920 @@ LOAD /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/ 0x080004f8 __aeabi_ldiv0 0x080004f8 __aeabi_idiv0 *(.text*) - .text.main 0x080004fc 0x40 ./Core/Src/main.o - 0x080004fc main - .text.SystemClock_Config - 0x0800053c 0xbc ./Core/Src/main.o - 0x0800053c SystemClock_Config - .text.MX_CAN1_Init - 0x080005f8 0x68 ./Core/Src/main.o - .text.MX_CAN2_Init - 0x08000660 0x68 ./Core/Src/main.o - .text.MX_GPIO_Init - 0x080006c8 0x140 ./Core/Src/main.o - .text.StartDefaultTask - 0x08000808 0x10 ./Core/Src/main.o - 0x08000808 StartDefaultTask - .text.HAL_TIM_PeriodElapsedCallback - 0x08000818 0x24 ./Core/Src/main.o - 0x08000818 HAL_TIM_PeriodElapsedCallback - .text.Error_Handler - 0x0800083c 0xc ./Core/Src/main.o - 0x0800083c Error_Handler - .text.assert_failed - 0x08000848 0x16 ./Core/Src/main.o - 0x08000848 assert_failed - *fill* 0x0800085e 0x2 - .text.HAL_MspInit - 0x08000860 0x58 ./Core/Src/stm32f4xx_hal_msp.o - 0x08000860 HAL_MspInit - .text.HAL_CAN_MspInit - 0x080008b8 0x140 ./Core/Src/stm32f4xx_hal_msp.o - 0x080008b8 HAL_CAN_MspInit - .text.HAL_InitTick - 0x080009f8 0xf8 ./Core/Src/stm32f4xx_hal_timebase_tim.o - 0x080009f8 HAL_InitTick - .text.NMI_Handler - 0x08000af0 0x8 ./Core/Src/stm32f4xx_it.o - 0x08000af0 NMI_Handler - .text.HardFault_Handler - 0x08000af8 0x8 ./Core/Src/stm32f4xx_it.o - 0x08000af8 HardFault_Handler - .text.MemManage_Handler - 0x08000b00 0x8 ./Core/Src/stm32f4xx_it.o - 0x08000b00 MemManage_Handler - .text.BusFault_Handler - 0x08000b08 0x8 ./Core/Src/stm32f4xx_it.o - 0x08000b08 BusFault_Handler - .text.UsageFault_Handler - 0x08000b10 0x8 ./Core/Src/stm32f4xx_it.o - 0x08000b10 UsageFault_Handler - .text.DebugMon_Handler - 0x08000b18 0xe ./Core/Src/stm32f4xx_it.o - 0x08000b18 DebugMon_Handler - *fill* 0x08000b26 0x2 - .text.TIM6_DAC_IRQHandler - 0x08000b28 0x14 ./Core/Src/stm32f4xx_it.o - 0x08000b28 TIM6_DAC_IRQHandler - .text.SystemInit - 0x08000b3c 0x24 ./Core/Src/system_stm32f4xx.o - 0x08000b3c SystemInit - .text.Reset_Handler - 0x08000b60 0x50 ./Core/Startup/startup_stm32f405rgtx.o - 0x08000b60 Reset_Handler - .text.Default_Handler - 0x08000bb0 0x2 ./Core/Startup/startup_stm32f405rgtx.o - 0x08000bb0 DMA1_Stream3_IRQHandler - 0x08000bb0 HASH_RNG_IRQHandler - 0x08000bb0 EXTI2_IRQHandler - 0x08000bb0 TIM8_CC_IRQHandler - 0x08000bb0 TIM1_CC_IRQHandler - 0x08000bb0 DMA2_Stream5_IRQHandler - 0x08000bb0 DMA1_Stream5_IRQHandler - 0x08000bb0 PVD_IRQHandler - 0x08000bb0 SDIO_IRQHandler - 0x08000bb0 TAMP_STAMP_IRQHandler - 0x08000bb0 CAN2_RX1_IRQHandler - 0x08000bb0 EXTI3_IRQHandler - 0x08000bb0 TIM8_TRG_COM_TIM14_IRQHandler - 0x08000bb0 TIM1_UP_TIM10_IRQHandler - 0x08000bb0 TIM8_UP_TIM13_IRQHandler - 0x08000bb0 I2C3_ER_IRQHandler - 0x08000bb0 EXTI0_IRQHandler - 0x08000bb0 I2C2_EV_IRQHandler - 0x08000bb0 DMA1_Stream2_IRQHandler - 0x08000bb0 CAN1_RX0_IRQHandler - 0x08000bb0 FPU_IRQHandler - 0x08000bb0 OTG_HS_WKUP_IRQHandler - 0x08000bb0 CAN2_SCE_IRQHandler - 0x08000bb0 DMA2_Stream2_IRQHandler - 0x08000bb0 SPI1_IRQHandler - 0x08000bb0 TIM1_BRK_TIM9_IRQHandler - 0x08000bb0 CAN2_RX0_IRQHandler - 0x08000bb0 DMA2_Stream3_IRQHandler - 0x08000bb0 USART6_IRQHandler - 0x08000bb0 USART3_IRQHandler - 0x08000bb0 CAN1_RX1_IRQHandler - 0x08000bb0 UART5_IRQHandler - 0x08000bb0 DMA2_Stream0_IRQHandler - 0x08000bb0 TIM4_IRQHandler - 0x08000bb0 I2C1_EV_IRQHandler - 0x08000bb0 DMA1_Stream6_IRQHandler - 0x08000bb0 DMA1_Stream1_IRQHandler - 0x08000bb0 UART4_IRQHandler - 0x08000bb0 TIM3_IRQHandler - 0x08000bb0 RCC_IRQHandler - 0x08000bb0 TIM8_BRK_TIM12_IRQHandler - 0x08000bb0 Default_Handler - 0x08000bb0 EXTI15_10_IRQHandler - 0x08000bb0 ADC_IRQHandler - 0x08000bb0 DMA1_Stream7_IRQHandler - 0x08000bb0 TIM7_IRQHandler - 0x08000bb0 CAN2_TX_IRQHandler - 0x08000bb0 TIM5_IRQHandler - 0x08000bb0 DMA2_Stream7_IRQHandler - 0x08000bb0 I2C3_EV_IRQHandler - 0x08000bb0 EXTI9_5_IRQHandler - 0x08000bb0 RTC_WKUP_IRQHandler - 0x08000bb0 SPI2_IRQHandler - 0x08000bb0 OTG_HS_EP1_IN_IRQHandler - 0x08000bb0 DMA1_Stream0_IRQHandler - 0x08000bb0 CAN1_TX_IRQHandler - 0x08000bb0 EXTI4_IRQHandler - 0x08000bb0 FSMC_IRQHandler - 0x08000bb0 OTG_HS_EP1_OUT_IRQHandler - 0x08000bb0 WWDG_IRQHandler - 0x08000bb0 TIM2_IRQHandler - 0x08000bb0 OTG_FS_WKUP_IRQHandler - 0x08000bb0 TIM1_TRG_COM_TIM11_IRQHandler - 0x08000bb0 OTG_HS_IRQHandler - 0x08000bb0 EXTI1_IRQHandler - 0x08000bb0 USART2_IRQHandler - 0x08000bb0 I2C2_ER_IRQHandler - 0x08000bb0 DMA2_Stream1_IRQHandler - 0x08000bb0 CAN1_SCE_IRQHandler - 0x08000bb0 FLASH_IRQHandler - 0x08000bb0 DMA2_Stream4_IRQHandler - 0x08000bb0 USART1_IRQHandler - 0x08000bb0 OTG_FS_IRQHandler - 0x08000bb0 SPI3_IRQHandler - 0x08000bb0 DMA1_Stream4_IRQHandler - 0x08000bb0 I2C1_ER_IRQHandler - 0x08000bb0 DMA2_Stream6_IRQHandler - 0x08000bb0 RTC_Alarm_IRQHandler - .text.stm32_lock_acquire - 0x08000bb2 0x64 ./Core/ThreadSafe/newlib_lock_glue.o - .text.stm32_lock_release - 0x08000c16 0x58 ./Core/ThreadSafe/newlib_lock_glue.o - .text.__retarget_lock_acquire_recursive - 0x08000c6e 0x2a ./Core/ThreadSafe/newlib_lock_glue.o - 0x08000c6e __retarget_lock_acquire_recursive - .text.__retarget_lock_release_recursive - 0x08000c98 0x2a ./Core/ThreadSafe/newlib_lock_glue.o - 0x08000c98 __retarget_lock_release_recursive - *fill* 0x08000cc2 0x2 - .text.HAL_Init - 0x08000cc4 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o - 0x08000cc4 HAL_Init - .text.HAL_IncTick - 0x08000d08 0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o - 0x08000d08 HAL_IncTick - .text.HAL_GetTick - 0x08000d30 0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o - 0x08000d30 HAL_GetTick - .text.HAL_CAN_Init - 0x08000d48 0x4d4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o - 0x08000d48 HAL_CAN_Init - .text.HAL_CAN_TxMailbox0CompleteCallback - 0x0800121c 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o - 0x0800121c HAL_CAN_TxMailbox0CompleteCallback - .text.HAL_CAN_TxMailbox1CompleteCallback - 0x08001230 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o - 0x08001230 HAL_CAN_TxMailbox1CompleteCallback - .text.HAL_CAN_TxMailbox2CompleteCallback - 0x08001244 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o - 0x08001244 HAL_CAN_TxMailbox2CompleteCallback - .text.HAL_CAN_TxMailbox0AbortCallback - 0x08001258 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o - 0x08001258 HAL_CAN_TxMailbox0AbortCallback - .text.HAL_CAN_TxMailbox1AbortCallback - 0x0800126c 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o - 0x0800126c HAL_CAN_TxMailbox1AbortCallback - .text.HAL_CAN_TxMailbox2AbortCallback - 0x08001280 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o - 0x08001280 HAL_CAN_TxMailbox2AbortCallback + .text.CAN_Logger_Init + 0x080004fc 0xbc ./Core/Src/canlog.o + 0x080004fc CAN_Logger_Init .text.HAL_CAN_RxFifo0MsgPendingCallback - 0x08001294 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o - 0x08001294 HAL_CAN_RxFifo0MsgPendingCallback + 0x080005b8 0x88 ./Core/Src/canlog.o + 0x080005b8 HAL_CAN_RxFifo0MsgPendingCallback + .text.vCANLoggerListen + 0x08000640 0x68 ./Core/Src/canlog.o + 0x08000640 vCANLoggerListen + .text.vLEDHeartbeat + 0x080006a8 0x5c ./Core/Src/canlog.o + 0x080006a8 vLEDHeartbeat + .text.main 0x08000704 0x1dc ./Core/Src/main.o + 0x08000704 main + .text.SystemClock_Config + 0x080008e0 0xd4 ./Core/Src/main.o + 0x080008e0 SystemClock_Config + .text.MX_CAN1_Init + 0x080009b4 0x70 ./Core/Src/main.o + .text.MX_CAN2_Init + 0x08000a24 0x70 ./Core/Src/main.o + .text.MX_SDIO_SD_Init + 0x08000a94 0x60 ./Core/Src/main.o + .text.MX_DMA_Init + 0x08000af4 0x50 ./Core/Src/main.o + .text.MX_GPIO_Init + 0x08000b44 0x14c ./Core/Src/main.o + .text.HAL_TIM_PeriodElapsedCallback + 0x08000c90 0x24 ./Core/Src/main.o + 0x08000c90 HAL_TIM_PeriodElapsedCallback + .text.Error_Handler + 0x08000cb4 0x80 ./Core/Src/main.o + 0x08000cb4 Error_Handler + .text.assert_failed + 0x08000d34 0x16 ./Core/Src/main.o + 0x08000d34 assert_failed + *fill* 0x08000d4a 0x2 + .text.HAL_MspInit + 0x08000d4c 0x58 ./Core/Src/stm32f4xx_hal_msp.o + 0x08000d4c HAL_MspInit + .text.HAL_CAN_MspInit + 0x08000da4 0x140 ./Core/Src/stm32f4xx_hal_msp.o + 0x08000da4 HAL_CAN_MspInit + .text.HAL_SD_MspInit + 0x08000ee4 0x1e0 ./Core/Src/stm32f4xx_hal_msp.o + 0x08000ee4 HAL_SD_MspInit + .text.HAL_InitTick + 0x080010c4 0xf8 ./Core/Src/stm32f4xx_hal_timebase_tim.o + 0x080010c4 HAL_InitTick + .text.NMI_Handler + 0x080011bc 0x8 ./Core/Src/stm32f4xx_it.o + 0x080011bc NMI_Handler + .text.HardFault_Handler + 0x080011c4 0x8 ./Core/Src/stm32f4xx_it.o + 0x080011c4 HardFault_Handler + .text.MemManage_Handler + 0x080011cc 0x8 ./Core/Src/stm32f4xx_it.o + 0x080011cc MemManage_Handler + .text.BusFault_Handler + 0x080011d4 0x8 ./Core/Src/stm32f4xx_it.o + 0x080011d4 BusFault_Handler + .text.UsageFault_Handler + 0x080011dc 0x8 ./Core/Src/stm32f4xx_it.o + 0x080011dc UsageFault_Handler + .text.DebugMon_Handler + 0x080011e4 0xe ./Core/Src/stm32f4xx_it.o + 0x080011e4 DebugMon_Handler + *fill* 0x080011f2 0x2 + .text.SDIO_IRQHandler + 0x080011f4 0x14 ./Core/Src/stm32f4xx_it.o + 0x080011f4 SDIO_IRQHandler + .text.TIM6_DAC_IRQHandler + 0x08001208 0x14 ./Core/Src/stm32f4xx_it.o + 0x08001208 TIM6_DAC_IRQHandler + .text.DMA2_Stream3_IRQHandler + 0x0800121c 0x14 ./Core/Src/stm32f4xx_it.o + 0x0800121c DMA2_Stream3_IRQHandler + .text.DMA2_Stream6_IRQHandler + 0x08001230 0x14 ./Core/Src/stm32f4xx_it.o + 0x08001230 DMA2_Stream6_IRQHandler + .text.SystemInit + 0x08001244 0x24 ./Core/Src/system_stm32f4xx.o + 0x08001244 SystemInit + .text.Reset_Handler + 0x08001268 0x50 ./Core/Startup/startup_stm32f405rgtx.o + 0x08001268 Reset_Handler + .text.Default_Handler + 0x080012b8 0x2 ./Core/Startup/startup_stm32f405rgtx.o + 0x080012b8 DMA1_Stream3_IRQHandler + 0x080012b8 HASH_RNG_IRQHandler + 0x080012b8 EXTI2_IRQHandler + 0x080012b8 TIM8_CC_IRQHandler + 0x080012b8 TIM1_CC_IRQHandler + 0x080012b8 DMA2_Stream5_IRQHandler + 0x080012b8 DMA1_Stream5_IRQHandler + 0x080012b8 PVD_IRQHandler + 0x080012b8 TAMP_STAMP_IRQHandler + 0x080012b8 CAN2_RX1_IRQHandler + 0x080012b8 EXTI3_IRQHandler + 0x080012b8 TIM8_TRG_COM_TIM14_IRQHandler + 0x080012b8 TIM1_UP_TIM10_IRQHandler + 0x080012b8 TIM8_UP_TIM13_IRQHandler + 0x080012b8 I2C3_ER_IRQHandler + 0x080012b8 EXTI0_IRQHandler + 0x080012b8 I2C2_EV_IRQHandler + 0x080012b8 DMA1_Stream2_IRQHandler + 0x080012b8 CAN1_RX0_IRQHandler + 0x080012b8 FPU_IRQHandler + 0x080012b8 OTG_HS_WKUP_IRQHandler + 0x080012b8 CAN2_SCE_IRQHandler + 0x080012b8 DMA2_Stream2_IRQHandler + 0x080012b8 SPI1_IRQHandler + 0x080012b8 TIM1_BRK_TIM9_IRQHandler + 0x080012b8 CAN2_RX0_IRQHandler + 0x080012b8 USART6_IRQHandler + 0x080012b8 USART3_IRQHandler + 0x080012b8 CAN1_RX1_IRQHandler + 0x080012b8 UART5_IRQHandler + 0x080012b8 DMA2_Stream0_IRQHandler + 0x080012b8 TIM4_IRQHandler + 0x080012b8 I2C1_EV_IRQHandler + 0x080012b8 DMA1_Stream6_IRQHandler + 0x080012b8 DMA1_Stream1_IRQHandler + 0x080012b8 UART4_IRQHandler + 0x080012b8 TIM3_IRQHandler + 0x080012b8 RCC_IRQHandler + 0x080012b8 TIM8_BRK_TIM12_IRQHandler + 0x080012b8 Default_Handler + 0x080012b8 EXTI15_10_IRQHandler + 0x080012b8 ADC_IRQHandler + 0x080012b8 DMA1_Stream7_IRQHandler + 0x080012b8 TIM7_IRQHandler + 0x080012b8 CAN2_TX_IRQHandler + 0x080012b8 TIM5_IRQHandler + 0x080012b8 DMA2_Stream7_IRQHandler + 0x080012b8 I2C3_EV_IRQHandler + 0x080012b8 EXTI9_5_IRQHandler + 0x080012b8 RTC_WKUP_IRQHandler + 0x080012b8 SPI2_IRQHandler + 0x080012b8 OTG_HS_EP1_IN_IRQHandler + 0x080012b8 DMA1_Stream0_IRQHandler + 0x080012b8 CAN1_TX_IRQHandler + 0x080012b8 EXTI4_IRQHandler + 0x080012b8 FSMC_IRQHandler + 0x080012b8 OTG_HS_EP1_OUT_IRQHandler + 0x080012b8 WWDG_IRQHandler + 0x080012b8 TIM2_IRQHandler + 0x080012b8 OTG_FS_WKUP_IRQHandler + 0x080012b8 TIM1_TRG_COM_TIM11_IRQHandler + 0x080012b8 OTG_HS_IRQHandler + 0x080012b8 EXTI1_IRQHandler + 0x080012b8 USART2_IRQHandler + 0x080012b8 I2C2_ER_IRQHandler + 0x080012b8 DMA2_Stream1_IRQHandler + 0x080012b8 CAN1_SCE_IRQHandler + 0x080012b8 FLASH_IRQHandler + 0x080012b8 DMA2_Stream4_IRQHandler + 0x080012b8 USART1_IRQHandler + 0x080012b8 OTG_FS_IRQHandler + 0x080012b8 SPI3_IRQHandler + 0x080012b8 DMA1_Stream4_IRQHandler + 0x080012b8 I2C1_ER_IRQHandler + 0x080012b8 RTC_Alarm_IRQHandler + .text.stm32_lock_acquire + 0x080012ba 0x64 ./Core/ThreadSafe/newlib_lock_glue.o + .text.stm32_lock_release + 0x0800131e 0x58 ./Core/ThreadSafe/newlib_lock_glue.o + .text.__retarget_lock_acquire_recursive + 0x08001376 0x2a ./Core/ThreadSafe/newlib_lock_glue.o + 0x08001376 __retarget_lock_acquire_recursive + .text.__retarget_lock_release_recursive + 0x080013a0 0x2a ./Core/ThreadSafe/newlib_lock_glue.o + 0x080013a0 __retarget_lock_release_recursive + *fill* 0x080013ca 0x2 + .text.HAL_Init + 0x080013cc 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x080013cc HAL_Init + .text.HAL_IncTick + 0x08001410 0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x08001410 HAL_IncTick + .text.HAL_GetTick + 0x08001438 0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x08001438 HAL_GetTick + .text.HAL_Delay + 0x08001450 0x48 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x08001450 HAL_Delay + .text.HAL_CAN_Init + 0x08001498 0x4d4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o + 0x08001498 HAL_CAN_Init + .text.HAL_CAN_ConfigFilter + 0x0800196c 0x298 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o + 0x0800196c HAL_CAN_ConfigFilter + .text.HAL_CAN_Start + 0x08001c04 0x88 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o + 0x08001c04 HAL_CAN_Start + .text.HAL_CAN_GetRxMessage + 0x08001c8c 0x25c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o + 0x08001c8c HAL_CAN_GetRxMessage + .text.HAL_CAN_ActivateNotification + 0x08001ee8 0x64 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o + 0x08001ee8 HAL_CAN_ActivateNotification + .text.HAL_CAN_TxMailbox0CompleteCallback + 0x08001f4c 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o + 0x08001f4c HAL_CAN_TxMailbox0CompleteCallback + .text.HAL_CAN_TxMailbox1CompleteCallback + 0x08001f60 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o + 0x08001f60 HAL_CAN_TxMailbox1CompleteCallback + .text.HAL_CAN_TxMailbox2CompleteCallback + 0x08001f74 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o + 0x08001f74 HAL_CAN_TxMailbox2CompleteCallback + .text.HAL_CAN_TxMailbox0AbortCallback + 0x08001f88 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o + 0x08001f88 HAL_CAN_TxMailbox0AbortCallback + .text.HAL_CAN_TxMailbox1AbortCallback + 0x08001f9c 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o + 0x08001f9c HAL_CAN_TxMailbox1AbortCallback + .text.HAL_CAN_TxMailbox2AbortCallback + 0x08001fb0 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o + 0x08001fb0 HAL_CAN_TxMailbox2AbortCallback .text.HAL_CAN_RxFifo0FullCallback - 0x080012a8 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o - 0x080012a8 HAL_CAN_RxFifo0FullCallback + 0x08001fc4 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o + 0x08001fc4 HAL_CAN_RxFifo0FullCallback .text.HAL_CAN_RxFifo1MsgPendingCallback - 0x080012bc 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o - 0x080012bc HAL_CAN_RxFifo1MsgPendingCallback + 0x08001fd8 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o + 0x08001fd8 HAL_CAN_RxFifo1MsgPendingCallback .text.HAL_CAN_RxFifo1FullCallback - 0x080012d0 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o - 0x080012d0 HAL_CAN_RxFifo1FullCallback + 0x08001fec 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o + 0x08001fec HAL_CAN_RxFifo1FullCallback .text.HAL_CAN_SleepCallback - 0x080012e4 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o - 0x080012e4 HAL_CAN_SleepCallback + 0x08002000 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o + 0x08002000 HAL_CAN_SleepCallback .text.HAL_CAN_WakeUpFromRxMsgCallback - 0x080012f8 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o - 0x080012f8 HAL_CAN_WakeUpFromRxMsgCallback + 0x08002014 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o + 0x08002014 HAL_CAN_WakeUpFromRxMsgCallback .text.HAL_CAN_ErrorCallback - 0x0800130c 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o - 0x0800130c HAL_CAN_ErrorCallback + 0x08002028 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o + 0x08002028 HAL_CAN_ErrorCallback + .text.HAL_CAN_GetState + 0x0800203c 0x50 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./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o - *fill* 0x0800147a 0x2 + 0x08002198 0x66 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + *fill* 0x080021fe 0x2 .text.HAL_NVIC_SetPriorityGrouping - 0x0800147c 0x40 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o - 0x0800147c HAL_NVIC_SetPriorityGrouping + 0x08002200 0x40 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + 0x08002200 HAL_NVIC_SetPriorityGrouping .text.HAL_NVIC_SetPriority - 0x080014bc 0x58 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o - 0x080014bc HAL_NVIC_SetPriority + 0x08002240 0x58 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + 0x08002240 HAL_NVIC_SetPriority .text.HAL_NVIC_EnableIRQ - 0x08001514 0x30 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o - 0x08001514 HAL_NVIC_EnableIRQ + 0x08002298 0x30 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + 0x08002298 HAL_NVIC_EnableIRQ + .text.HAL_DMA_Init + 0x080022c8 0x434 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + 0x080022c8 HAL_DMA_Init + .text.HAL_DMA_Abort_IT + 0x080026fc 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + 0x080026fc HAL_DMA_Abort_IT + .text.HAL_DMA_IRQHandler + 0x08002740 0x314 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + 0x08002740 HAL_DMA_IRQHandler + .text.DMA_CalcBaseAndBitshift + 0x08002a54 0x6c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .text.DMA_CheckFifoParam + 0x08002ac0 0xf8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .text.HAL_GPIO_Init - 0x08001544 0x5a8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o - 0x08001544 HAL_GPIO_Init + 0x08002bb8 0x5a8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + 0x08002bb8 HAL_GPIO_Init + .text.HAL_GPIO_WritePin + 0x08003160 0x58 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + 0x08003160 HAL_GPIO_WritePin + .text.HAL_GPIO_TogglePin + 0x080031b8 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + 0x080031b8 HAL_GPIO_TogglePin .text.HAL_RCC_OscConfig - 0x08001aec 0x658 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o - 0x08001aec HAL_RCC_OscConfig + 0x080031fc 0x658 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + 0x080031fc HAL_RCC_OscConfig .text.HAL_RCC_ClockConfig - 0x08002144 0x31c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o - 0x08002144 HAL_RCC_ClockConfig + 0x08003854 0x31c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + 0x08003854 HAL_RCC_ClockConfig .text.HAL_RCC_GetSysClockFreq - 0x08002460 0x188 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o - 0x08002460 HAL_RCC_GetSysClockFreq + 0x08003b70 0x188 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + 0x08003b70 HAL_RCC_GetSysClockFreq .text.HAL_RCC_GetHCLKFreq - 0x080025e8 0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o - 0x080025e8 HAL_RCC_GetHCLKFreq + 0x08003cf8 0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + 0x08003cf8 HAL_RCC_GetHCLKFreq .text.HAL_RCC_GetPCLK1Freq - 0x08002600 0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o - 0x08002600 HAL_RCC_GetPCLK1Freq + 0x08003d10 0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + 0x08003d10 HAL_RCC_GetPCLK1Freq .text.HAL_RCC_GetClockConfig - 0x08002628 0x64 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o - 0x08002628 HAL_RCC_GetClockConfig + 0x08003d38 0x64 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + 0x08003d38 HAL_RCC_GetClockConfig + .text.HAL_SD_Init + 0x08003d9c 0x124 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + 0x08003d9c HAL_SD_Init + .text.HAL_SD_InitCard + 0x08003ec0 0xf0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + 0x08003ec0 HAL_SD_InitCard + .text.HAL_SD_IRQHandler + 0x08003fb0 0x30c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + 0x08003fb0 HAL_SD_IRQHandler + .text.HAL_SD_TxCpltCallback + 0x080042bc 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + 0x080042bc HAL_SD_TxCpltCallback + .text.HAL_SD_RxCpltCallback + 0x080042d0 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + 0x080042d0 HAL_SD_RxCpltCallback + .text.HAL_SD_ErrorCallback + 0x080042e4 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + 0x080042e4 HAL_SD_ErrorCallback + .text.HAL_SD_AbortCallback + 0x080042f8 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + 0x080042f8 HAL_SD_AbortCallback + .text.HAL_SD_GetCardCSD + 0x0800430c 0x348 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + 0x0800430c HAL_SD_GetCardCSD + .text.HAL_SD_ConfigWideBusOperation + 0x08004654 0x158 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + 0x08004654 HAL_SD_ConfigWideBusOperation + .text.HAL_SD_GetCardState + 0x080047ac 0x40 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + 0x080047ac HAL_SD_GetCardState + .text.SD_DMATxAbort + 0x080047ec 0x6e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.SD_DMARxAbort + 0x0800485a 0x6e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.SD_InitCard + 0x080048c8 0x19c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.SD_PowerON + 0x08004a64 0x11c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.SD_SendStatus + 0x08004b80 0x50 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.SD_WideBus_Enable + 0x08004bd0 0x96 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.SD_WideBus_Disable + 0x08004c66 0x96 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.SD_FindSCR + 0x08004cfc 0x1b4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.SD_Read_IT + 0x08004eb0 0xa2 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .text.SD_Write_IT + 0x08004f52 0xaa ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o .text.HAL_TIM_Base_Init - 0x0800268c 0x238 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o - 0x0800268c HAL_TIM_Base_Init + 0x08004ffc 0x238 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + 0x08004ffc HAL_TIM_Base_Init .text.HAL_TIM_Base_MspInit - 0x080028c4 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o - 0x080028c4 HAL_TIM_Base_MspInit + 0x08005234 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + 0x08005234 HAL_TIM_Base_MspInit .text.HAL_TIM_Base_Start_IT - 0x080028d8 0x18c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o - 0x080028d8 HAL_TIM_Base_Start_IT + 0x08005248 0x18c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + 0x08005248 HAL_TIM_Base_Start_IT .text.HAL_TIM_IRQHandler - 0x08002a64 0x1e0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o - 0x08002a64 HAL_TIM_IRQHandler + 0x080053d4 0x1e0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + 0x080053d4 HAL_TIM_IRQHandler .text.HAL_TIM_OC_DelayElapsedCallback - 0x08002c44 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o - 0x08002c44 HAL_TIM_OC_DelayElapsedCallback + 0x080055b4 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + 0x080055b4 HAL_TIM_OC_DelayElapsedCallback .text.HAL_TIM_IC_CaptureCallback - 0x08002c58 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o - 0x08002c58 HAL_TIM_IC_CaptureCallback + 0x080055c8 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + 0x080055c8 HAL_TIM_IC_CaptureCallback .text.HAL_TIM_PWM_PulseFinishedCallback - 0x08002c6c 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o - 0x08002c6c HAL_TIM_PWM_PulseFinishedCallback + 0x080055dc 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + 0x080055dc HAL_TIM_PWM_PulseFinishedCallback .text.HAL_TIM_TriggerCallback - 0x08002c80 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o - 0x08002c80 HAL_TIM_TriggerCallback + 0x080055f0 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + 0x080055f0 HAL_TIM_TriggerCallback .text.TIM_Base_SetConfig - 0x08002c94 0x14c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o - 0x08002c94 TIM_Base_SetConfig + 0x08005604 0x14c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + 0x08005604 TIM_Base_SetConfig .text.HAL_TIMEx_CommutCallback - 0x08002de0 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o - 0x08002de0 HAL_TIMEx_CommutCallback + 0x08005750 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + 0x08005750 HAL_TIMEx_CommutCallback .text.HAL_TIMEx_BreakCallback - 0x08002df4 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o - 0x08002df4 HAL_TIMEx_BreakCallback + 0x08005764 0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + 0x08005764 HAL_TIMEx_BreakCallback + .text.SDIO_Init + 0x08005778 0xf4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + 0x08005778 SDIO_Init + .text.SDIO_ReadFIFO + 0x0800586c 0x1a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + 0x0800586c SDIO_ReadFIFO + .text.SDIO_WriteFIFO + 0x08005886 0x22 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0x8 ./Core/Src/system_stm32f4xx.o - 0x08005d54 APBPrescTable - 0x08005d5c . = ALIGN (0x4) + 0x0800a2b0 0x8 ./Core/Src/system_stm32f4xx.o + 0x0800a2b0 APBPrescTable + .rodata.flagBitshiftOffset.0 + 0x0800a2b8 0x8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + 0x0800a2c0 . = ALIGN (0x4) -.ARM.extab 0x08005d5c 0x0 - 0x08005d5c . = ALIGN (0x4) +.ARM.extab 0x0800a2c0 0x0 + 0x0800a2c0 . = ALIGN (0x4) *(.ARM.extab* .gnu.linkonce.armextab.*) - 0x08005d5c . = ALIGN (0x4) + 0x0800a2c0 . = ALIGN (0x4) -.ARM 0x08005d5c 0x8 - 0x08005d5c . = ALIGN (0x4) - 0x08005d5c __exidx_start = . +.ARM 0x0800a2c0 0x8 + 0x0800a2c0 . = ALIGN (0x4) + 0x0800a2c0 __exidx_start = . *(.ARM.exidx*) - .ARM.exidx 0x08005d5c 0x8 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/libgcc.a(_udivmoddi4.o) - 0x08005d64 __exidx_end = . - 0x08005d64 . = ALIGN (0x4) + .ARM.exidx 0x0800a2c0 0x8 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/libgcc.a(_udivmoddi4.o) + 0x0800a2c8 __exidx_end = . + 0x0800a2c8 . = ALIGN (0x4) -.preinit_array 0x08005d64 0x0 - 0x08005d64 . = ALIGN (0x4) - 0x08005d64 PROVIDE (__preinit_array_start = .) +.preinit_array 0x0800a2c8 0x0 + 0x0800a2c8 . = ALIGN (0x4) + 0x0800a2c8 PROVIDE (__preinit_array_start = .) *(.preinit_array*) - 0x08005d64 PROVIDE (__preinit_array_end = .) - 0x08005d64 . = ALIGN (0x4) + 0x0800a2c8 PROVIDE (__preinit_array_end = .) + 0x0800a2c8 . = ALIGN (0x4) -.init_array 0x08005d64 0x4 - 0x08005d64 . = ALIGN (0x4) - 0x08005d64 PROVIDE (__init_array_start = .) +.init_array 0x0800a2c8 0x4 + 0x0800a2c8 . = ALIGN (0x4) + 0x0800a2c8 PROVIDE (__init_array_start = .) *(SORT_BY_NAME(.init_array.*)) *(.init_array*) - .init_array 0x08005d64 0x4 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/crtbegin.o - 0x08005d68 PROVIDE (__init_array_end = .) - 0x08005d68 . = ALIGN (0x4) + .init_array 0x0800a2c8 0x4 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/crtbegin.o + 0x0800a2cc PROVIDE (__init_array_end = .) + 0x0800a2cc . = ALIGN (0x4) -.fini_array 0x08005d68 0x4 - 0x08005d68 . = ALIGN (0x4) +.fini_array 0x0800a2cc 0x4 + 0x0800a2cc . = ALIGN (0x4) [!provide] PROVIDE (__fini_array_start = .) *(SORT_BY_NAME(.fini_array.*)) *(.fini_array*) - .fini_array 0x08005d68 0x4 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/crtbegin.o + .fini_array 0x0800a2cc 0x4 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/crtbegin.o [!provide] PROVIDE (__fini_array_end = .) - 0x08005d6c . = ALIGN (0x4) - 0x08005d6c _sidata = LOADADDR (.data) + 0x0800a2d0 . = ALIGN (0x4) + 0x0800a2d0 _sidata = LOADADDR (.data) -.rel.dyn 0x08005d6c 0x0 - .rel.iplt 0x08005d6c 0x0 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/crtbegin.o +.rel.dyn 0x0800a2d0 0x0 + .rel.iplt 0x0800a2d0 0x0 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/crtbegin.o -.data 0x20000000 0x60 load address 0x08005d6c +.data 0x20000000 0x78 load address 0x0800a2d0 0x20000000 . = ALIGN (0x4) 0x20000000 _sdata = . *(.data) *(.data*) + .data.led_can1 + 0x20000000 0x8 ./Core/Src/main.o + 0x20000000 led_can1 + .data.led_can2 + 0x20000008 0x8 ./Core/Src/main.o + 0x20000008 led_can2 + .data.led_error + 0x20000010 0x8 ./Core/Src/main.o + 0x20000010 led_error .data.SystemCoreClock - 0x20000000 0x4 ./Core/Src/system_stm32f4xx.o - 0x20000000 SystemCoreClock + 0x20000018 0x4 ./Core/Src/system_stm32f4xx.o + 0x20000018 SystemCoreClock .data.uwTickPrio - 0x20000004 0x4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o - 0x20000004 uwTickPrio + 0x2000001c 0x4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x2000001c uwTickPrio .data.uwTickFreq - 0x20000008 0x1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o - 0x20000008 uwTickFreq - *fill* 0x20000009 0x3 + 0x20000020 0x1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x20000020 uwTickFreq + *fill* 0x20000021 0x3 .data.uxCriticalNesting - 0x2000000c 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o + 0x20000024 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o .data._impure_ptr - 0x20000010 0x4 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-impure.o) - 0x20000010 _impure_ptr + 0x20000028 0x4 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-impure.o) + 0x20000028 _impure_ptr .data._impure_data - 0x20000014 0x4c /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-impure.o) - 0x20000014 _impure_data + 0x2000002c 0x4c /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-impure.o) + 0x2000002c _impure_data *(.RamFunc) *(.RamFunc*) - 0x20000060 . = ALIGN (0x4) - 0x20000060 _edata = . - 0x08005dcc _siccmram = LOADADDR (.ccmram) + 0x20000078 . = ALIGN (0x4) + 0x20000078 _edata = . + 0x0800a348 _siccmram = LOADADDR (.ccmram) -.igot.plt 0x20000060 0x0 load address 0x08005dcc - .igot.plt 0x20000060 0x0 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/crtbegin.o +.igot.plt 0x20000078 0x0 load address 0x0800a348 + .igot.plt 0x20000078 0x0 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/crtbegin.o -.ccmram 0x10000000 0x0 load address 0x08005dcc +.ccmram 0x10000000 0x0 load address 0x0800a348 0x10000000 . = ALIGN (0x4) 0x10000000 _sccmram = . *(.ccmram) @@ -5199,140 +6022,169 @@ LOAD /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/ 0x10000000 _eccmram = . 0x10000000 . = ALIGN (0x4) -.bss 0x20000060 0x4c68 - 0x20000060 _sbss = . - 0x20000060 __bss_start__ = _sbss +.bss 0x20000078 0x4dd8 + 0x20000078 _sbss = . + 0x20000078 __bss_start__ = _sbss *(.bss) - .bss 0x20000060 0x1c /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/crtbegin.o + .bss 0x20000078 0x1c /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/crtbegin.o *(.bss*) - .bss.hcan1 0x2000007c 0x64 ./Core/Src/main.o - 0x2000007c hcan1 - .bss.hcan2 0x200000e0 0x64 ./Core/Src/main.o - 0x200000e0 hcan2 - .bss.defaultTaskHandle - 0x20000144 0x4 ./Core/Src/main.o - 0x20000144 defaultTaskHandle + .bss.hcan1 0x20000094 0x64 ./Core/Src/main.o + 0x20000094 hcan1 + .bss.hcan2 0x200000f8 0x64 ./Core/Src/main.o + 0x200000f8 hcan2 + .bss.hsd 0x2000015c 0x84 ./Core/Src/main.o + 0x2000015c hsd + .bss.hdma_sdio_rx + 0x200001e0 0x60 ./Core/Src/main.o + 0x200001e0 hdma_sdio_rx + .bss.hdma_sdio_tx + 0x20000240 0x60 ./Core/Src/main.o + 0x20000240 hdma_sdio_tx + .bss.ledContextCAN1 + 0x200002a0 0xc ./Core/Src/main.o + 0x200002a0 ledContextCAN1 + .bss.ledContextCAN2 + 0x200002ac 0xc ./Core/Src/main.o + 0x200002ac ledContextCAN2 + .bss.xSemaphoreCAN1 + 0x200002b8 0x4 ./Core/Src/main.o + 0x200002b8 xSemaphoreCAN1 + .bss.xSemaphoreCAN2 + 0x200002bc 0x4 ./Core/Src/main.o + 0x200002bc xSemaphoreCAN2 + .bss.xHeartbeatTimerCAN1 + 0x200002c0 0x4 ./Core/Src/main.o + 0x200002c0 xHeartbeatTimerCAN1 + .bss.xHeartbeatTimerCAN2 + 0x200002c4 0x4 ./Core/Src/main.o + 0x200002c4 xHeartbeatTimerCAN2 + .bss.xCAN1RxQueue + 0x200002c8 0x4 ./Core/Src/main.o + 0x200002c8 xCAN1RxQueue + .bss.xCAN2RxQueue + 0x200002cc 0x4 ./Core/Src/main.o + 0x200002cc xCAN2RxQueue .bss.HAL_RCC_CAN1_CLK_ENABLED - 0x20000148 0x4 ./Core/Src/stm32f4xx_hal_msp.o - .bss.htim6 0x2000014c 0x48 ./Core/Src/stm32f4xx_hal_timebase_tim.o - 0x2000014c htim6 + 0x200002d0 0x4 ./Core/Src/stm32f4xx_hal_msp.o + .bss.htim6 0x200002d4 0x48 ./Core/Src/stm32f4xx_hal_timebase_tim.o + 0x200002d4 htim6 .bss.__lock___malloc_recursive_mutex - 0x20000194 0xc ./Core/ThreadSafe/newlib_lock_glue.o - 0x20000194 __lock___malloc_recursive_mutex - .bss.uwTick 0x200001a0 0x4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o - 0x200001a0 uwTick + 0x2000031c 0xc ./Core/ThreadSafe/newlib_lock_glue.o + 0x2000031c __lock___malloc_recursive_mutex + .bss.uwTick 0x20000328 0x4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x20000328 uwTick .bss.KernelState - 0x200001a4 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + 0x2000032c 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .bss.Idle_TCB.3 - 0x200001a8 0xa8 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + 0x20000330 0xa8 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .bss.Idle_Stack.2 - 0x20000250 0x200 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + 0x200003d8 0x200 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .bss.Timer_TCB.1 - 0x20000450 0xa8 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + 0x200005d8 0xa8 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .bss.Timer_Stack.0 - 0x200004f8 0x400 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + 0x20000680 0x400 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .bss.xQueueRegistry - 0x200008f8 0x40 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o - 0x200008f8 xQueueRegistry + 0x20000a80 0x40 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + 0x20000a80 xQueueRegistry .bss.pxCurrentTCB - 0x20000938 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o - 0x20000938 pxCurrentTCB + 0x20000ac0 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x20000ac0 pxCurrentTCB .bss.pxReadyTasksLists - 0x2000093c 0x460 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x20000ac4 0x460 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o .bss.xDelayedTaskList1 - 0x20000d9c 0x14 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x20000f24 0x14 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o .bss.xDelayedTaskList2 - 0x20000db0 0x14 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x20000f38 0x14 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o .bss.pxDelayedTaskList - 0x20000dc4 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x20000f4c 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o .bss.pxOverflowDelayedTaskList - 0x20000dc8 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x20000f50 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o .bss.xPendingReadyList - 0x20000dcc 0x14 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x20000f54 0x14 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o .bss.xTasksWaitingTermination - 0x20000de0 0x14 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./Core/Startup/startup_stm32f405rgtx.o - .debug_str 0x000cc536 0xd64f ./Core/ThreadSafe/newlib_lock_glue.o - .debug_str 0x000cc536 0xba38e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o - .debug_str 0x000cc536 0xba293 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o - .debug_str 0x000cc536 0xba10c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o - .debug_str 0x000cc536 0xb9994 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o - .debug_str 0x000cc536 0xb9c4d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o - .debug_str 0x000cc536 0xbabb5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o - .debug_str 0x000cc536 0xba3c1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o - .debug_str 0x000cc536 0xc476f ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o - .debug_str 0x000cc536 0xac2c ./Middlewares/Third_Party/FreeRTOS/Source/list.o - .debug_str 0x000cc536 0xc76c ./Middlewares/Third_Party/FreeRTOS/Source/queue.o - .debug_str 0x000cc536 0xd571 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o - .debug_str 0x000cc536 0xcfbd ./Middlewares/Third_Party/FreeRTOS/Source/timers.o - .debug_str 0x000cc536 0xb96a ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o - .debug_str 0x000cc536 0xb56e ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o +.debug_str 0x00000000 0xd1f03 + .debug_str 0x00000000 0xd1f03 ./Core/Src/canlog.o + 0xc612b (size before relaxing) + .debug_str 0x000d1f03 0xc7460 ./Core/Src/main.o + .debug_str 0x000d1f03 0xc6856 ./Core/Src/stm32f4xx_hal_msp.o + .debug_str 0x000d1f03 0xbeac3 ./Core/Src/stm32f4xx_hal_timebase_tim.o + .debug_str 0x000d1f03 0xc613f ./Core/Src/stm32f4xx_it.o + .debug_str 0x000d1f03 0xbdfed ./Core/Src/system_stm32f4xx.o + .debug_str 0x000d1f03 0x71 ./Core/Startup/startup_stm32f405rgtx.o + .debug_str 0x000d1f03 0xd5ea ./Core/ThreadSafe/newlib_lock_glue.o + .debug_str 0x000d1f03 0xbeb70 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_str 0x000d1f03 0xbea75 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o + .debug_str 0x000d1f03 0xbe8ee ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_str 0x000d1f03 0xbe415 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_str 0x000d1f03 0xbe176 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_str 0x000d1f03 0xbe42f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_str 0x000d1f03 0xbed74 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_str 0x000d1f03 0xbf397 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_str 0x000d1f03 0xbeba3 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_str 0x000d1f03 0xbe482 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_str 0x000d1f03 0xc8f51 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_str 0x000d1f03 0xabc7 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_str 0x000d1f03 0xc707 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_str 0x000d1f03 0xd50c ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_str 0x000d1f03 0xcf58 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_str 0x000d1f03 0xb905 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o + .debug_str 0x000d1f03 0xb509 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o .comment 0x00000000 0x43 - .comment 0x00000000 0x43 ./Core/Src/main.o + .comment 0x00000000 0x43 ./Core/Src/canlog.o 0x44 (size before relaxing) + .comment 0x00000043 0x44 ./Core/Src/main.o .comment 0x00000043 0x44 ./Core/Src/stm32f4xx_hal_msp.o .comment 0x00000043 0x44 ./Core/Src/stm32f4xx_hal_timebase_tim.o .comment 0x00000043 0x44 ./Core/Src/stm32f4xx_it.o @@ -5656,10 +6615,13 @@ LOAD /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/ .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o .comment 0x00000043 0x44 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .comment 0x00000043 0x44 ./Middlewares/Third_Party/FreeRTOS/Source/list.o .comment 0x00000043 0x44 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o @@ -5668,39 +6630,43 @@ LOAD /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/ .comment 0x00000043 0x44 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o .comment 0x00000043 0x44 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o -.debug_frame 0x00000000 0x519c - .debug_frame 0x00000000 0x12c ./Core/Src/main.o - .debug_frame 0x0000012c 0x7c ./Core/Src/stm32f4xx_hal_msp.o - .debug_frame 0x000001a8 0x6c ./Core/Src/stm32f4xx_hal_timebase_tim.o - .debug_frame 0x00000214 0xc0 ./Core/Src/stm32f4xx_it.o - .debug_frame 0x000002d4 0x50 ./Core/Src/system_stm32f4xx.o - .debug_frame 0x00000324 0x268 ./Core/ThreadSafe/newlib_lock_glue.o - .debug_frame 0x0000058c 0x31c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o - .debug_frame 0x000008a8 0x57c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o - .debug_frame 0x00000e24 0x4bc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o - .debug_frame 0x000012e0 0x138 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o - .debug_frame 0x00001418 0x1dc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o - .debug_frame 0x000015f4 0x1144 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o - .debug_frame 0x00002738 0x604 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o - .debug_frame 0x00002d3c 0xb9c ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o - .debug_frame 0x000038d8 0xc4 ./Middlewares/Third_Party/FreeRTOS/Source/list.o - .debug_frame 0x0000399c 0x5c0 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o - .debug_frame 0x00003f5c 0x8b0 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o - .debug_frame 0x0000480c 0x3e4 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o - .debug_frame 0x00004bf0 0x18c ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o - .debug_frame 0x00004d7c 0x118 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o - .debug_frame 0x00004e94 0x50 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-mallocr.o) - .debug_frame 0x00004ee4 0x30 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-mlock.o) - .debug_frame 0x00004f14 0x144 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-findfp.o) - .debug_frame 0x00005058 0x20 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-memset.o) - .debug_frame 0x00005078 0x2c /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-init.o) - .debug_frame 0x000050a4 0x38 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-reent.o) - .debug_frame 0x000050dc 0x28 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-memcpy-stub.o) - .debug_frame 0x00005104 0x38 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-freer.o) - .debug_frame 0x0000513c 0x2c /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/libgcc.a(_aeabi_uldivmod.o) - .debug_frame 0x00005168 0x34 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/libgcc.a(_udivmoddi4.o) +.debug_frame 0x00000000 0x61e8 + .debug_frame 0x00000000 0x9c ./Core/Src/canlog.o + .debug_frame 0x0000009c 0x158 ./Core/Src/main.o + .debug_frame 0x000001f4 0xc4 ./Core/Src/stm32f4xx_hal_msp.o + .debug_frame 0x000002b8 0x6c ./Core/Src/stm32f4xx_hal_timebase_tim.o + .debug_frame 0x00000324 0x114 ./Core/Src/stm32f4xx_it.o + .debug_frame 0x00000438 0x50 ./Core/Src/system_stm32f4xx.o + .debug_frame 0x00000488 0x268 ./Core/ThreadSafe/newlib_lock_glue.o + .debug_frame 0x000006f0 0x31c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_frame 0x00000a0c 0x57c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o + .debug_frame 0x00000f88 0x4bc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_frame 0x00001444 0x234 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_frame 0x00001678 0x138 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_frame 0x000017b0 0x1dc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_frame 0x0000198c 0x620 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o + .debug_frame 0x00001fac 0x1144 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_frame 0x000030f0 0x604 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_frame 0x000036f4 0x694 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o + .debug_frame 0x00003d88 0xb9c ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_frame 0x00004924 0xc4 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_frame 0x000049e8 0x5c0 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_frame 0x00004fa8 0x8b0 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_frame 0x00005858 0x3e4 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_frame 0x00005c3c 0x18c ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o + .debug_frame 0x00005dc8 0x118 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_frame 0x00005ee0 0x50 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-mallocr.o) + .debug_frame 0x00005f30 0x30 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-mlock.o) + .debug_frame 0x00005f60 0x144 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-findfp.o) + .debug_frame 0x000060a4 0x20 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-memset.o) + .debug_frame 0x000060c4 0x2c /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-init.o) + .debug_frame 0x000060f0 0x38 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-reent.o) + .debug_frame 0x00006128 0x28 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-memcpy-stub.o) + .debug_frame 0x00006150 0x38 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-freer.o) + .debug_frame 0x00006188 0x2c /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/libgcc.a(_aeabi_uldivmod.o) + .debug_frame 0x000061b4 0x34 /Applications/STMicroelectronics/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+fp/hard/libgcc.a(_udivmoddi4.o) .debug_line_str - 0x00000000 0xba + 0x00000000 0x55 .debug_line_str - 0x00000000 0xba ./Core/Startup/startup_stm32f405rgtx.o + 0x00000000 0x55 ./Core/Startup/startup_stm32f405rgtx.o diff --git a/Debug/makefile b/Debug/makefile index 23986b9..d0db3d0 100644 --- a/Debug/makefile +++ b/Debug/makefile @@ -65,8 +65,8 @@ all: main-build main-build: can_logger.elf secondary-outputs # Tool invocations -can_logger.elf can_logger.map: $(OBJS) $(USER_OBJS) /Users/erickahmed/Library/Mobile\ Documents/com~apple~CloudDocs/Engineering/Ingegneria\ del\ Veicolo\ LT/3T\ -\ Prova\ Finale/Tesi/code/can_logger/STM32F405RGTX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS) - arm-none-eabi-gcc -o "can_logger.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m4 -T"/Users/erickahmed/Library/Mobile Documents/com~apple~CloudDocs/Engineering/Ingegneria del Veicolo LT/3T - Prova Finale/Tesi/code/can_logger/STM32F405RGTX_FLASH.ld" --specs=nosys.specs -Wl,-Map="can_logger.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -Wl,--end-group +can_logger.elf can_logger.map: $(OBJS) $(USER_OBJS) /Users/erickahmed/TESI/Tesi/can_logger/STM32F405RGTX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-gcc -o "can_logger.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m4 -T"/Users/erickahmed/TESI/Tesi/can_logger/STM32F405RGTX_FLASH.ld" --specs=nosys.specs -Wl,-Map="can_logger.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -Wl,--end-group @echo 'Finished building target: $@' @echo ' ' diff --git a/Debug/objects.list b/Debug/objects.list index 9f0b5c8..c2ac67e 100644 --- a/Debug/objects.list +++ b/Debug/objects.list @@ -1,3 +1,4 @@ +"./Core/Src/canlog.o" "./Core/Src/freertos.o" "./Core/Src/main.o" "./Core/Src/stm32f4xx_hal_msp.o" @@ -18,12 +19,15 @@ "./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o" "./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o" "./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.o" "./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o" "./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o" "./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o" "./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.o" "./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o" "./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.o" "./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o" "./Middlewares/Third_Party/FreeRTOS/Source/croutine.o" "./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o" diff --git a/Drivers/CMSIS/Include/cmsis_armclang 2.h b/Drivers/CMSIS/Include/cmsis_armclang 2.h new file mode 100644 index 0000000..6911417 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_armclang 2.h @@ -0,0 +1,1503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.4.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/Drivers/CMSIS/Include/cmsis_gcc 2.h b/Drivers/CMSIS/Include/cmsis_gcc 2.h new file mode 100644 index 0000000..67bda4e --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_gcc 2.h @@ -0,0 +1,2211 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/Drivers/CMSIS/Include/cmsis_iccarm 2.h b/Drivers/CMSIS/Include/cmsis_iccarm 2.h new file mode 100644 index 0000000..65b824b --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_iccarm 2.h @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/Drivers/CMSIS/Include/cmsis_version 2.h b/Drivers/CMSIS/Include/cmsis_version 2.h new file mode 100644 index 0000000..8b4765f --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_version 2.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.5 + * @date 02. February 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/Drivers/CMSIS/Include/core_cm0 2.h b/Drivers/CMSIS/Include/core_cm0 2.h new file mode 100644 index 0000000..6441ff3 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm0 2.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm1 2.h b/Drivers/CMSIS/Include/core_cm1 2.h new file mode 100644 index 0000000..76b4569 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm1 2.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm35p 2.h b/Drivers/CMSIS/Include/core_cm35p 2.h new file mode 100644 index 0000000..3843d95 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm35p 2.h @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.1.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_starmc1 2.h b/Drivers/CMSIS/Include/core_starmc1 2.h new file mode 100644 index 0000000..d86c8d3 --- /dev/null +++ b/Drivers/CMSIS/Include/core_starmc1 2.h @@ -0,0 +1,3592 @@ +/**************************************************************************//** + * @file core_starmc1.h + * @brief CMSIS ArmChina STAR-MC1 Core Peripheral Access Layer Header File + * @version V1.0.2 + * @date 07. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. + * Copyright (c) 2018-2022 Arm China. + * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_STAR_H_GENERIC +#define __CORE_STAR_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup STAR-MC1 + @{ + */ + +#include "cmsis_version.h" + +/* Macro Define for STAR-MC1 */ +#define __STAR_MC (1U) /*!< STAR-MC Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_STAR_H_DEPENDANT +#define __CORE_STAR_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __STAR_REV + #define __STAR_REV 0x0000U + #warning "__STAR_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group STAR-MC1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for STAR-MC1 processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED_ADD1[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: F00-D00=0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +typedef struct +{ + __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */ + __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */ +}EMSS_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +#define SCB_CLIDR_IC_Pos 0U /*!< SCB CLIDR: IC Position */ +#define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) /*!< SCB CLIDR: IC Mask */ + +#define SCB_CLIDR_DC_Pos 1U /*!< SCB CLIDR: DC Position */ +#define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) /*!< SCB CLIDR: DC Mask */ + + + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache line Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_LEVEL_Pos 1U /*!< SCB DCISW: Level Position */ +#define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) /*!< SCB DCISW: Level Mask */ + +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean line by Set-way Register Definitions */ +#define SCB_DCCSW_LEVEL_Pos 1U /*!< SCB DCCSW: Level Position */ +#define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) /*!< SCB DCCSW: Level Mask */ + +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_LEVEL_Pos 1U /*!< SCB DCCISW: Level Position */ +#define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) /*!< SCB DCCISW: Level Mask */ + +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* ArmChina: Implementation Defined */ +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_DCCLEAN_Pos 16U /*!< SCB CACR: DCCLEAN Position */ +#define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCCLEAN Mask */ + +#define SCB_CACR_ICACTIVE_Pos 13U /*!< SCB CACR: ICACTIVE Position */ +#define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: ICACTIVE Mask */ + +#define SCB_CACR_DCACTIVE_Pos 12U /*!< SCB CACR: DCACTIVE Position */ +#define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCACTIVE Mask */ + +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define EMSS_BASE (0xE001E000UL) /*!AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/** + \brief Software Reset + \details Initiates a system reset request to reset the CPU. + */ +__NO_RETURN __STATIC_INLINE void __SW_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */ + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */ + SCB_AIRCR_SYSRESETREQ_Msk ); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti 2.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti 2.h new file mode 100644 index 0000000..b18a228 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti 2.h @@ -0,0 +1,366 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_exti.h + * @author MCD Application Team + * @brief Header file of EXTI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS.Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32f4xx_HAL_EXTI_H +#define STM32f4xx_HAL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Types EXTI Exported Types + * @{ + */ +typedef enum +{ + HAL_EXTI_COMMON_CB_ID = 0x00U +} EXTI_CallbackIDTypeDef; + +/** + * @brief EXTI Handle structure definition + */ +typedef struct +{ + uint32_t Line; /*!< Exti line number */ + void (* PendingCallback)(void); /*!< Exti pending callback */ +} EXTI_HandleTypeDef; + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter + can be a value of @ref EXTI_Trigger */ + uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ +} EXTI_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_Line EXTI Line + * @{ + */ +#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */ +#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */ +#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */ +#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */ +#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */ +#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */ +#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */ +#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */ +#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */ +#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */ +#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */ +#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */ +#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */ +#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */ +#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */ +#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */ +#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */ +#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#if defined(EXTI_IMR_IM18) +#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */ +#else +#define EXTI_LINE_18 (EXTI_RESERVED | 0x12u) /*!< No interrupt supported in this line */ +#endif /* EXTI_IMR_IM18 */ +#if defined(EXTI_IMR_IM19) +#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ +#else +#define EXTI_LINE_19 (EXTI_RESERVED | 0x13u) /*!< No interrupt supported in this line */ +#endif /* EXTI_IMR_IM19 */ +#if defined(EXTI_IMR_IM20) +#define EXTI_LINE_20 (EXTI_CONFIG | 0x14u) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */ +#else +#define EXTI_LINE_20 (EXTI_RESERVED | 0x14u) /*!< No interrupt supported in this line */ +#endif /* EXTI_IMR_IM20 */ +#define EXTI_LINE_21 (EXTI_CONFIG | 0x15u) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ +#define EXTI_LINE_22 (EXTI_CONFIG | 0x16u) /*!< External interrupt line 22 Connected to the RTC Wakeup event */ +#if defined(EXTI_IMR_IM23) +#define EXTI_LINE_23 (EXTI_CONFIG | 0x17u) /*!< External interrupt line 23 Connected to the LPTIM1 asynchronous event */ +#endif /* EXTI_IMR_IM23 */ + +/** + * @} + */ + +/** @defgroup EXTI_Mode EXTI Mode + * @{ + */ +#define EXTI_MODE_NONE 0x00000000u +#define EXTI_MODE_INTERRUPT 0x00000001u +#define EXTI_MODE_EVENT 0x00000002u +/** + * @} + */ + +/** @defgroup EXTI_Trigger EXTI Trigger + * @{ + */ + +#define EXTI_TRIGGER_NONE 0x00000000u +#define EXTI_TRIGGER_RISING 0x00000001u +#define EXTI_TRIGGER_FALLING 0x00000002u +#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) +/** + * @} + */ + +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ +#define EXTI_GPIOA 0x00000000u +#define EXTI_GPIOB 0x00000001u +#define EXTI_GPIOC 0x00000002u +#if defined (GPIOD) +#define EXTI_GPIOD 0x00000003u +#endif /* GPIOD */ +#if defined (GPIOE) +#define EXTI_GPIOE 0x00000004u +#endif /* GPIOE */ +#if defined (GPIOF) +#define EXTI_GPIOF 0x00000005u +#endif /* GPIOF */ +#if defined (GPIOG) +#define EXTI_GPIOG 0x00000006u +#endif /* GPIOG */ +#if defined (GPIOH) +#define EXTI_GPIOH 0x00000007u +#endif /* GPIOH */ +#if defined (GPIOI) +#define EXTI_GPIOI 0x00000008u +#endif /* GPIOI */ +#if defined (GPIOJ) +#define EXTI_GPIOJ 0x00000009u +#endif /* GPIOJ */ +#if defined (GPIOK) +#define EXTI_GPIOK 0x0000000Au +#endif /* GPIOK */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +/** + * @brief EXTI Line property definition + */ +#define EXTI_PROPERTY_SHIFT 24u +#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT) +#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO) + +/** + * @brief EXTI bit usage + */ +#define EXTI_PIN_MASK 0x0000001Fu + +/** + * @brief EXTI Mask for interrupt & event mode + */ +#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) + +/** + * @brief EXTI Mask for trigger possibilities + */ +#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) + +/** + * @brief EXTI Line number + */ +#if defined(EXTI_IMR_IM23) +#define EXTI_LINE_NB 24UL +#else +#define EXTI_LINE_NB 23UL +#endif /* EXTI_IMR_IM23 */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Macros EXTI Private Macros + * @{ + */ +#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \ + ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB)) + +#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \ + (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u)) + +#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) + +#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING) + +#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u) + +#if !defined (GPIOD) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOH)) +#elif !defined (GPIOE) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOH)) +#elif !defined (GPIOF) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOH)) +#elif !defined (GPIOI) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH)) +#elif !defined (GPIOJ) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOI)) +#else +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOI) || \ + ((__PORT__) == EXTI_GPIOJ) || \ + ((__PORT__) == EXTI_GPIOK)) +#endif /* GPIOD */ + +#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI Exported Functions + * @brief EXTI Exported Functions + * @{ + */ + +/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions + * @brief Configuration functions + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32f4xx_HAL_EXTI_H */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex 2.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex 2.h new file mode 100644 index 0000000..5fa89db --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex 2.h @@ -0,0 +1,1063 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_flash_ex.h + * @author MCD Application Team + * @brief Header file of FLASH HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_FLASH_EX_H +#define __STM32F4xx_HAL_FLASH_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASHEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeErase; /*!< Mass erase or sector Erase. + This parameter can be a value of @ref FLASHEx_Type_Erase */ + + uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. + This parameter must be a value of @ref FLASHEx_Banks */ + + uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled + This parameter must be a value of @ref FLASHEx_Sectors */ + + uint32_t NbSectors; /*!< Number of sectors to be erased. + This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ + + uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism + This parameter must be a value of @ref FLASHEx_Voltage_Range */ + +} FLASH_EraseInitTypeDef; + +/** + * @brief FLASH Option Bytes Program structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< Option byte to be configured. + This parameter can be a value of @ref FLASHEx_Option_Type */ + + uint32_t WRPState; /*!< Write protection activation or deactivation. + This parameter can be a value of @ref FLASHEx_WRP_State */ + + uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected. + The value of this parameter depend on device used within the same series */ + + uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors. + This parameter must be a value of @ref FLASHEx_Banks */ + + uint32_t RDPLevel; /*!< Set the read protection level. + This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ + + uint32_t BORLevel; /*!< Set the BOR Level. + This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */ + + uint8_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. */ + +} FLASH_OBProgramInitTypeDef; + +/** + * @brief FLASH Advanced Option Bytes Program structure definition + */ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +typedef struct +{ + uint32_t OptionType; /*!< Option byte to be configured for extension. + This parameter can be a value of @ref FLASHEx_Advanced_Option_Type */ + + uint32_t PCROPState; /*!< PCROP activation or deactivation. + This parameter can be a value of @ref FLASHEx_PCROP_State */ + +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) + uint16_t Sectors; /*!< specifies the sector(s) set for PCROP. + This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */ +#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx ||\ + STM32F412Cx || STM32F413xx || STM32F423xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) + uint32_t Banks; /*!< Select banks for PCROP activation/deactivation of all sectors. + This parameter must be a value of @ref FLASHEx_Banks */ + + uint16_t SectorsBank1; /*!< Specifies the sector(s) set for PCROP for Bank1. + This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */ + + uint16_t SectorsBank2; /*!< Specifies the sector(s) set for PCROP for Bank2. + This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */ + + uint8_t BootConfig; /*!< Specifies Option bytes for boot config. + This parameter can be a value of @ref FLASHEx_Dual_Boot */ + +#endif /*STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +} FLASH_AdvOBProgramInitTypeDef; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || + STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASHEx_Type_Erase FLASH Type Erase + * @{ + */ +#define FLASH_TYPEERASE_SECTORS 0x00000000U /*!< Sectors erase only */ +#define FLASH_TYPEERASE_MASSERASE 0x00000001U /*!< Flash Mass erase activation */ +/** + * @} + */ + +/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range + * @{ + */ +#define FLASH_VOLTAGE_RANGE_1 0x00000000U /*!< Device operating range: 1.8V to 2.1V */ +#define FLASH_VOLTAGE_RANGE_2 0x00000001U /*!< Device operating range: 2.1V to 2.7V */ +#define FLASH_VOLTAGE_RANGE_3 0x00000002U /*!< Device operating range: 2.7V to 3.6V */ +#define FLASH_VOLTAGE_RANGE_4 0x00000003U /*!< Device operating range: 2.7V to 3.6V + External Vpp */ +/** + * @} + */ + +/** @defgroup FLASHEx_WRP_State FLASH WRP State + * @{ + */ +#define OB_WRPSTATE_DISABLE 0x00000000U /*!< Disable the write protection of the desired bank 1 sectors */ +#define OB_WRPSTATE_ENABLE 0x00000001U /*!< Enable the write protection of the desired bank 1 sectors */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Type FLASH Option Type + * @{ + */ +#define OPTIONBYTE_WRP 0x00000001U /*!< WRP option byte configuration */ +#define OPTIONBYTE_RDP 0x00000002U /*!< RDP option byte configuration */ +#define OPTIONBYTE_USER 0x00000004U /*!< USER option byte configuration */ +#define OPTIONBYTE_BOR 0x00000008U /*!< BOR option byte configuration */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection + * @{ + */ +#define OB_RDP_LEVEL_0 ((uint8_t)0xAA) +#define OB_RDP_LEVEL_1 ((uint8_t)0x55) +#define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2 + it s no more possible to go back to level 1 or 0 */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog + * @{ + */ +#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */ +#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP + * @{ + */ +#define OB_STOP_NO_RST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ +/** + * @} + */ + + +/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY + * @{ + */ +#define OB_STDBY_NO_RST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ +/** + * @} + */ + +/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level + * @{ + */ +#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */ +#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */ +#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */ +#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */ +/** + * @} + */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** @defgroup FLASHEx_PCROP_State FLASH PCROP State + * @{ + */ +#define OB_PCROP_STATE_DISABLE 0x00000000U /*!< Disable PCROP */ +#define OB_PCROP_STATE_ENABLE 0x00000001U /*!< Enable PCROP */ +/** + * @} + */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\ + STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ + STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +/** @defgroup FLASHEx_Advanced_Option_Type FLASH Advanced Option Type + * @{ + */ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +#define OPTIONBYTE_PCROP 0x00000001U /*!< PCROP option byte configuration */ +#define OPTIONBYTE_BOOTCONFIG 0x00000002U /*!< BOOTConfig option byte configuration */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ + defined(STM32F423xx) +#define OPTIONBYTE_PCROP 0x00000001U /*!= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \ + (((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) <= FLASH_OTP_END))) + +#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL)) + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFF000000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F413xx) || defined(STM32F423xx) +#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFF8000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F413xx || STM32F423xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) +#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ + +#if defined(STM32F401xC) +#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F401xC */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\ + defined(STM32F412Rx) || defined(STM32F412Cx) +#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F413xx) || defined(STM32F423xx) +#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFF8000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F413xx || STM32F423xx */ + +#if defined(STM32F401xC) +#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F401xC */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\ + defined(STM32F412Rx) || defined(STM32F412Cx) +#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +#define IS_OB_BOOT(BOOT) (((BOOT) == OB_DUAL_BOOT_ENABLE) || ((BOOT) == OB_DUAL_BOOT_DISABLE)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PCROP_SELECTED) || ((PCROP) == OB_PCROP_DESELECTED)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\ + STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ + STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASH Private Functions + * @{ + */ +void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange); +void FLASH_FlushCaches(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_FLASH_EX_H */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr 2.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr 2.h new file mode 100644 index 0000000..a7273d5 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr 2.h @@ -0,0 +1,436 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_pwr.h + * @author MCD Application Team + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_PWR_H +#define __STM32F4xx_HAL_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Types PWR Exported Types + * @{ + */ + +/** + * @brief PWR PVD configuration structure definition + */ +typedef struct +{ + uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. + This parameter can be a value of @ref PWR_PVD_detection_level */ + + uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWR_PVD_Mode */ +}PWR_PVDTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins + * @{ + */ +#define PWR_WAKEUP_PIN1 0x00000100U +/** + * @} + */ + +/** @defgroup PWR_PVD_detection_level PWR PVD detection level + * @{ + */ +#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 +#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 +#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 +#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 +#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 +#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 +#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 +#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7/* External input analog voltage + (Compare internally to VREFINT) */ +/** + * @} + */ + +/** @defgroup PWR_PVD_Mode PWR PVD Mode + * @{ + */ +#define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */ +#define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + + +/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode + * @{ + */ +#define PWR_MAINREGULATOR_ON 0x00000000U +#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS +/** + * @} + */ + +/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) +#define PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR ((uint8_t)0x03) + +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry + * @{ + */ +#define PWR_STOPENTRY_WFI ((uint8_t)0x01) +#define PWR_STOPENTRY_WFE ((uint8_t)0x02) +#define PWR_STOPENTRY_WFE_NO_EVT_CLEAR ((uint8_t)0x03) +/** + * @} + */ + +/** @defgroup PWR_Flag PWR Flag + * @{ + */ +#define PWR_FLAG_WU PWR_CSR_WUF +#define PWR_FLAG_SB PWR_CSR_SBF +#define PWR_FLAG_PVDO PWR_CSR_PVDO +#define PWR_FLAG_BRR PWR_CSR_BRR +#define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Macro PWR Exported Macro + * @{ + */ + +/** @brief Check PWR flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event + * was received from the WKUP pin or from the RTC alarm (Alarm A + * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup. + * An additional wakeup event is detected if the WKUP pin is enabled + * (by setting the EWUP bit) when the WKUP pin level is already high. + * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was + * resumed from StandBy mode. + * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled + * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode + * For this reason, this bit is equal to 0 after Standby or reset + * until the PVDE bit is set. + * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset + * when the device wakes up from Standby mode or by a system reset + * or power reset. + * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage + * scaling output selection is ready. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the PWR's pending flags. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U) + +/** + * @brief Enable the PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable the PVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD)) + +/** + * @brief Enable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD)) + +/** + * @brief Enable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + + +/** + * @brief Disable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + + +/** + * @brief PVD EXTI line configuration: set rising & falling edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\ + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\ + }while(0U) + +/** + * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. + * This parameter can be: + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\ + }while(0U) + +/** + * @brief checks whether the specified PVD Exti interrupt flag is set or not. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) + +/** + * @brief Clear the PVD Exti flag. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) + +/** + * @brief Generates a Software interrupt on PVD EXTI line. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD)) + +/** + * @} + */ + +/* Include PWR HAL Extension module */ +#include "stm32f4xx_hal_pwr_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_PWR_DeInit(void); +void HAL_PWR_EnableBkUpAccess(void); +void HAL_PWR_DisableBkUpAccess(void); +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ +/* Peripheral Control functions **********************************************/ +/* PVD configuration */ +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_EnablePVD(void); +void HAL_PWR_DisablePVD(void); + +/* WakeUp pins configuration */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); + +/* Low Power modes entry */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTANDBYMode(void); + +/* Power PVD IRQ Handler */ +void HAL_PWR_PVD_IRQHandler(void); +void HAL_PWR_PVDCallback(void); + +/* Cortex System Control functions *******************************************/ +void HAL_PWR_EnableSleepOnExit(void); +void HAL_PWR_DisableSleepOnExit(void); +void HAL_PWR_EnableSEVOnPend(void); +void HAL_PWR_DisableSEVOnPend(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PWR_Private_Constants PWR Private Constants + * @{ + */ + +/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line + * @{ + */ +#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ +/** + * @} + */ + +/** @defgroup PWR_register_alias_address PWR Register alias address + * @{ + */ +/* ------------- PWR registers bit address in the alias region ---------------*/ +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) +#define PWR_CR_OFFSET 0x00U +#define PWR_CSR_OFFSET 0x04U +#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET) +#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET) +/** + * @} + */ + +/** @defgroup PWR_CR_register_alias PWR CR Register alias address + * @{ + */ +/* --- CR Register ---*/ +/* Alias word address of DBP bit */ +#define DBP_BIT_NUMBER PWR_CR_DBP_Pos +#define CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U)) + +/* Alias word address of PVDE bit */ +#define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos +#define CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U)) + +/* Alias word address of VOS bit */ +#define VOS_BIT_NUMBER PWR_CR_VOS_Pos +#define CR_VOS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (VOS_BIT_NUMBER * 4U)) +/** + * @} + */ + +/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address + * @{ + */ +/* --- CSR Register ---*/ +/* Alias word address of EWUP bit */ +#define EWUP_BIT_NUMBER PWR_CSR_EWUP_Pos +#define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U)) +/** + * @} + */ + +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PWR_Private_Macros PWR Private Macros + * @{ + */ + +/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters + * @{ + */ +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ + ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ + ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ + ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) +#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ + ((MODE) == PWR_PVD_MODE_NORMAL)) +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) + +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || \ + ((ENTRY) == PWR_SLEEPENTRY_WFE) || \ + ((ENTRY) == PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR)) + +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || \ + ((ENTRY) == PWR_STOPENTRY_WFE) || \ + ((ENTRY) == PWR_STOPENTRY_WFE_NO_EVT_CLEAR)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F4xx_HAL_PWR_H */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus 2.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus 2.h new file mode 100644 index 0000000..ce19d4d --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus 2.h @@ -0,0 +1,2105 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_bus.h + * @author MCD Application Team + * @brief Header file of BUS LL module. + + @verbatim + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_LL_BUS_H +#define __STM32F4xx_LL_BUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup BUS_LL BUS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + * @{ + */ + +/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + * @{ + */ +#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN +#define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN +#define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN +#if defined(GPIOD) +#define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN +#endif /* GPIOD */ +#if defined(GPIOE) +#define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN +#endif /* GPIOE */ +#if defined(GPIOF) +#define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN +#endif /* GPIOF */ +#if defined(GPIOG) +#define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN +#endif /* GPIOG */ +#if defined(GPIOH) +#define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN +#endif /* GPIOH */ +#if defined(GPIOI) +#define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN +#endif /* GPIOI */ +#if defined(GPIOJ) +#define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN +#endif /* GPIOJ */ +#if defined(GPIOK) +#define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN +#endif /* GPIOK */ +#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN +#if defined(RCC_AHB1ENR_BKPSRAMEN) +#define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN +#endif /* RCC_AHB1ENR_BKPSRAMEN */ +#if defined(RCC_AHB1ENR_CCMDATARAMEN) +#define LL_AHB1_GRP1_PERIPH_CCMDATARAM RCC_AHB1ENR_CCMDATARAMEN +#endif /* RCC_AHB1ENR_CCMDATARAMEN */ +#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN +#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN +#if defined(RCC_AHB1ENR_RNGEN) +#define LL_AHB1_GRP1_PERIPH_RNG RCC_AHB1ENR_RNGEN +#endif /* RCC_AHB1ENR_RNGEN */ +#if defined(DMA2D) +#define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN +#endif /* DMA2D */ +#if defined(ETH) +#define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN +#define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN +#define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN +#define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN +#endif /* ETH */ +#if defined(USB_OTG_HS) +#define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN +#define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN +#endif /* USB_OTG_HS */ +#define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN +#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN +#if defined(RCC_AHB1LPENR_SRAM2LPEN) +#define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN +#endif /* RCC_AHB1LPENR_SRAM2LPEN */ +#if defined(RCC_AHB1LPENR_SRAM3LPEN) +#define LL_AHB1_GRP1_PERIPH_SRAM3 RCC_AHB1LPENR_SRAM3LPEN +#endif /* RCC_AHB1LPENR_SRAM3LPEN */ +/** + * @} + */ + +#if defined(RCC_AHB2_SUPPORT) +/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH + * @{ + */ +#define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU +#if defined(DCMI) +#define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN +#endif /* DCMI */ +#if defined(CRYP) +#define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN +#endif /* CRYP */ +#if defined(AES) +#define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN +#endif /* AES */ +#if defined(HASH) +#define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN +#endif /* HASH */ +#if defined(RCC_AHB2ENR_RNGEN) +#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN +#endif /* RCC_AHB2ENR_RNGEN */ +#if defined(USB_OTG_FS) +#define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN +#endif /* USB_OTG_FS */ +/** + * @} + */ +#endif /* RCC_AHB2_SUPPORT */ + +#if defined(RCC_AHB3_SUPPORT) +/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH + * @{ + */ +#define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU +#if defined(FSMC_Bank1) +#define LL_AHB3_GRP1_PERIPH_FSMC RCC_AHB3ENR_FSMCEN +#endif /* FSMC_Bank1 */ +#if defined(FMC_Bank1) +#define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN +#endif /* FMC_Bank1 */ +#if defined(QUADSPI) +#define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN +#endif /* QUADSPI */ +/** + * @} + */ +#endif /* RCC_AHB3_SUPPORT */ + +/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + * @{ + */ +#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU +#if defined(TIM2) +#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN +#endif /* TIM2 */ +#if defined(TIM3) +#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN +#endif /* TIM3 */ +#if defined(TIM4) +#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN +#endif /* TIM4 */ +#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN +#if defined(TIM6) +#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN +#endif /* TIM6 */ +#if defined(TIM7) +#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN +#endif /* TIM7 */ +#if defined(TIM12) +#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN +#endif /* TIM12 */ +#if defined(TIM13) +#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN +#endif /* TIM13 */ +#if defined(TIM14) +#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN +#endif /* TIM14 */ +#if defined(LPTIM1) +#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN +#endif /* LPTIM1 */ +#if defined(RCC_APB1ENR_RTCAPBEN) +#define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCAPBEN +#endif /* RCC_APB1ENR_RTCAPBEN */ +#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN +#if defined(SPI2) +#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN +#endif /* SPI2 */ +#if defined(SPI3) +#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN +#endif /* SPI3 */ +#if defined(SPDIFRX) +#define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN +#endif /* SPDIFRX */ +#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN +#if defined(USART3) +#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN +#endif /* USART3 */ +#if defined(UART4) +#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN +#endif /* UART4 */ +#if defined(UART5) +#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN +#endif /* UART5 */ +#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN +#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN +#if defined(I2C3) +#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN +#endif /* I2C3 */ +#if defined(FMPI2C1) +#define LL_APB1_GRP1_PERIPH_FMPI2C1 RCC_APB1ENR_FMPI2C1EN +#endif /* FMPI2C1 */ +#if defined(CAN1) +#define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN +#endif /* CAN1 */ +#if defined(CAN2) +#define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN +#endif /* CAN2 */ +#if defined(CAN3) +#define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN +#endif /* CAN3 */ +#if defined(CEC) +#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN +#endif /* CEC */ +#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN +#if defined(DAC1) +#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN +#endif /* DAC1 */ +#if defined(UART7) +#define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN +#endif /* UART7 */ +#if defined(UART8) +#define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN +#endif /* UART8 */ +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + * @{ + */ +#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN +#if defined(TIM8) +#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN +#endif /* TIM8 */ +#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN +#if defined(USART6) +#define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN +#endif /* USART6 */ +#if defined(UART9) +#define LL_APB2_GRP1_PERIPH_UART9 RCC_APB2ENR_UART9EN +#endif /* UART9 */ +#if defined(UART10) +#define LL_APB2_GRP1_PERIPH_UART10 RCC_APB2ENR_UART10EN +#endif /* UART10 */ +#define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN +#if defined(ADC2) +#define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN +#endif /* ADC2 */ +#if defined(ADC3) +#define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN +#endif /* ADC3 */ +#if defined(SDIO) +#define LL_APB2_GRP1_PERIPH_SDIO RCC_APB2ENR_SDIOEN +#endif /* SDIO */ +#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN +#if defined(SPI4) +#define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN +#endif /* SPI4 */ +#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN +#if defined(RCC_APB2ENR_EXTITEN) +#define LL_APB2_GRP1_PERIPH_EXTI RCC_APB2ENR_EXTITEN +#endif /* RCC_APB2ENR_EXTITEN */ +#define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN +#if defined(TIM10) +#define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN +#endif /* TIM10 */ +#define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN +#if defined(SPI5) +#define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN +#endif /* SPI5 */ +#if defined(SPI6) +#define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN +#endif /* SPI6 */ +#if defined(SAI1) +#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN +#endif /* SAI1 */ +#if defined(SAI2) +#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN +#endif /* SAI2 */ +#if defined(LTDC) +#define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN +#endif /* LTDC */ +#if defined(DSI) +#define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN +#endif /* DSI */ +#if defined(DFSDM1_Channel0) +#define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN +#endif /* DFSDM1_Channel0 */ +#if defined(DFSDM2_Channel0) +#define LL_APB2_GRP1_PERIPH_DFSDM2 RCC_APB2ENR_DFSDM2EN +#endif /* DFSDM2_Channel0 */ +#define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + * @{ + */ + +/** @defgroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ + +/** + * @brief Enable AHB1 peripherals clock. + * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR RNGEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clock is enabled or not + * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); +} + +/** + * @brief Disable AHB1 peripherals clock. + * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR RNGEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1ENR, Periphs); +} + +/** + * @brief Force AHB1 peripherals reset. + * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR RNGRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB1RSTR, Periphs); +} + +/** + * @brief Release AHB1 peripherals reset. + * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1RSTR, Periphs); +} + +/** + * @brief Enable AHB1 peripheral clocks in low-power mode + * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR RNGLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB1 peripheral clocks in low-power mode + * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR RNGLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1LPENR, Periphs); +} + +/** + * @} + */ + +#if defined(RCC_AHB2_SUPPORT) +/** @defgroup BUS_LL_EF_AHB2 AHB2 + * @{ + */ + +/** + * @brief Enable AHB2 peripherals clock. + * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB2 peripheral clock is enabled or not + * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs); +} + +/** + * @brief Disable AHB2 peripherals clock. + * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2ENR, Periphs); +} + +/** + * @brief Force AHB2 peripherals reset. + * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB2RSTR, Periphs); +} + +/** + * @brief Release AHB2 peripherals reset. + * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2RSTR, Periphs); +} + +/** + * @brief Enable AHB2 peripheral clocks in low-power mode + * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n + * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n + * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n + * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n + * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n + * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB2 peripheral clocks in low-power mode + * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n + * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n + * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n + * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n + * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n + * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2LPENR, Periphs); +} + +/** + * @} + */ +#endif /* RCC_AHB2_SUPPORT */ + +#if defined(RCC_AHB3_SUPPORT) +/** @defgroup BUS_LL_EF_AHB3 AHB3 + * @{ + */ + +/** + * @brief Enable AHB3 peripherals clock. + * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR FSMCEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB3 peripheral clock is enabled or not + * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR FSMCEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs); +} + +/** + * @brief Disable AHB3 peripherals clock. + * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR FSMCEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3ENR, Periphs); +} + +/** + * @brief Force AHB3 peripherals reset. + * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR FSMCRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_ALL + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB3RSTR, Periphs); +} + +/** + * @brief Release AHB3 peripherals reset. + * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR FSMCRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3RSTR, Periphs); +} + +/** + * @brief Enable AHB3 peripheral clocks in low-power mode + * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n + * AHB3LPENR FSMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n + * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB3LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB3 peripheral clocks in low-power mode + * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n + * AHB3LPENR FSMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n + * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3LPENR, Periphs); +} + +/** + * @} + */ +#endif /* RCC_AHB3_SUPPORT */ + +/** @defgroup BUS_LL_EF_APB1 APB1 + * @{ + */ + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n + * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR FMPI2C1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n + * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n + * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n + * APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n + * APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n + * APB1ENR RTCAPBEN LL_APB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR FMPI2C1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR RTCAPBEN LL_APB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); +} + +/** + * @brief Disable APB1 peripherals clock. + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n + * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR FMPI2C1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n + * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n + * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n + * APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n + * APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n + * APB1ENR RTCAPBEN LL_APB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1ENR, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR FMPI2C1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR UART8RST LL_APB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1RSTR, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR FMPI2C1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1RSTR, Periphs); +} + +/** + * @brief Enable APB1 peripheral clocks in low-power mode + * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR RTCAPBLPEN LL_APB1_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB1 peripheral clocks in low-power mode + * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR RTCAPBLPEN LL_APB1_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB2 APB2 + * @{ + */ + +/** + * @brief Enable APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n + * APB2ENR UART9EN LL_APB2_GRP1_EnableClock\n + * APB2ENR UART10EN LL_APB2_GRP1_EnableClock\n + * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n + * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SDIOEN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n + * APB2ENR EXTITEN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n + * APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n + * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR DFSDM2EN LL_APB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) + + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB2 peripheral clock is enabled or not + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR UART9EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR UART10EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SDIOEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR EXTITEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI6EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR DFSDM2EN LL_APB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); +} + +/** + * @brief Disable APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n + * APB2ENR UART9EN LL_APB2_GRP1_DisableClock\n + * APB2ENR UART10EN LL_APB2_GRP1_DisableClock\n + * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n + * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SDIOEN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n + * APB2ENR EXTITEN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI6EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n + * APB2ENR DSIEN LL_APB2_GRP1_DisableClock\n + * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR DFSDM2EN LL_APB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2ENR, Periphs); +} + +/** + * @brief Force APB2 peripherals reset. + * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR UART9RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR UART10RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SDIORST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI6RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR DFSDM2RST LL_APB2_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC + * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Release APB2 peripherals reset. + * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR UART9RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR UART10RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SDIORST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI6RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR DFSDM2RST LL_APB2_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC + * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Enable APB2 peripheral clocks in low-power mode + * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR UART9LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR UART10LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR ADC2LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR ADC3LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SDIOLPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR EXTITLPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SPI6LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR LTDCLPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR DFSDM2LPEN LL_APB2_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB2 peripheral clocks in low-power mode + * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR UART9LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR UART10LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR ADC2LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR ADC3LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SDIOLPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR EXTITLPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SPI6LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR LTDCLPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR DFSDM2LPEN LL_APB2_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2LPENR, Periphs); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_LL_BUS_H */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc 2.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc 2.h new file mode 100644 index 0000000..1d3c652 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc 2.h @@ -0,0 +1,1145 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_sdmmc.h + * @author MCD Application Team + * @brief Header file of SDMMC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F4xx_LL_SDMMC_H +#define STM32F4xx_LL_SDMMC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(SDIO) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_Driver + * @{ + */ + +/** @addtogroup SDMMC_LL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types + * @{ + */ + +/** + * @brief SDMMC Configuration Structure definition + */ +typedef struct +{ + uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ + + uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is + enabled or disabled. + This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */ + + uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or + disabled when the bus is idle. + This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ + + uint32_t BusWide; /*!< Specifies the SDMMC bus width. + This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ + + uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled. + This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ + + uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. + This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ + +}SDIO_InitTypeDef; + + +/** + * @brief SDMMC Command Control structure + */ +typedef struct +{ + uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent + to a card as part of a command message. If a command + contains an argument, it must be loaded into this register + before writing the command to the command register. */ + + uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and + Max_Data = 64 */ + + uint32_t Response; /*!< Specifies the SDMMC response type. + This parameter can be a value of @ref SDMMC_LL_Response_Type */ + + uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is + enabled or disabled. + This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ + + uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM) + is enabled or disabled. + This parameter can be a value of @ref SDMMC_LL_CPSM_State */ +}SDIO_CmdInitTypeDef; + + +/** + * @brief SDMMC Data Control structure + */ +typedef struct +{ + uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ + + uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ + + uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. + This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */ + + uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer + is a read or write. + This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ + + uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. + This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ + + uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM) + is enabled or disabled. + This parameter can be a value of @ref SDMMC_LL_DPSM_State */ +}SDIO_DataInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants + * @{ + */ +#define SDMMC_ERROR_NONE 0x00000000U /*!< No error */ +#define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /*!< Command response received (but CRC check failed) */ +#define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /*!< Data block sent/received (CRC check failed) */ +#define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /*!< Command response timeout */ +#define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /*!< Data timeout */ +#define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /*!< Transmit FIFO underrun */ +#define SDMMC_ERROR_RX_OVERRUN 0x00000020U /*!< Receive FIFO overrun */ +#define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /*!< Misaligned address */ +#define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the + number of transferred bytes does not match the block length */ +#define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /*!< An error in the sequence of erase command occurs */ +#define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /*!< An invalid selection for erase groups */ +#define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /*!< Attempt to program a write protect block */ +#define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock + command or if there was an attempt to access a locked card */ +#define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /*!< CRC check of the previous command failed */ +#define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /*!< Command is not legal for the card state */ +#define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /*!< Card internal ECC was applied but failed to correct the data */ +#define SDMMC_ERROR_CC_ERR 0x00008000U /*!< Internal card controller error */ +#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /*!< General or unknown error */ +#define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /*!< The card could not sustain data reading in stream rmode */ +#define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /*!< The card could not sustain data programming in stream mode */ +#define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /*!< CID/CSD overwrite error */ +#define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /*!< Only partial address space was erased */ +#define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /*!< Command has been executed without using internal ECC */ +#define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out + of erase sequence command was received */ +#define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /*!< Error in sequence of authentication */ +#define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /*!< Error in case of invalid voltage range */ +#define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /*!< Error when addressed block is out of range */ +#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /*!< Error when command request is not applicable */ +#define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /*!< the used parameter is not valid */ +#define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /*!< Error when feature is not insupported */ +#define SDMMC_ERROR_BUSY 0x20000000U /*!< Error when transfer process is busy */ +#define SDMMC_ERROR_DMA 0x40000000U /*!< Error while DMA transfer */ +#define SDMMC_ERROR_TIMEOUT 0x80000000U /*!< Timeout error */ + +/** + * @brief SDMMC Commands Index + */ +#define SDMMC_CMD_GO_IDLE_STATE 0U /*!< Resets the SD memory card. */ +#define SDMMC_CMD_SEND_OP_COND 1U /*!< Sends host capacity support information and activates the card's initialization process. */ +#define SDMMC_CMD_ALL_SEND_CID 2U /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ +#define SDMMC_CMD_SET_REL_ADDR 3U /*!< Asks the card to publish a new relative address (RCA). */ +#define SDMMC_CMD_SET_DSR 4U /*!< Programs the DSR of all cards. */ +#define SDMMC_CMD_SDMMC_SEN_OP_COND 5U /*!< Sends host capacity support information (HCS) and asks the accessed card to send its + operating condition register (OCR) content in the response on the CMD line. */ +#define SDMMC_CMD_HS_SWITCH 6U /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ +#define SDMMC_CMD_SEL_DESEL_CARD 7U /*!< Selects the card by its own relative address and gets deselected by any other address */ +#define SDMMC_CMD_HS_SEND_EXT_CSD 8U /*!< Sends SD Memory Card interface condition, which includes host supply voltage information + and asks the card whether card supports voltage. */ +#define SDMMC_CMD_SEND_CSD 9U /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ +#define SDMMC_CMD_SEND_CID 10U /*!< Addressed card sends its card identification (CID) on the CMD line. */ +#define SDMMC_CMD_READ_DAT_UNTIL_STOP 11U /*!< SD card doesn't support it. */ +#define SDMMC_CMD_STOP_TRANSMISSION 12U /*!< Forces the card to stop transmission. */ +#define SDMMC_CMD_SEND_STATUS 13U /*!< Addressed card sends its status register. */ +#define SDMMC_CMD_HS_BUSTEST_READ 14U /*!< Reserved */ +#define SDMMC_CMD_GO_INACTIVE_STATE 15U /*!< Sends an addressed card into the inactive state. */ +#define SDMMC_CMD_SET_BLOCKLEN 16U /*!< Sets the block length (in bytes for SDSC) for all following block commands + (read, write, lock). Default block length is fixed to 512 Bytes. Not effective + for SDHS and SDXC. */ +#define SDMMC_CMD_READ_SINGLE_BLOCK 17U /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of + fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_READ_MULT_BLOCK 18U /*!< Continuously transfers data blocks from card to host until interrupted by + STOP_TRANSMISSION command. */ +#define SDMMC_CMD_HS_BUSTEST_WRITE 19U /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ +#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP 20U /*!< Speed class control command. */ +#define SDMMC_CMD_SET_BLOCK_COUNT 23U /*!< Specify block count for CMD18 and CMD25. */ +#define SDMMC_CMD_WRITE_SINGLE_BLOCK 24U /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of + fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_WRITE_MULT_BLOCK 25U /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ +#define SDMMC_CMD_PROG_CID 26U /*!< Reserved for manufacturers. */ +#define SDMMC_CMD_PROG_CSD 27U /*!< Programming of the programmable bits of the CSD. */ +#define SDMMC_CMD_SET_WRITE_PROT 28U /*!< Sets the write protection bit of the addressed group. */ +#define SDMMC_CMD_CLR_WRITE_PROT 29U /*!< Clears the write protection bit of the addressed group. */ +#define SDMMC_CMD_SEND_WRITE_PROT 30U /*!< Asks the card to send the status of the write protection bits. */ +#define SDMMC_CMD_SD_ERASE_GRP_START 32U /*!< Sets the address of the first write block to be erased. (For SD card only). */ +#define SDMMC_CMD_SD_ERASE_GRP_END 33U /*!< Sets the address of the last write block of the continuous range to be erased. */ +#define SDMMC_CMD_ERASE_GRP_START 35U /*!< Sets the address of the first write block to be erased. Reserved for each command + system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE_GRP_END 36U /*!< Sets the address of the last write block of the continuous range to be erased. + Reserved for each command system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE 38U /*!< Reserved for SD security applications. */ +#define SDMMC_CMD_FAST_IO 39U /*!< SD card doesn't support it (Reserved). */ +#define SDMMC_CMD_GO_IRQ_STATE 40U /*!< SD card doesn't support it (Reserved). */ +#define SDMMC_CMD_LOCK_UNLOCK 42U /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by + the SET_BLOCK_LEN command. */ +#define SDMMC_CMD_APP_CMD 55U /*!< Indicates to the card that the next command is an application specific command rather + than a standard command. */ +#define SDMMC_CMD_GEN_CMD 56U /*!< Used either to transfer a data block to the card or to get a data block from the card + for general purpose/application specific commands. */ +#define SDMMC_CMD_NO_CMD 64U /*!< No command */ + +/** + * @brief Following commands are SD Card Specific commands. + * SDMMC_APP_CMD should be sent before sending these commands. + */ +#define SDMMC_CMD_APP_SD_SET_BUSWIDTH 6U /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus + widths are given in SCR register. */ +#define SDMMC_CMD_SD_APP_STATUS 13U /*!< (ACMD13) Sends the SD status. */ +#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS 22U /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with + 32bit+CRC data block. */ +#define SDMMC_CMD_SD_APP_OP_COND 41U /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to + send its operating condition register (OCR) content in the response on the CMD line. */ +#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT 42U /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ +#define SDMMC_CMD_SD_APP_SEND_SCR 51U /*!< Reads the SD Configuration Register (SCR). */ +#define SDMMC_CMD_SDMMC_RW_DIRECT 52U /*!< For SD I/O card only, reserved for security specification. */ +#define SDMMC_CMD_SDMMC_RW_EXTENDED 53U /*!< For SD I/O card only, reserved for security specification. */ + +/** + * @brief Following commands are SD Card Specific security commands. + * SDMMC_CMD_APP_CMD should be sent before sending these commands. + */ +#define SDMMC_CMD_SD_APP_GET_MKB 43U +#define SDMMC_CMD_SD_APP_GET_MID 44U +#define SDMMC_CMD_SD_APP_SET_CER_RN1 45U +#define SDMMC_CMD_SD_APP_GET_CER_RN2 46U +#define SDMMC_CMD_SD_APP_SET_CER_RES2 47U +#define SDMMC_CMD_SD_APP_GET_CER_RES1 48U +#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK 18U +#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK 25U +#define SDMMC_CMD_SD_APP_SECURE_ERASE 38U +#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA 49U +#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB 48U + +/** + * @brief Masks for errors Card Status R1 (OCR Register) + */ +#define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U +#define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U +#define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U +#define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U +#define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U +#define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U +#define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U +#define SDMMC_OCR_COM_CRC_FAILED 0x00800000U +#define SDMMC_OCR_ILLEGAL_CMD 0x00400000U +#define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U +#define SDMMC_OCR_CC_ERROR 0x00100000U +#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U +#define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U +#define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U +#define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U +#define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U +#define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U +#define SDMMC_OCR_ERASE_RESET 0x00002000U +#define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U +#define SDMMC_OCR_ERRORBITS 0xFDFFE008U + +/** + * @brief Masks for R6 Response + */ +#define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U +#define SDMMC_R6_ILLEGAL_CMD 0x00004000U +#define SDMMC_R6_COM_CRC_FAILED 0x00008000U + +#define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U +#define SDMMC_HIGH_CAPACITY 0x40000000U +#define SDMMC_STD_CAPACITY 0x00000000U +#define SDMMC_CHECK_PATTERN 0x000001AAU +#define SD_SWITCH_1_8V_CAPACITY 0x01000000U + +#define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU + +#define SDMMC_MAX_TRIAL 0x0000FFFFU + +#define SDMMC_ALLZERO 0x00000000U + +#define SDMMC_WIDE_BUS_SUPPORT 0x00040000U +#define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U +#define SDMMC_CARD_LOCKED 0x02000000U + +#ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (ms) */ +#define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) +#endif /* SDMMC_DATATIMEOUT */ + +#ifndef SDMMC_SWDATATIMEOUT /*Software Data Timeout (ms) */ +#define SDMMC_SWDATATIMEOUT SDMMC_DATATIMEOUT +#endif /* SDMMC_SWDATATIMEOUT */ + +#define SDMMC_0TO7BITS 0x000000FFU +#define SDMMC_8TO15BITS 0x0000FF00U +#define SDMMC_16TO23BITS 0x00FF0000U +#define SDMMC_24TO31BITS 0xFF000000U +#define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU + +#define SDMMC_HALFFIFO 0x00000008U +#define SDMMC_HALFFIFOBYTES 0x00000020U + +/** + * @brief Command Class supported + */ +#define SDIO_CCCC_ERASE 0x00000020U + +#define SDIO_CMDTIMEOUT 5000U /* Command send and response timeout */ +#define SDIO_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */ +#define SDIO_STOPTRANSFERTIMEOUT 100000000U /* Timeout for STOP TRANSMISSION command */ + +/** @defgroup SDIO_LL_Clock_Edge Clock Edge + * @{ + */ +#define SDIO_CLOCK_EDGE_RISING 0x00000000U +#define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE + +#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \ + ((EDGE) == SDIO_CLOCK_EDGE_FALLING)) +/** + * @} + */ + +/** @defgroup SDIO_LL_Clock_Bypass Clock Bypass + * @{ + */ +#define SDIO_CLOCK_BYPASS_DISABLE 0x00000000U +#define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS + +#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \ + ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE)) +/** + * @} + */ + +/** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving + * @{ + */ +#define SDIO_CLOCK_POWER_SAVE_DISABLE 0x00000000U +#define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV + +#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \ + ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE)) +/** + * @} + */ + +/** @defgroup SDIO_LL_Bus_Wide Bus Width + * @{ + */ +#define SDIO_BUS_WIDE_1B 0x00000000U +#define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0 +#define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1 + +#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \ + ((WIDE) == SDIO_BUS_WIDE_4B) || \ + ((WIDE) == SDIO_BUS_WIDE_8B)) +/** + * @} + */ + +/** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control + * @{ + */ +#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE 0x00000000U +#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN + +#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \ + ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE)) +/** + * @} + */ + +/** @defgroup SDIO_LL_Clock_Division Clock Division + * @{ + */ +#define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFFU) +/** + * @} + */ + +/** @defgroup SDIO_LL_Command_Index Command Index + * @{ + */ +#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40U) +/** + * @} + */ + +/** @defgroup SDIO_LL_Response_Type Response Type + * @{ + */ +#define SDIO_RESPONSE_NO 0x00000000U +#define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0 +#define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP + +#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \ + ((RESPONSE) == SDIO_RESPONSE_SHORT) || \ + ((RESPONSE) == SDIO_RESPONSE_LONG)) +/** + * @} + */ + +/** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt + * @{ + */ +#define SDIO_WAIT_NO 0x00000000U +#define SDIO_WAIT_IT SDIO_CMD_WAITINT +#define SDIO_WAIT_PEND SDIO_CMD_WAITPEND + +#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \ + ((WAIT) == SDIO_WAIT_IT) || \ + ((WAIT) == SDIO_WAIT_PEND)) +/** + * @} + */ + +/** @defgroup SDIO_LL_CPSM_State CPSM State + * @{ + */ +#define SDIO_CPSM_DISABLE 0x00000000U +#define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN + +#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \ + ((CPSM) == SDIO_CPSM_ENABLE)) +/** + * @} + */ + +/** @defgroup SDIO_LL_Response_Registers Response Register + * @{ + */ +#define SDIO_RESP1 0x00000000U +#define SDIO_RESP2 0x00000004U +#define SDIO_RESP3 0x00000008U +#define SDIO_RESP4 0x0000000CU + +#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \ + ((RESP) == SDIO_RESP2) || \ + ((RESP) == SDIO_RESP3) || \ + ((RESP) == SDIO_RESP4)) +/** + * @} + */ + +/** @defgroup SDIO_LL_Data_Length Data Length + * @{ + */ +#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU) +/** + * @} + */ + +/** @defgroup SDIO_LL_Data_Block_Size Data Block Size + * @{ + */ +#define SDIO_DATABLOCK_SIZE_1B 0x00000000U +#define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0 +#define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1 +#define SDIO_DATABLOCK_SIZE_8B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1) +#define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2 +#define SDIO_DATABLOCK_SIZE_32B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2) +#define SDIO_DATABLOCK_SIZE_64B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2) +#define SDIO_DATABLOCK_SIZE_128B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2) +#define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3 +#define SDIO_DATABLOCK_SIZE_512B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_3) +#define SDIO_DATABLOCK_SIZE_1024B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3) +#define SDIO_DATABLOCK_SIZE_2048B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3) +#define SDIO_DATABLOCK_SIZE_4096B (SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) +#define SDIO_DATABLOCK_SIZE_8192B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) +#define SDIO_DATABLOCK_SIZE_16384B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) + +#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_16384B)) +/** + * @} + */ + +/** @defgroup SDIO_LL_Transfer_Direction Transfer Direction + * @{ + */ +#define SDIO_TRANSFER_DIR_TO_CARD 0x00000000U +#define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR + +#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \ + ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO)) +/** + * @} + */ + +/** @defgroup SDIO_LL_Transfer_Type Transfer Type + * @{ + */ +#define SDIO_TRANSFER_MODE_BLOCK 0x00000000U +#define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE + +#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \ + ((MODE) == SDIO_TRANSFER_MODE_STREAM)) +/** + * @} + */ + +/** @defgroup SDIO_LL_DPSM_State DPSM State + * @{ + */ +#define SDIO_DPSM_DISABLE 0x00000000U +#define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN + +#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\ + ((DPSM) == SDIO_DPSM_ENABLE)) +/** + * @} + */ + +/** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode + * @{ + */ +#define SDIO_READ_WAIT_MODE_DATA2 0x00000000U +#define SDIO_READ_WAIT_MODE_CLK (SDIO_DCTRL_RWMOD) + +#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \ + ((MODE) == SDIO_READ_WAIT_MODE_DATA2)) +/** + * @} + */ + +/** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources + * @{ + */ +#define SDIO_IT_CCRCFAIL SDIO_MASK_CCRCFAILIE +#define SDIO_IT_DCRCFAIL SDIO_MASK_DCRCFAILIE +#define SDIO_IT_CTIMEOUT SDIO_MASK_CTIMEOUTIE +#define SDIO_IT_DTIMEOUT SDIO_MASK_DTIMEOUTIE +#define SDIO_IT_TXUNDERR SDIO_MASK_TXUNDERRIE +#define SDIO_IT_RXOVERR SDIO_MASK_RXOVERRIE +#define SDIO_IT_CMDREND SDIO_MASK_CMDRENDIE +#define SDIO_IT_CMDSENT SDIO_MASK_CMDSENTIE +#define SDIO_IT_DATAEND SDIO_MASK_DATAENDIE +#if defined(SDIO_STA_STBITERR) +#define SDIO_IT_STBITERR SDIO_MASK_STBITERRIE +#endif +#define SDIO_IT_DBCKEND SDIO_MASK_DBCKENDIE +#define SDIO_IT_CMDACT SDIO_MASK_CMDACTIE +#define SDIO_IT_TXACT SDIO_MASK_TXACTIE +#define SDIO_IT_RXACT SDIO_MASK_RXACTIE +#define SDIO_IT_TXFIFOHE SDIO_MASK_TXFIFOHEIE +#define SDIO_IT_RXFIFOHF SDIO_MASK_RXFIFOHFIE +#define SDIO_IT_TXFIFOF SDIO_MASK_TXFIFOFIE +#define SDIO_IT_RXFIFOF SDIO_MASK_RXFIFOFIE +#define SDIO_IT_TXFIFOE SDIO_MASK_TXFIFOEIE +#define SDIO_IT_RXFIFOE SDIO_MASK_RXFIFOEIE +#define SDIO_IT_TXDAVL SDIO_MASK_TXDAVLIE +#define SDIO_IT_RXDAVL SDIO_MASK_RXDAVLIE +#define SDIO_IT_SDIOIT SDIO_MASK_SDIOITIE +#if defined(SDIO_CMD_CEATACMD) +#define SDIO_IT_CEATAEND SDIO_MASK_CEATAENDIE +#endif +/** + * @} + */ + +/** @defgroup SDIO_LL_Flags Flags + * @{ + */ +#define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL +#define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL +#define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT +#define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT +#define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR +#define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR +#define SDIO_FLAG_CMDREND SDIO_STA_CMDREND +#define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT +#define SDIO_FLAG_DATAEND SDIO_STA_DATAEND +#if defined(SDIO_STA_STBITERR) +#define SDIO_FLAG_STBITERR SDIO_STA_STBITERR +#endif +#define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND +#define SDIO_FLAG_CMDACT SDIO_STA_CMDACT +#define SDIO_FLAG_TXACT SDIO_STA_TXACT +#define SDIO_FLAG_RXACT SDIO_STA_RXACT +#define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE +#define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF +#define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF +#define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF +#define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE +#define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE +#define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL +#define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL +#define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT +#if defined(SDIO_CMD_CEATACMD) +#define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND +#endif +#define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\ + SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR |\ + SDIO_FLAG_CMDREND | SDIO_FLAG_CMDSENT | SDIO_FLAG_DATAEND |\ + SDIO_FLAG_DBCKEND | SDIO_FLAG_SDIOIT)) + +#define SDIO_STATIC_CMD_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND |\ + SDIO_FLAG_CMDSENT)) + +#define SDIO_STATIC_DATA_FLAGS ((uint32_t)(SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR |\ + SDIO_FLAG_RXOVERR | SDIO_FLAG_DATAEND | SDIO_FLAG_DBCKEND)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SDIO_LL_Exported_macros SDIO_LL Exported Macros + * @{ + */ + +/** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region + * @{ + */ +/* ------------ SDIO registers bit address in the alias region -------------- */ +#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) + +/* --- CLKCR Register ---*/ +/* Alias word address of CLKEN bit */ +#define CLKCR_OFFSET (SDIO_OFFSET + 0x04U) +#define CLKEN_BITNUMBER 0x08U +#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U)) + +/* --- CMD Register ---*/ +/* Alias word address of SDIOSUSPEND bit */ +#define CMD_OFFSET (SDIO_OFFSET + 0x0CU) +#define SDIOSUSPEND_BITNUMBER 0x0BU +#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U)) + +/* Alias word address of ENCMDCOMPL bit */ +#define ENCMDCOMPL_BITNUMBER 0x0CU +#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U)) + +/* Alias word address of NIEN bit */ +#define NIEN_BITNUMBER 0x0DU +#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U)) + +/* Alias word address of ATACMD bit */ +#define ATACMD_BITNUMBER 0x0EU +#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U)) + +/* --- DCTRL Register ---*/ +/* Alias word address of DMAEN bit */ +#define DCTRL_OFFSET (SDIO_OFFSET + 0x2CU) +#define DMAEN_BITNUMBER 0x03U +#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U)) + +/* Alias word address of RWSTART bit */ +#define RWSTART_BITNUMBER 0x08U +#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U)) + +/* Alias word address of RWSTOP bit */ +#define RWSTOP_BITNUMBER 0x09U +#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U)) + +/* Alias word address of RWMOD bit */ +#define RWMOD_BITNUMBER 0x0AU +#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U)) + +/* Alias word address of SDIOEN bit */ +#define SDIOEN_BITNUMBER 0x0BU +#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U)) +/** + * @} + */ + +/** @defgroup SDIO_LL_Register Bits And Addresses Definitions + * @brief SDIO_LL registers bit address in the alias region + * @{ + */ +/* ---------------------- SDIO registers bit mask --------------------------- */ +/* --- CLKCR Register ---*/ +/* CLKCR register clear mask */ +#define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\ + SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\ + SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN)) + +/* --- DCTRL Register ---*/ +/* SDIO DCTRL Clear Mask */ +#define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\ + SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE)) + +/* --- CMD Register ---*/ +/* CMD Register clear mask */ +#define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\ + SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\ + SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND)) + +/* SDIO Initialization Frequency (400KHz max) */ +#define SDIO_INIT_CLK_DIV ((uint8_t)0x76) /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */ + +/* SDIO Data Transfer Frequency (25MHz max) */ +#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0) /* 48MHz / (SDMMC_TRANSFER_CLK_DIV + 2) < 25MHz */ +/** + * @} + */ + +/** @defgroup SDIO_LL_Interrupt_Clock Interrupt And Clock Configuration + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ + +/** + * @brief Enable the SDIO device. + * @param __INSTANCE__: SDIO Instance + * @retval None + */ +#define __SDIO_ENABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE) + +/** + * @brief Disable the SDIO device. + * @param __INSTANCE__: SDIO Instance + * @retval None + */ +#define __SDIO_DISABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE) + +/** + * @brief Enable the SDIO DMA transfer. + * @param __INSTANCE__: SDIO Instance + * @retval None + */ +#define __SDIO_DMA_ENABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE) + +/** + * @brief Disable the SDIO DMA transfer. + * @param __INSTANCE__: SDIO Instance + * @retval None + */ +#define __SDIO_DMA_DISABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE) + +/** + * @brief Enable the SDIO device interrupt. + * @param __INSTANCE__ : Pointer to SDIO register base + * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt + * @retval None + */ +#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) + +/** + * @brief Disable the SDIO device interrupt. + * @param __INSTANCE__ : Pointer to SDIO register base + * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt + * @retval None + */ +#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) + +/** + * @brief Checks whether the specified SDIO flag is set or not. + * @param __INSTANCE__ : Pointer to SDIO register base + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_CMDACT: Command transfer in progress + * @arg SDIO_FLAG_TXACT: Data transmit in progress + * @arg SDIO_FLAG_RXACT: Data receive in progress + * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty + * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full + * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full + * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full + * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty + * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty + * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO + * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO + * @arg SDIO_FLAG_SDIOIT: SDIO interrupt received + * @retval The new state of SDIO_FLAG (SET or RESET). + */ +#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U) + + +/** + * @brief Clears the SDIO pending flags. + * @param __INSTANCE__ : Pointer to SDIO register base + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_SDIOIT: SDIO interrupt received + * @retval None + */ +#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) + +/** + * @brief Checks whether the specified SDIO interrupt has occurred or not. + * @param __INSTANCE__ : Pointer to SDIO register base + * @param __INTERRUPT__: specifies the SDIO interrupt source to check. + * This parameter can be one of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt + * @retval The new state of SDIO_IT (SET or RESET). + */ +#define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Clears the SDIO's interrupt pending bits. + * @param __INSTANCE__ : Pointer to SDIO register base + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt + * @retval None + */ +#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) + +/** + * @brief Enable Start the SD I/O Read Wait operation. + * @param __INSTANCE__ : Pointer to SDIO register base + * @retval None + */ +#define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE) + +/** + * @brief Disable Start the SD I/O Read Wait operations. + * @param __INSTANCE__ : Pointer to SDIO register base + * @retval None + */ +#define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE) + +/** + * @brief Enable Start the SD I/O Read Wait operation. + * @param __INSTANCE__ : Pointer to SDIO register base + * @retval None + */ +#define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE) + +/** + * @brief Disable Stop the SD I/O Read Wait operations. + * @param __INSTANCE__ : Pointer to SDIO register base + * @retval None + */ +#define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE) + +/** + * @brief Enable the SD I/O Mode Operation. + * @param __INSTANCE__ : Pointer to SDIO register base + * @retval None + */ +#define __SDIO_OPERATION_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE) + +/** + * @brief Disable the SD I/O Mode Operation. + * @param __INSTANCE__ : Pointer to SDIO register base + * @retval None + */ +#define __SDIO_OPERATION_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE) + +/** + * @brief Enable the SD I/O Suspend command sending. + * @param __INSTANCE__ : Pointer to SDIO register base + * @retval None + */ +#define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE) + +/** + * @brief Disable the SD I/O Suspend command sending. + * @param __INSTANCE__ : Pointer to SDIO register base + * @retval None + */ +#define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE) + +#if defined(SDIO_CMD_CEATACMD) +/** + * @brief Enable the command completion signal. + * @retval None + */ +#define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE) + +/** + * @brief Disable the command completion signal. + * @retval None + */ +#define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE) + +/** + * @brief Enable the CE-ATA interrupt. + * @retval None + */ +#define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0U) + +/** + * @brief Disable the CE-ATA interrupt. + * @retval None + */ +#define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1U) + +/** + * @brief Enable send CE-ATA command (CMD61). + * @retval None + */ +#define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE) + +/** + * @brief Disable send CE-ATA command (CMD61). + * @retval None + */ +#define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE) + +#endif +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SDMMC_LL_Exported_Functions + * @{ + */ + +/* Initialization/de-initialization functions **********************************/ +/** @addtogroup HAL_SDMMC_LL_Group1 + * @{ + */ +HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init); +/** + * @} + */ + +/* I/O operation functions *****************************************************/ +/** @addtogroup HAL_SDMMC_LL_Group2 + * @{ + */ +uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx); +HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData); +/** + * @} + */ + +/* Peripheral Control functions ************************************************/ +/** @addtogroup HAL_SDMMC_LL_Group3 + * @{ + */ +HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx); +HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx); +uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx); + +/* Command path state machine (CPSM) management functions */ +HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command); +uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx); +uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response); + +/* Data path state machine (DPSM) management functions */ +HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data); +uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx); +uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx); + +/* SDMMC Cards mode management functions */ +HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode); +/** + * @} + */ + +/* SDMMC Commands management functions */ +/** @addtogroup HAL_SDMMC_LL_Group4 + * @{ + */ +uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize); +uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd); +uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd); +uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd); +uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd); +uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd); +uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd); +uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd); +uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd); +uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx); +uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx); +uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr); +uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx); +uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx); +uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument); +uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t Argument); +uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth); +uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx); +uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx); +uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument); +uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA); +uint32_t SDMMC_CmdSetRelAddMmc(SDIO_TypeDef *SDIOx, uint16_t RCA); +uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument); +uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx); +uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument); +uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument); +uint32_t SDMMC_CmdSendEXTCSD(SDIO_TypeDef *SDIOx, uint32_t Argument); +/** + * @} + */ + +/* SDMMC Responses management functions *****************************************/ +/** @addtogroup HAL_SDMMC_LL_Group5 + * @{ + */ +uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout); +uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx); +uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx); +uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA); +uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* SDIO */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F4xx_LL_SDMMC_H */ diff --git a/LICENSE b/LICENSE.md similarity index 100% rename from LICENSE rename to LICENSE.md diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2 2.h b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2 2.h new file mode 100644 index 0000000..0d3634d --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2 2.h @@ -0,0 +1,734 @@ +/* -------------------------------------------------------------------------- + * Portions Copyright © 2017 STMicroelectronics International N.V. All rights reserved. + * Portions Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * -------------------------------------------------------------------------- + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: cmsis_os2.h + * Purpose: CMSIS RTOS2 wrapper for FreeRTOS + * + *---------------------------------------------------------------------------*/ + +#ifndef CMSIS_OS2_H_ +#define CMSIS_OS2_H_ + +#ifndef __NO_RETURN +#if defined(__CC_ARM) +#define __NO_RETURN __declspec(noreturn) +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define __NO_RETURN __attribute__((__noreturn__)) +#elif defined(__GNUC__) +#define __NO_RETURN __attribute__((__noreturn__)) +#elif defined(__ICCARM__) +#define __NO_RETURN __noreturn +#else +#define __NO_RETURN +#endif +#endif + +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// ==== Enumerations, structures, defines ==== + +/// Version information. +typedef struct { + uint32_t api; ///< API version (major.minor.rev: mmnnnrrrr dec). + uint32_t kernel; ///< Kernel version (major.minor.rev: mmnnnrrrr dec). +} osVersion_t; + +/// Kernel state. +typedef enum { + osKernelInactive = 0, ///< Inactive. + osKernelReady = 1, ///< Ready. + osKernelRunning = 2, ///< Running. + osKernelLocked = 3, ///< Locked. + osKernelSuspended = 4, ///< Suspended. + osKernelError = -1, ///< Error. + osKernelReserved = 0x7FFFFFFFU ///< Prevents enum down-size compiler optimization. +} osKernelState_t; + +/// Thread state. +typedef enum { + osThreadInactive = 0, ///< Inactive. + osThreadReady = 1, ///< Ready. + osThreadRunning = 2, ///< Running. + osThreadBlocked = 3, ///< Blocked. + osThreadTerminated = 4, ///< Terminated. + osThreadError = -1, ///< Error. + osThreadReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osThreadState_t; + +/// Priority values. +typedef enum { + osPriorityNone = 0, ///< No priority (not initialized). + osPriorityIdle = 1, ///< Reserved for Idle thread. + osPriorityLow = 8, ///< Priority: low + osPriorityLow1 = 8+1, ///< Priority: low + 1 + osPriorityLow2 = 8+2, ///< Priority: low + 2 + osPriorityLow3 = 8+3, ///< Priority: low + 3 + osPriorityLow4 = 8+4, ///< Priority: low + 4 + osPriorityLow5 = 8+5, ///< Priority: low + 5 + osPriorityLow6 = 8+6, ///< Priority: low + 6 + osPriorityLow7 = 8+7, ///< Priority: low + 7 + osPriorityBelowNormal = 16, ///< Priority: below normal + osPriorityBelowNormal1 = 16+1, ///< Priority: below normal + 1 + osPriorityBelowNormal2 = 16+2, ///< Priority: below normal + 2 + osPriorityBelowNormal3 = 16+3, ///< Priority: below normal + 3 + osPriorityBelowNormal4 = 16+4, ///< Priority: below normal + 4 + osPriorityBelowNormal5 = 16+5, ///< Priority: below normal + 5 + osPriorityBelowNormal6 = 16+6, ///< Priority: below normal + 6 + osPriorityBelowNormal7 = 16+7, ///< Priority: below normal + 7 + osPriorityNormal = 24, ///< Priority: normal + osPriorityNormal1 = 24+1, ///< Priority: normal + 1 + osPriorityNormal2 = 24+2, ///< Priority: normal + 2 + osPriorityNormal3 = 24+3, ///< Priority: normal + 3 + osPriorityNormal4 = 24+4, ///< Priority: normal + 4 + osPriorityNormal5 = 24+5, ///< Priority: normal + 5 + osPriorityNormal6 = 24+6, ///< Priority: normal + 6 + osPriorityNormal7 = 24+7, ///< Priority: normal + 7 + osPriorityAboveNormal = 32, ///< Priority: above normal + osPriorityAboveNormal1 = 32+1, ///< Priority: above normal + 1 + osPriorityAboveNormal2 = 32+2, ///< Priority: above normal + 2 + osPriorityAboveNormal3 = 32+3, ///< Priority: above normal + 3 + osPriorityAboveNormal4 = 32+4, ///< Priority: above normal + 4 + osPriorityAboveNormal5 = 32+5, ///< Priority: above normal + 5 + osPriorityAboveNormal6 = 32+6, ///< Priority: above normal + 6 + osPriorityAboveNormal7 = 32+7, ///< Priority: above normal + 7 + osPriorityHigh = 40, ///< Priority: high + osPriorityHigh1 = 40+1, ///< Priority: high + 1 + osPriorityHigh2 = 40+2, ///< Priority: high + 2 + osPriorityHigh3 = 40+3, ///< Priority: high + 3 + osPriorityHigh4 = 40+4, ///< Priority: high + 4 + osPriorityHigh5 = 40+5, ///< Priority: high + 5 + osPriorityHigh6 = 40+6, ///< Priority: high + 6 + osPriorityHigh7 = 40+7, ///< Priority: high + 7 + osPriorityRealtime = 48, ///< Priority: realtime + osPriorityRealtime1 = 48+1, ///< Priority: realtime + 1 + osPriorityRealtime2 = 48+2, ///< Priority: realtime + 2 + osPriorityRealtime3 = 48+3, ///< Priority: realtime + 3 + osPriorityRealtime4 = 48+4, ///< Priority: realtime + 4 + osPriorityRealtime5 = 48+5, ///< Priority: realtime + 5 + osPriorityRealtime6 = 48+6, ///< Priority: realtime + 6 + osPriorityRealtime7 = 48+7, ///< Priority: realtime + 7 + osPriorityISR = 56, ///< Reserved for ISR deferred thread. + osPriorityError = -1, ///< System cannot determine priority or illegal priority. + osPriorityReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osPriority_t; + +/// Entry point of a thread. +typedef void (*osThreadFunc_t) (void *argument); + +/// Timer callback function. +typedef void (*osTimerFunc_t) (void *argument); + +/// Timer type. +typedef enum { + osTimerOnce = 0, ///< One-shot timer. + osTimerPeriodic = 1 ///< Repeating timer. +} osTimerType_t; + +// Timeout value. +#define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value. + +// Flags options (\ref osThreadFlagsWait and \ref osEventFlagsWait). +#define osFlagsWaitAny 0x00000000U ///< Wait for any flag (default). +#define osFlagsWaitAll 0x00000001U ///< Wait for all flags. +#define osFlagsNoClear 0x00000002U ///< Do not clear flags which have been specified to wait for. + +// Flags errors (returned by osThreadFlagsXxxx and osEventFlagsXxxx). +#define osFlagsError 0x80000000U ///< Error indicator. +#define osFlagsErrorUnknown 0xFFFFFFFFU ///< osError (-1). +#define osFlagsErrorTimeout 0xFFFFFFFEU ///< osErrorTimeout (-2). +#define osFlagsErrorResource 0xFFFFFFFDU ///< osErrorResource (-3). +#define osFlagsErrorParameter 0xFFFFFFFCU ///< osErrorParameter (-4). +#define osFlagsErrorISR 0xFFFFFFFAU ///< osErrorISR (-6). + +// Thread attributes (attr_bits in \ref osThreadAttr_t). +#define osThreadDetached 0x00000000U ///< Thread created in detached mode (default) +#define osThreadJoinable 0x00000001U ///< Thread created in joinable mode + +// Mutex attributes (attr_bits in \ref osMutexAttr_t). +#define osMutexRecursive 0x00000001U ///< Recursive mutex. +#define osMutexPrioInherit 0x00000002U ///< Priority inherit protocol. +#define osMutexRobust 0x00000008U ///< Robust mutex. + +/// Status code values returned by CMSIS-RTOS functions. +typedef enum { + osOK = 0, ///< Operation completed successfully. + osError = -1, ///< Unspecified RTOS error: run-time error but no other error message fits. + osErrorTimeout = -2, ///< Operation not completed within the timeout period. + osErrorResource = -3, ///< Resource not available. + osErrorParameter = -4, ///< Parameter error. + osErrorNoMemory = -5, ///< System is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorISR = -6, ///< Not allowed in ISR context: the function cannot be called from interrupt service routines. + osStatusReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osStatus_t; + + +/// \details Thread ID identifies the thread. +typedef void *osThreadId_t; + +/// \details Timer ID identifies the timer. +typedef void *osTimerId_t; + +/// \details Event Flags ID identifies the event flags. +typedef void *osEventFlagsId_t; + +/// \details Mutex ID identifies the mutex. +typedef void *osMutexId_t; + +/// \details Semaphore ID identifies the semaphore. +typedef void *osSemaphoreId_t; + +/// \details Memory Pool ID identifies the memory pool. +typedef void *osMemoryPoolId_t; + +/// \details Message Queue ID identifies the message queue. +typedef void *osMessageQueueId_t; + + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + + +/// Attributes structure for thread. +typedef struct { + const char *name; ///< name of the thread + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *stack_mem; ///< memory for stack + uint32_t stack_size; ///< size of stack + osPriority_t priority; ///< initial thread priority (default: osPriorityNormal) + TZ_ModuleId_t tz_module; ///< TrustZone module identifier + uint32_t reserved; ///< reserved (must be 0) +} osThreadAttr_t; + +/// Attributes structure for timer. +typedef struct { + const char *name; ///< name of the timer + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osTimerAttr_t; + +/// Attributes structure for event flags. +typedef struct { + const char *name; ///< name of the event flags + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osEventFlagsAttr_t; + +/// Attributes structure for mutex. +typedef struct { + const char *name; ///< name of the mutex + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osMutexAttr_t; + +/// Attributes structure for semaphore. +typedef struct { + const char *name; ///< name of the semaphore + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osSemaphoreAttr_t; + +/// Attributes structure for memory pool. +typedef struct { + const char *name; ///< name of the memory pool + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *mp_mem; ///< memory for data storage + uint32_t mp_size; ///< size of provided memory for data storage +} osMemoryPoolAttr_t; + +/// Attributes structure for message queue. +typedef struct { + const char *name; ///< name of the message queue + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *mq_mem; ///< memory for data storage + uint32_t mq_size; ///< size of provided memory for data storage +} osMessageQueueAttr_t; + + +// ==== Kernel Management Functions ==== + +/// Initialize the RTOS Kernel. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelInitialize (void); + +/// Get RTOS Kernel Information. +/// \param[out] version pointer to buffer for retrieving version information. +/// \param[out] id_buf pointer to buffer for retrieving kernel identification string. +/// \param[in] id_size size of buffer for kernel identification string. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size); + +/// Get the current RTOS Kernel state. +/// \return current RTOS Kernel state. +osKernelState_t osKernelGetState (void); + +/// Start the RTOS Kernel scheduler. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelStart (void); + +/// Lock the RTOS Kernel scheduler. +/// \return previous lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelLock (void); + +/// Unlock the RTOS Kernel scheduler. +/// \return previous lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelUnlock (void); + +/// Restore the RTOS Kernel scheduler lock state. +/// \param[in] lock lock state obtained by \ref osKernelLock or \ref osKernelUnlock. +/// \return new lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelRestoreLock (int32_t lock); + +/// Suspend the RTOS Kernel scheduler. +/// \return time in ticks, for how long the system can sleep or power-down. +uint32_t osKernelSuspend (void); + +/// Resume the RTOS Kernel scheduler. +/// \param[in] sleep_ticks time in ticks for how long the system was in sleep or power-down mode. +void osKernelResume (uint32_t sleep_ticks); + +/// Get the RTOS kernel tick count. +/// \return RTOS kernel current tick count. +uint32_t osKernelGetTickCount (void); + +/// Get the RTOS kernel tick frequency. +/// \return frequency of the kernel tick in hertz, i.e. kernel ticks per second. +uint32_t osKernelGetTickFreq (void); + +/// Get the RTOS kernel system timer count. +/// \return RTOS kernel current system timer count as 32-bit value. +uint32_t osKernelGetSysTimerCount (void); + +/// Get the RTOS kernel system timer frequency. +/// \return frequency of the system timer in hertz, i.e. timer ticks per second. +uint32_t osKernelGetSysTimerFreq (void); + + +// ==== Thread Management Functions ==== + +/// Create a thread and add it to Active Threads. +/// \param[in] func thread function. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \param[in] attr thread attributes; NULL: default values. +/// \return thread ID for reference by other functions or NULL in case of error. +osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr); + +/// Get name of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return name as NULL terminated string. +const char *osThreadGetName (osThreadId_t thread_id); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +osThreadId_t osThreadGetId (void); + +/// Get current thread state of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return current thread state of the specified thread. +osThreadState_t osThreadGetState (osThreadId_t thread_id); + +/// Get stack size of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return stack size in bytes. +uint32_t osThreadGetStackSize (osThreadId_t thread_id); + +/// Get available stack space of a thread based on stack watermark recording during execution. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return remaining stack space in bytes. +uint32_t osThreadGetStackSpace (osThreadId_t thread_id); + +/// Change priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority); + +/// Get current priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return current priority value of the specified thread. +osPriority_t osThreadGetPriority (osThreadId_t thread_id); + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadYield (void); + +/// Suspend execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadSuspend (osThreadId_t thread_id); + +/// Resume execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadResume (osThreadId_t thread_id); + +/// Detach a thread (thread storage can be reclaimed when thread terminates). +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadDetach (osThreadId_t thread_id); + +/// Wait for specified thread to terminate. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadJoin (osThreadId_t thread_id); + +/// Terminate execution of current running thread. +__NO_RETURN void osThreadExit (void); + +/// Terminate execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadTerminate (osThreadId_t thread_id); + +/// Get number of active threads. +/// \return number of active threads. +uint32_t osThreadGetCount (void); + +/// Enumerate active threads. +/// \param[out] thread_array pointer to array for retrieving thread IDs. +/// \param[in] array_items maximum number of items in array for retrieving thread IDs. +/// \return number of enumerated threads. +uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items); + + +// ==== Thread Flags Functions ==== + +/// Set the specified Thread Flags of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \param[in] flags specifies the flags of the thread that shall be set. +/// \return thread flags after setting or error code if highest bit set. +uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags); + +/// Clear the specified Thread Flags of current running thread. +/// \param[in] flags specifies the flags of the thread that shall be cleared. +/// \return thread flags before clearing or error code if highest bit set. +uint32_t osThreadFlagsClear (uint32_t flags); + +/// Get the current Thread Flags of current running thread. +/// \return current thread flags. +uint32_t osThreadFlagsGet (void); + +/// Wait for one or more Thread Flags of the current running thread to become signaled. +/// \param[in] flags specifies the flags to wait for. +/// \param[in] options specifies flags options (osFlagsXxxx). +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return thread flags before clearing or error code if highest bit set. +uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout); + + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay). +/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value +/// \return status code that indicates the execution status of the function. +osStatus_t osDelay (uint32_t ticks); + +/// Wait until specified time. +/// \param[in] ticks absolute time in ticks +/// \return status code that indicates the execution status of the function. +osStatus_t osDelayUntil (uint32_t ticks); + + +// ==== Timer Management Functions ==== + +/// Create and Initialize a timer. +/// \param[in] func function pointer to callback function. +/// \param[in] type \ref osTimerOnce for one-shot or \ref osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer callback function. +/// \param[in] attr timer attributes; NULL: default values. +/// \return timer ID for reference by other functions or NULL in case of error. +osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr); + +/// Get name of a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return name as NULL terminated string. +const char *osTimerGetName (osTimerId_t timer_id); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value of the timer. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks); + +/// Stop a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerStop (osTimerId_t timer_id); + +/// Check if a timer is running. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return 0 not running, 1 running. +uint32_t osTimerIsRunning (osTimerId_t timer_id); + +/// Delete a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerDelete (osTimerId_t timer_id); + + +// ==== Event Flags Management Functions ==== + +/// Create and Initialize an Event Flags object. +/// \param[in] attr event flags attributes; NULL: default values. +/// \return event flags ID for reference by other functions or NULL in case of error. +osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr); + +/// Get name of an Event Flags object. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return name as NULL terminated string. +const char *osEventFlagsGetName (osEventFlagsId_t ef_id); + +/// Set the specified Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags that shall be set. +/// \return event flags after setting or error code if highest bit set. +uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags); + +/// Clear the specified Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags that shall be cleared. +/// \return event flags before clearing or error code if highest bit set. +uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags); + +/// Get the current Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return current event flags. +uint32_t osEventFlagsGet (osEventFlagsId_t ef_id); + +/// Wait for one or more Event Flags to become signaled. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags to wait for. +/// \param[in] options specifies flags options (osFlagsXxxx). +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event flags before clearing or error code if highest bit set. +uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout); + +/// Delete an Event Flags object. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id); + + +// ==== Mutex Management Functions ==== + +/// Create and Initialize a Mutex object. +/// \param[in] attr mutex attributes; NULL: default values. +/// \return mutex ID for reference by other functions or NULL in case of error. +osMutexId_t osMutexNew (const osMutexAttr_t *attr); + +/// Get name of a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return name as NULL terminated string. +const char *osMutexGetName (osMutexId_t mutex_id); + +/// Acquire a Mutex or timeout if it is locked. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout); + +/// Release a Mutex that was acquired by \ref osMutexAcquire. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexRelease (osMutexId_t mutex_id); + +/// Get Thread which owns a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return thread ID of owner thread or NULL when mutex was not acquired. +osThreadId_t osMutexGetOwner (osMutexId_t mutex_id); + +/// Delete a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexDelete (osMutexId_t mutex_id); + + +// ==== Semaphore Management Functions ==== + +/// Create and Initialize a Semaphore object. +/// \param[in] max_count maximum number of available tokens. +/// \param[in] initial_count initial number of available tokens. +/// \param[in] attr semaphore attributes; NULL: default values. +/// \return semaphore ID for reference by other functions or NULL in case of error. +osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr); + +/// Get name of a Semaphore object. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return name as NULL terminated string. +const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id); + +/// Acquire a Semaphore token or timeout if no tokens are available. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout); + +/// Release a Semaphore token up to the initial maximum count. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id); + +/// Get current Semaphore token count. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return number of tokens available. +uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id); + +/// Delete a Semaphore object. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id); + + +// ==== Memory Pool Management Functions ==== + +/// Create and Initialize a Memory Pool object. +/// \param[in] block_count maximum number of memory blocks in memory pool. +/// \param[in] block_size memory block size in bytes. +/// \param[in] attr memory pool attributes; NULL: default values. +/// \return memory pool ID for reference by other functions or NULL in case of error. +osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr); + +/// Get name of a Memory Pool object. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return name as NULL terminated string. +const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id); + +/// Allocate a memory block from a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return address of the allocated memory block or NULL in case of no memory is available. +void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout); + +/// Return an allocated memory block back to a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \param[in] block address of the allocated memory block to be returned to the memory pool. +/// \return status code that indicates the execution status of the function. +osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block); + +/// Get maximum number of memory blocks in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return maximum number of memory blocks. +uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id); + +/// Get memory block size in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return memory block size in bytes. +uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id); + +/// Get number of memory blocks used in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return number of memory blocks used. +uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id); + +/// Get number of memory blocks available in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return number of memory blocks available. +uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id); + +/// Delete a Memory Pool object. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id); + + +// ==== Message Queue Management Functions ==== + +/// Create and Initialize a Message Queue object. +/// \param[in] msg_count maximum number of messages in queue. +/// \param[in] msg_size maximum message size in bytes. +/// \param[in] attr message queue attributes; NULL: default values. +/// \return message queue ID for reference by other functions or NULL in case of error. +osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr); + +/// Get name of a Message Queue object. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return name as NULL terminated string. +const char *osMessageQueueGetName (osMessageQueueId_t mq_id); + +/// Put a Message into a Queue or timeout if Queue is full. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \param[in] msg_ptr pointer to buffer with message to put into a queue. +/// \param[in] msg_prio message priority. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout); + +/// Get a Message from a Queue or timeout if Queue is empty. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \param[out] msg_ptr pointer to buffer for message to get from a queue. +/// \param[out] msg_prio pointer to buffer for message priority or NULL. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout); + +/// Get maximum number of messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return maximum number of messages. +uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id); + +/// Get maximum message size in a Memory Pool. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return maximum message size in bytes. +uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id); + +/// Get number of queued messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return number of queued messages. +uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id); + +/// Get number of available slots for messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return number of available slots for messages. +uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id); + +/// Reset a Message Queue to initial empty state. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id); + +/// Delete a Message Queue object. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id); + + +#ifdef __cplusplus +} +#endif + +#endif // CMSIS_OS2_H_ diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes 2.h b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes 2.h new file mode 100644 index 0000000..79a185b --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes 2.h @@ -0,0 +1,160 @@ +/* + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* + * When the MPU is used the standard (non MPU) API functions are mapped to + * equivalents that start "MPU_", the prototypes for which are defined in this + * header files. This will cause the application code to call the MPU_ version + * which wraps the non-MPU version with privilege promoting then demoting code, + * so the kernel code always runs will full privileges. + */ + + +#ifndef MPU_PROTOTYPES_H +#define MPU_PROTOTYPES_H + +/* MPU versions of tasks.h API functions. */ +BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskStartScheduler( void ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL; +TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL; +char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL; +TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) FREERTOS_SYSTEM_CALL; +void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL; +uint32_t MPU_ulTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +uint32_t MPU_ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskIncrementTick( void ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskMissedYield( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) FREERTOS_SYSTEM_CALL; + +/* MPU versions of queue.h API functions. */ +BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL; +QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL; +QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; + +/* MPU versions of timers.h API functions. */ +TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL; +TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) FREERTOS_SYSTEM_CALL; +void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerCreateTimerTask( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; + +/* MPU versions of event_group.h API functions. */ +EventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL; +EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup ) FREERTOS_SYSTEM_CALL; + +/* MPU versions of message/stream_buffer.h API functions. */ +size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL; +StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ) FREERTOS_SYSTEM_CALL; +StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) FREERTOS_SYSTEM_CALL; + + + +#endif /* MPU_PROTOTYPES_H */ + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/portable 2.h b/Middlewares/Third_Party/FreeRTOS/Source/include/portable 2.h new file mode 100644 index 0000000..47ceab9 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/portable 2.h @@ -0,0 +1,199 @@ +/* + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/*----------------------------------------------------------- + * Portable layer API. Each function must be defined for each port. + *----------------------------------------------------------*/ + +#ifndef PORTABLE_H +#define PORTABLE_H + +/* Each FreeRTOS port has a unique portmacro.h header file. Originally a +pre-processor definition was used to ensure the pre-processor found the correct +portmacro.h file for the port being used. That scheme was deprecated in favour +of setting the compiler's include path such that it found the correct +portmacro.h file - removing the need for the constant and allowing the +portmacro.h file to be located anywhere in relation to the port being used. +Purely for reasons of backward compatibility the old method is still valid, but +to make it clear that new projects should not use it, support for the port +specific constants has been moved into the deprecated_definitions.h header +file. */ +#include "deprecated_definitions.h" + +/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h +did not result in a portmacro.h header file being included - and it should be +included here. In this case the path to the correct portmacro.h header file +must be set in the compiler's include path. */ +#ifndef portENTER_CRITICAL + #include "portmacro.h" +#endif + +#if portBYTE_ALIGNMENT == 32 + #define portBYTE_ALIGNMENT_MASK ( 0x001f ) +#endif + +#if portBYTE_ALIGNMENT == 16 + #define portBYTE_ALIGNMENT_MASK ( 0x000f ) +#endif + +#if portBYTE_ALIGNMENT == 8 + #define portBYTE_ALIGNMENT_MASK ( 0x0007 ) +#endif + +#if portBYTE_ALIGNMENT == 4 + #define portBYTE_ALIGNMENT_MASK ( 0x0003 ) +#endif + +#if portBYTE_ALIGNMENT == 2 + #define portBYTE_ALIGNMENT_MASK ( 0x0001 ) +#endif + +#if portBYTE_ALIGNMENT == 1 + #define portBYTE_ALIGNMENT_MASK ( 0x0000 ) +#endif + +#ifndef portBYTE_ALIGNMENT_MASK + #error "Invalid portBYTE_ALIGNMENT definition" +#endif + +#ifndef portNUM_CONFIGURABLE_REGIONS + #define portNUM_CONFIGURABLE_REGIONS 1 +#endif + +#ifndef portHAS_STACK_OVERFLOW_CHECKING + #define portHAS_STACK_OVERFLOW_CHECKING 0 +#endif + +#ifndef portARCH_NAME + #define portARCH_NAME NULL +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#include "mpu_wrappers.h" + +/* + * Setup the stack of a new task so it is ready to be placed under the + * scheduler control. The registers have to be placed on the stack in + * the order that the port expects to find them. + * + */ +#if( portUSING_MPU_WRAPPERS == 1 ) + #if( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION; + #else + StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION; + #endif +#else + #if( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION; + #else + StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION; + #endif +#endif + +/* Used by heap_5.c to define the start address and size of each memory region +that together comprise the total FreeRTOS heap space. */ +typedef struct HeapRegion +{ + uint8_t *pucStartAddress; + size_t xSizeInBytes; +} HeapRegion_t; + +/* Used to pass information about the heap out of vPortGetHeapStats(). */ +typedef struct xHeapStats +{ + size_t xAvailableHeapSpaceInBytes; /* The total heap size currently available - this is the sum of all the free blocks, not the largest block that can be allocated. */ + size_t xSizeOfLargestFreeBlockInBytes; /* The maximum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */ + size_t xSizeOfSmallestFreeBlockInBytes; /* The minimum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */ + size_t xNumberOfFreeBlocks; /* The number of free memory blocks within the heap at the time vPortGetHeapStats() is called. */ + size_t xMinimumEverFreeBytesRemaining; /* The minimum amount of total free memory (sum of all free blocks) there has been in the heap since the system booted. */ + size_t xNumberOfSuccessfulAllocations; /* The number of calls to pvPortMalloc() that have returned a valid memory block. */ + size_t xNumberOfSuccessfulFrees; /* The number of calls to vPortFree() that has successfully freed a block of memory. */ +} HeapStats_t; + +/* + * Used to define multiple heap regions for use by heap_5.c. This function + * must be called before any calls to pvPortMalloc() - not creating a task, + * queue, semaphore, mutex, software timer, event group, etc. will result in + * pvPortMalloc being called. + * + * pxHeapRegions passes in an array of HeapRegion_t structures - each of which + * defines a region of memory that can be used as the heap. The array is + * terminated by a HeapRegions_t structure that has a size of 0. The region + * with the lowest start address must appear first in the array. + */ +void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION; + +/* + * Returns a HeapStats_t structure filled with information about the current + * heap state. + */ +void vPortGetHeapStats( HeapStats_t *pxHeapStats ); + +/* + * Map to the memory management routines required for the port. + */ +void *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION; +void vPortFree( void *pv ) PRIVILEGED_FUNCTION; +void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION; +size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION; +size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION; + +/* + * Setup the hardware ready for the scheduler to take control. This generally + * sets up a tick interrupt and sets timers for the correct tick frequency. + */ +BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION; + +/* + * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so + * the hardware is left in its original condition after the scheduler stops + * executing. + */ +void vPortEndScheduler( void ) PRIVILEGED_FUNCTION; + +/* + * The structures and methods of manipulating the MPU are contained within the + * port layer. + * + * Fills the xMPUSettings structure with the memory region information + * contained in xRegions. + */ +#if( portUSING_MPU_WRAPPERS == 1 ) + struct xMEMORY_REGION; + void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth ) PRIVILEGED_FUNCTION; +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* PORTABLE_H */ + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/queue 2.h b/Middlewares/Third_Party/FreeRTOS/Source/include/queue 2.h new file mode 100644 index 0000000..fb82315 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/queue 2.h @@ -0,0 +1,1655 @@ +/* + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef QUEUE_H +#define QUEUE_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h" must appear in source files before "include queue.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#include "task.h" + +/** + * Type by which queues are referenced. For example, a call to xQueueCreate() + * returns an QueueHandle_t variable that can then be used as a parameter to + * xQueueSend(), xQueueReceive(), etc. + */ +struct QueueDefinition; /* Using old naming convention so as not to break kernel aware debuggers. */ +typedef struct QueueDefinition * QueueHandle_t; + +/** + * Type by which queue sets are referenced. For example, a call to + * xQueueCreateSet() returns an xQueueSet variable that can then be used as a + * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc. + */ +typedef struct QueueDefinition * QueueSetHandle_t; + +/** + * Queue sets can contain both queues and semaphores, so the + * QueueSetMemberHandle_t is defined as a type to be used where a parameter or + * return value can be either an QueueHandle_t or an SemaphoreHandle_t. + */ +typedef struct QueueDefinition * QueueSetMemberHandle_t; + +/* For internal use only. */ +#define queueSEND_TO_BACK ( ( BaseType_t ) 0 ) +#define queueSEND_TO_FRONT ( ( BaseType_t ) 1 ) +#define queueOVERWRITE ( ( BaseType_t ) 2 ) + +/* For internal use only. These definitions *must* match those in queue.c. */ +#define queueQUEUE_TYPE_BASE ( ( uint8_t ) 0U ) +#define queueQUEUE_TYPE_SET ( ( uint8_t ) 0U ) +#define queueQUEUE_TYPE_MUTEX ( ( uint8_t ) 1U ) +#define queueQUEUE_TYPE_COUNTING_SEMAPHORE ( ( uint8_t ) 2U ) +#define queueQUEUE_TYPE_BINARY_SEMAPHORE ( ( uint8_t ) 3U ) +#define queueQUEUE_TYPE_RECURSIVE_MUTEX ( ( uint8_t ) 4U ) + +/** + * queue. h + * 
+ QueueHandle_t xQueueCreate(
+							  UBaseType_t uxQueueLength,
+							  UBaseType_t uxItemSize
+						  );
+ *
+ * + * Creates a new queue instance, and returns a handle by which the new queue + * can be referenced. + * + * Internally, within the FreeRTOS implementation, queues use two blocks of + * memory. The first block is used to hold the queue's data structures. The + * second block is used to hold items placed into the queue. If a queue is + * created using xQueueCreate() then both blocks of memory are automatically + * dynamically allocated inside the xQueueCreate() function. (see + * http://www.freertos.org/a00111.html). If a queue is created using + * xQueueCreateStatic() then the application writer must provide the memory that + * will get used by the queue. xQueueCreateStatic() therefore allows a queue to + * be created without using any dynamic memory allocation. + * + * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html + * + * @param uxQueueLength The maximum number of items that the queue can contain. + * + * @param uxItemSize The number of bytes each item in the queue will require. + * Items are queued by copy, not by reference, so this is the number of bytes + * that will be copied for each posted item. Each item on the queue must be + * the same size. + * + * @return If the queue is successfully create then a handle to the newly + * created queue is returned. If the queue cannot be created then 0 is + * returned. + * + * Example usage: + 
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ };
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+	if( xQueue1 == 0 )
+	{
+		// Queue was not created and must not be used.
+	}
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue2 == 0 )
+	{
+		// Queue was not created and must not be used.
+	}
+
+	// ... Rest of task code.
+ }
+
+ * \defgroup xQueueCreate xQueueCreate + * \ingroup QueueManagement + */ +#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + #define xQueueCreate( uxQueueLength, uxItemSize ) xQueueGenericCreate( ( uxQueueLength ), ( uxItemSize ), ( queueQUEUE_TYPE_BASE ) ) +#endif + +/** + * queue. h + * 
+ QueueHandle_t xQueueCreateStatic(
+							  UBaseType_t uxQueueLength,
+							  UBaseType_t uxItemSize,
+							  uint8_t *pucQueueStorageBuffer,
+							  StaticQueue_t *pxQueueBuffer
+						  );
+ *
+ * + * Creates a new queue instance, and returns a handle by which the new queue + * can be referenced. + * + * Internally, within the FreeRTOS implementation, queues use two blocks of + * memory. The first block is used to hold the queue's data structures. The + * second block is used to hold items placed into the queue. If a queue is + * created using xQueueCreate() then both blocks of memory are automatically + * dynamically allocated inside the xQueueCreate() function. (see + * http://www.freertos.org/a00111.html). If a queue is created using + * xQueueCreateStatic() then the application writer must provide the memory that + * will get used by the queue. xQueueCreateStatic() therefore allows a queue to + * be created without using any dynamic memory allocation. + * + * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html + * + * @param uxQueueLength The maximum number of items that the queue can contain. + * + * @param uxItemSize The number of bytes each item in the queue will require. + * Items are queued by copy, not by reference, so this is the number of bytes + * that will be copied for each posted item. Each item on the queue must be + * the same size. + * + * @param pucQueueStorageBuffer If uxItemSize is not zero then + * pucQueueStorageBuffer must point to a uint8_t array that is at least large + * enough to hold the maximum number of items that can be in the queue at any + * one time - which is ( uxQueueLength * uxItemsSize ) bytes. If uxItemSize is + * zero then pucQueueStorageBuffer can be NULL. + * + * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which + * will be used to hold the queue's data structure. + * + * @return If the queue is created then a handle to the created queue is + * returned. If pxQueueBuffer is NULL then NULL is returned. + * + * Example usage: + 
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ };
+
+ #define QUEUE_LENGTH 10
+ #define ITEM_SIZE sizeof( uint32_t )
+
+ // xQueueBuffer will hold the queue structure.
+ StaticQueue_t xQueueBuffer;
+
+ // ucQueueStorage will hold the items posted to the queue.  Must be at least
+ // [(queue length) * ( queue item size)] bytes long.
+ uint8_t ucQueueStorage[ QUEUE_LENGTH * ITEM_SIZE ];
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( QUEUE_LENGTH, // The number of items the queue can hold.
+							ITEM_SIZE	  // The size of each item in the queue
+							&( ucQueueStorage[ 0 ] ), // The buffer that will hold the items in the queue.
+							&xQueueBuffer ); // The buffer that will hold the queue structure.
+
+	// The queue is guaranteed to be created successfully as no dynamic memory
+	// allocation is used.  Therefore xQueue1 is now a handle to a valid queue.
+
+	// ... Rest of task code.
+ }
+
+ * \defgroup xQueueCreateStatic xQueueCreateStatic + * \ingroup QueueManagement + */ +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + #define xQueueCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxQueueBuffer ) xQueueGenericCreateStatic( ( uxQueueLength ), ( uxItemSize ), ( pucQueueStorage ), ( pxQueueBuffer ), ( queueQUEUE_TYPE_BASE ) ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * queue. h + * 
+ BaseType_t xQueueSendToToFront(
+								   QueueHandle_t	xQueue,
+								   const void		*pvItemToQueue,
+								   TickType_t		xTicksToWait
+							   );
+ *
+ * + * Post an item to the front of a queue. The item is queued by copy, not by + * reference. This function must not be called from an interrupt service + * routine. See xQueueSendFromISR () for an alternative which may be used + * in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0 and the + * queue is full. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * + * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + 
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+
+ * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT ) + +/** + * queue. h + * 
+ BaseType_t xQueueSendToBack(
+								   QueueHandle_t	xQueue,
+								   const void		*pvItemToQueue,
+								   TickType_t		xTicksToWait
+							   );
+ *
+ * + * This is a macro that calls xQueueGenericSend(). + * + * Post an item to the back of a queue. The item is queued by copy, not by + * reference. This function must not be called from an interrupt service + * routine. See xQueueSendFromISR () for an alternative which may be used + * in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0 and the queue + * is full. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * + * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + 
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+
+ * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK ) + +/** + * queue. h + * 
+ BaseType_t xQueueSend(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue,
+							  TickType_t xTicksToWait
+						 );
+ *
+ * + * This is a macro that calls xQueueGenericSend(). It is included for + * backward compatibility with versions of FreeRTOS.org that did not + * include the xQueueSendToFront() and xQueueSendToBack() macros. It is + * equivalent to xQueueSendToBack(). + * + * Post an item on a queue. The item is queued by copy, not by reference. + * This function must not be called from an interrupt service routine. + * See xQueueSendFromISR () for an alternative which may be used in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0 and the + * queue is full. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * + * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + 
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+
+ * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK ) + +/** + * queue. h + * 
+ BaseType_t xQueueOverwrite(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue
+						 );
+ *
+ * + * Only for use with queues that have a length of one - so the queue is either + * empty or full. + * + * Post an item on a queue. If the queue is already full then overwrite the + * value held in the queue. The item is queued by copy, not by reference. + * + * This function must not be called from an interrupt service routine. + * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR. + * + * @param xQueue The handle of the queue to which the data is being sent. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and + * therefore has the same return values as xQueueSendToFront(). However, pdPASS + * is the only value that can be returned because xQueueOverwrite() will write + * to the queue even when the queue is already full. + * + * Example usage: + 
+
+ void vFunction( void *pvParameters )
+ {
+ QueueHandle_t xQueue;
+ uint32_t ulVarToSend, ulValReceived;
+
+	// Create a queue to hold one uint32_t value.  It is strongly
+	// recommended *not* to use xQueueOverwrite() on queues that can
+	// contain more than one value, and doing so will trigger an assertion
+	// if configASSERT() is defined.
+	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+
+	// Write the value 10 to the queue using xQueueOverwrite().
+	ulVarToSend = 10;
+	xQueueOverwrite( xQueue, &ulVarToSend );
+
+	// Peeking the queue should now return 10, but leave the value 10 in
+	// the queue.  A block time of zero is used as it is known that the
+	// queue holds a value.
+	ulValReceived = 0;
+	xQueuePeek( xQueue, &ulValReceived, 0 );
+
+	if( ulValReceived != 10 )
+	{
+		// Error unless the item was removed by a different task.
+	}
+
+	// The queue is still full.  Use xQueueOverwrite() to overwrite the
+	// value held in the queue with 100.
+	ulVarToSend = 100;
+	xQueueOverwrite( xQueue, &ulVarToSend );
+
+	// This time read from the queue, leaving the queue empty once more.
+	// A block time of 0 is used again.
+	xQueueReceive( xQueue, &ulValReceived, 0 );
+
+	// The value read should be the last value written, even though the
+	// queue was already full when the value was written.
+	if( ulValReceived != 100 )
+	{
+		// Error!
+	}
+
+	// ...
+}
+
+ * \defgroup xQueueOverwrite xQueueOverwrite + * \ingroup QueueManagement + */ +#define xQueueOverwrite( xQueue, pvItemToQueue ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE ) + + +/** + * queue. h + * 
+ BaseType_t xQueueGenericSend(
+									QueueHandle_t xQueue,
+									const void * pvItemToQueue,
+									TickType_t xTicksToWait
+									BaseType_t xCopyPosition
+								);
+ *
+ * + * It is preferred that the macros xQueueSend(), xQueueSendToFront() and + * xQueueSendToBack() are used in place of calling this function directly. + * + * Post an item on a queue. The item is queued by copy, not by reference. + * This function must not be called from an interrupt service routine. + * See xQueueSendFromISR () for an alternative which may be used in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0 and the + * queue is full. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * + * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the + * item at the back of the queue, or queueSEND_TO_FRONT to place the item + * at the front of the queue (for high priority messages). + * + * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + 
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );
+	}
+
+	// ... Rest of task code.
+ }
+
+ * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
+ BaseType_t xQueuePeek(
+							 QueueHandle_t xQueue,
+							 void * const pvBuffer,
+							 TickType_t xTicksToWait
+						 );
+ * + * Receive an item from a queue without removing the item from the queue. + * The item is received by copy so a buffer of adequate size must be + * provided. The number of bytes copied into the buffer was defined when + * the queue was created. + * + * Successfully received items remain on the queue so will be returned again + * by the next call, or a call to xQueueReceive(). + * + * This macro must not be used in an interrupt service routine. See + * xQueuePeekFromISR() for an alternative that can be called from an interrupt + * service routine. + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for an item to receive should the queue be empty at the time + * of the call. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue + * is empty. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * Example usage: + 
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Send a pointer to a struct AMessage object.  Don't block if the
+	// queue is already full.
+	pxMessage = & xMessage;
+	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to peek the data from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+	if( xQueue != 0 )
+	{
+		// Peek a message on the created queue.  Block for 10 ticks if a
+		// message is not immediately available.
+		if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+		{
+			// pcRxedMessage now points to the struct AMessage variable posted
+			// by vATask, but the item still remains on the queue.
+		}
+	}
+
+	// ... Rest of task code.
+ }
+
+ * \defgroup xQueuePeek xQueuePeek + * \ingroup QueueManagement + */ +BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
+ BaseType_t xQueuePeekFromISR(
+									QueueHandle_t xQueue,
+									void *pvBuffer,
+								);
+ * + * A version of xQueuePeek() that can be called from an interrupt service + * routine (ISR). + * + * Receive an item from a queue without removing the item from the queue. + * The item is received by copy so a buffer of adequate size must be + * provided. The number of bytes copied into the buffer was defined when + * the queue was created. + * + * Successfully received items remain on the queue so will be returned again + * by the next call, or a call to xQueueReceive(). + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * \defgroup xQueuePeekFromISR xQueuePeekFromISR + * \ingroup QueueManagement + */ +BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
+ BaseType_t xQueueReceive(
+								 QueueHandle_t xQueue,
+								 void *pvBuffer,
+								 TickType_t xTicksToWait
+							);
+ * + * Receive an item from a queue. The item is received by copy so a buffer of + * adequate size must be provided. The number of bytes copied into the buffer + * was defined when the queue was created. + * + * Successfully received items are removed from the queue. + * + * This function must not be used in an interrupt service routine. See + * xQueueReceiveFromISR for an alternative that can. + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for an item to receive should the queue be empty at the time + * of the call. xQueueReceive() will return immediately if xTicksToWait + * is zero and the queue is empty. The time is defined in tick periods so the + * constant portTICK_PERIOD_MS should be used to convert to real time if this is + * required. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * Example usage: + 
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Send a pointer to a struct AMessage object.  Don't block if the
+	// queue is already full.
+	pxMessage = & xMessage;
+	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to receive from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+	if( xQueue != 0 )
+	{
+		// Receive a message on the created queue.  Block for 10 ticks if a
+		// message is not immediately available.
+		if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+		{
+			// pcRxedMessage now points to the struct AMessage variable posted
+			// by vATask.
+		}
+	}
+
+	// ... Rest of task code.
+ }
+
+ * \defgroup xQueueReceive xQueueReceive + * \ingroup QueueManagement + */ +BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue );
+ * + * Return the number of messages stored in a queue. + * + * @param xQueue A handle to the queue being queried. + * + * @return The number of messages available in the queue. + * + * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting + * \ingroup QueueManagement + */ +UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue );
+ * + * Return the number of free spaces available in a queue. This is equal to the + * number of items that can be sent to the queue before the queue becomes full + * if no items are removed. + * + * @param xQueue A handle to the queue being queried. + * + * @return The number of spaces available in the queue. + * + * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting + * \ingroup QueueManagement + */ +UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
void vQueueDelete( QueueHandle_t xQueue );
+ * + * Delete a queue - freeing all the memory allocated for storing of items + * placed on the queue. + * + * @param xQueue A handle to the queue to be deleted. + * + * \defgroup vQueueDelete vQueueDelete + * \ingroup QueueManagement + */ +void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
+ BaseType_t xQueueSendToFrontFromISR(
+										 QueueHandle_t xQueue,
+										 const void *pvItemToQueue,
+										 BaseType_t *pxHigherPriorityTaskWoken
+									  );
+
+ * + * This is a macro that calls xQueueGenericSendFromISR(). + * + * Post an item to the front of a queue. It is safe to use this macro from + * within an interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueSendToFromFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the data was successfully sent to the queue, otherwise + * errQUEUE_FULL. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + 
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPrioritTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		taskYIELD ();
+	}
+ }
+
+ * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT ) + + +/** + * queue. h + * 
+ BaseType_t xQueueSendToBackFromISR(
+										 QueueHandle_t xQueue,
+										 const void *pvItemToQueue,
+										 BaseType_t *pxHigherPriorityTaskWoken
+									  );
+
+ * + * This is a macro that calls xQueueGenericSendFromISR(). + * + * Post an item to the back of a queue. It is safe to use this macro from + * within an interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueSendToBackFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the data was successfully sent to the queue, otherwise + * errQUEUE_FULL. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + 
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		taskYIELD ();
+	}
+ }
+
+ * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK ) + +/** + * queue. h + * 
+ BaseType_t xQueueOverwriteFromISR(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue,
+							  BaseType_t *pxHigherPriorityTaskWoken
+						 );
+ *
+ * + * A version of xQueueOverwrite() that can be used in an interrupt service + * routine (ISR). + * + * Only for use with queues that can hold a single item - so the queue is either + * empty or full. + * + * Post an item on a queue. If the queue is already full then overwrite the + * value held in the queue. The item is queued by copy, not by reference. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueOverwriteFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return xQueueOverwriteFromISR() is a macro that calls + * xQueueGenericSendFromISR(), and therefore has the same return values as + * xQueueSendToFrontFromISR(). However, pdPASS is the only value that can be + * returned because xQueueOverwriteFromISR() will write to the queue even when + * the queue is already full. + * + * Example usage: + 
+
+ QueueHandle_t xQueue;
+
+ void vFunction( void *pvParameters )
+ {
+ 	// Create a queue to hold one uint32_t value.  It is strongly
+	// recommended *not* to use xQueueOverwriteFromISR() on queues that can
+	// contain more than one value, and doing so will trigger an assertion
+	// if configASSERT() is defined.
+	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+}
+
+void vAnInterruptHandler( void )
+{
+// xHigherPriorityTaskWoken must be set to pdFALSE before it is used.
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+uint32_t ulVarToSend, ulValReceived;
+
+	// Write the value 10 to the queue using xQueueOverwriteFromISR().
+	ulVarToSend = 10;
+	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+	// The queue is full, but calling xQueueOverwriteFromISR() again will still
+	// pass because the value held in the queue will be overwritten with the
+	// new value.
+	ulVarToSend = 100;
+	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+	// Reading from the queue will now return 100.
+
+	// ...
+
+	if( xHigherPrioritytaskWoken == pdTRUE )
+	{
+		// Writing to the queue caused a task to unblock and the unblocked task
+		// has a priority higher than or equal to the priority of the currently
+		// executing task (the task this interrupt interrupted).  Perform a context
+		// switch so this interrupt returns directly to the unblocked task.
+		portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.
+	}
+}
+
+ * \defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR + * \ingroup QueueManagement + */ +#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE ) + +/** + * queue. h + * 
+ BaseType_t xQueueSendFromISR(
+									 QueueHandle_t xQueue,
+									 const void *pvItemToQueue,
+									 BaseType_t *pxHigherPriorityTaskWoken
+								);
+
+ * + * This is a macro that calls xQueueGenericSendFromISR(). It is included + * for backward compatibility with versions of FreeRTOS.org that did not + * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR() + * macros. + * + * Post an item to the back of a queue. It is safe to use this function from + * within an interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueSendFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the data was successfully sent to the queue, otherwise + * errQUEUE_FULL. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + 
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		// Actual macro used here is port specific.
+		portYIELD_FROM_ISR ();
+	}
+ }
+
+ * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK ) + +/** + * queue. h + * 
+ BaseType_t xQueueGenericSendFromISR(
+										   QueueHandle_t		xQueue,
+										   const	void	*pvItemToQueue,
+										   BaseType_t	*pxHigherPriorityTaskWoken,
+										   BaseType_t	xCopyPosition
+									   );
+
+ * + * It is preferred that the macros xQueueSendFromISR(), + * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place + * of calling this function directly. xQueueGiveFromISR() is an + * equivalent for use by semaphores that don't actually copy any data. + * + * Post an item on a queue. It is safe to use this function from within an + * interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueGenericSendFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the + * item at the back of the queue, or queueSEND_TO_FRONT to place the item + * at the front of the queue (for high priority messages). + * + * @return pdTRUE if the data was successfully sent to the queue, otherwise + * errQUEUE_FULL. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + 
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWokenByPost;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWokenByPost = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post each byte.
+		xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.  Note that the
+	// name of the yield function required is port specific.
+	if( xHigherPriorityTaskWokenByPost )
+	{
+		portYIELD_FROM_ISR();
+	}
+ }
+
+ * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION; +BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
+ BaseType_t xQueueReceiveFromISR(
+									   QueueHandle_t	xQueue,
+									   void	*pvBuffer,
+									   BaseType_t *pxTaskWoken
+								   );
+ *
+ * + * Receive an item from a queue. It is safe to use this function from within an + * interrupt service routine. + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @param pxTaskWoken A task may be blocked waiting for space to become + * available on the queue. If xQueueReceiveFromISR causes such a task to + * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will + * remain unchanged. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * Example usage: + 
+
+ QueueHandle_t xQueue;
+
+ // Function to create a queue and post some values.
+ void vAFunction( void *pvParameters )
+ {
+ char cValueToPost;
+ const TickType_t xTicksToWait = ( TickType_t )0xff;
+
+	// Create a queue capable of containing 10 characters.
+	xQueue = xQueueCreate( 10, sizeof( char ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Post some characters that will be used within an ISR.  If the queue
+	// is full then this task will block for xTicksToWait ticks.
+	cValueToPost = 'a';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+	cValueToPost = 'b';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+
+	// ... keep posting characters ... this task may block when the queue
+	// becomes full.
+
+	cValueToPost = 'c';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+ }
+
+ // ISR that outputs all the characters received on the queue.
+ void vISR_Routine( void )
+ {
+ BaseType_t xTaskWokenByReceive = pdFALSE;
+ char cRxedChar;
+
+	while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
+	{
+		// A character was received.  Output the character now.
+		vOutputCharacter( cRxedChar );
+
+		// If removing the character from the queue woke the task that was
+		// posting onto the queue cTaskWokenByReceive will have been set to
+		// pdTRUE.  No matter how many times this loop iterates only one
+		// task will be woken.
+	}
+
+	if( cTaskWokenByPost != ( char ) pdFALSE;
+	{
+		taskYIELD ();
+	}
+ }
+
+ * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR + * \ingroup QueueManagement + */ +BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/* + * Utilities to query queues that are safe to use from an ISR. These utilities + * should be used only from witin an ISR, or within a critical section. + */ +BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + +/* + * The functions defined above are for passing data to and from tasks. The + * functions below are the equivalents for passing data to and from + * co-routines. + * + * These functions are called from the co-routine macro implementation and + * should not be called directly from application code. Instead use the macro + * wrappers defined within croutine.h. + */ +BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken ); +BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxTaskWoken ); +BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait ); +BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait ); + +/* + * For internal use only. Use xSemaphoreCreateMutex(), + * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling + * these functions directly. + */ +QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION; +QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION; +QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION; +QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION; +BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION; +TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION; + +/* + * For internal use only. Use xSemaphoreTakeMutexRecursive() or + * xSemaphoreGiveMutexRecursive() instead of calling these functions directly. + */ +BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION; + +/* + * Reset a queue back to its original empty state. The return value is now + * obsolete and is always set to pdPASS. + */ +#define xQueueReset( xQueue ) xQueueGenericReset( xQueue, pdFALSE ) + +/* + * The registry is provided as a means for kernel aware debuggers to + * locate queues, semaphores and mutexes. Call vQueueAddToRegistry() add + * a queue, semaphore or mutex handle to the registry if you want the handle + * to be available to a kernel aware debugger. If you are not using a kernel + * aware debugger then this function can be ignored. + * + * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the + * registry can hold. configQUEUE_REGISTRY_SIZE must be greater than 0 + * within FreeRTOSConfig.h for the registry to be available. Its value + * does not effect the number of queues, semaphores and mutexes that can be + * created - just the number that the registry can hold. + * + * @param xQueue The handle of the queue being added to the registry. This + * is the handle returned by a call to xQueueCreate(). Semaphore and mutex + * handles can also be passed in here. + * + * @param pcName The name to be associated with the handle. This is the + * name that the kernel aware debugger will display. The queue registry only + * stores a pointer to the string - so the string must be persistent (global or + * preferably in ROM/Flash), not on the stack. + */ +#if( configQUEUE_REGISTRY_SIZE > 0 ) + void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ +#endif + +/* + * The registry is provided as a means for kernel aware debuggers to + * locate queues, semaphores and mutexes. Call vQueueAddToRegistry() add + * a queue, semaphore or mutex handle to the registry if you want the handle + * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to + * remove the queue, semaphore or mutex from the register. If you are not using + * a kernel aware debugger then this function can be ignored. + * + * @param xQueue The handle of the queue being removed from the registry. + */ +#if( configQUEUE_REGISTRY_SIZE > 0 ) + void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +#endif + +/* + * The queue registry is provided as a means for kernel aware debuggers to + * locate queues, semaphores and mutexes. Call pcQueueGetName() to look + * up and return the name of a queue in the queue registry from the queue's + * handle. + * + * @param xQueue The handle of the queue the name of which will be returned. + * @return If the queue is in the registry then a pointer to the name of the + * queue is returned. If the queue is not in the registry then NULL is + * returned. + */ +#if( configQUEUE_REGISTRY_SIZE > 0 ) + const char *pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ +#endif + +/* + * Generic version of the function used to creaet a queue using dynamic memory + * allocation. This is called by other functions and macros that create other + * RTOS objects that use the queue structure as their base. + */ +#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION; +#endif + +/* + * Generic version of the function used to creaet a queue using dynamic memory + * allocation. This is called by other functions and macros that create other + * RTOS objects that use the queue structure as their base. + */ +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION; +#endif + +/* + * Queue sets provide a mechanism to allow a task to block (pend) on a read + * operation from multiple queues or semaphores simultaneously. + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * A queue set must be explicitly created using a call to xQueueCreateSet() + * before it can be used. Once created, standard FreeRTOS queues and semaphores + * can be added to the set using calls to xQueueAddToSet(). + * xQueueSelectFromSet() is then used to determine which, if any, of the queues + * or semaphores contained in the set is in a state where a queue read or + * semaphore take operation would be successful. + * + * Note 1: See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html + * for reasons why queue sets are very rarely needed in practice as there are + * simpler methods of blocking on multiple objects. + * + * Note 2: Blocking on a queue set that contains a mutex will not cause the + * mutex holder to inherit the priority of the blocked task. + * + * Note 3: An additional 4 bytes of RAM is required for each space in a every + * queue added to a queue set. Therefore counting semaphores that have a high + * maximum count value should not be added to a queue set. + * + * Note 4: A receive (in the case of a queue) or take (in the case of a + * semaphore) operation must not be performed on a member of a queue set unless + * a call to xQueueSelectFromSet() has first returned a handle to that set member. + * + * @param uxEventQueueLength Queue sets store events that occur on + * the queues and semaphores contained in the set. uxEventQueueLength specifies + * the maximum number of events that can be queued at once. To be absolutely + * certain that events are not lost uxEventQueueLength should be set to the + * total sum of the length of the queues added to the set, where binary + * semaphores and mutexes have a length of 1, and counting semaphores have a + * length set by their maximum count value. Examples: + * + If a queue set is to hold a queue of length 5, another queue of length 12, + * and a binary semaphore, then uxEventQueueLength should be set to + * (5 + 12 + 1), or 18. + * + If a queue set is to hold three binary semaphores then uxEventQueueLength + * should be set to (1 + 1 + 1 ), or 3. + * + If a queue set is to hold a counting semaphore that has a maximum count of + * 5, and a counting semaphore that has a maximum count of 3, then + * uxEventQueueLength should be set to (5 + 3), or 8. + * + * @return If the queue set is created successfully then a handle to the created + * queue set is returned. Otherwise NULL is returned. + */ +QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION; + +/* + * Adds a queue or semaphore to a queue set that was previously created by a + * call to xQueueCreateSet(). + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * Note 1: A receive (in the case of a queue) or take (in the case of a + * semaphore) operation must not be performed on a member of a queue set unless + * a call to xQueueSelectFromSet() has first returned a handle to that set member. + * + * @param xQueueOrSemaphore The handle of the queue or semaphore being added to + * the queue set (cast to an QueueSetMemberHandle_t type). + * + * @param xQueueSet The handle of the queue set to which the queue or semaphore + * is being added. + * + * @return If the queue or semaphore was successfully added to the queue set + * then pdPASS is returned. If the queue could not be successfully added to the + * queue set because it is already a member of a different queue set then pdFAIL + * is returned. + */ +BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; + +/* + * Removes a queue or semaphore from a queue set. A queue or semaphore can only + * be removed from a set if the queue or semaphore is empty. + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * @param xQueueOrSemaphore The handle of the queue or semaphore being removed + * from the queue set (cast to an QueueSetMemberHandle_t type). + * + * @param xQueueSet The handle of the queue set in which the queue or semaphore + * is included. + * + * @return If the queue or semaphore was successfully removed from the queue set + * then pdPASS is returned. If the queue was not in the queue set, or the + * queue (or semaphore) was not empty, then pdFAIL is returned. + */ +BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; + +/* + * xQueueSelectFromSet() selects from the members of a queue set a queue or + * semaphore that either contains data (in the case of a queue) or is available + * to take (in the case of a semaphore). xQueueSelectFromSet() effectively + * allows a task to block (pend) on a read operation on all the queues and + * semaphores in a queue set simultaneously. + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * Note 1: See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html + * for reasons why queue sets are very rarely needed in practice as there are + * simpler methods of blocking on multiple objects. + * + * Note 2: Blocking on a queue set that contains a mutex will not cause the + * mutex holder to inherit the priority of the blocked task. + * + * Note 3: A receive (in the case of a queue) or take (in the case of a + * semaphore) operation must not be performed on a member of a queue set unless + * a call to xQueueSelectFromSet() has first returned a handle to that set member. + * + * @param xQueueSet The queue set on which the task will (potentially) block. + * + * @param xTicksToWait The maximum time, in ticks, that the calling task will + * remain in the Blocked state (with other tasks executing) to wait for a member + * of the queue set to be ready for a successful queue read or semaphore take + * operation. + * + * @return xQueueSelectFromSet() will return the handle of a queue (cast to + * a QueueSetMemberHandle_t type) contained in the queue set that contains data, + * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained + * in the queue set that is available, or NULL if no such queue or semaphore + * exists before before the specified block time expires. + */ +QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/* + * A version of xQueueSelectFromSet() that can be used from an ISR. + */ +QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; + +/* Not public API functions. */ +void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION; +BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) PRIVILEGED_FUNCTION; +void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION; +UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + + +#ifdef __cplusplus +} +#endif + +#endif /* QUEUE_H */ + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/semphr 2.h b/Middlewares/Third_Party/FreeRTOS/Source/include/semphr 2.h new file mode 100644 index 0000000..ff21a39 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/semphr 2.h @@ -0,0 +1,1140 @@ +/* + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef SEMAPHORE_H +#define SEMAPHORE_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h" must appear in source files before "include semphr.h" +#endif + +#include "queue.h" + +typedef QueueHandle_t SemaphoreHandle_t; + +#define semBINARY_SEMAPHORE_QUEUE_LENGTH ( ( uint8_t ) 1U ) +#define semSEMAPHORE_QUEUE_ITEM_LENGTH ( ( uint8_t ) 0U ) +#define semGIVE_BLOCK_TIME ( ( TickType_t ) 0U ) + + +/** + * semphr. h + * 
vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore )
+ * + * In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a binary semaphore! + * http://www.freertos.org/RTOS-task-notifications.html + * + * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the + * xSemaphoreCreateBinary() function. Note that binary semaphores created using + * the vSemaphoreCreateBinary() macro are created in a state such that the + * first call to 'take' the semaphore would pass, whereas binary semaphores + * created using xSemaphoreCreateBinary() are created in a state such that the + * the semaphore must first be 'given' before it can be 'taken'. + * + * Macro that implements a semaphore by using the existing queue mechanism. + * The queue length is 1 as this is a binary semaphore. The data size is 0 + * as we don't want to actually store any data - we just want to know if the + * queue is empty or full. + * + * This type of semaphore can be used for pure synchronisation between tasks or + * between an interrupt and a task. The semaphore need not be given back once + * obtained, so one task/interrupt can continuously 'give' the semaphore while + * another continuously 'takes' the semaphore. For this reason this type of + * semaphore does not use a priority inheritance mechanism. For an alternative + * that does use priority inheritance see xSemaphoreCreateMutex(). + * + * @param xSemaphore Handle to the created semaphore. Should be of type SemaphoreHandle_t. + * + * Example usage: + 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
+    // This is a macro so pass the variable in directly.
+    vSemaphoreCreateBinary( xSemaphore );
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+
+ * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary + * \ingroup Semaphores + */ +#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + #define vSemaphoreCreateBinary( xSemaphore ) \ + { \ + ( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE ); \ + if( ( xSemaphore ) != NULL ) \ + { \ + ( void ) xSemaphoreGive( ( xSemaphore ) ); \ + } \ + } +#endif + +/** + * semphr. h + * 
SemaphoreHandle_t xSemaphoreCreateBinary( void )
+ * + * Creates a new binary semaphore instance, and returns a handle by which the + * new semaphore can be referenced. + * + * In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a binary semaphore! + * http://www.freertos.org/RTOS-task-notifications.html + * + * Internally, within the FreeRTOS implementation, binary semaphores use a block + * of memory, in which the semaphore structure is stored. If a binary semaphore + * is created using xSemaphoreCreateBinary() then the required memory is + * automatically dynamically allocated inside the xSemaphoreCreateBinary() + * function. (see http://www.freertos.org/a00111.html). If a binary semaphore + * is created using xSemaphoreCreateBinaryStatic() then the application writer + * must provide the memory. xSemaphoreCreateBinaryStatic() therefore allows a + * binary semaphore to be created without using any dynamic memory allocation. + * + * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this + * xSemaphoreCreateBinary() function. Note that binary semaphores created using + * the vSemaphoreCreateBinary() macro are created in a state such that the + * first call to 'take' the semaphore would pass, whereas binary semaphores + * created using xSemaphoreCreateBinary() are created in a state such that the + * the semaphore must first be 'given' before it can be 'taken'. + * + * This type of semaphore can be used for pure synchronisation between tasks or + * between an interrupt and a task. The semaphore need not be given back once + * obtained, so one task/interrupt can continuously 'give' the semaphore while + * another continuously 'takes' the semaphore. For this reason this type of + * semaphore does not use a priority inheritance mechanism. For an alternative + * that does use priority inheritance see xSemaphoreCreateMutex(). + * + * @return Handle to the created semaphore, or NULL if the memory required to + * hold the semaphore's data structures could not be allocated. + * + * Example usage: + 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateBinary();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+
+ * \defgroup xSemaphoreCreateBinary xSemaphoreCreateBinary + * \ingroup Semaphores + */ +#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + #define xSemaphoreCreateBinary() xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE ) +#endif + +/** + * semphr. h + * 
SemaphoreHandle_t xSemaphoreCreateBinaryStatic( StaticSemaphore_t *pxSemaphoreBuffer )
+ * + * Creates a new binary semaphore instance, and returns a handle by which the + * new semaphore can be referenced. + * + * NOTE: In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a binary semaphore! + * http://www.freertos.org/RTOS-task-notifications.html + * + * Internally, within the FreeRTOS implementation, binary semaphores use a block + * of memory, in which the semaphore structure is stored. If a binary semaphore + * is created using xSemaphoreCreateBinary() then the required memory is + * automatically dynamically allocated inside the xSemaphoreCreateBinary() + * function. (see http://www.freertos.org/a00111.html). If a binary semaphore + * is created using xSemaphoreCreateBinaryStatic() then the application writer + * must provide the memory. xSemaphoreCreateBinaryStatic() therefore allows a + * binary semaphore to be created without using any dynamic memory allocation. + * + * This type of semaphore can be used for pure synchronisation between tasks or + * between an interrupt and a task. The semaphore need not be given back once + * obtained, so one task/interrupt can continuously 'give' the semaphore while + * another continuously 'takes' the semaphore. For this reason this type of + * semaphore does not use a priority inheritance mechanism. For an alternative + * that does use priority inheritance see xSemaphoreCreateMutex(). + * + * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t, + * which will then be used to hold the semaphore's data structure, removing the + * need for the memory to be allocated dynamically. + * + * @return If the semaphore is created then a handle to the created semaphore is + * returned. If pxSemaphoreBuffer is NULL then NULL is returned. + * + * Example usage: + 
+ SemaphoreHandle_t xSemaphore = NULL;
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+    // The semaphore's data structures will be placed in the xSemaphoreBuffer
+    // variable, the address of which is passed into the function.  The
+    // function's parameter is not NULL, so the function will not attempt any
+    // dynamic memory allocation, and therefore the function will not return
+    // return NULL.
+    xSemaphore = xSemaphoreCreateBinary( &xSemaphoreBuffer );
+
+    // Rest of task code goes here.
+ }
+
+ * \defgroup xSemaphoreCreateBinaryStatic xSemaphoreCreateBinaryStatic + * \ingroup Semaphores + */ +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + #define xSemaphoreCreateBinaryStatic( pxStaticSemaphore ) xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticSemaphore, queueQUEUE_TYPE_BINARY_SEMAPHORE ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * semphr. h + * 
xSemaphoreTake(
+ *                   SemaphoreHandle_t xSemaphore,
+ *                   TickType_t xBlockTime
+ *               )
+ * + * Macro to obtain a semaphore. The semaphore must have previously been + * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or + * xSemaphoreCreateCounting(). + * + * @param xSemaphore A handle to the semaphore being taken - obtained when + * the semaphore was created. + * + * @param xBlockTime The time in ticks to wait for the semaphore to become + * available. The macro portTICK_PERIOD_MS can be used to convert this to a + * real time. A block time of zero can be used to poll the semaphore. A block + * time of portMAX_DELAY can be used to block indefinitely (provided + * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h). + * + * @return pdTRUE if the semaphore was obtained. pdFALSE + * if xBlockTime expired without the semaphore becoming available. + * + * Example usage: + 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // A task that creates a semaphore.
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    xSemaphore = xSemaphoreCreateBinary();
+ }
+
+ // A task that uses the semaphore.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xSemaphore != NULL )
+    {
+        // See if we can obtain the semaphore.  If the semaphore is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the semaphore and can now access the
+            // shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource.  Release the
+            // semaphore.
+            xSemaphoreGive( xSemaphore );
+        }
+        else
+        {
+            // We could not obtain the semaphore and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+
+ * \defgroup xSemaphoreTake xSemaphoreTake + * \ingroup Semaphores + */ +#define xSemaphoreTake( xSemaphore, xBlockTime ) xQueueSemaphoreTake( ( xSemaphore ), ( xBlockTime ) ) + +/** + * semphr. h + * xSemaphoreTakeRecursive( + * SemaphoreHandle_t xMutex, + * TickType_t xBlockTime + * ) + * + * Macro to recursively obtain, or 'take', a mutex type semaphore. + * The mutex must have previously been created using a call to + * xSemaphoreCreateRecursiveMutex(); + * + * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this + * macro to be available. + * + * This macro must not be used on mutexes created using xSemaphoreCreateMutex(). + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * @param xMutex A handle to the mutex being obtained. This is the + * handle returned by xSemaphoreCreateRecursiveMutex(); + * + * @param xBlockTime The time in ticks to wait for the semaphore to become + * available. The macro portTICK_PERIOD_MS can be used to convert this to a + * real time. A block time of zero can be used to poll the semaphore. If + * the task already owns the semaphore then xSemaphoreTakeRecursive() will + * return immediately no matter what the value of xBlockTime. + * + * @return pdTRUE if the semaphore was obtained. pdFALSE if xBlockTime + * expired without the semaphore becoming available. + * + * Example usage: + 
+ SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+    // Create the mutex to guard a shared resource.
+    xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xMutex != NULL )
+    {
+        // See if we can obtain the mutex.  If the mutex is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the mutex and can now access the
+            // shared resource.
+
+            // ...
+            // For some reason due to the nature of the code further calls to
+            // xSemaphoreTakeRecursive() are made on the same mutex.  In real
+            // code these would not be just sequential calls as this would make
+            // no sense.  Instead the calls are likely to be buried inside
+            // a more complex call structure.
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+            // The mutex has now been 'taken' three times, so will not be
+            // available to another task until it has also been given back
+            // three times.  Again it is unlikely that real code would have
+            // these calls sequentially, but instead buried in a more complex
+            // call structure.  This is just for illustrative purposes.
+            xSemaphoreGiveRecursive( xMutex );
+            xSemaphoreGiveRecursive( xMutex );
+            xSemaphoreGiveRecursive( xMutex );
+
+            // Now the mutex can be taken by other tasks.
+        }
+        else
+        {
+            // We could not obtain the mutex and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+
+ * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive + * \ingroup Semaphores + */ +#if( configUSE_RECURSIVE_MUTEXES == 1 ) + #define xSemaphoreTakeRecursive( xMutex, xBlockTime ) xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) ) +#endif + +/** + * semphr. h + * 
xSemaphoreGive( SemaphoreHandle_t xSemaphore )
+ * + * Macro to release a semaphore. The semaphore must have previously been + * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or + * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake(). + * + * This macro must not be used from an ISR. See xSemaphoreGiveFromISR () for + * an alternative which can be used from an ISR. + * + * This macro must also not be used on semaphores created using + * xSemaphoreCreateRecursiveMutex(). + * + * @param xSemaphore A handle to the semaphore being released. This is the + * handle returned when the semaphore was created. + * + * @return pdTRUE if the semaphore was released. pdFALSE if an error occurred. + * Semaphores are implemented using queues. An error can occur if there is + * no space on the queue to post a message - indicating that the + * semaphore was not first obtained correctly. + * + * Example usage: + 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    xSemaphore = vSemaphoreCreateBinary();
+
+    if( xSemaphore != NULL )
+    {
+        if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+        {
+            // We would expect this call to fail because we cannot give
+            // a semaphore without first "taking" it!
+        }
+
+        // Obtain the semaphore - don't block if the semaphore is not
+        // immediately available.
+        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) )
+        {
+            // We now have the semaphore and can access the shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource so can free the
+            // semaphore.
+            if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+            {
+                // We would not expect this call to fail because we must have
+                // obtained the semaphore to get here.
+            }
+        }
+    }
+ }
+
+ * \defgroup xSemaphoreGive xSemaphoreGive + * \ingroup Semaphores + */ +#define xSemaphoreGive( xSemaphore ) xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK ) + +/** + * semphr. h + * 
xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex )
+ * + * Macro to recursively release, or 'give', a mutex type semaphore. + * The mutex must have previously been created using a call to + * xSemaphoreCreateRecursiveMutex(); + * + * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this + * macro to be available. + * + * This macro must not be used on mutexes created using xSemaphoreCreateMutex(). + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * @param xMutex A handle to the mutex being released, or 'given'. This is the + * handle returned by xSemaphoreCreateMutex(); + * + * @return pdTRUE if the semaphore was given. + * + * Example usage: + 
+ SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+    // Create the mutex to guard a shared resource.
+    xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xMutex != NULL )
+    {
+        // See if we can obtain the mutex.  If the mutex is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the mutex and can now access the
+            // shared resource.
+
+            // ...
+            // For some reason due to the nature of the code further calls to
+			// xSemaphoreTakeRecursive() are made on the same mutex.  In real
+			// code these would not be just sequential calls as this would make
+			// no sense.  Instead the calls are likely to be buried inside
+			// a more complex call structure.
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+            // The mutex has now been 'taken' three times, so will not be
+			// available to another task until it has also been given back
+			// three times.  Again it is unlikely that real code would have
+			// these calls sequentially, it would be more likely that the calls
+			// to xSemaphoreGiveRecursive() would be called as a call stack
+			// unwound.  This is just for demonstrative purposes.
+            xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+
+			// Now the mutex can be taken by other tasks.
+        }
+        else
+        {
+            // We could not obtain the mutex and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+
+ * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive + * \ingroup Semaphores + */ +#if( configUSE_RECURSIVE_MUTEXES == 1 ) + #define xSemaphoreGiveRecursive( xMutex ) xQueueGiveMutexRecursive( ( xMutex ) ) +#endif + +/** + * semphr. h + * 
+ xSemaphoreGiveFromISR(
+                          SemaphoreHandle_t xSemaphore,
+                          BaseType_t *pxHigherPriorityTaskWoken
+                      )
+ * + * Macro to release a semaphore. The semaphore must have previously been + * created with a call to xSemaphoreCreateBinary() or xSemaphoreCreateCounting(). + * + * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex()) + * must not be used with this macro. + * + * This macro can be used from an ISR. + * + * @param xSemaphore A handle to the semaphore being released. This is the + * handle returned when the semaphore was created. + * + * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xSemaphoreGiveFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL. + * + * Example usage: + 
+ \#define LONG_TIME 0xffff
+ \#define TICKS_TO_WAIT	10
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // Repetitive task.
+ void vATask( void * pvParameters )
+ {
+    for( ;; )
+    {
+        // We want this task to run every 10 ticks of a timer.  The semaphore
+        // was created before this task was started.
+
+        // Block waiting for the semaphore to become available.
+        if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
+        {
+            // It is time to execute.
+
+            // ...
+
+            // We have finished our task.  Return to the top of the loop where
+            // we will block on the semaphore until it is time to execute
+            // again.  Note when using the semaphore for synchronisation with an
+			// ISR in this manner there is no need to 'give' the semaphore back.
+        }
+    }
+ }
+
+ // Timer ISR
+ void vTimerISR( void * pvParameters )
+ {
+ static uint8_t ucLocalTickCount = 0;
+ static BaseType_t xHigherPriorityTaskWoken;
+
+    // A timer tick has occurred.
+
+    // ... Do other time functions.
+
+    // Is it time for vATask () to run?
+	xHigherPriorityTaskWoken = pdFALSE;
+    ucLocalTickCount++;
+    if( ucLocalTickCount >= TICKS_TO_WAIT )
+    {
+        // Unblock the task by releasing the semaphore.
+        xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );
+
+        // Reset the count so we release the semaphore again in 10 ticks time.
+        ucLocalTickCount = 0;
+    }
+
+    if( xHigherPriorityTaskWoken != pdFALSE )
+    {
+        // We can force a context switch here.  Context switching from an
+        // ISR uses port specific syntax.  Check the demo task for your port
+        // to find the syntax required.
+    }
+ }
+
+ * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR + * \ingroup Semaphores + */ +#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken ) xQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) ) + +/** + * semphr. h + * 
+ xSemaphoreTakeFromISR(
+                          SemaphoreHandle_t xSemaphore,
+                          BaseType_t *pxHigherPriorityTaskWoken
+                      )
+ * + * Macro to take a semaphore from an ISR. The semaphore must have + * previously been created with a call to xSemaphoreCreateBinary() or + * xSemaphoreCreateCounting(). + * + * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex()) + * must not be used with this macro. + * + * This macro can be used from an ISR, however taking a semaphore from an ISR + * is not a common operation. It is likely to only be useful when taking a + * counting semaphore when an interrupt is obtaining an object from a resource + * pool (when the semaphore count indicates the number of resources available). + * + * @param xSemaphore A handle to the semaphore being taken. This is the + * handle returned when the semaphore was created. + * + * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xSemaphoreTakeFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the semaphore was successfully taken, otherwise + * pdFALSE + */ +#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken ) xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) ) + +/** + * semphr. h + * 
SemaphoreHandle_t xSemaphoreCreateMutex( void )
+ * + * Creates a new mutex type semaphore instance, and returns a handle by which + * the new mutex can be referenced. + * + * Internally, within the FreeRTOS implementation, mutex semaphores use a block + * of memory, in which the mutex structure is stored. If a mutex is created + * using xSemaphoreCreateMutex() then the required memory is automatically + * dynamically allocated inside the xSemaphoreCreateMutex() function. (see + * http://www.freertos.org/a00111.html). If a mutex is created using + * xSemaphoreCreateMutexStatic() then the application writer must provided the + * memory. xSemaphoreCreateMutexStatic() therefore allows a mutex to be created + * without using any dynamic memory allocation. + * + * Mutexes created using this function can be accessed using the xSemaphoreTake() + * and xSemaphoreGive() macros. The xSemaphoreTakeRecursive() and + * xSemaphoreGiveRecursive() macros must not be used. + * + * This type of semaphore uses a priority inheritance mechanism so a task + * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the + * semaphore it is no longer required. + * + * Mutex type semaphores cannot be used from within interrupt service routines. + * + * See xSemaphoreCreateBinary() for an alternative implementation that can be + * used for pure synchronisation (where one task or interrupt always 'gives' the + * semaphore and another always 'takes' the semaphore) and from within interrupt + * service routines. + * + * @return If the mutex was successfully created then a handle to the created + * semaphore is returned. If there was not enough heap to allocate the mutex + * data structures then NULL is returned. + * + * Example usage: + 
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateMutex();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+
+ * \defgroup xSemaphoreCreateMutex xSemaphoreCreateMutex + * \ingroup Semaphores + */ +#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + #define xSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX ) +#endif + +/** + * semphr. h + * 
SemaphoreHandle_t xSemaphoreCreateMutexStatic( StaticSemaphore_t *pxMutexBuffer )
+ * + * Creates a new mutex type semaphore instance, and returns a handle by which + * the new mutex can be referenced. + * + * Internally, within the FreeRTOS implementation, mutex semaphores use a block + * of memory, in which the mutex structure is stored. If a mutex is created + * using xSemaphoreCreateMutex() then the required memory is automatically + * dynamically allocated inside the xSemaphoreCreateMutex() function. (see + * http://www.freertos.org/a00111.html). If a mutex is created using + * xSemaphoreCreateMutexStatic() then the application writer must provided the + * memory. xSemaphoreCreateMutexStatic() therefore allows a mutex to be created + * without using any dynamic memory allocation. + * + * Mutexes created using this function can be accessed using the xSemaphoreTake() + * and xSemaphoreGive() macros. The xSemaphoreTakeRecursive() and + * xSemaphoreGiveRecursive() macros must not be used. + * + * This type of semaphore uses a priority inheritance mechanism so a task + * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the + * semaphore it is no longer required. + * + * Mutex type semaphores cannot be used from within interrupt service routines. + * + * See xSemaphoreCreateBinary() for an alternative implementation that can be + * used for pure synchronisation (where one task or interrupt always 'gives' the + * semaphore and another always 'takes' the semaphore) and from within interrupt + * service routines. + * + * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t, + * which will be used to hold the mutex's data structure, removing the need for + * the memory to be allocated dynamically. + * + * @return If the mutex was successfully created then a handle to the created + * mutex is returned. If pxMutexBuffer was NULL then NULL is returned. + * + * Example usage: + 
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xMutexBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // A mutex cannot be used before it has been created.  xMutexBuffer is
+    // into xSemaphoreCreateMutexStatic() so no dynamic memory allocation is
+    // attempted.
+    xSemaphore = xSemaphoreCreateMutexStatic( &xMutexBuffer );
+
+    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+    // so there is no need to check it.
+ }
+
+ * \defgroup xSemaphoreCreateMutexStatic xSemaphoreCreateMutexStatic + * \ingroup Semaphores + */ + #if( configSUPPORT_STATIC_ALLOCATION == 1 ) + #define xSemaphoreCreateMutexStatic( pxMutexBuffer ) xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + + +/** + * semphr. h + * 
SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void )
+ * + * Creates a new recursive mutex type semaphore instance, and returns a handle + * by which the new recursive mutex can be referenced. + * + * Internally, within the FreeRTOS implementation, recursive mutexs use a block + * of memory, in which the mutex structure is stored. If a recursive mutex is + * created using xSemaphoreCreateRecursiveMutex() then the required memory is + * automatically dynamically allocated inside the + * xSemaphoreCreateRecursiveMutex() function. (see + * http://www.freertos.org/a00111.html). If a recursive mutex is created using + * xSemaphoreCreateRecursiveMutexStatic() then the application writer must + * provide the memory that will get used by the mutex. + * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to + * be created without using any dynamic memory allocation. + * + * Mutexes created using this macro can be accessed using the + * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros. The + * xSemaphoreTake() and xSemaphoreGive() macros must not be used. + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * This type of semaphore uses a priority inheritance mechanism so a task + * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the + * semaphore it is no longer required. + * + * Mutex type semaphores cannot be used from within interrupt service routines. + * + * See xSemaphoreCreateBinary() for an alternative implementation that can be + * used for pure synchronisation (where one task or interrupt always 'gives' the + * semaphore and another always 'takes' the semaphore) and from within interrupt + * service routines. + * + * @return xSemaphore Handle to the created mutex semaphore. Should be of type + * SemaphoreHandle_t. + * + * Example usage: + 
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateRecursiveMutex();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+
+ * \defgroup xSemaphoreCreateRecursiveMutex xSemaphoreCreateRecursiveMutex + * \ingroup Semaphores + */ +#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) ) + #define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX ) +#endif + +/** + * semphr. h + * 
SemaphoreHandle_t xSemaphoreCreateRecursiveMutexStatic( StaticSemaphore_t *pxMutexBuffer )
+ * + * Creates a new recursive mutex type semaphore instance, and returns a handle + * by which the new recursive mutex can be referenced. + * + * Internally, within the FreeRTOS implementation, recursive mutexs use a block + * of memory, in which the mutex structure is stored. If a recursive mutex is + * created using xSemaphoreCreateRecursiveMutex() then the required memory is + * automatically dynamically allocated inside the + * xSemaphoreCreateRecursiveMutex() function. (see + * http://www.freertos.org/a00111.html). If a recursive mutex is created using + * xSemaphoreCreateRecursiveMutexStatic() then the application writer must + * provide the memory that will get used by the mutex. + * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to + * be created without using any dynamic memory allocation. + * + * Mutexes created using this macro can be accessed using the + * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros. The + * xSemaphoreTake() and xSemaphoreGive() macros must not be used. + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * This type of semaphore uses a priority inheritance mechanism so a task + * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the + * semaphore it is no longer required. + * + * Mutex type semaphores cannot be used from within interrupt service routines. + * + * See xSemaphoreCreateBinary() for an alternative implementation that can be + * used for pure synchronisation (where one task or interrupt always 'gives' the + * semaphore and another always 'takes' the semaphore) and from within interrupt + * service routines. + * + * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t, + * which will then be used to hold the recursive mutex's data structure, + * removing the need for the memory to be allocated dynamically. + * + * @return If the recursive mutex was successfully created then a handle to the + * created recursive mutex is returned. If pxMutexBuffer was NULL then NULL is + * returned. + * + * Example usage: + 
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xMutexBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // A recursive semaphore cannot be used before it is created.  Here a
+    // recursive mutex is created using xSemaphoreCreateRecursiveMutexStatic().
+    // The address of xMutexBuffer is passed into the function, and will hold
+    // the mutexes data structures - so no dynamic memory allocation will be
+    // attempted.
+    xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xMutexBuffer );
+
+    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+    // so there is no need to check it.
+ }
+
+ * \defgroup xSemaphoreCreateRecursiveMutexStatic xSemaphoreCreateRecursiveMutexStatic + * \ingroup Semaphores + */ +#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) ) + #define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore ) xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, pxStaticSemaphore ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * semphr. h + * 
SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount )
+ * + * Creates a new counting semaphore instance, and returns a handle by which the + * new counting semaphore can be referenced. + * + * In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a counting semaphore! + * http://www.freertos.org/RTOS-task-notifications.html + * + * Internally, within the FreeRTOS implementation, counting semaphores use a + * block of memory, in which the counting semaphore structure is stored. If a + * counting semaphore is created using xSemaphoreCreateCounting() then the + * required memory is automatically dynamically allocated inside the + * xSemaphoreCreateCounting() function. (see + * http://www.freertos.org/a00111.html). If a counting semaphore is created + * using xSemaphoreCreateCountingStatic() then the application writer can + * instead optionally provide the memory that will get used by the counting + * semaphore. xSemaphoreCreateCountingStatic() therefore allows a counting + * semaphore to be created without using any dynamic memory allocation. + * + * Counting semaphores are typically used for two things: + * + * 1) Counting events. + * + * In this usage scenario an event handler will 'give' a semaphore each time + * an event occurs (incrementing the semaphore count value), and a handler + * task will 'take' a semaphore each time it processes an event + * (decrementing the semaphore count value). The count value is therefore + * the difference between the number of events that have occurred and the + * number that have been processed. In this case it is desirable for the + * initial count value to be zero. + * + * 2) Resource management. + * + * In this usage scenario the count value indicates the number of resources + * available. To obtain control of a resource a task must first obtain a + * semaphore - decrementing the semaphore count value. When the count value + * reaches zero there are no free resources. When a task finishes with the + * resource it 'gives' the semaphore back - incrementing the semaphore count + * value. In this case it is desirable for the initial count value to be + * equal to the maximum count value, indicating that all resources are free. + * + * @param uxMaxCount The maximum count value that can be reached. When the + * semaphore reaches this value it can no longer be 'given'. + * + * @param uxInitialCount The count value assigned to the semaphore when it is + * created. + * + * @return Handle to the created semaphore. Null if the semaphore could not be + * created. + * + * Example usage: + 
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+ SemaphoreHandle_t xSemaphore = NULL;
+
+    // Semaphore cannot be used before a call to xSemaphoreCreateCounting().
+    // The max value to which the semaphore can count should be 10, and the
+    // initial value assigned to the count should be 0.
+    xSemaphore = xSemaphoreCreateCounting( 10, 0 );
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+
+ * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting + * \ingroup Semaphores + */ +#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + #define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) ) +#endif + +/** + * semphr. h + * 
SemaphoreHandle_t xSemaphoreCreateCountingStatic( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount, StaticSemaphore_t *pxSemaphoreBuffer )
+ * + * Creates a new counting semaphore instance, and returns a handle by which the + * new counting semaphore can be referenced. + * + * In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a counting semaphore! + * http://www.freertos.org/RTOS-task-notifications.html + * + * Internally, within the FreeRTOS implementation, counting semaphores use a + * block of memory, in which the counting semaphore structure is stored. If a + * counting semaphore is created using xSemaphoreCreateCounting() then the + * required memory is automatically dynamically allocated inside the + * xSemaphoreCreateCounting() function. (see + * http://www.freertos.org/a00111.html). If a counting semaphore is created + * using xSemaphoreCreateCountingStatic() then the application writer must + * provide the memory. xSemaphoreCreateCountingStatic() therefore allows a + * counting semaphore to be created without using any dynamic memory allocation. + * + * Counting semaphores are typically used for two things: + * + * 1) Counting events. + * + * In this usage scenario an event handler will 'give' a semaphore each time + * an event occurs (incrementing the semaphore count value), and a handler + * task will 'take' a semaphore each time it processes an event + * (decrementing the semaphore count value). The count value is therefore + * the difference between the number of events that have occurred and the + * number that have been processed. In this case it is desirable for the + * initial count value to be zero. + * + * 2) Resource management. + * + * In this usage scenario the count value indicates the number of resources + * available. To obtain control of a resource a task must first obtain a + * semaphore - decrementing the semaphore count value. When the count value + * reaches zero there are no free resources. When a task finishes with the + * resource it 'gives' the semaphore back - incrementing the semaphore count + * value. In this case it is desirable for the initial count value to be + * equal to the maximum count value, indicating that all resources are free. + * + * @param uxMaxCount The maximum count value that can be reached. When the + * semaphore reaches this value it can no longer be 'given'. + * + * @param uxInitialCount The count value assigned to the semaphore when it is + * created. + * + * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t, + * which will then be used to hold the semaphore's data structure, removing the + * need for the memory to be allocated dynamically. + * + * @return If the counting semaphore was successfully created then a handle to + * the created counting semaphore is returned. If pxSemaphoreBuffer was NULL + * then NULL is returned. + * + * Example usage: + 
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ void vATask( void * pvParameters )
+ {
+ SemaphoreHandle_t xSemaphore = NULL;
+
+    // Counting semaphore cannot be used before they have been created.  Create
+    // a counting semaphore using xSemaphoreCreateCountingStatic().  The max
+    // value to which the semaphore can count is 10, and the initial value
+    // assigned to the count will be 0.  The address of xSemaphoreBuffer is
+    // passed in and will be used to hold the semaphore structure, so no dynamic
+    // memory allocation will be used.
+    xSemaphore = xSemaphoreCreateCounting( 10, 0, &xSemaphoreBuffer );
+
+    // No memory allocation was attempted so xSemaphore cannot be NULL, so there
+    // is no need to check its value.
+ }
+
+ * \defgroup xSemaphoreCreateCountingStatic xSemaphoreCreateCountingStatic + * \ingroup Semaphores + */ +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + #define xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, pxSemaphoreBuffer ) xQueueCreateCountingSemaphoreStatic( ( uxMaxCount ), ( uxInitialCount ), ( pxSemaphoreBuffer ) ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * semphr. h + * 
void vSemaphoreDelete( SemaphoreHandle_t xSemaphore );
+ * + * Delete a semaphore. This function must be used with care. For example, + * do not delete a mutex type semaphore if the mutex is held by a task. + * + * @param xSemaphore A handle to the semaphore to be deleted. + * + * \defgroup vSemaphoreDelete vSemaphoreDelete + * \ingroup Semaphores + */ +#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) ) + +/** + * semphr.h + * 
TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex );
+ * + * If xMutex is indeed a mutex type semaphore, return the current mutex holder. + * If xMutex is not a mutex type semaphore, or the mutex is available (not held + * by a task), return NULL. + * + * Note: This is a good way of determining if the calling task is the mutex + * holder, but not a good way of determining the identity of the mutex holder as + * the holder may change between the function exiting and the returned value + * being tested. + */ +#define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) ) + +/** + * semphr.h + * 
TaskHandle_t xSemaphoreGetMutexHolderFromISR( SemaphoreHandle_t xMutex );
+ * + * If xMutex is indeed a mutex type semaphore, return the current mutex holder. + * If xMutex is not a mutex type semaphore, or the mutex is available (not held + * by a task), return NULL. + * + */ +#define xSemaphoreGetMutexHolderFromISR( xSemaphore ) xQueueGetMutexHolderFromISR( ( xSemaphore ) ) + +/** + * semphr.h + * 
UBaseType_t uxSemaphoreGetCount( SemaphoreHandle_t xSemaphore );
+ * + * If the semaphore is a counting semaphore then uxSemaphoreGetCount() returns + * its current count value. If the semaphore is a binary semaphore then + * uxSemaphoreGetCount() returns 1 if the semaphore is available, and 0 if the + * semaphore is not available. + * + */ +#define uxSemaphoreGetCount( xSemaphore ) uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) ) + +#endif /* SEMAPHORE_H */ + + diff --git a/NOTICE.md b/NOTICE.md new file mode 100644 index 0000000..e6d3f7b --- /dev/null +++ b/NOTICE.md @@ -0,0 +1,15 @@ +# Third-Party Notices + +This project is built with open source components and includes third-party software: + +## 1. Original Application Code +- **Copyright (c) 2026 Erick Ahmed** +- **License:** [GNU General Public License v3.0](https://git.erickahmed.com/erickahmed/j1939_logger/src/branch/main/LICENSE.md) + +## 2. STM32F4 HAL Drivers +- **Copyright (c) 2016 STMicroelectronics** +- **License:** [BSD 3-Clause License](https://git.erickahmed.com/erickahmed/j1939_logger/src/branch/main/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt) + +## 3. STM32 CMSIS +- **Copyright (c) 2017 STMicroelectronics** +- **License:** [Apache License 2.0](https://git.erickahmed.com/erickahmed/j1939_logger/src/branch/main/Drivers/CMSIS/LICENSE.txt)