From 001b7886d64bd79c0bf6c7a74448f516409ad16c Mon Sep 17 00:00:00 2001
From: Erick <ahmederick00@gmail.com>
Date: Tue, 1 Mar 2022 23:35:40 +0100
Subject: [PATCH] testbench dump

---
 gates/testbench/and16_tb.v                  | 16 ++++++++++++++++
 gates/testbench/and_tb.v                    |  2 +-
 gates/testbench/{demux._tb.v => demux_tb.v} |  2 ++
 gates/testbench/{mux.v => mux_tb.v}         |  2 +-
 gates/testbench/nand_tb.v                   |  2 +-
 gates/testbench/nor_tb.v                    | 18 ++++++++++++++++++
 gates/testbench/not_tb.v                    |  2 +-
 gates/testbench/or_tb.v                     |  2 +-
 gates/testbench/xnor_tb.v                   | 18 ++++++++++++++++++
 gates/testbench/xor_tb.v                    | 18 ++++++++++++++++++
 10 files changed, 77 insertions(+), 5 deletions(-)
 create mode 100644 gates/testbench/and16_tb.v
 rename gates/testbench/{demux._tb.v => demux_tb.v} (95%)
 rename gates/testbench/{mux.v => mux_tb.v} (97%)
 create mode 100644 gates/testbench/nor_tb.v
 create mode 100644 gates/testbench/xnor_tb.v
 create mode 100644 gates/testbench/xor_tb.v

diff --git a/gates/testbench/and16_tb.v b/gates/testbench/and16_tb.v
new file mode 100644
index 0000000..92fd3ad
--- /dev/null
+++ b/gates/testbench/and16_tb.v
@@ -0,0 +1,16 @@
+include "predefined/and16.v"
+
+module and_tb();
+    reg ta,tb;
+    wire ty;
+    and_gate dut(y, ta, tb);
+        initial begin
+            ta = 0'b16;
+            tb = 0'b16;
+            i=0
+            for(i<=15, i=i+1)
+                $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+                ta = ta+1;
+                tb = tb+1;
+        end
+endmodule
\ No newline at end of file
diff --git a/gates/testbench/and_tb.v b/gates/testbench/and_tb.v
index 777003e..2e63b96 100644
--- a/gates/testbench/and_tb.v
+++ b/gates/testbench/and_tb.v
@@ -1,4 +1,4 @@
-include "and_gate.v"
+include "predefined/and_gate.v"
 
 module and_tb();
     reg ta,tb;
diff --git a/gates/testbench/demux._tb.v b/gates/testbench/demux_tb.v
similarity index 95%
rename from gates/testbench/demux._tb.v
rename to gates/testbench/demux_tb.v
index e814b61..c8a655d 100644
--- a/gates/testbench/demux._tb.v
+++ b/gates/testbench/demux_tb.v
@@ -1,3 +1,5 @@
+include "predefined/demux.v"
+
 module demux_tb();
     reg a,b, sel;
     output y;
diff --git a/gates/testbench/mux.v b/gates/testbench/mux_tb.v
similarity index 97%
rename from gates/testbench/mux.v
rename to gates/testbench/mux_tb.v
index 010821c..29e6e01 100644
--- a/gates/testbench/mux.v
+++ b/gates/testbench/mux_tb.v
@@ -1,4 +1,4 @@
-include "mux.v"
+include "predefined/mux.v"
 
 module mux_tb();
     reg a,b, sel;
diff --git a/gates/testbench/nand_tb.v b/gates/testbench/nand_tb.v
index 217aede..f8c8784 100644
--- a/gates/testbench/nand_tb.v
+++ b/gates/testbench/nand_tb.v
@@ -1,4 +1,4 @@
-include "nand_gate.v"
+include "predefined/nand_gate.v"
 
 module nand_tb();
     reg ta,tb;
diff --git a/gates/testbench/nor_tb.v b/gates/testbench/nor_tb.v
new file mode 100644
index 0000000..a4c0416
--- /dev/null
+++ b/gates/testbench/nor_tb.v
@@ -0,0 +1,18 @@
+include "predefined/nor_gate.v"
+
+module nor_tb();
+    reg ta, tb;
+    wire ty;
+
+    nor_gate dut(y, ta, tb);
+
+    initial begin
+        ta=0, tb=0;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=0, tb=1;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=1, tb=0;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=1, tb=1;
+    end
+endmodule
\ No newline at end of file
diff --git a/gates/testbench/not_tb.v b/gates/testbench/not_tb.v
index c4b0daa..0aba768 100644
--- a/gates/testbench/not_tb.v
+++ b/gates/testbench/not_tb.v
@@ -1,4 +1,4 @@
-include "not_gate.v"
+include "predefined/not_gate.v"
 
 module not_tb();
     reg ta;
diff --git a/gates/testbench/or_tb.v b/gates/testbench/or_tb.v
index d0d89a2..17fe633 100644
--- a/gates/testbench/or_tb.v
+++ b/gates/testbench/or_tb.v
@@ -1,4 +1,4 @@
-include "or_gate.v"
+include "predefined/or_gate.v"
 
 module or_tb();
     reg ta, tb;
diff --git a/gates/testbench/xnor_tb.v b/gates/testbench/xnor_tb.v
new file mode 100644
index 0000000..814e8e9
--- /dev/null
+++ b/gates/testbench/xnor_tb.v
@@ -0,0 +1,18 @@
+include "predefined/xnor_gate.v"
+
+module xnor_tb();
+    reg ta, tb;
+    wire ty;
+
+    xnor_gate dut(y, ta, tb);
+
+    initial begin
+        ta=0, tb=0;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=0, tb=1;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=1, tb=0;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=1, tb=1;
+    end
+endmodule
\ No newline at end of file
diff --git a/gates/testbench/xor_tb.v b/gates/testbench/xor_tb.v
new file mode 100644
index 0000000..a4c0416
--- /dev/null
+++ b/gates/testbench/xor_tb.v
@@ -0,0 +1,18 @@
+include "predefined/nor_gate.v"
+
+module nor_tb();
+    reg ta, tb;
+    wire ty;
+
+    nor_gate dut(y, ta, tb);
+
+    initial begin
+        ta=0, tb=0;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=0, tb=1;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=1, tb=0;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=1, tb=1;
+    end
+endmodule
\ No newline at end of file