From 1dd49c3f4050045e2ed572931f3119c1afd89385 Mon Sep 17 00:00:00 2001 From: Erick Date: Mon, 7 Mar 2022 02:16:45 +0100 Subject: [PATCH] Update and16_tb.v --- testbench/and16_tb.v | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/testbench/and16_tb.v b/testbench/and16_tb.v index 9224499..067c3d4 100644 --- a/testbench/and16_tb.v +++ b/testbench/and16_tb.v @@ -1,11 +1,18 @@ 'include "predefined/and16.v" -module and_tb(); - reg [15:0]ta, [15:0]tb; +module and16_tb(); + reg [15:0]ta; + reg [15:0]tb; wire [15:0]y; and16 dut(y, ta, tb); initial begin - - $monitor("IN: %b, %b ",ta, tb, "OUT: ",y); + ta = 15'b000000000000000; tb = 15'b000000000000000; + $monitor("IN: %b, %b ", ta, tb, "OUT: ", y); + #5 ta = 15'b011010010110010; tb = 15'b000000000000000; + $monitor("IN: %b, %b ", ta, tb, "OUT: ", y); + #5 ta = 15'b000000000000000; tb = 15'b100010110101110; + $monitor("IN: %b, %b ", ta, tb, "OUT: ", y); + #5 ta = 15'b111111111111111; tb = 15'b111111111111111; + $monitor("IN: %b, %b ", ta, tb, "OUT: ", y); end endmodule \ No newline at end of file