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Update README.md

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Erick
2022-03-07 03:03:19 +01:00
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@@ -9,7 +9,8 @@ Most of the gates also have a 16-bit version and eventually a n-way version (som
Ex: a 4-way mux gate: Ex: a 4-way mux gate:
'''
module mux4way(out, i0, i1, i2, i3, sel0, sel1); module mux4way(out, i0, i1, i2, i3, sel0, sel1);
input i0, i1, i2, i3; input i0, i1, i2, i3;
input [3:0]sel; input [3:0]sel;
@@ -29,7 +30,6 @@ Ex: a 4-way mux gate:
or4way(out, tmp0, tmp1, tmp2, tmp3); or4way(out, tmp0, tmp1, tmp2, tmp3);
endmodule endmodule
'''
#### Predefined gates (path: /gates/predefined) #### Predefined gates (path: /gates/predefined)
The predefined gates are by default implemented on Verilog/Systemverilog. Thus they are not strictly needed for building more advanced gates or chipset, but I still decided to add them as reference and learning purposes. The predefined gates are by default implemented on Verilog/Systemverilog. Thus they are not strictly needed for building more advanced gates or chipset, but I still decided to add them as reference and learning purposes.