eeeck/iceberg
Archived
1
0
Fork 0
Code Activity

Update README.md

Browse Source
This commit is contained in:
Erick
2022-03-07 03:03:19 +01:00
committed by GitHub
parent dbbc633381
commit 2874592f4f
1 changed files with 4 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files
README.md
+4 -4
View File
@@ -9,7 +9,8 @@ Most of the gates also have a 16-bit version and eventually a n-way version (som
Ex: a 4-way mux gate: Ex: a 4-way mux gate:
'''
module mux4way(out, i0, i1, i2, i3, sel0, sel1); module mux4way(out, i0, i1, i2, i3, sel0, sel1);
input i0, i1, i2, i3; input i0, i1, i2, i3;
input [3:0]sel; input [3:0]sel;
@@ -28,8 +29,7 @@ Ex: a 4-way mux gate:
and(tmp3, i3, sel1); and(tmp3, i3, sel1);
or4way(out, tmp0, tmp1, tmp2, tmp3); or4way(out, tmp0, tmp1, tmp2, tmp3);
endmodule endmodule
'''
#### Predefined gates (path: /gates/predefined) #### Predefined gates (path: /gates/predefined)
The predefined gates are by default implemented on Verilog/Systemverilog. Thus they are not strictly needed for building more advanced gates or chipset, but I still decided to add them as reference and learning purposes. The predefined gates are by default implemented on Verilog/Systemverilog. Thus they are not strictly needed for building more advanced gates or chipset, but I still decided to add them as reference and learning purposes.
@@ -98,4 +98,4 @@ To visually see the functioning of a gate and it's testbench you need to use *gt
## Resources ## Resources
- Online Verilog Compiler: https://www.tutorialspoint.com/compile_verilog_online.php - Online Verilog Compiler: https://www.tutorialspoint.com/compile_verilog_online.php
- Online FPGA Simulator: https://simulator.nirajmmenon.com/ - Online FPGA Simulator: https://simulator.nirajmmenon.com/