From 3223f3a6afdf8dea1b10a8910004a7db00f9e7e5 Mon Sep 17 00:00:00 2001
From: Erick <ahmederick00@gmail.com>
Date: Tue, 8 Mar 2022 15:08:04 +0100
Subject: [PATCH] Create bit_reg.sv

bit_reg.v is a single bit register that uses a data flipflop
---
 memory/registers/bit_reg.sv | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
 create mode 100644 memory/registers/bit_reg.sv

diff --git a/memory/registers/bit_reg.sv b/memory/registers/bit_reg.sv
new file mode 100644
index 0000000..51aebbf
--- /dev/null
+++ b/memory/registers/bit_reg.sv
@@ -0,0 +1,14 @@
+import d_flipflop::scope;
+
+package bit_reg (
+    input in;
+    input load;
+    input clk;
+    output out;
+    output out_compl;
+);
+
+    mux(tmp, in, out, load);
+    d_flipflop(out, out_compl, tmp, clk);
+
+endpackage
\ No newline at end of file