From 3ade6ba96a81a4b433cd2d03e1b2ac750d5164d8 Mon Sep 17 00:00:00 2001
From: Erick <ahmederick00@gmail.com>
Date: Mon, 7 Mar 2022 02:17:10 +0100
Subject: [PATCH] create sr flipflop logic

---
 memory/sr_flipflop.sv | 13 +++++++++++++
 1 file changed, 13 insertions(+)
 create mode 100644 memory/sr_flipflop.sv

diff --git a/memory/sr_flipflop.sv b/memory/sr_flipflop.sv
new file mode 100644
index 0000000..8458635
--- /dev/null
+++ b/memory/sr_flipflop.sv
@@ -0,0 +1,13 @@
+'include "gates/nand16.v"
+
+module sr_flipflop (
+    input s, r, clk,
+    output q, q_compl
+);
+
+nand16 nand0(tmp0, s, clk);
+nand16 nand1(tmp1, r, clk);
+nand16 nand2(q, tmp0, q_compl);
+nand16 nand3(q_compl, tmp1, q);
+
+endmodule
\ No newline at end of file