diff --git a/README.md b/README.md
index 989d2cb..21282fb 100644
--- a/README.md
+++ b/README.md
@@ -1,5 +1,5 @@
 # Square One - From logic gates to 16-bit OS
-Square One is a virtual computer built from scratch, starting from the logic gates and CPU to an assembler and compiler, whilst at the very high level Java is implemented-
+Square One is a virtual computer built from scratch, built starting from the logic gates and CPU to an assembler and compiler, whilst at the very high level Java is implemented.
 
 ## Architecture
 
@@ -9,8 +9,7 @@ Most of the gates also have a 16-bit version and eventually a n-way version (som
 
 Ex: a 4-way mux gate:
 
-'''
-
+'''v
 module mux4way(out, i0, i1, i2, i3, sel0, sel1);
     input i0, i1, i2, i3;
     input [3:0]sel;
@@ -29,18 +28,15 @@ module mux4way(out, i0, i1, i2, i3, sel0, sel1);
     and(tmp3, i3, sel1);
 
     or4way(out, tmp0, tmp1, tmp2, tmp3);
-
 endmodule
-
 '''
 
 #### Predefined gates (path: /gates/predefined)
 The predefined gates are by default implemented on Verilog/Systemverilog. Thus they are not strictly needed for building more advanced gates or chipset, but I still decided to add them as reference and learning purposes.
 
-#### Testbenches (path: /testbenches)
-Testbenches are a way to test the implementation of a particular gate using a Verilog compiler. They output a set of I/O command to test the correct implementation of a given gate.
+### Processor (path: /cpu)
 
-### Arithmetic Logic Unit (path: /alu)
+#### Arithmetic Logic Unit (path: /cpu/alu)
 The ALU is written is Systemverilog (such as the CPU and other complex components). It handles two 16-bit inputs, a 6-bit opcode and a 16-bit output and a 2-bit sign flag. It computes the following instructions:
 
     x+y
@@ -86,6 +82,10 @@ And the 2-bit sign flag is:
     1 (if output = 0)
     2 (if output > 0)
 
+
+## Testbenches (path: /testbenches)
+Testbenches are a way to test the implementation of a particular gate using a Verilog compiler. They output a set of I/O command to test the correct implementation of a given gate.
+
 ## Usage
 #### Verilog/Systemverilog logic gates
 To run any Verilog (.v) or Systemverilog (.sv) file, use *iverilog* (available for Windows, Linux and MacOS) using the command: