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Erick
2022-03-22 17:09:01 +01:00
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README.md
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@@ -83,9 +83,15 @@ And the 2-bit sign flag is:
1 (if output = 0) 1 (if output = 0)
2 (if output > 0) 2 (if output > 0)
### Memory
### Assembler
### Compiler
## Testbenches (path: /testbenches)
Testbenches are a way to test the implementation of a particular gate using a Verilog compiler. They output a set of I/O command to test the correct implementation of a given gate.
## Usage ## Usage
#### Verilog/Systemverilog logic gates #### Verilog/Systemverilog logic gates