adding new paragraphs

2022-03-22 17:09:01 +01:00
parent a52dbe03fc
commit 4d0a1bb944
1 changed files with 10 additions and 4 deletions
@@ -83,9 +83,15 @@ And the 2-bit sign flag is:
    1 (if output = 0)
    2 (if output > 0)

+### Memory
+
+
+### Assembler
+
+
+### Compiler
+

-## Testbenches (path: /testbenches)
-Testbenches are a way to test the implementation of a particular gate using a Verilog compiler. They output a set of I/O command to test the correct implementation of a given gate.

 ## Usage
 #### Verilog/Systemverilog logic gates