From 613178fc34bde2225bf64cc44c5bdf7be8216953 Mon Sep 17 00:00:00 2001
From: Erick <ahmederick00@gmail.com>
Date: Fri, 4 Mar 2022 01:39:07 +0100
Subject: [PATCH] creation of an ALU

---
 cpu/alu/adder.sv     | 18 ++++++++++++++++++
 cpu/alu/adder16.sv   | 20 ++++++++++++++++++++
 cpu/alu/halfadder.sv | 11 +++++++++++
 cpu/cpu.sv           |  0
 4 files changed, 49 insertions(+)
 create mode 100644 cpu/alu/adder.sv
 create mode 100644 cpu/alu/adder16.sv
 create mode 100644 cpu/alu/halfadder.sv
 create mode 100644 cpu/cpu.sv

diff --git a/cpu/alu/adder.sv b/cpu/alu/adder.sv
new file mode 100644
index 0000000..8eaac51
--- /dev/null
+++ b/cpu/alu/adder.sv
@@ -0,0 +1,18 @@
+'include "cpu/alu/halfadder.sv"
+
+module adder (
+    output sum_bit,
+    output carry_bit,
+    input a,
+    input b,
+    input c
+);
+
+halfadder halfadd(tmpXor0, tmpAnd0, a, b);
+
+xor sum_final(sum_bit, tmpXor0, c);
+
+and carry_tmp0(tmpAnd1, tmpXor0, c);
+or carry_final(carry_bit, tmpAnd0, tmpAnd1);
+
+endmodule
\ No newline at end of file
diff --git a/cpu/alu/adder16.sv b/cpu/alu/adder16.sv
new file mode 100644
index 0000000..05b2ff1
--- /dev/null
+++ b/cpu/alu/adder16.sv
@@ -0,0 +1,20 @@
+'include "cpu/alu/adder.sv"
+
+module adder16 (
+    output [15:0]sum_bit,
+    output [15:0]carry_bit
+    input [15:0]a,
+    input [15:0]b,
+    input [15:0]c,
+);
+
+halfadder(tmpXor0, tmpAnd0, a, b)
+
+xor sum_final(sum_bit, tmpXor0, c);
+
+and carry_tmp0(tmpAnd1, tmpXor0, c);
+or carry_final(carry_bit, tmpAnd0, tmpAnd1);
+
+endmodule
+
+
diff --git a/cpu/alu/halfadder.sv b/cpu/alu/halfadder.sv
new file mode 100644
index 0000000..d075979
--- /dev/null
+++ b/cpu/alu/halfadder.sv
@@ -0,0 +1,11 @@
+module halfadder (
+    output sum_bit,
+    output carry_bit,
+    input a,
+    input b
+);
+
+xor sum_g(sum_bit, a, b);
+and carry_g(carry_bit, a, b);
+
+endmodule
\ No newline at end of file
diff --git a/cpu/cpu.sv b/cpu/cpu.sv
new file mode 100644
index 0000000..e69de29