Grouped the gates and corrected xnor16.v nor16.v (#6)

Alright!

gates/and/and16.v

@@ -0,0 +1,22 @@
+module and16(y16, a16, b16);
+    input [15:0]a16;
+    input [15:0]b16;
+    output [15:0]y16;
+
+    and and0(y16[0], a16[0], b16[0]);
+    and and1(y16[1], a16[1], b16[1]);
+    and and2(y16[2], a16[2], b16[2]);
+    and and3(y16[3], a16[3], b16[3]);
+    and and4(y16[4], a16[4], b16[4]);
+    and and5(y16[5], a16[5], b16[5]);
+    and and6(y16[6], a16[6], b16[6]);
+    and and7(y16[7], a16[7], b16[7]);
+    and and8(y16[8], a16[8], b16[8]);
+    and and9(y16[9], a16[9], b16[9]);
+    and and10(y16[10], a16[10], b16[10]);
+    and and11(y16[11], a16[11], b16[11]);
+    and and12(y16[12], a16[12], b16[12]);
+    and and13(y16[13], a16[13], b16[13]);
+    and and14(y16[14], a16[14], b16[14]);
+    and and15(y16[15], a16[15], b16[15]);
+endmodule

gates/and/and8way.v

@@ -0,0 +1,15 @@
+module and8way(out, i0, i1, i2, i3, i4, i5, i6, i7);
+    input i0, i1, i2, i3, i4, i5, i6, i7;
+    output out;
+    wire tmp01, tmp23, tmp45, tmp67, tmp0123, tmp4567;
+
+    and andA(tmp01, i0, i1);
+    and andB(tmp23, i2, i3);
+    and andC(tmp45, i4, i5);
+    and andD(tmp67, i6, i7);
+
+    and andAB(tmp0123, tmp01, tmp23);
+    and andCD(tmp4567, tmp45, tmp67);
+
+    and andFinal(out, tmp0123, tmp4567);
+endmodule

gates/and/and8way16.v

@@ -0,0 +1,29 @@
+'include "and16.v"
+
+module and8way16(out, i0, i1, i2, i3, i4, i5, i6, i7);
+    input [15:0]i0;
+    input [15:0]i1;
+    input [15:0]i2;
+    input [15:0]i3;
+    input [15:0]i4;
+    input [15:0]i5;
+    input [15:0]i6;
+    input [15:0]i7;
+    output [15:0]out;
+    wire [15:0]tmp01;
+    wire [15:0]tmp23;
+    wire [15:0]tmp45;
+    wire [15:0]tmp67;
+    wire [15:0]tmp0123;
+    wire [15:0]tmp4567;
+
+    and16 andA(tmp01, i0, i1);
+    and16 andB(tmp23, i2, i3);
+    and16 andC(tmp45, i4, i5);
+    and16 andD(tmp67, i6, i7);
+
+    and16 andAB(tmp0123, tmp01, tmp23);
+    and16 andCD(tmp4567, tmp45, tmp67);
+
+    and16 andFinal(out, tmp0123, tmp4567);
+endmodule