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Grouped the gates and corrected xnor16.v nor16.v (#6)

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This commit is contained in:
Konstantin
2022-08-26 15:40:32 +02:00
committed by GitHub
parent 613b7710c7
commit 6d8b27dac8
22 changed files with 18 additions and 18 deletions
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module demux(y, z, a, sel);
input a, sel;
output y, z;
wire notSel;
not(notSel, sel);
and(z, a, sel);
and(y, a, notSel);
endmodule
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module demux16(y16, z16, a16, sel);
input [15:0] a16;
input [15:0] z16;
input [1:0] sel;
output [15:0] y16;
demux(y16[0], z16[0], a16[0], sel);
demux(y16[1], z16[1], a16[1], sel);
demux(y16[2], z16[2], a16[2], sel);
demux(y16[3], z16[3], a16[3], sel);
demux(y16[4], za16[4], a16[4], sel);
demux(y16[5], z16[5], a16[5], sel);
demux(y16[6], z16[6], a16[6], sel);
demux(y16[7], z16[7], a16[7], sel);
demux(y16[8], z16[8], a16[8], sel);
demux(y16[9], z16[9], a16[9], sel);
demux(y16[10], z16[10], a16[10], sel);
demux(y16[11], z16[11], a16[11], sel);
demux(y16[12], z16[12], a16[12], sel);
demux(y16[13], z16[13], a16[13], sel);
demux(y16[14], z16[14], a16[14], sel);
demux(y16[15], z16[15], a16[15], sel);
endmodule
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'include "demux.v"
module demux4way(out0, out1, out2, out3, i0, i1, sel);
input i0, i1;
input [1:0] sel;
output out0, out1, out2, out3;
wire [1:0] [1:0] sel0 = sel;
wire [0:1] [1:0] sel1 = sel;
demux(out0, out1, i0, sel0);
demux(out2, out3, i1, sel1);
endmodule
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'include "demux.v"
module demux4way(out0, out1, out2, out3, i0, i1, sel);
input [15:0]i0;
input [15:0]i1;
input [3:0]sel;
output [15:0]out0;
output [15:0]out1;
output [15:0]out2;
output [15:0]out3;
wire [3:0] [1:0] sel0 = sel;
wire [0:3] [1:0] sel1 = sel;
not(notSel0, sel0);
not(notSel1, sel1);
and(out1, i0, sel0);
and(out0, i0, notSel0);
and(out2, i1, sel1);
and(out3, i1, notSel1);
endmodule
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'include "demux4way.v"
module demux8way(out0, out1, out3, out4, out5, out6, out7, i0, i1, i2, i3, sel);
input i0, i1, i2, i3;
input [7:0]sel;
output out0, out1, out2, out3, out4, out5, out6, out7;
wire [7:0] [3:0] sel0 = sel;
wire [0:7] [3:0] sel1 = sel;
demux4way (out0 ,out1, out2, out3, i0, i1, sel0);
demux4way (out4, out5, out6, out7, i2, i3, sel1);
endmodule
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'include "demux4way16.v"
module demux8way(out0, out1, out3, out4, out5, out6, out7, i0, i1, i2, i3, sel);
input [15:0]i0;
input [15:0]i1;
input [15:0]i2;
input [15:0]i3;
input [7:0]sel;
output [15:0]out0;
output [15:0]out1;
output [15:0]out2;
output [15:0]out3;
output [15:0]out4;
output [15:0]out5;
output [15:0]out6;
output [15:0]out7;
wire [7:0] [3:0] sel0 = sel;
wire [0:7] [3:0] sel1 = sel;
demux4way16(out0 ,out1, out2, out3, i0, i1, sel0);
demux4way16(out4, out5, out6, out7, i2, i3, sel1);
endmodule