Grouped the gates and corrected xnor16.v nor16.v (#6)

Alright!

gates/mux/mux.v

@@ -0,0 +1,10 @@
+module mux(y, a, b, sel);
+    input a, b, sel;
+    output y;
+    wire notSel, andA, andB;
+
+    not(notSel, sel);
+    and(andA, a, sel);
+    and(andB, b, notSel);
+    or(y, andA, andB);
+endmodule

gates/mux/mux16.v

@@ -0,0 +1,23 @@
+module mux16(y16, a16, b16, sel);
+    input [15:0] a16;
+    input[15:0] b16;
+    input sel;
+    output [15:0] y16;
+
+    mux(y16[0],  a16[0],  b16[0],  sel);
+    mux(y16[1],  a16[1],  b16[1],  sel);
+    mux(y16[2],  a16[2],  b16[2],  sel);
+    mux(y16[3],  a16[3],  b16[3],  sel);
+    mux(y16[4],  a16[4],  b16[4],  sel);
+    mux(y16[5],  a16[5],  b16[5],  sel);
+    mux(y16[6],  a16[6],  b16[6],  sel);
+    mux(y16[7],  a16[7],  b16[7],  sel);
+    mux(y16[8],  a16[8],  b16[8],  sel);
+    mux(y16[9],  a16[9],  b16[9],  sel);
+    mux(y16[10], a16[10], b16[10], sel);
+    mux(y16[11], a16[11], b16[11], sel);
+    mux(y16[12], a16[12], b16[12], sel);
+    mux(y16[13], a16[13], b16[13], sel);
+    mux(y16[14], a16[14], b16[14], sel);
+    mux(y16[15], a16[15], b16[15], sel);
+endmodule

gates/mux/mux4way.v

@@ -0,0 +1,23 @@
+'include "mux.v"
+'include "or4way.v"
+
+module mux4way(out, i0, i1, i2, i3, sel0, sel1);
+    input i0, i1, i2, i3;
+    input [3:0]sel;
+    output [3:0]out;
+    wire tmp0, tmp1, tmp2, tmp3;
+
+    wire [3:0] [1:0] sel0 = sel;
+    wire [0:3] [1:0] sel1 = sel;
+
+    not(notSel0, sel0);
+    not(notSel1, sel1);
+
+    and(tmp0, i0, notSel0);
+    and(tmp1, i1, sel0);
+    and(tmp2, i2, notSel1);
+    and(tmp3, i3, sel1);
+
+    or4way(out, tmp0, tmp1, tmp2, tmp3);
+
+endmodule

gates/mux/mux4way16.v

@@ -0,0 +1,27 @@
+'include "and16.v"
+'include "not16.v"
+'include "or4way.v"
+
+module mux4way16(out, i0, i1, i2, i3, sel);
+    input [15:0]i0;
+    input [15:0]i1;
+    input [15:0]i2;
+    input [15:0]i3;
+    input [1:0]sel;
+    output [15:0]out;
+    wire [15:0]tmp0;
+    wire [15:0]tmp1;
+    wire [15:0]tmp2;
+    wire [15:0]tmp3;
+
+    wire [2:0] [15:0] sel16 = sel;
+
+    not16(notSel16, sel16);
+
+    and16(tmp0, i0, notSel16);
+    and16(tmp1, i1, sel16);
+    and16(tmp2, i2, notSel16);
+    and16(tmp3, i3, sel16);
+
+    or4way16(out, tmp0, tmp1, tmp2, tmp3);
+endmodule

gates/mux/mux8way16.v

@@ -0,0 +1,24 @@
+'include "mux4way16.v"
+'include "mux16.v"
+
+module mux8way16(out, i0, i1, i2, i3, i4, i5, i6, i7, sel);
+    input [15:0]i0;
+    input [15:0]i1;
+    input [15:0]i2;
+    input [15:0]i3;
+    input [15:0]i4;
+    input [15:0]i5;
+    input [15:0]i6;
+    input [15:0]i7;
+    input [7:0]sel;
+    output [15:0]out;
+    wire tmpMux1, tmpMux1;
+
+    wire [7:0] [3:0] sel0 = sel;
+    wire [0:7] [3:0] sel1 = sel;
+
+    mux4way16(tmpMux0, i0, i1, i2, i3, sel0);
+    mux4way16(tmpMux1, i4, i5, i6, i7, sel1);
+
+    mux16(out, tmpMux0, tmpMux1, sel);
+endmodule