Grouped the gates and corrected xnor16.v nor16.v (#6)

Alright!
2022-08-26 15:40:32 +02:00
parent 613b7710c7
commit 6d8b27dac8
22 changed files with 18 additions and 18 deletions
@@ -0,0 +1,10 @@
+module mux(y, a, b, sel);
+    input a, b, sel;
+    output y;
+    wire notSel, andA, andB;
+
+    not(notSel, sel);
+    and(andA, a, sel);
+    and(andB, b, notSel);
+    or(y, andA, andB);
+endmodule