Grouped the gates and corrected xnor16.v nor16.v (#6)

Alright!

gates/or/or16.v

@@ -0,0 +1,22 @@
+module or16(y16, a16, b16);
+    input [15:0] a16;
+    input [15:0] b16;
+    output [15:0] y16;
+
+    or(y16[0], a16[0], b16[0]);
+    or(y16[1], a16[1], b16[1]);
+    or(y16[2], a16[2], b16[2]);
+    or(y16[3], a16[3], b16[3]);
+    or(y16[4], a16[4], b16[4]);
+    or(y16[5], a16[5], b16[5]);
+    or(y16[6], a16[6], b16[6]);
+    or(y16[7], a16[7], b16[7]);
+    or(y16[8], a16[8], b16[8]);
+    or(y16[9], a16[9], b16[9]);
+    or(y16[10], a16[10], b16[10]);
+    or(y16[11], a16[11], b16[11]);
+    or(y16[12], a16[12], b16[12]);
+    or(y16[13], a16[13], b16[13]);
+    or(y16[14], a16[14], b16[14]);
+    or(y16[15], a16[15], b16[15]);
+endmodule

gates/or/or4way.v

@@ -0,0 +1,10 @@
+module or4way(out, i0, i1, i2, i3);
+    input i0, i1, i2, i3;
+    output [3:0]out;
+    wire tmp01, tmp23,;
+
+    or(tmp01, i0, i1);
+    or(tmp23, i2, i3);
+    or(out, tmp01, tmp23);
+
+endmodule

gates/or/or4way16.v

@@ -0,0 +1,14 @@
+module or4way16(out, i0, i1, i2, i3);
+    input [15:0]i0;
+    input [15:0]i1;
+    input [15:0]i2;
+    input [15:0]i3;
+    output [15:0]out;
+    wire [15:0]tmp01;
+    wire [15:0]tmp23,;
+
+    or(tmp01, i0, i1);
+    or(tmp23, i2, i3);
+    or(out, tmp01, tmp23);
+
+endmodule

gates/or/or8way.v

@@ -0,0 +1,11 @@
+'include "or4way.v"
+
+module or8way(out4, i0, i1, i2, i3, i4, i5, i6, i7);
+    input i0, i1, i2, i3, i4, i5, i6, i7;
+    output out;
+    wire tmp0, tmp1;
+
+    or4way(tmp0, i0, i1, i2, i3);
+    or4way(tmp1, i4, i5, i6, i7);
+    or(out, tmp0, tmp1);
+endmodule

gates/or/or8way16.v

@@ -0,0 +1,29 @@
+'include "or16.v"
+
+module or8way16(out, i0, i1, i2, i3, i4, i5, i6, i7);
+    input [15:0]i0;
+    input [15:0]i1;
+    input [15:0]i2;
+    input [15:0]i3;
+    input [15:0]i4;
+    input [15:0]i5;
+    input [15:0]i6;
+    input [15:0]i7;
+    output [15:0] out;
+    wire [15:0]tmp01;
+    wire [15:0]tmp23;
+    wire [15:0]tmp45;
+    wire [15:0]tmp67;
+    wire [15:0]tmp0123;
+    wire [15:0]tmp4567;
+
+    or16 or01(tmp01, i0, i1);
+    or16 or23(tmp23, i2, i3);
+    or16 or45(tmp45, i4, i5);
+    or16 or67(tmp67, i6, i7);
+
+    or16 or0123(tmp0123, tmp01, tmp23);
+    or16 or4567(tmp4567, tmp45, tmp67);
+
+    or16 final(out, tmp0123, tmp4567);
+endmodule