created sr, jk and data flipflops

2022-03-08 13:54:42 +01:00
parent a4c9507c3c
commit b5d5fb5a05
4 changed files with 41 additions and 13 deletions
@@ -0,0 +1,15 @@
+'include "gates/nand3way16.v"
+
+import sr_flipflop::*;
+
+package d_flipflop (
+    output [15:0]dq, [15:0]dq_compl
+    input [15:0]d, clk,
+);
+
+nand16(tmp0, d, clk);
+nand16(tmp1, clk, tmp0);
+
+sr_flipflop(dq, dq_compl, tmp0, tmp1);
+
+endpackage