diff --git a/README.md b/README.md
index 56c78ec..1c0a17b 100644
--- a/README.md
+++ b/README.md
@@ -8,31 +8,30 @@ Logic gates are the lowest level point from which this project is implemented. T
 Most of the gates also have a 16-bit version and eventually a n-way version (some even n-way-16-bit).
 
 Ex: a 4-way mux gate:
+'''
 
-    include "mux.v"
-    include "or4way.v"
+module mux4way(out, i0, i1, i2, i3, sel0, sel1);
+    input i0, i1, i2, i3;
+    input [3:0]sel;
+    output [3:0]out;
+    wire tmp0, tmp1, tmp2, tmp3;
 
-    module mux4way(out, i0, i1, i2, i3, sel0, sel1);
-        input i0, i1, i2, i3;
-        input [3:0]sel;
-        output [3:0]out;
-        wire tmp0, tmp1, tmp2, tmp3;
+    wire [3:0] [1:0] sel0 = sel;
+    wire [0:3] [1:0] sel1 = sel;
 
-        wire [3:0] [1:0] sel0 = sel;
-        wire [0:3] [1:0] sel1 = sel;
+    not(notSel0, sel0);
+    not(notSel1, sel1);
 
-        not(notSel0, sel0);
-        not(notSel1, sel1);
+    and(tmp0, i0, notSel0);
+    and(tmp1, i1, sel0);
+    and(tmp2, i2, notSel1);
+    and(tmp3, i3, sel1);
 
-        and(tmp0, i0, notSel0);
-        and(tmp1, i1, sel0);
-        and(tmp2, i2, notSel1);
-        and(tmp3, i3, sel1);
+    or4way(out, tmp0, tmp1, tmp2, tmp3);
 
-        or4way(out, tmp0, tmp1, tmp2, tmp3);
-
-    endmodule
+endmodule
 
+'''
 #### Predefined gates (path: /gates/predefined)
 The predefined gates are by default implemented on Verilog/Systemverilog. Thus they are not strictly needed for building more advanced gates or chipset, but I still decided to add them as reference and learning purposes.
 
@@ -42,6 +41,7 @@ Testbenches are a way to test the implementation of a particular gate using a Ve
 Ex: testbench for a xor gate:
 
 '''
+
 module xor_tb();
     reg ta, tb;
     wire ty;
@@ -58,6 +58,7 @@ module xor_tb();
         ta=1, tb=1;
     end
 endmodule
+
 '''
 
 ### Arithmetic Logic Unit (path: /alu)