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Erick
2022-03-05 00:03:13 +01:00
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@@ -8,7 +8,6 @@ Logic gates are the lowest level point from which this project is implemented. T
Most of the gates also have a 16-bit version and eventually a n-way version (some even n-way-16-bit). Most of the gates also have a 16-bit version and eventually a n-way version (some even n-way-16-bit).
Ex: a 4-way mux gate: Ex: a 4-way mux gate:
'''
module mux4way(out, i0, i1, i2, i3, sel0, sel1); module mux4way(out, i0, i1, i2, i3, sel0, sel1);
input i0, i1, i2, i3; input i0, i1, i2, i3;
@@ -31,7 +30,6 @@ module mux4way(out, i0, i1, i2, i3, sel0, sel1);
endmodule endmodule
'''
#### Predefined gates (path: /gates/predefined) #### Predefined gates (path: /gates/predefined)
The predefined gates are by default implemented on Verilog/Systemverilog. Thus they are not strictly needed for building more advanced gates or chipset, but I still decided to add them as reference and learning purposes. The predefined gates are by default implemented on Verilog/Systemverilog. Thus they are not strictly needed for building more advanced gates or chipset, but I still decided to add them as reference and learning purposes.
@@ -40,8 +38,6 @@ Testbenches are a way to test the implementation of a particular gate using a Ve
Ex: testbench for a xor gate: Ex: testbench for a xor gate:
'''
module xor_tb(); module xor_tb();
reg ta, tb; reg ta, tb;
wire ty; wire ty;
@@ -59,8 +55,6 @@ module xor_tb();
end end
endmodule endmodule
'''
### Arithmetic Logic Unit (path: /alu) ### Arithmetic Logic Unit (path: /alu)
The ALU is written is Systemverilog (such as the CPU and other complex components). It handles 16-bit values and performs numerous operations, as: The ALU is written is Systemverilog (such as the CPU and other complex components). It handles 16-bit values and performs numerous operations, as: