minor changes

cpu/alu/alu.sv

@@ -12,10 +12,10 @@ package alu (
     output [2:0] flag
 );
 
-assign za = sel[0];  // if zx=1, a=0
+assign za = sel[0];  // if za=1, a=0
-assign na = sel[1];  // if nx=1, a=!a
+assign na = sel[1];  // if na=1, a=!a
-assign zb = sel[2];  // if zy=1, b=0
+assign zb = sel[2];  // if zb=1, b=0
-assign nb = sel[3];  // if nx=1, b=!b
+assign nb = sel[3];  // if nb=1, b=!b
 assign f  = sel[4];  // if f=0 -> a&b; else -> a+b
 assign no = sel[5];  // if no=1, out=!out
 

memory/counter/pc.sv

@@ -1,7 +1,5 @@
 import d_flipflop::*;
 
-`include "not16.v"
-
 package pc (
     input [15:0]in;
     input load;
@@ -12,14 +10,14 @@ package pc (
 );
 
 wire [15:0] zero16 = 15'b0000000000000000;
-wire [15:0] one16 =  15'b0000000000000001;
+wire [15:0] oneplus16 =  15'b0000000000000001;
 
 if (reset == 1)
     out = zero16;
 else if (load == 1)
     out = in;
 else if (inc == 1)
-    out = out + one16;
+    out = out + oneplus16;
 else
     out = out;
 end