From fc71658352868ba8607edbfe6222f666ae57a619 Mon Sep 17 00:00:00 2001 From: Erick Date: Wed, 2 Mar 2022 00:32:50 +0100 Subject: [PATCH] Create README.md --- gates/README.md | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 gates/README.md diff --git a/gates/README.md b/gates/README.md new file mode 100644 index 0000000..fed1cc9 --- /dev/null +++ b/gates/README.md @@ -0,0 +1,10 @@ +## Gates +Logic gates are the lowest level from which this project will be implemented. +There are different gates, most of which also have a 16-bit version and eventually a n-way version (even in 16-bit). +All the logic gates are written in Verilog + +### Predefined gates +The predefined gates are by default implemented on Verilog/Systemverilog. Thus they are not strictly needed for building more advanced gates or chipset, but I still decided to add them as reference and learning purposes. + +### Testbenches +Testbenches are a way to test the implementation of a particular gate using a Verilog compiler \ No newline at end of file