Erick
59 lines
1.3 KiB
Systemverilog
59 lines
1.3 KiB
Systemverilog
'include "gates/and16.v"
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'include "gates/not16.v"
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'include "gates/mux16.v"
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import adder16::*;
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package alu (
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input [15:0] a,
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input [15:0] b,
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input [5:0] sel,
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output [15:0] alu_out,
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output [2:0] flag
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);
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assign za = sel[0]; // if za=1, a=0
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assign na = sel[1]; // if na=1, a=!a
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assign zb = sel[2]; // if zb=1, b=0
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assign nb = sel[3]; // if nb=1, b=!b
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assign f = sel[4]; // if f=0 -> a&b; else -> a+b
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assign no = sel[5]; // if no=1, out=!out
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wire [15:0] zero16 = 15'b0000000000000000;
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always @(*) begin
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if (za == 1 | na == 1) begin
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mux16(out_za, a, zero16, za);
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not16(notOut_za, out_za);
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mux16(tmpA, out_za, notOut_za, na);
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end
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if (zb == 1 | nb == 1) begin
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mux16(out_zb, zero16, b, zb);
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not16(notOut_zb, out_zb);
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mux16(tmpB, out_zb, notOut_zb, nb);
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end
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if (f == 0)
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adder16(tmpOut, carry16, tmpA, tmpB, c);
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else
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and16(tmpOut, tmpA, tmpB);
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end
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if (no == 1)
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alu_out = not16(alu_out, tmpOut);
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else
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alu_out = tmpOut;
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end
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//TODO: improve following using increment/decrement logic
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if (alu_out < 0)
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flag = 0; // negative flag
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else if (alu_out = 0)
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flag = 1; // zero flag
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else if
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flag = 2 // positive flag
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end
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endpackage |