Erick
13 lines
395 B
Verilog
13 lines
395 B
Verilog
'include "demux4way.v"
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module demux8way(out0, out1, out3, out4, out5, out6, out7, i0, i1, i2, i3, sel);
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input i0, i1, i2, i3;
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input [7:0]sel;
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output out0, out1, out2, out3, out4, out5, out6, out7;
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wire [7:0] [3:0] sel0 = sel;
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wire [0:7] [3:0] sel1 = sel;
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demux4way (out0 ,out1, out2, out3, i0, i1, sel0);
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demux4way (out4, out5, out6, out7, i2, i3, sel1);
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endmodule |