Erick
34 lines
788 B
Systemverilog
34 lines
788 B
Systemverilog
import ram4096::*;
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package ram16384 (
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input [16384:0]in;
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input [13:0]addr;
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input load;
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input clk
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output [16384:0]out;
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);
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wire [4095:0] [4095:0] in0 = in;
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wire [8191:4095] [4095:0] in1 = in;
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wire [12287:8191] [4095:0] in2 = in;
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wire [16383:12287] [4095:0] in3 = in;
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wire [13:0] [11:0] addr0 = in;
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wire [0:13] [11:0] addr1 = in;
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wire [4095:0]out0;
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wire [4095:0]out1;
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wire [4095:0]out2;
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wire [4095:0]out3;
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ram4096 clstr0(in0, addr0, load, clk, out0);
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ram4096 clstr1(in1, addr0, load, clk, out1);
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ram4096 clstr2(in2, addr0, load, clk, out2);
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ram4096 clstr3(in3, addr0, load, clk, out3);
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wire [4095:0] [4095:0] out0 = out;
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wire [4095:0] [8191:4095] out1 = out;
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wire [4095:0] [12287:8191] out2 = out;
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wire [4095:0] [16383:12287] out3 = out;
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endpackage |