Erick
17 lines
241 B
Systemverilog
17 lines
241 B
Systemverilog
package lookahead (
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output [15:0]carry_bit,
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input [15:0]a,
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input [15:0]b,
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);
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res = and16(y, a, b);
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for (i=0; i<15 ; i=i+1)
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if (res[i] = 0)
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carry_bit[i] = 0;
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else
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carry_bit[i] = 1;
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end
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end
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endpackage |