Erick
17 lines
368 B
Verilog
17 lines
368 B
Verilog
include "and_gate.v"
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include "nor_gate.v"
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include "not_gate.v"
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module xnor_gate(a, b, y);
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input a, b;
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output y;
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logic selA, selB, tmpNorA, tmpNorB;
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always @ (a or b)begin
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not_gate(a, selA);
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not_gate(b, selB);
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and_gate(a, selB, tmpNorA)
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and_gate(selA, b, tmpNorB)
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nor_gate(tmpNorA, tmpNorB, y)
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end
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endmodule |