Erick
17 lines
363 B
Verilog
17 lines
363 B
Verilog
include "and_gate.v"
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include "or_gate.v"
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include "not_gate.v"
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module xnor_gate(a, b, y);
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input a, b;
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output y;
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logic selA, selB, tmpOrA, tmpOrB;
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always @ (a or b)begin
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not_gate(a, selA);
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not_gate(b, selB);
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and_gate(a, selB, tmpOrA);
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and_gate(selA, b, tmpOrB);
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or_gate(tmpOrA, tmpOrB, y);
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end
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endmodule |