Erick
9 lines
155 B
Verilog
9 lines
155 B
Verilog
module demux(y, z, a, sel);
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input a, sel;
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output y, z;
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wire notSel;
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not(notSel, sel);
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and(z, a, sel);
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and(y, a, notSel);
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endmodule |