Erick
17 lines
594 B
Systemverilog
17 lines
594 B
Systemverilog
'include "cpu/alu/halfadder.sv"
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module halfadder_tb();
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reg ta,tb;
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wire t_sum, t_carry;
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halfadder dut(t_sum, t_carry, ta, tb);
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initial begin
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ta = 0; tb = 0;
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$monitor("A/B: %b, %b ",ta, tb, "S/C: %b, %b",t_sum, t_carry);
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#5 ta = 1; tb = 0;
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$monitor("A/B: %b, %b ",ta, tb, "S/C: %b, %b",t_sum, t_carry);
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#5 ta = 0; tb = 1;
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$monitor("A/B: %b, %b ",ta, tb, "S/C: %b, %b",t_sum, t_carry);
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#5 ta = 1; tb = 1;
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$monitor("A/B: %b, %b ",ta, tb, "S/C: %b, %b",t_sum, t_carry);
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end
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endmodule |