Erick
28 lines
822 B
Systemverilog
28 lines
822 B
Systemverilog
import reg16::*;
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`include "demux8way.v"
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`include "mux8way16.v"
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package ram8 (
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input [7:0]in;
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input [2:0]addr;
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input load;
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input clk
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output [7:0]outp;
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);
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wire [7:0]out_cmpl;
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wire [7:0] [2:0] addr = lnaddr;
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demux8way (load, load, load, load, lnaddr, out[0], out[1], out[2], out[3], out[4], out[5], out[6], out[7]);
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bit_reg (in[0], load, clk, out[0], out_cmpl[0]);
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bit_reg (in[1], load, clk, out[1], out_cmpl[1]);
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bit_reg (in[2], load, clk, out[2], out_cmpl[2]);
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bit_reg (in[3], load, clk, out[3], out_cmpl[3]);
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bit_reg (in[4], load, clk, out[4], out_cmpl[4]);
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bit_reg (in[5], load, clk, out[5], out_cmpl[5]);
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bit_reg (in[6], load, clk, out[6], out_cmpl[6]);
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bit_reg (in[7], load, clk, out[7], out_cmpl[7]);
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mux8way16 (out[0], out[1], out[2], out[3], out[4], out[5], out[6], out[7], outp);
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endpackage |