Erick
18 lines
657 B
Verilog
18 lines
657 B
Verilog
'include "predefined/and16.v"
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module and16_tb();
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reg [15:0]ta;
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reg [15:0]tb;
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wire [15:0]y;
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and16 dut(y, ta, tb);
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initial begin
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ta = 15'b000000000000000; tb = 15'b000000000000000;
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$monitor("IN: %b, %b ", ta, tb, "OUT: ", y);
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#5 ta = 15'b011010010110010; tb = 15'b000000000000000;
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$monitor("IN: %b, %b ", ta, tb, "OUT: ", y);
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#5 ta = 15'b000000000000000; tb = 15'b100010110101110;
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$monitor("IN: %b, %b ", ta, tb, "OUT: ", y);
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#5 ta = 15'b111111111111111; tb = 15'b111111111111111;
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$monitor("IN: %b, %b ", ta, tb, "OUT: ", y);
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end
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endmodule |