Erick
15 lines
281 B
Verilog
15 lines
281 B
Verilog
'include "gates/nand16.v"
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module nand3way16(y16, a16, b16, c16);
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input [15:0]a16;
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input [15:0]b16;
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input [15:0]c16;
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output [15:0]y16;
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wire tmp0[15:0], tmp1[15:0]
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nand16(tmp0, a16, b16);
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nand16(tmp1, tmp0, tmp0);
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nand16(y16, tmp1, c16);
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endmodule |