Erick
15 lines
375 B
Systemverilog
15 lines
375 B
Systemverilog
'include "gates/nand3way16.v"
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import sr_flipflop::*;
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package jk_flipflop (
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output [15:0]jkq, [15:0]jkq_compl
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input [15:0]j, [15:0]k, [15:0]clk //FIXME: is 26bit clock correct? Like can it go only as 0000000000000000 and 1111111111111111?
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);
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nand3way16(notS, jkq_compl, j, clk);
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nand3way16(notR, jkq, k, clk);
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sr_flipflop(jkq, jkq_compl, notS, notR);
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endpackage |