11 lines
187 B
Systemverilog
11 lines
187 B
Systemverilog
'include "gates/nand16.v"
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package sr_flipflop (
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output [15:0]srq, [15:0]srq_compl
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input [15:0]s, [15:0]r
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);
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nand16 nand0(q, s, q_compl);
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nand16 nand1(q_compl, r, q);
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endpackage |