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iceberg/memory/flipflop/sr_flipflop.sv
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2022-03-08 13:54:42 +01:00

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Systemverilog

'include "gates/nand16.v"
package sr_flipflop (
output [15:0]srq, [15:0]srq_compl
input [15:0]s, [15:0]r
);
nand16 nand0(q, s, q_compl);
nand16 nand1(q_compl, r, q);
endpackage