Erick
21 lines
327 B
Systemverilog
21 lines
327 B
Systemverilog
'include "cpu/alu/adder.sv"
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module adder16 (
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output [15:0]sum_bit,
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output [15:0]carry_bit
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input [15:0]a,
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input [15:0]b,
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input [15:0]c,
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);
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halfadder(tmpXor0, tmpAnd0, a, b)
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xor sum_final(sum_bit, tmpXor0, c);
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and carry_tmp0(tmpAnd1, tmpXor0, c);
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or carry_final(carry_bit, tmpAnd0, tmpAnd1);
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endmodule
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