Erick
32 lines
1.1 KiB
Verilog
32 lines
1.1 KiB
Verilog
'include "predefined/mux.v"
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module mux_tb();
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reg a,b, sel;
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output y;
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mux dut(a, b, sel, y);
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initial begin
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a = 0; b = 0; sel = 0;
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$monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
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#5;
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a = 1; b = 0; sel = 0;
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$monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
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#5;
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a = 0; b = 1; sel = 0;
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$monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
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#5;
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a = 1; b = 1; sel = 0;
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$monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
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#5;
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a = 0; b = 0; sel = 1;
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$monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
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#5;
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a = 1; b = 0; sel = 1;
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$monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
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#5;
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a = 0; b = 1; sel = 1;
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$monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
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#5;
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a = 1; b = 1; sel = 1;
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$monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
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end
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endmodule |