Erick
20 lines
617 B
Verilog
20 lines
617 B
Verilog
'include "predefined/demux.v"
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module demux_tb();
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reg a,b, sel;
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output y;
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demux dut(y, z, a, sel);
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initial begin
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a = 0; sel = 0;
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$monitor("IN: %b ",a, "SEL: ",sel, " OUT: a: %b, b: %b", y, z);
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#5;
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a = 1;sel = 0;
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$monitor("IN: %b ",a, "SEL: ",sel, " OUT: a: %b, b: %b", y, z);
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#5;
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a = 0; sel = 1;
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$monitor("IN: %b ",a, "SEL: ",sel, " OUT: a: %b, b: %b", y, z);
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#5;
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a = 1; sel = 1;
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$monitor("IN: %b ",a, "SEL: ",sel, " OUT: a: %b, b: %b", y, z);
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end
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endmodule |