diff --git a/src/timer.inc b/src/timer.inc
index ce8985d..993e17c 100644
--- a/src/timer.inc
+++ b/src/timer.inc
@@ -3,8 +3,13 @@ timer0_set:
     ldi     r16,        (1 << WGM01)        ; Load 00000010 to register (bit 1=CTC)
     out     TCCR0A,     r16                 ; On T/C Control Register A, enable CTC and
 
-    ldi     r16,        244                             ; Load counter target limit value (ticks)
-    out     OCR0A,      r16                             ; Compare target to current counter
+    ldi     r16,        244                 ; Load counter target limit value (ticks)
+    out     OCR0A,      r16                 ; Compare target to current counter
+
+    ldi     r16,        (1 << OCIE0A)       ; Output Compare Match A Interrupt Enable
+    out     TIMSK,      r16                 ; Allow Timer0 to interrupt (mask register)
+
+    ret
 
 ; Timer1 will be dynamically changed in main (tempo)
 timer1_set: