diff --git a/src/timer.inc b/src/timer.inc index c327e5b..db45f4f 100644 --- a/src/timer.inc +++ b/src/timer.inc @@ -15,18 +15,31 @@ timer0_set: ret -; Timer1 will be dynamically changed in main (tempo) -;timer1_set: - ; Load 10011011 to register: - ; CTC1 (Bit 7): Reset timer to 0 when it matches OCR1C - ; COM1A0 (Bit 4): Toggle OC1A (PB1) when it matches OCR1A - ; CS13, CS11, CS10 (Bits 3,1,0): Prescaler 1024 (1011) -; ldi r17, (1 << CTC1) | (1 << COM1A0) | (1 << CS13) | (1 << CS11) | (1 << CS10) -; out TCCR1, r16 ; On T/C Control Register 1, enable: CTC1 COM1A0 CS13 CS11 CS10 +.MACRO SET_BPM target_high, target_low + ldi r20, \target_high + ldi r19, \target_low +.endm -;timer1_use: -; ldi r17, 256 ; Load counter total value (ticks) -; ldi r17, 5 ; Load counter on value (ticks) - ; //TODO: change r17 on main and then call timer1_dyn to use the value already on r16 (so its dynamic) -; out OCR1C, r17 ; Compare target to current counter (frequency) -; out OCR1A, r17 ; Compare target to current counter (phase shift) +; ISR +timer1_isr: + in r21, SREG + push r21 + + ldi r21, 255 ; Phase increment (quantization) + add r17, r21 ; Add low byte to accumulator + adc r18, r1 ; Add high byte to accumulator + + cp r18, r20 ; Compare HB accumulator vs HB target + cpc r17, r19 ; Compare LB accumulator vs LB target + brlo .exit ; Exit if accumulator < target + + ;rjump send_midi (rjump or macro, let's see later...) + + ; To correct any overshoot of acc: + sub r17, r19 ; Subtract LB target from LB accumulator + sbc r18, r20 ; Subtract HB target from HB accumulator + +.exit: + pop r21 + out SREG, r21 + reti