From e74d9369e14c61b20dcc2c6453d2ac2f31069737 Mon Sep 17 00:00:00 2001 From: Erick Ahmed Date: Fri, 26 Dec 2025 22:07:17 +0100 Subject: [PATCH] Make comments more clear --- src/led.inc | 11 +++++++---- src/timer.inc | 34 +++++++++++++++++++--------------- 2 files changed, 26 insertions(+), 19 deletions(-) diff --git a/src/led.inc b/src/led.inc index c709726..766523e 100644 --- a/src/led.inc +++ b/src/led.inc @@ -1,8 +1,11 @@ +; Registers: +; r16: timer0 start and stop operations + start_blink: - ldi r16, (1 << OCF0A) ; Clear timer status flag + ldi r16, (1 << OCF0A) ; Write Output Compare Flag 0 A to 1 out TIFR, r16 ; Clear Timer0 interrupt flag register - clr r16 ; Clear register + clr r16 ; Cleanup register out TCNT0, r16 ; Reset Counter to 0 ldi r16, (1 << CS02) | (1 << CS00) ; Load prescaler value (00000101 = prescaler 1024) @@ -16,9 +19,9 @@ stop_blink: cbi PORTB, PB0 ; Set LED off clr r16 ; Cleanup register - out TCCR0B, r16 ; Stop timer0 by clearing prescaler + out TCCR0B, r16 ; Stop timer0 by clearing prescaler ldi r16, (1 << OCF0A) - out TIFR, r16 ; Clear Timer0 interrupt flag register + out TIFR, r16 ; Clear timer0 interrupt flag register reti diff --git a/src/timer.inc b/src/timer.inc index 993e17c..c327e5b 100644 --- a/src/timer.inc +++ b/src/timer.inc @@ -1,28 +1,32 @@ -; Timer0 is static and used for the led +; Registers: +; r16: timer0 setup (can reuse after ret) +; r17: timer1 dynamic setup (always needed) + +; Timer0 (static, low precision) timer0_set: - ldi r16, (1 << WGM01) ; Load 00000010 to register (bit 1=CTC) - out TCCR0A, r16 ; On T/C Control Register A, enable CTC and + ldi r16, (1 << WGM01) ; Write CTC (Clear Timer on Compare) to 1 + out TCCR0A, r16 ; On T/C Control Register A enable CTC waveform ldi r16, 244 ; Load counter target limit value (ticks) - out OCR0A, r16 ; Compare target to current counter + out OCR0A, r16 ; Load target for compatison with TCNT0 - ldi r16, (1 << OCIE0A) ; Output Compare Match A Interrupt Enable - out TIMSK, r16 ; Allow Timer0 to interrupt (mask register) + ldi r16, (1 << OCIE0A) ; Write Compare Match A Interrupt Enable to 1 + out TIMSK, r16 ; Allow Timer0 to interrupt ret ; Timer1 will be dynamically changed in main (tempo) -timer1_set: +;timer1_set: ; Load 10011011 to register: ; CTC1 (Bit 7): Reset timer to 0 when it matches OCR1C ; COM1A0 (Bit 4): Toggle OC1A (PB1) when it matches OCR1A ; CS13, CS11, CS10 (Bits 3,1,0): Prescaler 1024 (1011) - ldi r16, (1 << CTC1) | (1 << COM1A0) | (1 << CS13) | (1 << CS11) | (1 << CS10) - out TCCR1, r16 ; On T/C Control Register 1, enable: CTC1 COM1A0 CS13 CS11 CS10 +; ldi r17, (1 << CTC1) | (1 << COM1A0) | (1 << CS13) | (1 << CS11) | (1 << CS10) +; out TCCR1, r16 ; On T/C Control Register 1, enable: CTC1 COM1A0 CS13 CS11 CS10 -timer1_use: - ldi r16, 256 ; Load counter total value (ticks) - ldi r16, 5 ; Load counter on value (ticks) - ; //TODO: change r16 on main and then call timer1_dyn to use the value already on r16 (so its dynamic) - out OCR1C, r16 ; Compare target to current counter (frequency) - out OCR1A, r16 ; Compare target to current counter (phase shift) +;timer1_use: +; ldi r17, 256 ; Load counter total value (ticks) +; ldi r17, 5 ; Load counter on value (ticks) + ; //TODO: change r17 on main and then call timer1_dyn to use the value already on r16 (so its dynamic) +; out OCR1C, r17 ; Compare target to current counter (frequency) +; out OCR1A, r17 ; Compare target to current counter (phase shift)