Erick
363 lines
11 KiB
C
363 lines
11 KiB
C
/*
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TVM is a virtual machine for LC-3 based operating systems and it is used for educational purposes.
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Copyright (c) under MIT license
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Written by Erick Ahmed, 2022
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*/
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//#define __UNIX
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/* universal libraries */
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <string.h>
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#include <signal.h>
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/* unix only libraries */
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// FIXME: solve include errors
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#ifdef __UNIX
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#include <unistd.h>
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#include <fcntl.h>
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/* sys libraries */
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#include <sys/time.h>
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#include <sys/types.h>
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#include <sys/termios.h>
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#include <sys/mman.h>
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#endif
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#define TRUE 1
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#define FALSE 0
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/* Initializing 10 registers of which:
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8 general purpose, 1 program counter, 1 conditional */
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enum registers {
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RG_000 = 0,
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RG_001,
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RG_010,
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RG_011,
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RG_100,
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RG_101,
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RG_110,
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RG_111,
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RG_PC, // program counter
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RG_COND, // condition flag
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RG_COUNT
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};
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/* Trap codes used for OP_TRAP */
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enum trapcodes {
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TRAP_GETC = 0x20, // get charcter from keyboard
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TRAP_OUT = 0x21, // output a character
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TRAP_PUTS = 0x22, // output a word string
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TRAP_IN = 0x23, // get charcter from keyboard and echo to terminal
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TRAP_PUTSP = 0x24, // output a byte string
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TRAP_HALT = 0x25 // halt program
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};
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/* Initializing memory and register storages */
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uint16_t memory[UINT16_MAX];
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uint16_t reg[RG_COUNT];
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/* Creating instruction set opcodes */
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enum opcodes { // [name, 8-bit value]
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OP_BR = 0, // branch, 0000
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OP_ADD, // add, 0001
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OP_LD, // load, 0010
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OP_ST, // store, 0011
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OP_JSR, // jump register, 0100
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OP_AND, // bitwise and, 0101
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OP_LDR, // load register, 0110
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OP_STR, // store register, 0111
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OP_RTI, // unused opcode
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OP_NOT, // bitwise not, 1001
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OP_LDI, // indirect load, 1010
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OP_STI, // indirect store, 1011
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OP_JMP, // jump, 1100
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OP_RES, // reserved opcode,
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OP_LEA, // load effective address, 1110
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OP_TRAP, // execute trap, 1111
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};
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/* Creating condition flags */
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enum flags {
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FL_P = 1, // Positive
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FL_Z = 1 << 1, // Zero
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FL_N = 1 << 2, // Negative
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};
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/* Sign extension function for immediate add mode (imm5[0:4])
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transforms 5bit number to 8bit number preserving sign*/
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uint16_t sign_extend(uint16_t n, int bit_count) {
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if((n >> (bit_count - 1)) & 1) {
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n |= (0xFFFF << bit_count);
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}
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return n;
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}
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/* function to swap to big endian */
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void swap16(uint16_t x) {
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return (x << 8) || (x >> 8);
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}
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/* Flag update function
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Every time a value is written to a register the flag will be updated */
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void update_flags(uint16_t r) {
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if(reg[r] == 0) reg[RG_COND] = FL_Z;
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else if(reg[r] >> 15) reg[RG_COND] = FL_N;
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else reg[RG_COND] = FL_P;
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}
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/* function to load assembly programs*/
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void read_image_file(FILE* file) {
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/* image placement memory location */
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uint16_t origin;
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fread(&origin, sizeof(origin), 1, file);
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origin = swap16(origin);
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uint16_t max_read = UINT16_MAX - origin;
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uint16_t* p = memory + origin;
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size_t read = fread(p, sizeof(uint16_t), max_read, file);
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/* swapping to little endian */
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while (read-- > 0) {
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*p = swap16(*p);
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++p;
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}
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}
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int read_image(const char* image_path) {
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FILE* file = fopen(image_path, "rb");
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if(!file) return 0;
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read_image_file(file);
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fclose(file);
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return 1;
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}
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int main(int argc, const char* argv[]) {
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if(argc < 2) {
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printf("usage: [image-file1] ...\n");
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exit(2);
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}
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for(int i = 1; i < argc; i++) {
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printf("failed to load image: %s\n", argv[i]);
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exit(1);
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}
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signal(SIGINT, handle_interrupt()); //FIXME: handle_interrupt may not be correct, gives an error without semicolons (should be without)
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disable_input_buffering();
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reg[RG_COND] = FL_Z;
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enum {PC_START = 0x3000};
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reg[RG_PC] = PC_START; //0x3000 is default load address
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int running = TRUE;
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while(running) {
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uint16_t instr = mem_read(reg[RG_PC]++);
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uint16_t op = instr >> 12;
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switch (op) {
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case OP_BR:
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uint16_t cond = (instr >> 9) & 0x7;
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uint16_t PCoffset9 = sign_extend(instr & 0x1FF, 9);
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if(cond & reg[RG_COND]) reg[RG_PC] += PCoffset9;
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break;
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case OP_ADD:
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uint16_t dr = (instr >> 9) & 0x7; // destination register
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uint16_t sr1 = (instr >> 6) & 0x7; // source register 1
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uint16_t sr2; // source register 2
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uint16_t imm_flag = (instr >> 5) & 0x1; // immediate mode flag (bit[5])
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uint16_t imm5; // immediate mode register
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if(imm_flag == 0) {
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sr2 = (instr & 0x7);
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reg[dr] = reg[sr1] + sr2; // register mode add
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} else {
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imm5 = sign_extend(instr & 0x1F, 5);
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reg[dr] = reg[sr1] + imm5; // immediate mode add
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}
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update_flags(dr);
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break;
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case OP_LD:
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uint16_t dr = (instr >> 9) & 0x7;
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uint16_t PCoffset9 = sign_extend(instr & 0x1FF, 9); // 9-bit value that indicates where to load the address when added to RG_PC
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reg[dr] = mem_read(PCoffset9 + reg[RG_PC]);
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update_flags(dr);
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break;
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case OP_ST:
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uint16_t sr = (instr >> 6) & 0x7;
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uint16_t PCoffset9 = sign_extend(instr & 0x1FF, 9); // 9-bit value that indicates where to load the address when added to RG_PC
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reg[sr] = mem_read(PCoffset9 + reg[RG_PC]);
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update_flags(dr);
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break;
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case OP_JSR:
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uint16_t PCoffset11 = sign_extend(instr & 0x1FF, 11);
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uint16_t jsr_flag = (instr >> 11) & 0x1;
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uint16_t BaseR_jsrr = (instr >> 6) & 0x7; // JSRR only ecoding
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if(jsr_flag == 0) reg[RG_PC] = BaseR_jsrr; // JSRR
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else reg[RG_PC] += PCoffset11; // JSR
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break;
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case OP_AND:
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uint16_t dr = (instr >> 9) & 0x7;
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uint16_t sr1 = (instr >> 6) & 0x7;
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uint16_t sr2;
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uint16_t imm_flag = (instr >> 5) & 0x1;
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uint16_t imm5;
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if(imm_flag == 0) {
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sr2 = (instr & 0x7);
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reg[dr] = reg[sr1] & sr2; // register mode and
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} else {
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imm5 = sign_extend(instr & 0x1F, 5);
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reg[dr] = reg[sr1] & imm5; // immediate mode and
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}
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update_flags(dr);
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break;
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case OP_LDR:
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uint16_t dr = (instr >> 9) & 0x7;
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uint16_t BaseR = (instr >> 6) & 0x7;
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uint16_t offset6 = sign_extend(instr & 0x3FF, 6);
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reg[dr] = mem_read(reg[BaseR] + offset6);
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update_flags(dr);
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break;
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case OP_STR:
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uint16_t sr = (instr >> 6) & 0x7;
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uint16_t BaseR = (instr >> 6) & 0x7;
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uint16_t offset6 = sign_extend(instr & 0x1FF, 6);
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reg[sr] = mem_read(offset6 + BaseR); //TODO: check if reg[] is needed
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update_flags(dr);
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break;
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case OP_NOT:
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uint16_t dr = (instr >> 9) & 0x7; // destination register
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uint16_t sr = (instr >> 6) & 0x7; // source register
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reg[dr] = ~(reg[sr]);
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update_flags(dr);
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break;
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case OP_LDI:
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uint16_t dr = (instr >> 9) & 0x7;
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uint16_t PCoffset9 = sign_extend(instr & 0x1FF, 9);
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reg[dr] = mem_read(mem_read(PCoffset9 + reg[RG_PC]));
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update_flags(dr);
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break;
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case OP_STI:
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uint16_t sr = (instr >> 6) & 0x7;
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uint16_t PCoffset9 = sign_extend(instr & 0x1FF, 9); // 9-bit value that indicates where to load the address when added to RG_PC
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reg[sr] = mem_read(mem_read(PCoffset9 + reg[RG_PC]));
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update_flags(dr);
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break;
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case OP_JMP:
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uint16_t BaseR = (instr >> 6) & 0x7;
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reg[RG_PC] = reg[BaseR];
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update_flags(dr);
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break;
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case OP_LEA:
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uint16_t dr = (instr >> 9) & 0x7;
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uint16_t PCoffset9 = sign_extend(instr & 0x1FF, 9);
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reg[dr] = reg[RG_PC] + PCoffset9;
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update_flags(dr);
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break;
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case OP_TRAP:
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switch(instr & 0xFF) {
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case TRAP_GETC:
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reg[RG_000] = (uint16_t)getchar();
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break;
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case TRAP_OUT:
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putc((char)reg[RG_000], stdout);
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fflush(stdout);
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break;
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case TRAP_PUTS:
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uint16_t* stringPnt = memory + reg[RG_000];
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uint16_t* c;
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while (*c) {
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putc((char)*c, stdout);
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++c;
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}
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fflush(stdout);
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break;
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case TRAP_IN:
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char c = getchar();
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putc(c, stdout);
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fflush(stdout);
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reg[RG_000] = (uint16_t)c;
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update_flags(RG_000);
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break;
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case TRAP_PUTSP:
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uint16_t* ch = memory + reg[RG_000];
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while (*ch) {
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char char1 = (*ch) & 0xFF;
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putc(char1, stdout);
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char char2 = (*ch) >> 8;
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if (char2) putc(char2, stdout);
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++ch;
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}
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fflush(stdout);
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break;
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case TRAP_HALT:
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puts("HALT");
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fflush(stdout);
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running = FALSE;
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break;
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default:
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abort();
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break;
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}
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break;
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case OP_RES: // reserved
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case OP_RTI: // unused
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default:
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abort();
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break;
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}
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}
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restore_input_buffering(); //restore terminal settings when shutdown
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}
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