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Erick
2026-04-17 17:00:52 +02:00
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package/boot/uboot-zyxel/files/cpu/rt2880/Makefile
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#
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a
START = start.o
SOBJS-y = cache.o lowlevel_init.o
COBJS-y = rt2880_soc.o cpu.o interrupts.o
SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
START := $(addprefix $(obj),$(START))
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
package/boot/uboot-zyxel/files/cpu/rt2880/cache.S
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/*
* Cache-handling routined for MIPS CPUs
*
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/cacheops.h>
#define RA t8
/*
* 16kB is the maximum size of instruction and data caches on MIPS 4K,
* 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience.
*
* Note that the above size is the maximum size of primary cache. U-Boot
* doesn't have L2 cache support for now.
*/
#define MIPS_MAX_CACHE_SIZE 0x10000
#define INDEX_BASE CKSEG0
.macro cache_op op addr
.set push
.set noreorder
.set mips3
cache \op, 0(\addr)
.set pop
.endm
/*
* cacheop macro to automate cache operations
* first some helpers...
*/
#define _mincache(size, maxsize) \
bltu size,maxsize,9f ; \
move size,maxsize ; \
9:
#define _align(minaddr, maxaddr, linesize) \
.set noat ; \
subu AT,linesize,1 ; \
not AT ; \
and minaddr,AT ; \
addu maxaddr,-1 ; \
and maxaddr,AT ; \
.set at
/* general operations */
#define doop1(op1) \
cache op1,0(a0)
#define doop2(op1, op2) \
cache op1,0(a0) ; \
nop ; \
cache op2,0(a0)
/* specials for cache initialisation */
#define doop1lw(op1) \
lw zero,0(a0)
#define doop1lw1(op1) \
cache op1,0(a0) ; \
lw zero,0(a0) ; \
cache op1,0(a0)
#define doop121(op1,op2) \
cache op1,0(a0) ; \
nop; \
cache op2,0(a0) ; \
nop; \
cache op1,0(a0)
#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
.set noreorder ; \
10: doop##tag##ops ; \
bne minaddr,maxaddr,10b ; \
add minaddr,linesize ; \
.set reorder
/* finally the cache operation macros */
#define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
blez n,11f ; \
addu n,kva ; \
_align(kva, n, cacheLineSize) ; \
_oploopn(kva, n, cacheLineSize, tag, ops) ; \
11:
#define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
_mincache(n, cacheSize); \
blez n,11f ; \
addu n,kva ; \
_align(kva, n, cacheLineSize) ; \
_oploopn(kva, n, cacheLineSize, tag, ops) ; \
11:
#define vcacheop(kva, n, cacheSize, cacheLineSize, op) \
vcacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
#define icacheop(kva, n, cacheSize, cacheLineSize, op) \
icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
.macro f_fill64 dst, offset, val
LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
#if LONGSIZE == 4
LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
#endif
.endm
/*
* mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
*/
LEAF(mips_init_icache)
blez a1, 9f
mtc0 zero, CP0_TAGLO
/* clear tag to invalidate */
PTR_LI t0, INDEX_BASE
PTR_ADDU t1, t0, a1
1: cache_op Index_Store_Tag_I t0
PTR_ADDU t0, a2
bne t0, t1, 1b
/* fill once, so data field parity is correct */
PTR_LI t0, INDEX_BASE
2: cache_op Fill t0
PTR_ADDU t0, a2
bne t0, t1, 2b
/* invalidate again - prudent but not strictly neccessary */
PTR_LI t0, INDEX_BASE
1: cache_op Index_Store_Tag_I t0
PTR_ADDU t0, a2
bne t0, t1, 1b
9: jr ra
END(mips_init_icache)
/*
* mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
*/
LEAF(mips_init_dcache)
blez a1, 9f
mtc0 zero, CP0_TAGLO
/* clear all tags */
PTR_LI t0, INDEX_BASE
PTR_ADDU t1, t0, a1
1: cache_op Index_Store_Tag_D t0
PTR_ADDU t0, a2
bne t0, t1, 1b
/* load from each line (in cached space) */
PTR_LI t0, INDEX_BASE
2: LONG_L zero, 0(t0)
PTR_ADDU t0, a2
bne t0, t1, 2b
/* clear all tags */
PTR_LI t0, INDEX_BASE
1: cache_op Index_Store_Tag_D t0
PTR_ADDU t0, a2
bne t0, t1, 1b
9: jr ra
END(mips_init_dcache)
/*******************************************************************************
*
* mips_cache_reset - low level initialisation of the primary caches
*
* This routine initialises the primary caches to ensure that they
* have good parity. It must be called by the ROM before any cached locations
* are used to prevent the possibility of data with bad parity being written to
* memory.
* To initialise the instruction cache it is essential that a source of data
* with good parity is available. This routine
* will initialise an area of memory starting at location zero to be used as
* a source of parity.
*
* RETURNS: N/A
*
*/
NESTED(mips_cache_reset, 0, ra)
move RA, ra
li t2, CONFIG_SYS_ICACHE_SIZE
li t3, CONFIG_SYS_DCACHE_SIZE
li t4, CONFIG_SYS_CACHELINE_SIZE
move t5, t4
li v0, MIPS_MAX_CACHE_SIZE
/*
* Now clear that much memory starting from zero.
*/
PTR_LI a0, CKSEG1
PTR_ADDU a1, a0, v0
2: PTR_ADDIU a0, 64
f_fill64 a0, -64, zero
bne a0, a1, 2b
/*
* The caches are probably in an indeterminate state,
* so we force good parity into them by doing an
* invalidate, load/fill, invalidate for each line.
*/
/*
* Assume bottom of RAM will generate good parity for the cache.
*/
/*
* Initialize the I-cache first,
*/
move a1, t2
move a2, t4
PTR_LA t7, mips_init_icache
jalr t7
/*
* then initialize D-cache.
*/
move a1, t3
move a2, t5
PTR_LA t7, mips_init_dcache
jalr t7
jr RA
END(mips_cache_reset)
/*******************************************************************************
*
* dcache_status - get cache status
*
* RETURNS: 0 - cache disabled; 1 - cache enabled
*
*/
LEAF(dcache_status)
mfc0 t0, CP0_CONFIG
li t1, CONF_CM_UNCACHED
andi t0, t0, CONF_CM_CMASK
move v0, zero
beq t0, t1, 2f
li v0, 1
2: jr ra
END(dcache_status)
/*******************************************************************************
*
* dcache_disable - disable cache
*
* RETURNS: N/A
*
*/
LEAF(dcache_disable)
mfc0 t0, CP0_CONFIG
li t1, -8
and t0, t0, t1
ori t0, t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG
jr ra
END(dcache_disable)
/*******************************************************************************
*
* dcache_enable - enable cache
*
* RETURNS: N/A
*
*/
LEAF(dcache_enable)
mfc0 t0, CP0_CONFIG
ori t0, CONF_CM_CMASK
xori t0, CONF_CM_CMASK
ori t0, CONF_CM_CACHABLE_NONCOHERENT
mtc0 t0, CP0_CONFIG
jr ra
END(dcache_enable)
#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS
/*******************************************************************************
*
* mips_cache_lock - lock RAM area pointed to by a0 in cache.
*
* RETURNS: N/A
*
*/
#if defined(CONFIG_PURPLE)
# define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE/2)
#else
# define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE)
#endif
.globl mips_cache_lock
.ent mips_cache_lock
mips_cache_lock:
li a1, CKSEG0 - CACHE_LOCK_SIZE
addu a0, a1
li a2, CACHE_LOCK_SIZE
li a3, CONFIG_SYS_CACHELINE_SIZE
move a1, a2
icacheop(a0,a1,a2,a3,0x1d)
jr ra
.end mips_cache_lock
#endif /* CONFIG_SYS_INIT_RAM_LOCK_MIPS */
package/boot/uboot-zyxel/files/cpu/rt2880/config.mk
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#
# (C) Copyright 2003
# Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
v=$(shell $(AS) --version | grep 'GNU assembler' | egrep -o '2\.[0-9\.]+' | cut -d. -f2)
MIPSFLAGS:=$(shell \
if [ "$v" -lt "14" ]; then \
echo "-mcpu=4kc"; \
else \
echo "-march=4kc -mtune=4kc"; \
fi)
STANDALONE_LOAD_ADDR = 0x80200000 -T mipsel.lds
#ENDIANNESS = -EL
MIPSFLAGS += $(ENDIANNESS)
PLATFORM_CPPFLAGS += $(MIPSFLAGS)
package/boot/uboot-zyxel/files/cpu/rt2880/cpu.c
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/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <netdev.h>
#include <asm/mipsregs.h>
#include <asm/cacheops.h>
#include <asm/reboot.h>
#define cache_op(op,addr) \
__asm__ __volatile__( \
" .set push \n" \
" .set noreorder \n" \
" .set mips3\n\t \n" \
" cache %0, %1 \n" \
" .set pop \n" \
: \
: "i" (op), "R" (*(unsigned char *)(addr)))
void __attribute__((weak)) _machine_restart(void)
{
}
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
_machine_restart();
fprintf(stderr, "*** reset failed ***\n");
return 0;
}
void flush_cache(ulong start_addr, ulong size)
{
unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
unsigned long addr = start_addr & ~(lsize - 1);
unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
while (1) {
cache_op(Hit_Writeback_Inv_D, addr);
cache_op(Hit_Invalidate_I, addr);
if (addr == aend)
break;
addr += lsize;
}
}
void flush_dcache_range(ulong start_addr, ulong stop)
{
unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
unsigned long addr = start_addr & ~(lsize - 1);
unsigned long aend = (stop - 1) & ~(lsize - 1);
while (1) {
cache_op(Hit_Writeback_Inv_D, addr);
if (addr == aend)
break;
addr += lsize;
}
}
void invalidate_dcache_range(ulong start_addr, ulong stop)
{
unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
unsigned long addr = start_addr & ~(lsize - 1);
unsigned long aend = (stop - 1) & ~(lsize - 1);
while (1) {
cache_op(Hit_Invalidate_D, addr);
if (addr == aend)
break;
addr += lsize;
}
}
void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
{
write_c0_entrylo0(low0);
write_c0_pagemask(pagemask);
write_c0_entrylo1(low1);
write_c0_entryhi(hi);
write_c0_index(index);
tlb_write_indexed();
}
int cpu_eth_init(bd_t *bis)
{
#ifdef CONFIG_SOC_AU1X00
au1x00_enet_initialize(bis);
#endif
return 0;
}
package/boot/uboot-zyxel/files/cpu/rt2880/interrupts.c
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/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
void enable_interrupts(void)
{
}
int disable_interrupts(void)
{
return 0;
}
package/boot/uboot-zyxel/files/cpu/rt2880/lowlevel_init.S
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package/boot/uboot-zyxel/files/cpu/rt2880/rt2880_soc.c
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#include <common.h>
#include <command.h>
#include <asm/arch/rt_mmap.h>
#define SOFTRES_REG (RALINK_SYSCTL_BASE + 0x0034)
#define GORESET (0x01)
unsigned long mips_cpu_feq;
unsigned long mips_bus_feq;
void _machine_restart(void)
{
#if defined(RT6855A_FPGA_BOARD) || defined(RT6855A_ASIC_BOARD)
ra_outl(RALINK_TIMER_BASE + 0x2c, 0x1); //timer3 load value
ra_or(RALINK_TIMER_BASE, (1 << 5) | (1 << 25)); //timer3 enabled as watchdog
#else
*(volatile unsigned int*)(SOFTRES_REG) = GORESET;
#endif
}
void rt2880_freq_calculate(void)
{
u32 reg;
#ifdef ASIC_BOARD
u8 clk_sel __maybe_unused, clk_sel2 __maybe_unused;
#endif
reg = RALINK_REG(RT2880_SYSCFG_REG);
/*
* CPU_CLK_SEL (bit 21:20)
*/
#ifdef RT2880_FPGA_BOARD
mips_cpu_feq = 25 * 1000 *1000;
mips_bus_feq = mips_cpu_feq/2;
#elif defined (RT2883_FPGA_BOARD) || defined (RT3052_FPGA_BOARD) || defined (RT3352_FPGA_BOARD) || defined (RT5350_FPGA_BOARD)
mips_cpu_feq = 40 * 1000 *1000;
mips_bus_feq = mips_cpu_feq/3;
#elif defined (RT6855A_FPGA_BOARD)
mips_cpu_feq = 50 * 1000 *1000;
mips_bus_feq = mips_cpu_feq/2;
#elif defined (RT3883_FPGA_BOARD)
mips_cpu_feq = 40 * 1000 *1000;
mips_bus_feq = mips_cpu_feq;
#elif defined (RT6855_FPGA_BOARD) || defined (RT6352_FPGA_BOARD) || defined (RT71100_FPGA_BOARD)
/* FIXME */
mips_cpu_feq = 50 * 1000 *1000;
mips_bus_feq = mips_cpu_feq/4;
#elif defined (RT2883_ASIC_BOARD)
clk_sel = (reg>>20) & 0x03;
switch(clk_sel) {
case 0:
mips_cpu_feq = (380*1000*1000);
break;
case 1:
mips_cpu_feq = (400*1000*1000);
break;
case 2:
mips_cpu_feq = (420*1000*1000);
break;
case 3:
mips_cpu_feq = (430*1000*1000);
break;
}
mips_bus_feq = mips_cpu_feq/2;
#elif defined(RT3052_ASIC_BOARD)
#if defined(RT3350_ASIC_BOARD)
//MA10 is floating
mips_cpu_feq = (320*1000*1000);
#else
clk_sel = (reg>>18) & 0x01;
switch(clk_sel) {
case 0:
mips_cpu_feq = (320*1000*1000);
break;
case 1:
mips_cpu_feq = (384*1000*1000);
break;
}
#endif
mips_bus_feq = mips_cpu_feq / 3;
#elif defined(RT3352_ASIC_BOARD)
clk_sel = (reg>>8) & 0x01;
switch(clk_sel) {
case 0:
mips_cpu_feq = (384*1000*1000);
break;
case 1:
mips_cpu_feq = (400*1000*1000);
break;
}
mips_bus_feq = (133*1000*1000);
#elif defined(RT5350_ASIC_BOARD)
clk_sel2 = (reg>>10) & 0x01;
clk_sel = ((reg>>8) & 0x01) + (clk_sel2 * 2);
switch(clk_sel) {
case 0:
mips_cpu_feq = (360*1000*1000);
mips_bus_feq = (120*1000*1000);
break;
case 1:
//reserved
break;
case 2:
mips_cpu_feq = (320*1000*1000);
mips_bus_feq = (80*1000*1000);
break;
case 3:
mips_cpu_feq = (300*1000*1000);
mips_bus_feq = (100*1000*1000);
break;
}
#elif defined(RT6855_ASIC_BOARD)
mips_cpu_feq = (400*1000*1000);
mips_bus_feq = (133*1000*1000);
#elif defined (RT6855A_ASIC_BOARD)
/* FPGA is 25/32Mhz
* ASIC RT6856/RT6856A: DDR(0): 233.33, DDR(1): 175, SDR: 140
* RT6855/RT6855A: DDR(0): 166.67, DDR(1): 125, SDR: 140 */
reg = RALINK_REG(RT2880_SYSCFG_REG);
if ((reg & (1 << 25)) == 0) { /* SDR */
if ((reg & (1 << 9)) != 0)
mips_cpu_feq = (560*1000*1000);
else {
if ((reg & (1 << 26)) != 0)
mips_cpu_feq = (560*1000*1000);
else
mips_cpu_feq = (420*1000*1000);
}
mips_bus_feq = (140*1000*1000);
} else { /* DDR */
if ((reg & (1 << 9)) != 0) {
mips_cpu_feq = (700*1000*1000);
if ((reg & (1 << 26)) != 0)
mips_bus_feq = (175*1000*1000);
else
mips_bus_feq = 233333333;
} else {
mips_cpu_feq = (500*1000*1000);
if ((reg & (1 << 26)) != 0)
mips_bus_feq = (125*1000*1000);
else
mips_bus_feq = 166666667;
}
}
#elif defined(RT6352_ASIC_BOARD)
/* FIXME */
mips_cpu_feq = (600*1000*1000);
mips_bus_feq = (133*1000*1000);
#elif defined(RT71100_ASIC_BOARD)
/* FIXME */
mips_cpu_feq = (800*1000*1000);
mips_bus_feq = (133*1000*1000);
#elif defined (RT3883_ASIC_BOARD)
clk_sel = (reg>>8) & 0x03;
switch(clk_sel) {
case 0:
mips_cpu_feq = (250*1000*1000);
break;
case 1:
mips_cpu_feq = (384*1000*1000);
break;
case 2:
mips_cpu_feq = (480*1000*1000);
break;
case 3:
mips_cpu_feq = (500*1000*1000);
break;
}
#if defined (CFG_ENV_IS_IN_SPI)
if ((reg>>17) & 0x1) { //DDR2
switch(clk_sel) {
case 0:
mips_bus_feq = (125*1000*1000);
break;
case 1:
mips_bus_feq = (128*1000*1000);
break;
case 2:
mips_bus_feq = (160*1000*1000);
break;
case 3:
mips_bus_feq = (166*1000*1000);
break;
}
}
else {
switch(clk_sel) {
case 0:
mips_bus_feq = (83*1000*1000);
break;
case 1:
mips_bus_feq = (96*1000*1000);
break;
case 2:
mips_bus_feq = (120*1000*1000);
break;
case 3:
mips_bus_feq = (125*1000*1000);
break;
}
}
#elif defined ON_BOARD_SDR
switch(clk_sel) {
case 0:
mips_bus_feq = (83*1000*1000);
break;
case 1:
mips_bus_feq = (96*1000*1000);
break;
case 2:
mips_bus_feq = (120*1000*1000);
break;
case 3:
mips_bus_feq = (125*1000*1000);
break;
}
#elif defined ON_BOARD_DDR2
switch(clk_sel) {
case 0:
mips_bus_feq = (125*1000*1000);
break;
case 1:
mips_bus_feq = (128*1000*1000);
break;
case 2:
mips_bus_feq = (160*1000*1000);
break;
case 3:
mips_bus_feq = (166*1000*1000);
break;
}
#else
#error undef SDR or DDR
#endif
#else /* RT2880 ASIC version */
clk_sel = (reg>>20) & 0x03;
switch(clk_sel) {
#ifdef RT2880_MP
case 0:
mips_cpu_feq = (250*1000*1000);
break;
case 1:
mips_cpu_feq = (266*1000*1000);
break;
case 2:
mips_cpu_feq = (280*1000*1000);
break;
case 3:
mips_cpu_feq = (300*1000*1000);
break;
#else
case 0:
mips_cpu_feq = (233*1000*1000);
break;
case 1:
mips_cpu_feq = (250*1000*1000);
break;
case 2:
mips_cpu_feq = (266*1000*1000);
break;
case 3:
mips_cpu_feq = (280*1000*1000);
break;
#endif
}
mips_bus_feq = mips_cpu_feq/2;
#endif
//RALINK_REG(RT2880_SYSCFG_REG) = reg;
/* in general, the spec define 8192 refresh cycles/64ms
* 64ms/8192 = 7.8us
* 7.8us * 106.7Mhz(SDRAM clock) = 832
* the value of refresh cycle shall smaller than 832.
* so we config it at 0x300 (suggested by ASIC)
*/
#if defined(ON_BOARD_SDR) && defined(ON_BOARD_256M_DRAM_COMPONENT)
{
u32 tREF;
tREF = RALINK_REG(SDRAM_CFG1_REG);
tREF &= 0xffff0000;
#if defined(ASIC_BOARD)
tREF |= 0x00000300;
#elif defined(FPGA_BOARD)
tREF |= 0x000004B;
#else
#error "not exist"
#endif
RALINK_REG(SDRAM_CFG1_REG) = tREF;
}
#endif
printf("CPU frequency: %lu\n", mips_cpu_feq);
}
package/boot/uboot-zyxel/files/cpu/rt2880/start.S
+473
View File
@@ -0,0 +1,473 @@
/*
* Startup Code for MIPS32 CPU-core
*
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/arch/rt_mmap.h>
#if defined(RT6855A_FPGA_BOARD) || defined(RT6855A_ASIC_BOARD)
#define SDRAM_CFG0_REG RALINK_MEMCTRL_BASE+ 0x0
#define SDRAM_CFG1_REG RALINK_MEMCTRL_BASE+ 0x4
#else
#define SDRAM_CFG0_REG RALINK_SYSCTL_BASE + 0x0300
#define SDRAM_CFG1_REG RALINK_SYSCTL_BASE + 0x0304
#endif
#define SDRAM_CFG0_ALWAYS_ONE ( 1 << 31)
#define SDRAM_CFG1_SDRAM_INIT_START ( 1 << 31)
#define SDRAM_CFG1_SDRAM_INIT_DONE ( 1 << 30)
#if defined(RT6855A_FPGA_BOARD) || defined(RT6855A_ASIC_BOARD)
#define SDRAM_CFG0_MIPSREG s7
#define SDRAM_CFG1_MIPSREG s8
#define DDR_CFG0_MIPSREG s7
#define DDR_CFG1_MIPSREG s8
#endif
#if defined(RT6855A_FPGA_BOARD) || defined(RT6855A_ASIC_BOARD)
#define DELAY_USEC(us) ((700*(us))/3)
#else
#define DELAY_USEC(us) ((500*(us))/3)
#endif
/*
* For the moment disable interrupts, mark the kernel mode and
* set ST0_KX so that the CPU does not spit fire when using
* 64-bit addresses.
*/
.macro setup_c0_status set clr
.set push
mfc0 t0, CP0_STATUS
or t0, ST0_CU0 | \set | 0x1f | \clr
xor t0, 0x1f | \clr
mtc0 t0, CP0_STATUS
.set noreorder
sll zero, 3 # ehb
.set pop
.endm
.macro setup_c0_status_reset
#ifdef CONFIG_64BIT
setup_c0_status ST0_KX 0
#else
setup_c0_status 0 0
#endif
.endm
#define RVECENT(f,n) \
b f; nop
#define XVECENT(f,bev) \
b f ; \
li k0,bev
.set noreorder
.globl _start
.text
_start:
RVECENT(reset,0) /* U-boot entry point */
RVECENT(reset,1) /* software reboot */
#if defined(CONFIG_INCA_IP)
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
.word 0x00000000 /* phase of the flash */
#elif defined(CONFIG_PURPLE)
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
#else
RVECENT(romReserved,2)
#endif
RVECENT(romReserved,3)
RVECENT(romReserved,4)
RVECENT(romReserved,5)
RVECENT(romReserved,6)
RVECENT(romReserved,7)
RVECENT(romReserved,8)
RVECENT(romReserved,9)
RVECENT(romReserved,10)
RVECENT(romReserved,11)
RVECENT(romReserved,12)
RVECENT(romReserved,13)
RVECENT(romReserved,14)
RVECENT(romReserved,15)
RVECENT(romReserved,16)
RVECENT(romReserved,17)
RVECENT(romReserved,18)
RVECENT(romReserved,19)
RVECENT(romReserved,20)
RVECENT(romReserved,21)
RVECENT(romReserved,22)
RVECENT(romReserved,23)
RVECENT(romReserved,24)
RVECENT(romReserved,25)
RVECENT(romReserved,26)
RVECENT(romReserved,27)
RVECENT(romReserved,28)
RVECENT(romReserved,29)
RVECENT(romReserved,30)
RVECENT(romReserved,31)
RVECENT(romReserved,32)
RVECENT(romReserved,33)
RVECENT(romReserved,34)
RVECENT(romReserved,35)
RVECENT(romReserved,36)
RVECENT(romReserved,37)
RVECENT(romReserved,38)
RVECENT(romReserved,39)
RVECENT(romReserved,40)
RVECENT(romReserved,41)
RVECENT(romReserved,42)
RVECENT(romReserved,43)
RVECENT(romReserved,44)
RVECENT(romReserved,45)
RVECENT(romReserved,46)
RVECENT(romReserved,47)
RVECENT(romReserved,48)
RVECENT(romReserved,49)
RVECENT(romReserved,50)
RVECENT(romReserved,51)
RVECENT(romReserved,52)
RVECENT(romReserved,53)
RVECENT(romReserved,54)
RVECENT(romReserved,55)
RVECENT(romReserved,56)
RVECENT(romReserved,57)
RVECENT(romReserved,58)
RVECENT(romReserved,59)
RVECENT(romReserved,60)
RVECENT(romReserved,61)
RVECENT(romReserved,62)
RVECENT(romReserved,63)
XVECENT(romExcHandle,0x200) /* bfc00200: R4000 tlbmiss vector */
RVECENT(romReserved,65)
RVECENT(romReserved,66)
RVECENT(romReserved,67)
RVECENT(romReserved,68)
RVECENT(romReserved,69)
RVECENT(romReserved,70)
RVECENT(romReserved,71)
RVECENT(romReserved,72)
RVECENT(romReserved,73)
RVECENT(romReserved,74)
RVECENT(romReserved,75)
RVECENT(romReserved,76)
RVECENT(romReserved,77)
RVECENT(romReserved,78)
RVECENT(romReserved,79)
XVECENT(romExcHandle,0x280) /* bfc00280: R4000 xtlbmiss vector */
RVECENT(romReserved,81)
RVECENT(romReserved,82)
RVECENT(romReserved,83)
RVECENT(romReserved,84)
RVECENT(romReserved,85)
RVECENT(romReserved,86)
RVECENT(romReserved,87)
RVECENT(romReserved,88)
RVECENT(romReserved,89)
RVECENT(romReserved,90)
RVECENT(romReserved,91)
RVECENT(romReserved,92)
RVECENT(romReserved,93)
RVECENT(romReserved,94)
RVECENT(romReserved,95)
XVECENT(romExcHandle,0x300) /* bfc00300: R4000 cache vector */
RVECENT(romReserved,97)
RVECENT(romReserved,98)
RVECENT(romReserved,99)
RVECENT(romReserved,100)
RVECENT(romReserved,101)
RVECENT(romReserved,102)
RVECENT(romReserved,103)
RVECENT(romReserved,104)
RVECENT(romReserved,105)
RVECENT(romReserved,106)
RVECENT(romReserved,107)
RVECENT(romReserved,108)
RVECENT(romReserved,109)
RVECENT(romReserved,110)
RVECENT(romReserved,111)
XVECENT(romExcHandle,0x380) /* bfc00380: R4000 general vector */
RVECENT(romReserved,113)
RVECENT(romReserved,114)
RVECENT(romReserved,115)
RVECENT(romReserved,116)
RVECENT(romReserved,116)
RVECENT(romReserved,118)
RVECENT(romReserved,119)
RVECENT(romReserved,120)
RVECENT(romReserved,121)
RVECENT(romReserved,122)
RVECENT(romReserved,123)
RVECENT(romReserved,124)
RVECENT(romReserved,125)
RVECENT(romReserved,126)
RVECENT(romReserved,127)
/* We hope there are no more reserved vectors!
* 128 * 8 == 1024 == 0x400
* so this is address R_VEC+0x400 == 0xbfc00400
*/
#ifdef CONFIG_PURPLE
/* 0xbfc00400 */
.word 0xdc870000
.word 0xfca70000
.word 0x20840008
.word 0x20a50008
.word 0x20c6ffff
.word 0x14c0fffa
.word 0x00000000
.word 0x03e00008
.word 0x00000000
.word 0x00000000
/* 0xbfc00428 */
.word 0xdc870000
.word 0xfca70000
.word 0x20840008
.word 0x20a50008
.word 0x20c6ffff
.word 0x14c0fffa
.word 0x00000000
.word 0x03e00008
.word 0x00000000
.word 0x00000000
#endif /* CONFIG_PURPLE */
.align 4
reset:
/* Clear watch registers.
*/
mtc0 zero, CP0_WATCHLO
mtc0 zero, CP0_WATCHHI
/* WP(Watch Pending), SW0/1 should be cleared. */
mtc0 zero, CP0_CAUSE
setup_c0_status_reset
/* Init Timer */
mtc0 zero, CP0_COUNT
mtc0 zero, CP0_COMPARE
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT)
/* CONFIG0 register */
li t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG
#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
/* Initialize $gp.
*/
bal 1f
nop
.word _gp
1:
lw gp, 0(ra)
#if defined(RT6855A_ASIC_BOARD) || defined(RT6855A_FPGA_BOARD)
la t0, RALINK_SYSCTL_BASE + 0x8C
lw t1, 0(t0)
nop
srl t2, t1, 24+1
andi t2, t2, 0x1
bnez t2, 1f
nop
la t9, rt6855A_cpu_pll
jalr t9
/* bal rt6855A_cpu_pll */
nop
1:
la t0, RALINK_SYSCTL_BASE+0x834
lw t1, 0(t0)
ori t1, t1, 1<<8
sw t1, 0(t0)
nop
la t0, RALINK_SYSCTL_BASE+0x834
lw t1, 0(t0)
li t2, ~(1<<8)
and t1, t1, t2
sw t1, 0(t0)
nop
#endif
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT)
/* Initialize any external memory.
*/
la t9, lowlevel_init
jalr t9
nop
/* Initialize caches...
*/
la t9, mips_cache_reset
jalr t9
nop
/* ... and enable them.
*/
li t0, CONF_CM_CACHABLE_NONCOHERENT
mtc0 t0, CP0_CONFIG
#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
/* Set up temporary stack.
*/
#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS
li a0, CONFIG_SYS_INIT_SP_OFFSET
la t9, mips_cache_lock
jalr t9
nop
#endif
li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
la sp, 0(t0)
la t9, board_init_f
jr t9
nop
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* a0 = addr_sp
* a1 = gd
* a2 = destination address
*/
.globl relocate_code
.ent relocate_code
relocate_code:
move sp, a0 /* Set new stack pointer */
li t0, CONFIG_SYS_MONITOR_BASE
la t3, in_ram
lw t2, -12(t3) /* t2 <-- uboot_end_data */
move t1, a2
move s2, a2 /* s2 <-- destination address */
/*
* Fix $gp:
*
* New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
*/
move t6, gp
sub gp, CONFIG_SYS_MONITOR_BASE
add gp, a2 /* gp now adjusted */
sub s1, gp, t6 /* s1 <-- relocation offset */
/*
* t0 = source address
* t1 = target address
* t2 = source end address
*/
/*
* Save destination address and size for later usage in flush_cache()
*/
move s0, a1 /* save gd in s0 */
move a0, t1 /* a0 <-- destination addr */
sub a1, t2, t0 /* a1 <-- size */
/* On the purple board we copy the code earlier in a special way
* in order to solve flash problems
*/
#ifndef CONFIG_PURPLE
1:
lw t3, 0(t0)
sw t3, 0(t1)
addu t0, 4
ble t0, t2, 1b
addu t1, 4 /* delay slot */
#endif
/* If caches were enabled, we would have to flush them here.
*/
/* a0 & a1 are already set up for flush_cache(start, size) */
la t9, flush_cache
jalr t9
nop
/* Jump to where we've relocated ourselves.
*/
addi t0, s2, in_ram - _start
jr t0
nop
.word _gp
.word _GLOBAL_OFFSET_TABLE_
.word uboot_end_data
.word uboot_end
.word num_got_entries
in_ram:
/*
* Now we want to update GOT.
*
* GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
* generated by GNU ld. Skip these reserved entries from relocation.
*/
lw t3, -4(t0) /* t3 <-- num_got_entries */
lw t4, -16(t0) /* t4 <-- _GLOBAL_OFFSET_TABLE_ */
lw t5, -20(t0) /* t5 <-- _gp */
sub t4, t5 /* compute offset*/
add t4, t4, gp /* t4 now holds relocated _GLOBAL_OFFSET_TABLE_ */
addi t4, t4, 8 /* Skipping first two entries. */
li t2, 2
1:
lw t1, 0(t4)
beqz t1, 2f
add t1, s1
sw t1, 0(t4)
2:
addi t2, 1
blt t2, t3, 1b
addi t4, 4 /* delay slot */
/* Clear BSS.
*/
lw t1, -12(t0) /* t1 <-- uboot_end_data */
lw t2, -8(t0) /* t2 <-- uboot_end */
add t1, s1 /* adjust pointers */
add t2, s1
sub t1, 4
1:
addi t1, 4
bltl t1, t2, 1b
sw zero, 0(t1) /* delay slot */
move a0, s0 /* a0 <-- gd */
la t9, board_init_r
jr t9
move a1, s2 /* delay slot */
.end relocate_code
/* Exception handlers.
*/
romReserved:
b romReserved
romExcHandle:
b romExcHandle