eeeck/zyxel-vmg8825_b50b-cfw
1
1
Fork 0
Code Activity

Initial dump from Zyxel

Browse Source
This commit is contained in:
Erick
2026-04-17 17:00:52 +02:00
commit 81fec250f4
23116 changed files with 5231237 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
package/boot/uboot-zyxel/files/cpu/rt2880.old/Makefile
+44
View File
@@ -0,0 +1,44 @@
#
# (C) Copyright 2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(CPU).a
START = start.o
OBJS = cpu.o rt2880_soc.o interrupts.o
SOBJS = cache.o
all: .depend $(START) $(LIB)
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
#########################################################################
.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################
package/boot/uboot-zyxel/files/cpu/rt2880.old/cache.S
+302
View File
@@ -0,0 +1,302 @@
/*
* Cache-handling routined for MIPS 4K CPUs
*
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/cacheops.h>
#define K0BASE KSEG0
/* 16KB is the maximum size of instruction and data caches on
* MIPS 4K.
*/
#define MIPS_MAX_CACHE_SIZE 0x4000
/*
* cacheop macro to automate cache operations
* first some helpers...
*/
#define _mincache(size, maxsize) \
bltu size,maxsize,9f ; \
move size,maxsize ; \
9:
#define _align(minaddr, maxaddr, linesize) \
.set noat ; \
subu AT,linesize,1 ; \
not AT ; \
and minaddr,AT ; \
addu maxaddr,-1 ; \
and maxaddr,AT ; \
.set at
/* general operations */
#define doop1(op1) \
cache op1,0(a0)
#define doop2(op1, op2) \
cache op1,0(a0) ; \
nop ; \
cache op2,0(a0)
/* specials for cache initialisation */
#define doop1lw(op1) \
lw zero,0(a0)
#define doop1lw1(op1) \
cache op1,0(a0) ; \
lw zero,0(a0) ; \
cache op1,0(a0)
#define doop121(op1,op2) \
cache op1,0(a0) ; \
nop; \
cache op2,0(a0) ; \
nop; \
cache op1,0(a0)
#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
.set noreorder ; \
10: doop##tag##ops ; \
bne minaddr,maxaddr,10b ; \
add minaddr,linesize ; \
.set reorder
/* finally the cache operation macros */
#define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
blez n,11f ; \
addu n,kva ; \
_align(kva, n, cacheLineSize) ; \
_oploopn(kva, n, cacheLineSize, tag, ops) ; \
11:
#define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
_mincache(n, cacheSize); \
blez n,11f ; \
addu n,kva ; \
_align(kva, n, cacheLineSize) ; \
_oploopn(kva, n, cacheLineSize, tag, ops) ; \
11:
#define vcacheop(kva, n, cacheSize, cacheLineSize, op) \
vcacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
#define icacheop(kva, n, cacheSize, cacheLineSize, op) \
icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
/*******************************************************************************
*
* mips_cache_reset - low level initialisation of the primary caches
*
* This routine initialises the primary caches to ensure that they
* have good parity. It must be called by the ROM before any cached locations
* are used to prevent the possibility of data with bad parity being written to
* memory.
* To initialise the instruction cache it is essential that a source of data
* with good parity is available. This routine
* will initialise an area of memory starting at location zero to be used as
* a source of parity.
*
* RETURNS: N/A
*
*/
.globl mips_cache_reset
.ent mips_cache_reset
mips_cache_reset:
li t2, CONFIG_SYS_ICACHE_SIZE
li t3, CONFIG_SYS_DCACHE_SIZE
li t4, CONFIG_SYS_CACHELINE_SIZE
move t5, t4
#if 1
li v0, MIPS_MAX_CACHE_SIZE
/* Now clear that much memory starting from zero.
*/
li a0, KSEG1
addu a1, a0, v0
2: sw zero, 0(a0)
sw zero, 4(a0)
sw zero, 8(a0)
sw zero, 12(a0)
sw zero, 16(a0)
sw zero, 20(a0)
sw zero, 24(a0)
sw zero, 28(a0)
addu a0, 32
bltu a0, a1, 2b
nop
#endif
/* Set invalid tag.
*/
mtc0 zero, CP0_TAGLO
/*
* The caches are probably in an indeterminate state,
* so we force good parity into them by doing an
* invalidate, load/fill, invalidate for each line.
*/
/* Assume bottom of RAM will generate good parity for the cache.
*/
li a0, K0BASE
move a2, t2 # icacheSize
move a3, t4 # icacheLineSize
move a1, a2
icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill))
nop
/* To support Orion/R4600, we initialise the data cache in 3 passes.
*/
/* 1: initialise dcache tags.
*/
li a0, K0BASE
move a2, t3 # dcacheSize
move a3, t5 # dcacheLineSize
move a1, a2
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
nop
/* 2: fill dcache.
*/
li a0, K0BASE
move a2, t3 # dcacheSize
move a3, t5 # dcacheLineSize
move a1, a2
icacheopn(a0,a1,a2,a3,1lw,(dummy))
nop
/*
3: clear dcache tags.
*/
li a0, K0BASE
move a2, t3 # dcacheSize
move a3, t5 # dcacheLineSize
move a1, a2
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
nop
j ra
nop
nop
.end mips_cache_reset
/*******************************************************************************
*
* dcache_status - get cache status
*
* RETURNS: 0 - cache disabled; 1 - cache enabled
*
*/
.globl dcache_status
.ent dcache_status
dcache_status:
mfc0 v0, CP0_CONFIG
andi v0, v0, 1
j ra
.end dcache_status
/*******************************************************************************
*
* dcache_disable - disable cache
*
* RETURNS: N/A
*
*/
.globl dcache_disable
.ent dcache_disable
dcache_disable:
mfc0 t0, CP0_CONFIG
li t1, -8
and t0, t0, t1
ori t0, t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG
j ra
.end dcache_disable
/*******************************************************************************
*
* mips_cache_lock - lock RAM area pointed to by a0 in cache.
*
* RETURNS: N/A
*
*/
#if defined(CONFIG_PURPLE)
# define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE/2)
#else
# define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE)
#endif
.globl mips_cache_lock
.ent mips_cache_lock
mips_cache_lock:
j KAIKER_0
nop
nop
KAIKER_0:
li a1, K0BASE - CACHE_LOCK_SIZE
addu a0, a1
li a2, CACHE_LOCK_SIZE
li a3, CONFIG_SYS_CACHELINE_SIZE
move a1, a2
j KAIKER_1
nop
nop
KAIKER_1:
j KAIKER_11
nop
nop
KAIKER_11:
icacheop(a0,a1,a2,a3,0x1D)
j KAIKER_2
nop
nop
KAIKER_2:
j ra
.end mips_cache_lock
package/boot/uboot-zyxel/files/cpu/rt2880.old/config.mk
+36
View File
@@ -0,0 +1,36 @@
#
# (C) Copyright 2003
# Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
v=$(shell \
$(AS) --version|grep "GNU assembler"|awk -F . '{print $$2}')
MIPSFLAGS=$(shell \
if [ "$v" -lt "14" ]; then \
echo "-mcpu=4kc -mabicalls"; \
else \
echo "-march=4kc -mtune=4kc -mabicalls"; \
fi)
# Dennis Lee, Big Endian need -EB otherwise remove -EB
# echo "-mcpu=4kc -EB -mabicalls";
# echo "-march=4kc -mtune=4kc -Wa,-mips_allow_branch_to_undefined -mabicalls";
PLATFORM_CPPFLAGS += $(MIPSFLAGS)
STANDALONE_LOAD_ADDR = 0x80200000 -T mipsel.lds
package/boot/uboot-zyxel/files/cpu/rt2880.old/cpu.c
+62
View File
@@ -0,0 +1,62 @@
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/mipsregs.h>
#include <asm/arch/rt_mmap.h>
#if defined(RT6855A_FPGA_BOARD) || defined(RT6855A_ASIC_BOARD)
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
ra_outl(RALINK_TIMER_BASE + 0x2c, 0x1); //timer3 load value
ra_or(RALINK_TIMER_BASE, (1 << 5) | (1 << 25)); //timer3 enabled as watchdog
return 1;
}
#else
#define SOFTRES_REG (RALINK_SYSCTL_BASE + 0x0034)
#define GORESET (0x01)
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
*(volatile unsigned int*)(SOFTRES_REG) = GORESET;
return 1;
}
#endif
void flush_cache (ulong start_addr, ulong size)
{
}
#ifdef RT2880_U_BOOT_CMD_OPEN
void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ){
write_32bit_cp0_register(CP0_ENTRYLO0, low0);
write_32bit_cp0_register(CP0_PAGEMASK, pagemask);
write_32bit_cp0_register(CP0_ENTRYLO1, low1);
write_32bit_cp0_register(CP0_ENTRYHI, hi);
write_32bit_cp0_register(CP0_INDEX, index);
tlb_write_indexed();
}
#endif
package/boot/uboot-zyxel/files/cpu/rt2880.old/interrupts.c
+33
View File
@@ -0,0 +1,33 @@
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
void enable_interrupts(void)
{
}
int disable_interrupts(void)
{
return 0;
}
package/boot/uboot-zyxel/files/cpu/rt2880.old/rt2880_soc.c
+297
View File
@@ -0,0 +1,297 @@
#include <common.h>
#include <command.h>
#include <asm/arch/rt_mmap.h>
#define SOFTRES_REG (RALINK_SYSCTL_BASE + 0x0034)
#define GORESET (0x01)
unsigned long mips_cpu_feq;
unsigned long mips_bus_feq;
void _machine_restart(void)
{
#if defined(RT6855A_FPGA_BOARD) || defined(RT6855A_ASIC_BOARD)
ra_outl(RALINK_TIMER_BASE + 0x2c, 0x1); //timer3 load value
ra_or(RALINK_TIMER_BASE, (1 << 5) | (1 << 25)); //timer3 enabled as watchdog
#else
*(volatile unsigned int*)(SOFTRES_REG) = GORESET;
#endif
}
void rt2880_freq_calculate(void)
{
u32 reg;
#ifdef ASIC_BOARD
u8 clk_sel, clk_sel2;
#endif
reg = RALINK_REG(RT2880_SYSCFG_REG);
/*
* CPU_CLK_SEL (bit 21:20)
*/
#ifdef RT2880_FPGA_BOARD
mips_cpu_feq = 25 * 1000 *1000;
mips_bus_feq = mips_cpu_feq/2;
#elif defined (RT2883_FPGA_BOARD) || defined (RT3052_FPGA_BOARD) || defined (RT3352_FPGA_BOARD) || defined (RT5350_FPGA_BOARD)
mips_cpu_feq = 40 * 1000 *1000;
mips_bus_feq = mips_cpu_feq/3;
#elif defined (RT6855A_FPGA_BOARD)
mips_cpu_feq = 50 * 1000 *1000;
mips_bus_feq = mips_cpu_feq/2;
#elif defined (RT3883_FPGA_BOARD)
mips_cpu_feq = 40 * 1000 *1000;
mips_bus_feq = mips_cpu_feq;
#elif defined (RT6855_FPGA_BOARD) || defined (RT6352_FPGA_BOARD) || defined (RT71100_FPGA_BOARD)
/* FIXME */
mips_cpu_feq = 50 * 1000 *1000;
mips_bus_feq = mips_cpu_feq/4;
#elif defined (RT2883_ASIC_BOARD)
clk_sel = (reg>>20) & 0x03;
switch(clk_sel) {
case 0:
mips_cpu_feq = (380*1000*1000);
break;
case 1:
mips_cpu_feq = (400*1000*1000);
break;
case 2:
mips_cpu_feq = (420*1000*1000);
break;
case 3:
mips_cpu_feq = (430*1000*1000);
break;
}
mips_bus_feq = mips_cpu_feq/2;
#elif defined(RT3052_ASIC_BOARD)
#if defined(RT3350_ASIC_BOARD)
//MA10 is floating
mips_cpu_feq = (320*1000*1000);
#else
clk_sel = (reg>>18) & 0x01;
switch(clk_sel) {
case 0:
mips_cpu_feq = (320*1000*1000);
break;
case 1:
mips_cpu_feq = (384*1000*1000);
break;
}
#endif
mips_bus_feq = mips_cpu_feq / 3;
#elif defined(RT3352_ASIC_BOARD)
clk_sel = (reg>>8) & 0x01;
switch(clk_sel) {
case 0:
mips_cpu_feq = (384*1000*1000);
break;
case 1:
mips_cpu_feq = (400*1000*1000);
break;
}
mips_bus_feq = (133*1000*1000);
#elif defined(RT5350_ASIC_BOARD)
clk_sel2 = (reg>>10) & 0x01;
clk_sel = ((reg>>8) & 0x01) + (clk_sel2 * 2);
switch(clk_sel) {
case 0:
mips_cpu_feq = (360*1000*1000);
mips_bus_feq = (120*1000*1000);
break;
case 1:
//reserved
break;
case 2:
mips_cpu_feq = (320*1000*1000);
mips_bus_feq = (80*1000*1000);
break;
case 3:
mips_cpu_feq = (300*1000*1000);
mips_bus_feq = (100*1000*1000);
break;
}
#elif defined(RT6855_ASIC_BOARD)
mips_cpu_feq = (400*1000*1000);
mips_bus_feq = (133*1000*1000);
#elif defined (RT6855A_ASIC_BOARD)
/* FPGA is 25/32Mhz
* ASIC RT6856/RT6856A: DDR(0): 233.33, DDR(1): 175, SDR: 140
* RT6855/RT6855A: DDR(0): 166.67, DDR(1): 125, SDR: 140 */
reg = RALINK_REG(RT2880_SYSCFG_REG);
if ((reg & (1 << 25)) == 0) { /* SDR */
if ((reg & (1 << 9)) != 0)
mips_cpu_feq = (560*1000*1000);
else {
if ((reg & (1 << 26)) != 0)
mips_cpu_feq = (560*1000*1000);
else
mips_cpu_feq = (420*1000*1000);
}
mips_bus_feq = (140*1000*1000);
} else { /* DDR */
if ((reg & (1 << 9)) != 0) {
mips_cpu_feq = (700*1000*1000);
if ((reg & (1 << 26)) != 0)
mips_bus_feq = (175*1000*1000);
else
mips_bus_feq = 233333333;
} else {
mips_cpu_feq = (500*1000*1000);
if ((reg & (1 << 26)) != 0)
mips_bus_feq = (125*1000*1000);
else
mips_bus_feq = 166666667;
}
}
#elif defined(RT6352_ASIC_BOARD)
/* FIXME */
mips_cpu_feq = (600*1000*1000);
mips_bus_feq = (133*1000*1000);
#elif defined(RT71100_ASIC_BOARD)
/* FIXME */
mips_cpu_feq = (800*1000*1000);
mips_bus_feq = (133*1000*1000);
#elif defined (RT3883_ASIC_BOARD)
clk_sel = (reg>>8) & 0x03;
switch(clk_sel) {
case 0:
mips_cpu_feq = (250*1000*1000);
break;
case 1:
mips_cpu_feq = (384*1000*1000);
break;
case 2:
mips_cpu_feq = (480*1000*1000);
break;
case 3:
mips_cpu_feq = (500*1000*1000);
break;
}
#if defined (CFG_ENV_IS_IN_SPI)
if ((reg>>17) & 0x1) { //DDR2
switch(clk_sel) {
case 0:
mips_bus_feq = (125*1000*1000);
break;
case 1:
mips_bus_feq = (128*1000*1000);
break;
case 2:
mips_bus_feq = (160*1000*1000);
break;
case 3:
mips_bus_feq = (166*1000*1000);
break;
}
}
else {
switch(clk_sel) {
case 0:
mips_bus_feq = (83*1000*1000);
break;
case 1:
mips_bus_feq = (96*1000*1000);
break;
case 2:
mips_bus_feq = (120*1000*1000);
break;
case 3:
mips_bus_feq = (125*1000*1000);
break;
}
}
#elif defined ON_BOARD_SDR
switch(clk_sel) {
case 0:
mips_bus_feq = (83*1000*1000);
break;
case 1:
mips_bus_feq = (96*1000*1000);
break;
case 2:
mips_bus_feq = (120*1000*1000);
break;
case 3:
mips_bus_feq = (125*1000*1000);
break;
}
#elif defined ON_BOARD_DDR2
switch(clk_sel) {
case 0:
mips_bus_feq = (125*1000*1000);
break;
case 1:
mips_bus_feq = (128*1000*1000);
break;
case 2:
mips_bus_feq = (160*1000*1000);
break;
case 3:
mips_bus_feq = (166*1000*1000);
break;
}
#else
#error undef SDR or DDR
#endif
#else /* RT2880 ASIC version */
clk_sel = (reg>>20) & 0x03;
switch(clk_sel) {
#ifdef RT2880_MP
case 0:
mips_cpu_feq = (250*1000*1000);
break;
case 1:
mips_cpu_feq = (266*1000*1000);
break;
case 2:
mips_cpu_feq = (280*1000*1000);
break;
case 3:
mips_cpu_feq = (300*1000*1000);
break;
#else
case 0:
mips_cpu_feq = (233*1000*1000);
break;
case 1:
mips_cpu_feq = (250*1000*1000);
break;
case 2:
mips_cpu_feq = (266*1000*1000);
break;
case 3:
mips_cpu_feq = (280*1000*1000);
break;
#endif
}
mips_bus_feq = mips_cpu_feq/2;
#endif
//RALINK_REG(RT2880_SYSCFG_REG) = reg;
/* in general, the spec define 8192 refresh cycles/64ms
* 64ms/8192 = 7.8us
* 7.8us * 106.7Mhz(SDRAM clock) = 832
* the value of refresh cycle shall smaller than 832.
* so we config it at 0x300 (suggested by ASIC)
*/
#if defined(ON_BOARD_SDR) && defined(ON_BOARD_256M_DRAM_COMPONENT)
{
u32 tREF;
tREF = RALINK_REG(SDRAM_CFG1_REG);
tREF &= 0xffff0000;
#if defined(ASIC_BOARD)
tREF |= 0x00000300;
#elif defined(FPGA_BOARD)
tREF |= 0x000004B;
#else
#error "not exist"
#endif
RALINK_REG(SDRAM_CFG1_REG) = tREF;
}
#endif
printf("CPU frequency: %lu\n", mips_cpu_feq);
}
package/boot/uboot-zyxel/files/cpu/rt2880.old/start.S
+2057
View File
File diff suppressed because it is too large Load Diff