58 lines
1.4 KiB
C
58 lines
1.4 KiB
C
/* DDR system configuration */
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M_DDR_REG 0xe0000000 0x00000004
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M_DDR_REG 0xe0000004 0x00000004
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/* make sure we are in soft reset */
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M_DDR_REG 0xf6000000 0x00000200
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/* DDR speed */
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M_DDR_REG 0xe0000008 0x01c00180
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#if (RUBY_DDR_SPEED == 160)
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M_DDR_REG 0xe000000c 0x01000080
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M_DDR_REG 0xf6000004 0x00081027
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#elif (RUBY_DDR_SPEED == 200)
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M_DDR_REG 0xe000000c 0x00c00080
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M_DDR_REG 0xf6000004 0x00081030
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#elif (RUBY_DDR_SPEED == 250)
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M_DDR_REG 0xe000000c 0x00800080
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M_DDR_REG 0xf6000004 0x0008103c
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#elif (RUBY_DDR_SPEED == 320)
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M_DDR_REG 0xe000000c 0x00400080
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M_DDR_REG 0xf6000004 0x0008104e
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#elif (RUBY_DDR_SPEED == 400)
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M_DDR_REG 0xe000000c 0x00000080
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M_DDR_REG 0xf6000004 0x00081061
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#else
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#error RUBY_DDR_SPEED not supported
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#endif
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/* timing setup */
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M_DDR_REG 0xf6000048 0x00000000
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M_DDR_REG 0xf600002c 0x00000000
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M_DDR_REG 0xf6000030 0x00020b42
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M_DDR_REG 0xf6000058 0x0001ffff
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M_DDR_REG 0xf60000a4 0x10300800
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/* memory organization */
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#if RUBY_DDR_MICRON
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M_DDR_REG 0xf6000078 0x00004444
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M_DDR_REG 0xf600007c 0x3c3c3c3c
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M_DDR_REG 0xf600003c 0x00000777
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M_DDR_REG 0xf6000040 0xfff00000
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M_DDR_REG 0xf6000044 0x0fff3333
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#elif RUBY_DDR_ETRON
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M_DDR_REG 0xf6000078 0x00004343
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M_DDR_REG 0xf600007c 0x20202020
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M_DDR_REG 0xf600003c 0x00000f77
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M_DDR_REG 0xf6000040 0xfff00000
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M_DDR_REG 0xf6000044 0x0fff2222
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#else
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#error no memory organization defined
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#endif
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#if RUBY_DDR_16BIT
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M_DDR_REG 0xf6000000 0x00000205
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#else
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M_DDR_REG 0xf6000000 0x00000201
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#endif
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