86 lines
2.9 KiB
ArmAsm
86 lines
2.9 KiB
ArmAsm
/*
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* (C) Copyright 2010 Quantenna Communications Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <asm/arcregs.h>
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#include <asm/arch/platform.h>
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#if RUBY_MMAP_FLIP
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ruby_flip_mmap:
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.globl ruby_flip_mmap
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/* Code must be position-independent! */
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/*
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* Flush and invalidate data cache.
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* Please make sure that instructions which touch
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* d-cache are NOT used until flipping is done.
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*/
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/* Set flush mode for invalidate operation */
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lr r1, [ARC_REG_DC_CTRL]
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bset r1, r1, 0x6
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sr r1, [ARC_REG_DC_CTRL]
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/* Start invalidate operation */
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mov r1, 0x1
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sr r1, [ARC_REG_DC_IVDC]
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/* Check while cache invalidating will be finished */
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dcache_flush_continue:
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lr r1, [ARC_REG_DC_CTRL]
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and r1, r1, ARC_DC_FLUSH_STATUS_BIT
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brne r1, 0x0, dcache_flush_continue
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/* Prepare flipping.
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* After code is finished SRAM will be moved from 0x8000_0000 to 0x8800_0000,
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* and DDR from 0x0 to 0x8000_0000.
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*/
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mov r1, RUBY_SYS_CTL_BASE_ADDR
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mov r2, RUBY_SYS_CTL_LINUX_MAP(0x1) | RUBY_SYS_CTL_REMAP(0x3)
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st.di r2, [r1, RUBY_SYS_CTL_MASK - RUBY_SYS_CTL_BASE_ADDR]
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mov r2, RUBY_SYS_CTL_LINUX_MAP(0x1)
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.align ARC_ICACHE_LINE_LEN
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/* Do flipping.
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* Align to cache line to ensure we don't hit memory during following instructions.
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* Code must fit into 1 cache line (32 bytes).
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*/
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st.di r2, [r1, RUBY_SYS_CTL_CTRL - RUBY_SYS_CTL_BASE_ADDR]
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ld.di r2, [r1, RUBY_SYS_CTL_CTRL - RUBY_SYS_CTL_BASE_ADDR] /* read back to clear pipeline */
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sync /* wait for pipeline to flush */
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j boot_continue /* jump to absolute addr 0x88xx_xxxx */
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/* Align to cache line so code occupy strictly 1 cache line. */
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.align ARC_ICACHE_LINE_LEN
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boot_continue:
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/* Finalize flipping. */
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mov r2, 0x0
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st.di r2, [r1, RUBY_SYS_CTL_MASK - RUBY_SYS_CTL_BASE_ADDR]
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/* Let's discard instruction cache.
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*/
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mov r2, 0x1
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sr r2, [ARC_REG_IC_IVIC] /* invalidate i-cache */
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lr r2, [ARC_REG_IC_CTRL] /* read will be not completed until i-cache is invalidated */
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/* Done. We are now sitting in different addresses. */
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b ruby_boot
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#endif // #if RUBY_MMAP_FLIP
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