126 lines
4.0 KiB
C
126 lines
4.0 KiB
C
/*
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* (C) Copyright 2010 Quantenna Communications Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#define PCIE_REGION_BASE 0xB0000000
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#define PCIE_REGION_END 0xCFFFFFFF
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#define PCIE_CFG_MSI 1
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#define PCIE_CFG_BAR64 0
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#define PCIE_ROM_MASK_ADDR 0xE9001030
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#define PCIE_BAR_32 0
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#define PCIE_BAR_64 (RUBY_BIT(2))
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#define PCIE_BAR_PREFETCH (RUBY_BIT(3))
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#define PCIE_BAR_CFG(bar64) (PCIE_BAR_PREFETCH | ((bar64) ? PCIE_BAR_64 : PCIE_BAR_32))
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#define PCIE_BAR_SYSCTL 0
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#define PCIE_BAR_SYSCTL_LEN 0xFFFF
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#define PCIE_BAR_SYSCTL_LO 0xE0000000
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#define PCIE_BAR_SYSCTL_HI 0x00000000
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#define PCIE_BAR_SHMEM 2
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#define PCIE_BAR_SHMEM_LEN (RUBY_PCIE_BDA_SIZE - 1)
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#define PCIE_BAR_SHMEM_LO RUBY_PCIE_BDA_ADDR
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#define PCIE_BAR_SHMEM_HI 0x00000000
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#define PCIE_LINKUP (RUBY_BIT(8)|RUBY_BIT(9))
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#define PCIE_DEFAULT_CFG0 (0xff3c9410)
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/* ATU defines */
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#define PCIE_ATU_MEMREGION 0x00000000
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#define PCIE_ATU_BAR_MATCH 0xC0000000
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#define PCIE_ATU_BAR_MIN_SIZE 0x00010000 /* 64k */
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#define PCIE_ATU_BAR_EN(n) (((n) << 8) | PCIE_ATU_BAR_MATCH)
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/* Shared memory ATU BAR setup */
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#define PCIE_SHMEM_REGION RUBY_PCIE_ATU_IB_REGION(0)
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#define PCIE_SHMEM_ENABLE (PCIE_ATU_BAR_EN(PCIE_BAR_SHMEM))
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/* Syscfg ATU BAR setup */
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#define PCIE_SYSCTL_REGION RUBY_PCIE_ATU_IB_REGION(1)
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#define PCIE_SYSCTL_ENABLE (PCIE_ATU_BAR_EN(PCIE_BAR_SYSCTL))
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/* Size of MSI region */
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#define PCIE_MSIMEM_SIZE PCIE_ATU_BAR_MIN_SIZE
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#define PCIE_MSIMEM_SIZE_MASK (PCIE_ATU_BAR_MIN_SIZE - 1)
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/* Outbound Host Memoory translation setup */
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#define PCIE_HOSTMEM_EP_START PCIE_REGION_BASE
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#define PCIE_HOSTMEM_EP_END (PCIE_REGION_END - PCIE_MSIMEM_SIZE)
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#define PCIE_HOSTMEM_DMA_MASK (PCIE_HOSTMEM_EP_END - PCIE_HOSTMEM_EP_START)
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#define PCIE_HOSTMEM_REGION (RUBY_PCIE_ATU_OB_REGION(1))
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#define PCIE_HOSTMEM_EP_START_LO PCIE_REGION_BASE
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#define PCIE_HOSTMEM_EP_START_HI 0x00000000
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#define PCIE_HOSTMEM_START_LO 0x00000000
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#define PCIE_HOSTMEM_START_HI 0x00000000
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#define PCIE_HOSTMEM_REGION_ENABLE RUBY_PCIE_ATU_OB_ENABLE
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/* Outbound MSI ATU setup */
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/* MSI region is the upper 64kbytes of the PCIE slave area */
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#define PCIE_MSI_BASE 0xE9000050
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#define PCIE_MSI_CAP (PCIE_MSI_BASE + 0x0)
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#define PCIE_MSI_LOW_ADDR (PCIE_MSI_BASE + 0x4)
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#define PCIE_MSI_HIG_ADDR (PCIE_MSI_BASE + 0x8)
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#define PCIE_MSI_REGION (RUBY_PCIE_ATU_OB_REGION(0))
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#define PCIE_MSI_REGION_ENABLE RUBY_PCIE_ATU_OB_ENABLE
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#define MSI_EN RUBY_BIT(0)
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#define MSI_64_EN RUBY_BIT(7)
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#define PCIE_MSI_EP_END PCIE_REGION_END
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#define PCIE_MSI_EP_START_LO (PCIE_REGION_END - PCIE_MSIMEM_SIZE_MASK)
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#define PCIE_MSI_EP_START_HI 0x00000000
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#define PCIE_MSI_ADDR_OFFSET(a) ((a) & 0xFFFF)
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#define PCIE_MSI_ADDR_ALIGN(a) ((a) & (~0xFFFF))
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/* Default pcie lzma load addr */
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#define PCIE_FW_LZMA_LOAD QTNBOOT_COPY_DRAM_ADDR
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/* pcie boot control area */
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#define PCIE_BDA (0x80000000 + RUBY_PCIE_BDA_ADDR)
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#define PCIE_BDA_LEN RUBY_PCIE_BDA_SIZE
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/* pcie Root Complex defines */
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#define SYS_RST_PCIE (0x00002000)
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#define SYS_RST_IOSS (0x00000020)
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#define PCIE_CFG0_DEFAULT_VALUE (0xff3c9400)
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#define PCIE_CFG_RC_MODE (0x14)
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#define PCIE_IO_EN RUBY_BIT(0)
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#define PCIE_MEM_EN RUBY_BIT(1)
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#define PCIE_BUS_MASTER_EN RUBY_BIT(2)
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#define BUS_SCAN_TRY_MAX 1000
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#define PCIE_DEV_LINKUP_MASK 0x700
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#define PCIE_MSI_ENV "MSI"
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void board_pcie_init(size_t memsz, uint32_t flags );
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